From patchwork Thu Oct 17 22:57:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D97291575 for ; Thu, 17 Oct 2019 22:59:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF73F21D7A for ; Thu, 17 Oct 2019 22:59:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Maeg2k61" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF73F21D7A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:33794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLEjk-00025z-GD for patchwork-qemu-devel@patchwork.kernel.org; Thu, 17 Oct 2019 18:59:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40996) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLEif-0000GO-PW for qemu-devel@nongnu.org; Thu, 17 Oct 2019 18:58:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLEie-0002I9-8S for qemu-devel@nongnu.org; Thu, 17 Oct 2019 18:58:09 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53578) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iLEie-0002HM-1x; Thu, 17 Oct 2019 18:58:08 -0400 Received: by mail-wm1-x343.google.com with SMTP id i16so4174637wmd.3; Thu, 17 Oct 2019 15:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nOKNgWomZ9lXuw/D4odL98GxIJfJYjVtBJTZV5RcceI=; b=Maeg2k61piCHIXluhyO9gUNYNExzByQFk2wqlb1mahUZz8dU9FrqMb9QrtBHLxnSkP JDwLhtgio/87nmfb6fhzrRbEhlQkRTs3RfWTlSU6zp50NqbAXEGHnoKeBh6JRhQN2hk/ Ozj+jVKaVFjE3i69X0H2vTSIL148HQpcZywb0RnyzKZyUTxCCH5qSsdyniASIaCGXBs0 7O/cEEgz1xocWda1a+nxWGJdtfNGQonw8UwAVBN7kIdUjs+PsnvgAGRwyruHspZyaLKw bHvD1tiPegvkTdGUaztQ4E6i+wH3Y+V5Fjn+grixGSdK9izRNz/wT6iZ+MAFrSqzGGDq FfGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nOKNgWomZ9lXuw/D4odL98GxIJfJYjVtBJTZV5RcceI=; b=VtkIqTvMdrlNybkfq8iTE5scB2auZZ9SD6dAh+EDYbwxQUgTT4eoqNkv0DXcHJo+Ok kI1xbr8sJ3SlpBrI7wlQtpdT7zxcnvWLEZZ07S1B2/87l/0nX67uqMpIhTYTUv3KAaPk qWKx1wS4sNvTGLzAO8LCJRhOQTPFkwarLpvjMpEvgeu4P2iCBpRauJdhwlKHSB3RRS0y oM7DO0BvO6OwyoKerOrep0iMMWB1scNcoEr+x5iA6vhpfDCsTBB172sSqOwj91gStl4b eZG7FDC9JGfRsXjtqsEORUlzszyOG8tz9aWoWmAyCCmjyuteWRZRbrCW/Ywe1QakHoBk I7tw== X-Gm-Message-State: APjAAAX7F5UcqtMvoUrbKZztQoL/YUyFr6i3TG801mtE3U2AAfjqlGdp 4JchaoH69COsrtDs2ISNbPdgtFd2 X-Google-Smtp-Source: APXvYqzavyHeErn4Mr/TYhYSbRkUgbu95g4EvOf8OcPaMoJ9Go990ddsSowBB4yGf3Cs/mZzg0EVGw== X-Received: by 2002:a05:600c:21da:: with SMTP id x26mr4833814wmj.152.1571353086254; Thu, 17 Oct 2019 15:58:06 -0700 (PDT) Received: from localhost.localdomain (14.red-88-21-201.staticip.rima-tde.net. [88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 01/10] hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor Date: Fri, 18 Oct 2019 00:57:51 +0200 Message-Id: <20191017225800.6946-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" We will soon implement the SYS_timer. This timer is used by Linux in the thermal subsystem, so once available, the subsystem will be enabled and poll the temperature sensors. We need to provide the minimum required to keep Linux booting. Add a dummy thermal sensor returning ~25°C based on: https://github.com/raspberrypi/linux/blob/rpi-5.3.y/drivers/thermal/broadcom/bcm2835_thermal.c Signed-off-by: Philippe Mathieu-Daudé --- v2: - Explicit g_assert_not_reached() with comment (Alex) - Add vmstate and reset handler (Peter) checkpatch warning: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? This is OK because the regex are: F: hw/*/bcm283* F: include/hw/*/bcm283* --- hw/misc/Makefile.objs | 1 + hw/misc/bcm2835_thermal.c | 135 ++++++++++++++++++++++++++++++ include/hw/misc/bcm2835_thermal.h | 27 ++++++ 3 files changed, 163 insertions(+) create mode 100644 hw/misc/bcm2835_thermal.c create mode 100644 include/hw/misc/bcm2835_thermal.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index a150680966..c89f3816a5 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -53,6 +53,7 @@ common-obj-$(CONFIG_OMAP) += omap_tap.o common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o common-obj-$(CONFIG_RASPI) += bcm2835_property.o common-obj-$(CONFIG_RASPI) += bcm2835_rng.o +common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o common-obj-$(CONFIG_SLAVIO) += slavio_misc.o common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o diff --git a/hw/misc/bcm2835_thermal.c b/hw/misc/bcm2835_thermal.c new file mode 100644 index 0000000000..c6f3b1ad60 --- /dev/null +++ b/hw/misc/bcm2835_thermal.c @@ -0,0 +1,135 @@ +/* + * BCM2835 dummy thermal sensor + * + * Copyright (C) 2019 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/misc/bcm2835_thermal.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" + +REG32(CTL, 0) +FIELD(CTL, POWER_DOWN, 0, 1) +FIELD(CTL, RESET, 1, 1) +FIELD(CTL, BANDGAP_CTRL, 2, 3) +FIELD(CTL, INTERRUPT_ENABLE, 5, 1) +FIELD(CTL, DIRECT, 6, 1) +FIELD(CTL, INTERRUPT_CLEAR, 7, 1) +FIELD(CTL, HOLD, 8, 10) +FIELD(CTL, RESET_DELAY, 18, 8) +FIELD(CTL, REGULATOR_ENABLE, 26, 1) + +REG32(STAT, 4) +FIELD(STAT, DATA, 0, 10) +FIELD(STAT, VALID, 10, 1) +FIELD(STAT, INTERRUPT, 11, 1) + +#define THERMAL_OFFSET_C 412 +#define THERMAL_COEFF (-0.538f) + +static uint16_t bcm2835_thermal_temp2adc(int temp_C) +{ + return (temp_C - THERMAL_OFFSET_C) / THERMAL_COEFF; +} + +static uint64_t bcm2835_thermal_read(void *opaque, hwaddr addr, unsigned size) +{ + Bcm2835ThermalState *s = BCM2835_THERMAL(opaque); + uint32_t val = 0; + + switch (addr) { + case A_CTL: + val = s->ctl; + break; + case A_STAT: + /* Temperature is constantly 25°C. */ + val = FIELD_DP32(bcm2835_thermal_temp2adc(25), STAT, VALID, true); + break; + default: + /* MemoryRegionOps are aligned, so this can not happen. */ + g_assert_not_reached(); + } + return val; +} + +static void bcm2835_thermal_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + Bcm2835ThermalState *s = BCM2835_THERMAL(opaque); + + switch (addr) { + case A_CTL: + s->ctl = value; + break; + case A_STAT: + qemu_log_mask(LOG_GUEST_ERROR, "%s: write 0x%" PRIx64 + " to 0x%" HWADDR_PRIx "\n", + __func__, value, addr); + break; + default: + /* MemoryRegionOps are aligned, so this can not happen. */ + g_assert_not_reached(); + } +} + +static const MemoryRegionOps bcm2835_thermal_ops = { + .read = bcm2835_thermal_read, + .write = bcm2835_thermal_write, + .impl.max_access_size = 4, + .valid.min_access_size = 4, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void bcm2835_thermal_reset(DeviceState *dev) +{ + Bcm2835ThermalState *s = BCM2835_THERMAL(dev); + + s->ctl = 0; +} + +static void bcm2835_thermal_realize(DeviceState *dev, Error **errp) +{ + Bcm2835ThermalState *s = BCM2835_THERMAL(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_thermal_ops, + s, TYPE_BCM2835_THERMAL, 8); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static const VMStateDescription bcm2835_thermal_vmstate = { + .name = "bcm2835_thermal", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(ctl, Bcm2835ThermalState), + VMSTATE_END_OF_LIST() + } +}; + +static void bcm2835_thermal_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = bcm2835_thermal_realize; + dc->reset = bcm2835_thermal_reset; + dc->vmsd = &bcm2835_thermal_vmstate; +} + +static const TypeInfo bcm2835_thermal_info = { + .name = TYPE_BCM2835_THERMAL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Bcm2835ThermalState), + .class_init = bcm2835_thermal_class_init, +}; + +static void bcm2835_thermal_register_types(void) +{ + type_register_static(&bcm2835_thermal_info); +} + +type_init(bcm2835_thermal_register_types) diff --git a/include/hw/misc/bcm2835_thermal.h b/include/hw/misc/bcm2835_thermal.h new file mode 100644 index 0000000000..c3651b27ec --- /dev/null +++ b/include/hw/misc/bcm2835_thermal.h @@ -0,0 +1,27 @@ +/* + * BCM2835 dummy thermal sensor + * + * Copyright (C) 2019 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_BCM2835_THERMAL_H +#define HW_MISC_BCM2835_THERMAL_H + +#include "hw/sysbus.h" + +#define TYPE_BCM2835_THERMAL "bcm2835-thermal" + +#define BCM2835_THERMAL(obj) \ + OBJECT_CHECK(Bcm2835ThermalState, (obj), TYPE_BCM2835_THERMAL) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + MemoryRegion iomem; + uint32_t ctl; +} Bcm2835ThermalState; + +#endif From patchwork Thu Oct 17 22:57:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197291 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B56C1668 for ; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 02/10] hw/arm/bcm2835_peripherals: Use the thermal sensor block Date: Fri, 18 Oct 2019 00:57:52 +0200 Message-Id: <20191017225800.6946-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Alistair Francis , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Map the thermal sensor in the BCM2835 block. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2835_peripherals.c | 13 +++++++++++++ include/hw/arm/bcm2835_peripherals.h | 2 ++ include/hw/arm/raspi_platform.h | 1 + 3 files changed, 16 insertions(+) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index fdcf616c56..70bf927a02 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -111,6 +111,10 @@ static void bcm2835_peripherals_init(Object *obj) object_property_add_const_link(OBJECT(&s->dma), "dma-mr", OBJECT(&s->gpu_bus_mr), &error_abort); + /* Thermal */ + sysbus_init_child_obj(obj, "thermal", &s->thermal, sizeof(s->thermal), + TYPE_BCM2835_THERMAL); + /* GPIO */ sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO); @@ -321,6 +325,15 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) INTERRUPT_DMA0 + n)); } + /* THERMAL */ + object_property_set_bool(OBJECT(&s->thermal), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->peri_mr, THERMAL_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->thermal), 0)); + /* GPIO */ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); if (err) { diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index 62a4c7b559..be7ad9b499 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -20,6 +20,7 @@ #include "hw/misc/bcm2835_property.h" #include "hw/misc/bcm2835_rng.h" #include "hw/misc/bcm2835_mbox.h" +#include "hw/misc/bcm2835_thermal.h" #include "hw/sd/sdhci.h" #include "hw/sd/bcm2835_sdhost.h" #include "hw/gpio/bcm2835_gpio.h" @@ -53,6 +54,7 @@ typedef struct BCM2835PeripheralState { SDHCIState sdhci; BCM2835SDHostState sdhost; BCM2835GpioState gpio; + Bcm2835ThermalState thermal; UnimplementedDeviceState i2s; UnimplementedDeviceState spi[1]; UnimplementedDeviceState i2c[3]; diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h index cdcbca943f..61b04a1bd4 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -48,6 +48,7 @@ #define SPI0_OFFSET 0x204000 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */ #define OTP_OFFSET 0x20f000 +#define THERMAL_OFFSET 0x212000 #define BSC_SL_OFFSET 0x214000 /* SPI slave */ #define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */ #define EMMC1_OFFSET 0x300000 From patchwork Thu Oct 17 22:57:53 2019 Content-Type: text/plain; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 03/10] hw/timer/bcm2835: Add the BCM2835 SYS_timer Date: Fri, 18 Oct 2019 00:57:53 +0200 Message-Id: <20191017225800.6946-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add the 64-bit free running timer. Do not model the COMPARE register (no IRQ generated). This timer is used by Linux kernel and recently U-Boot: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clocksource/bcm2835_timer.c?h=v3.7 https://github.com/u-boot/u-boot/blob/v2019.07/include/configs/rpi.h#L19 Datasheet used: https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Signed-off-by: Philippe Mathieu-Daudé --- v2: - Add status/compare* registers - Add vmstate and reset handler checkpatch warning: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? This is OK because the regex are: F: hw/*/bcm283* F: include/hw/*/bcm283* --- hw/timer/Makefile.objs | 1 + hw/timer/bcm2835_systmr.c | 166 ++++++++++++++++++++++++++++++ hw/timer/trace-events | 5 + include/hw/timer/bcm2835_systmr.h | 33 ++++++ 4 files changed, 205 insertions(+) create mode 100644 hw/timer/bcm2835_systmr.c create mode 100644 include/hw/timer/bcm2835_systmr.h diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 123d92c969..696cda5905 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -47,3 +47,4 @@ common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) += cmsdk-apb-dualtimer.o common-obj-$(CONFIG_MSF2) += mss-timer.o +common-obj-$(CONFIG_RASPI) += bcm2835_systmr.o diff --git a/hw/timer/bcm2835_systmr.c b/hw/timer/bcm2835_systmr.c new file mode 100644 index 0000000000..49b40b55f9 --- /dev/null +++ b/hw/timer/bcm2835_systmr.c @@ -0,0 +1,166 @@ +/* + * BCM2835 SYS timer emulation + * + * Copyright (C) 2019 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Datasheet: BCM2835 ARM Peripherals (C6357-M-1398) + * https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf + * + * Only the free running 64-bit counter is implemented. + * The 4 COMPARE registers and the interruption are not implemented. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "hw/timer/bcm2835_systmr.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "trace.h" + +REG32(CTRL_STATUS, 0x00) +REG32(COUNTER_LOW, 0x04) +REG32(COUNTER_HIGH, 0x08) +REG32(COMPARE0, 0x0c) +REG32(COMPARE1, 0x10) +REG32(COMPARE2, 0x14) +REG32(COMPARE3, 0x18) + +static void bcm2835_systmr_update_irq(BCM2835SystemTimerState *s) +{ + bool enable = !!s->reg.status; + + trace_bcm2835_systmr_irq(enable); + qemu_set_irq(s->irq, enable); +} + +static void bcm2835_systmr_update_compare(BCM2835SystemTimerState *s, + unsigned timer_index) +{ + /* TODO fow now, since neither Linux nor U-boot use these timers. */ + qemu_log_mask(LOG_UNIMP, "COMPARE register %u not implemented\n", + timer_index); +} + +static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset, + unsigned size) +{ + BCM2835SystemTimerState *s = BCM2835_SYSTIMER(opaque); + uint64_t r = 0; + + switch (offset) { + case A_CTRL_STATUS: + r = s->reg.status; + break; + case A_COMPARE0 ... A_COMPARE3: + r = s->reg.compare[(offset - A_COMPARE0) >> 2]; + break; + case A_COUNTER_LOW: + case A_COUNTER_HIGH: + /* Free running counter at 1MHz */ + r = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL); + r >>= 8 * (offset - A_COUNTER_LOW); + r &= UINT32_MAX; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + break; + } + trace_bcm2835_systmr_read(offset, r); + + return r; +} + +static void bcm2835_systmr_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + BCM2835SystemTimerState *s = BCM2835_SYSTIMER(opaque); + + trace_bcm2835_systmr_write(offset, value); + switch (offset) { + case A_CTRL_STATUS: + s->reg.status &= ~value; /* Ack */ + bcm2835_systmr_update_irq(s); + break; + case A_COMPARE0 ... A_COMPARE3: + s->reg.compare[(offset - A_COMPARE0) >> 2] = value; + bcm2835_systmr_update_compare(s, (offset - A_COMPARE0) >> 2); + break; + case A_COUNTER_LOW: + case A_COUNTER_HIGH: + qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only ofs 0x%" HWADDR_PRIx "\n", + __func__, offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + break; + } +} + +static const MemoryRegionOps bcm2835_systmr_ops = { + .read = bcm2835_systmr_read, + .write = bcm2835_systmr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void bcm2835_systmr_reset(DeviceState *dev) +{ + BCM2835SystemTimerState *s = BCM2835_SYSTIMER(dev); + + s->reg.status = 0; + for (size_t i = 0; i < ARRAY_SIZE(s->reg.compare); i++) { + s->reg.compare[i] = 0; + } +} + +static void bcm2835_systmr_realize(DeviceState *dev, Error **errp) +{ + BCM2835SystemTimerState *s = BCM2835_SYSTIMER(dev); + + memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_systmr_ops, + s, "bcm2835-sys-timer", 0x20); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); +} + +static const VMStateDescription bcm2835_systmr_vmstate = { + .name = "bcm2835_sys_timer", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(reg.status, BCM2835SystemTimerState), + VMSTATE_UINT32_ARRAY(reg.compare, BCM2835SystemTimerState, 4), + VMSTATE_END_OF_LIST() + } +}; + +static void bcm2835_systmr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = bcm2835_systmr_realize; + dc->reset = bcm2835_systmr_reset; + dc->vmsd = &bcm2835_systmr_vmstate; +} + +static const TypeInfo bcm2835_systmr_info = { + .name = TYPE_BCM2835_SYSTIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BCM2835SystemTimerState), + .class_init = bcm2835_systmr_class_init, +}; + +static void bcm2835_systmr_register_types(void) +{ + type_register_static(&bcm2835_systmr_info); +} + +type_init(bcm2835_systmr_register_types); diff --git a/hw/timer/trace-events b/hw/timer/trace-events index db02a9142c..0aa399ac69 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -87,3 +87,8 @@ pl031_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl031_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl031_alarm_raised(void) "alarm raised" pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" + +# bcm2835_systmr.c +bcm2835_systmr_irq(bool enable) "timer irq state %u" +bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 +bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 diff --git a/include/hw/timer/bcm2835_systmr.h b/include/hw/timer/bcm2835_systmr.h new file mode 100644 index 0000000000..c0bc5c8127 --- /dev/null +++ b/include/hw/timer/bcm2835_systmr.h @@ -0,0 +1,33 @@ +/* + * BCM2835 SYS timer emulation + * + * Copyright (c) 2019 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef BCM2835_SYSTIMER_H +#define BCM2835_SYSTIMER_H + +#include "hw/sysbus.h" +#include "hw/irq.h" + +#define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer" +#define BCM2835_SYSTIMER(obj) \ + OBJECT_CHECK(BCM2835SystemTimerState, (obj), TYPE_BCM2835_SYSTIMER) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + + struct { + uint32_t status; + uint32_t compare[4]; + } reg; +} BCM2835SystemTimerState; + +#endif From patchwork Thu Oct 17 22:57:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0800F13B1 for ; Thu, 17 Oct 2019 23:06:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D02CE21835 for ; Thu, 17 Oct 2019 23:06:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RrPNgMKo" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D02CE21835 Authentication-Results: mail.kernel.org; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 04/10] hw/arm/bcm2835_peripherals: Use the SYS_timer Date: Fri, 18 Oct 2019 00:57:54 +0200 Message-Id: <20191017225800.6946-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Connect the recently added SYS_timer. Now U-Boot does not hang anymore polling a free running counter stuck at 0. This timer is also used by the Linux kernel thermal subsystem. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- v2: Remove spurious error check (Alex) --- hw/arm/bcm2835_peripherals.c | 17 ++++++++++++++++- include/hw/arm/bcm2835_peripherals.h | 3 ++- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 70bf927a02..17207ae07e 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -58,6 +58,10 @@ static void bcm2835_peripherals_init(Object *obj) /* Interrupt Controller */ sysbus_init_child_obj(obj, "ic", &s->ic, sizeof(s->ic), TYPE_BCM2835_IC); + /* SYS Timer */ + sysbus_init_child_obj(obj, "systimer", &s->systmr, sizeof(s->systmr), + TYPE_BCM2835_SYSTIMER); + /* UART0 */ sysbus_init_child_obj(obj, "uart0", &s->uart0, sizeof(s->uart0), TYPE_PL011); @@ -171,6 +175,18 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); + /* Sys Timer */ + object_property_set_bool(OBJECT(&s->systmr), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->peri_mr, ST_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systmr), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systmr), 0, + qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ, + INTERRUPT_ARM_TIMER)); + /* UART0 */ qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0)); object_property_set_bool(OBJECT(&s->uart0), true, "realized", &err); @@ -352,7 +368,6 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) } create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); - create_unimp(s, &s->systmr, "bcm2835-systimer", ST_OFFSET, 0x20); create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index be7ad9b499..7859281e11 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -24,6 +24,7 @@ #include "hw/sd/sdhci.h" #include "hw/sd/bcm2835_sdhost.h" #include "hw/gpio/bcm2835_gpio.h" +#include "hw/timer/bcm2835_systmr.h" #include "hw/misc/unimp.h" #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" @@ -39,7 +40,7 @@ typedef struct BCM2835PeripheralState { MemoryRegion ram_alias[4]; qemu_irq irq, fiq; - UnimplementedDeviceState systmr; + BCM2835SystemTimerState systmr; UnimplementedDeviceState armtmr; UnimplementedDeviceState cprman; UnimplementedDeviceState a2w; From patchwork Thu Oct 17 22:57:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8150912 for ; Thu, 17 Oct 2019 23:02:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDFAD21D7A for ; Thu, 17 Oct 2019 23:02:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dnrccJ+a" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BDFAD21D7A Authentication-Results: mail.kernel.org; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 05/10] hw/arm/bcm2836: Make the SoC code modular Date: Fri, 18 Oct 2019 00:57:55 +0200 Message-Id: <20191017225800.6946-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This file creates the BCM2836/BCM2837 blocks. The biggest differences with the BCM2838 we are going to add, are the base addresses of the interrupt controller and the peripherals. Add these addresses in the BCM283XInfo structure to make this block more modular. Remove the MCORE_OFFSET offset as it is not useful and rather confusing. Reviewed-by: Esteban Bosse Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 723aef6bf5..019e67b906 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -16,15 +16,11 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" -/* Peripheral base address seen by the CPU */ -#define BCM2836_PERI_BASE 0x3F000000 - -/* "QA7" (Pi2) interrupt controller and mailboxes etc. */ -#define BCM2836_CONTROL_BASE 0x40000000 - struct BCM283XInfo { const char *name; const char *cpu_type; + hwaddr peri_base; /* Peripheral base address seen by the CPU */ + hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ int clusterid; }; @@ -32,12 +28,16 @@ static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"), + .peri_base = 0x3f000000, + .ctrl_base = 0x40000000, .clusterid = 0xf, }, #ifdef TARGET_AARCH64 { .name = TYPE_BCM2837, .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), + .peri_base = 0x3f000000, + .ctrl_base = 0x40000000, .clusterid = 0x0, }, #endif @@ -104,7 +104,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, - BCM2836_PERI_BASE, 1); + info->peri_base, 1); /* bcm2836 interrupt controller (and mailboxes, etc.) */ object_property_set_bool(OBJECT(&s->control), true, "realized", &err); @@ -113,7 +113,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, BCM2836_CONTROL_BASE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); @@ -126,7 +126,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), - BCM2836_PERI_BASE + MSYNC_OFFSET, + info->peri_base, "reset-cbar", &err); if (err) { error_propagate(errp, err); From patchwork Thu Oct 17 22:57:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D121F13B1 for ; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 06/10] hw/arm/bcm2836: Create VideoCore address space in the SoC Date: Fri, 18 Oct 2019 00:57:56 +0200 Message-Id: <20191017225800.6946-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently the VideoCore is created in the Peripheral container as the 'GPU bus'. It is created there because the peripherals using DMA use physical addresses from the VideoCore bus. However the VideoCore is a GPU core placed at the same hierarchical level than the ARM cores. To match the datasheet design, create the VideoCore container in the SoC, and link it to the peripheral container. The VideoCore bus is 1GiB wide, accessible at 4 regions in different cache configurations. Add the full mapping. Before this commit the memory tree is: (qemu) info mtree address-space: bcm2835-dma-memory 0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu 0000000000000000-000000003fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff 0000000040000000-000000007fffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff 000000007e000000-000000007effffff (prio 1, i/o): alias bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff 0000000080000000-00000000bfffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff 00000000c0000000-00000000ffffffff (prio 0, i/o): alias bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff After: address-space: bcm2835-dma-memory 0000000000000000-000000003fffffff (prio 0, i/o): videocore-bus 0000000000000000-000000003fffffff (prio 1, i/o): alias vc-ram-alias @ram 0000000000000000-000000003fffffff 000000003e000000-000000003effffff (prio 2, i/o): alias vc-peripherals-alias @bcm2835-peripherals 0000000000000000-0000000000ffffff 0000000040000000-000000007fffffff (prio 0, i/o): alias cached-coherent @videocore-bus 0000000000000000-000000003fffffff 0000000080000000-00000000bfffffff (prio 0, i/o): alias cached @videocore-bus 0000000000000000-000000003fffffff 00000000c0000000-00000000ffffffff (prio 0, i/o): alias uncached @videocore-bus 0000000000000000-000000003fffffff Now the periferals are accessible from the uncached region too. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2835_peripherals.c | 45 +++++++++------------------- hw/arm/bcm2836.c | 43 ++++++++++++++++++++++++-- include/hw/arm/bcm2835_peripherals.h | 4 +-- include/hw/arm/bcm2836.h | 5 ++++ 4 files changed, 62 insertions(+), 35 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 17207ae07e..059e44a620 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -9,6 +9,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu/module.h" #include "hw/arm/bcm2835_peripherals.h" @@ -16,9 +17,6 @@ #include "hw/arm/raspi_platform.h" #include "sysemu/sysemu.h" -/* Peripheral base address on the VC (GPU) system bus */ -#define BCM2835_VC_PERI_BASE 0x7e000000 - /* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */ #define BCM2835_SDHC_CAPAREG 0x52134b4 @@ -45,10 +43,6 @@ static void bcm2835_peripherals_init(Object *obj) object_property_add_child(obj, "peripheral-io", OBJECT(&s->peri_mr), NULL); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); - /* Internal memory region for peripheral bus addresses (not exported) */ - memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32); - object_property_add_child(obj, "gpu-bus", OBJECT(&s->gpu_bus_mr), NULL); - /* Internal memory region for request/response communication with * mailbox-addressable peripherals (not exported) */ @@ -82,9 +76,6 @@ static void bcm2835_peripherals_init(Object *obj) object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size", &error_abort); - object_property_add_const_link(OBJECT(&s->fb), "dma-mr", - OBJECT(&s->gpu_bus_mr), &error_abort); - /* Property channel */ sysbus_init_child_obj(obj, "property", &s->property, sizeof(s->property), TYPE_BCM2835_PROPERTY); @@ -93,8 +84,6 @@ static void bcm2835_peripherals_init(Object *obj) object_property_add_const_link(OBJECT(&s->property), "fb", OBJECT(&s->fb), &error_abort); - object_property_add_const_link(OBJECT(&s->property), "dma-mr", - OBJECT(&s->gpu_bus_mr), &error_abort); /* Random Number Generator */ sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), @@ -112,9 +101,6 @@ static void bcm2835_peripherals_init(Object *obj) sysbus_init_child_obj(obj, "dma", &s->dma, sizeof(s->dma), TYPE_BCM2835_DMA); - object_property_add_const_link(OBJECT(&s->dma), "dma-mr", - OBJECT(&s->gpu_bus_mr), &error_abort); - /* Thermal */ sysbus_init_child_obj(obj, "thermal", &s->thermal, sizeof(s->thermal), TYPE_BCM2835_THERMAL); @@ -133,7 +119,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) { BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev); Object *obj; - MemoryRegion *ram; + MemoryRegion *ram, *vc; Error *err = NULL; uint64_t ram_size, vcram_size; int n; @@ -144,25 +130,16 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) __func__, error_get_pretty(err)); return; } - ram = MEMORY_REGION(obj); ram_size = memory_region_size(ram); - /* Map peripherals and RAM into the GPU address space. */ - memory_region_init_alias(&s->peri_mr_alias, OBJECT(s), - "bcm2835-peripherals", &s->peri_mr, 0, - memory_region_size(&s->peri_mr)); - - memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE, - &s->peri_mr_alias, 1); - - /* RAM is aliased four times (different cache configurations) on the GPU */ - for (n = 0; n < 4; n++) { - memory_region_init_alias(&s->ram_alias[n], OBJECT(s), - "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size); - memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30, - &s->ram_alias[n], 0); + obj = object_property_get_link(OBJECT(dev), "videocore", &err); + if (obj == NULL) { + error_setg(errp, "%s: required videocore link not found: %s", + __func__, error_get_pretty(err)); + return; } + vc = MEMORY_REGION(obj); /* Interrupt Controller */ object_property_set_bool(OBJECT(&s->ic), true, "realized", &err); @@ -243,6 +220,8 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) return; } + object_property_add_const_link(OBJECT(&s->fb), "dma-mr", + OBJECT(vc), &error_abort); object_property_set_bool(OBJECT(&s->fb), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -255,6 +234,8 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB)); /* Property channel */ + object_property_add_const_link(OBJECT(&s->property), "dma-mr", + OBJECT(vc), &error_abort); object_property_set_bool(OBJECT(&s->property), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -323,6 +304,8 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) INTERRUPT_SDIO)); /* DMA Channels */ + object_property_add_const_link(OBJECT(&s->dma), "dma-mr", + OBJECT(vc), &error_abort); object_property_set_bool(OBJECT(&s->dma), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 019e67b906..d712f36052 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -9,6 +9,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu/module.h" #include "cpu.h" @@ -16,6 +17,9 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +/* Peripheral base address on the VC (GPU) system bus */ +#define BCM2835_VC_PERI_BASE 0x3e000000 + struct BCM283XInfo { const char *name; const char *cpu_type; @@ -50,6 +54,21 @@ static void bcm2836_init(Object *obj) const BCM283XInfo *info = bc->info; int n; + /* VideoCore memory region */ + memory_region_init(&s->videocore.mr[0], obj, "videocore-bus", 1 * GiB); + object_property_add_child(obj, "videocore", + OBJECT(&s->videocore.mr[0]), NULL); + for (n = 1; n < BCM283X_NCPUS; n++) { + static const char *alias_name[] = { + NULL, "cached-coherent", "cached", "uncached" + }; + memory_region_init_alias(&s->videocore.mr[n], obj, + alias_name[n], &s->videocore.mr[0], + 0, 1 * GiB); + memory_region_add_subregion_overlap(&s->videocore.mr[0], n * GiB, + &s->videocore.mr[n], 0); + } + for (n = 0; n < BCM283X_NCPUS; n++) { object_initialize_child(obj, "cpu[*]", &s->cpus[n], sizeof(s->cpus[n]), info->cpu_type, &error_abort, NULL); @@ -71,6 +90,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) BCM283XState *s = BCM283X(dev); BCM283XClass *bc = BCM283X_GET_CLASS(dev); const BCM283XInfo *info = bc->info; + MemoryRegion *ram_mr, *peri_mr; Object *obj; Error *err = NULL; int n; @@ -83,26 +103,45 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) __func__, error_get_pretty(err)); return; } - + ram_mr = MEMORY_REGION(obj); object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj, &err); if (err) { error_propagate(errp, err); return; } + object_property_add_const_link(OBJECT(&s->peripherals), "videocore", + OBJECT(&s->videocore), &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err); if (err) { error_propagate(errp, err); return; } + /* Map peripherals and RAM into the GPU address space. */ + memory_region_init_alias(&s->videocore.ram_mr_alias, OBJECT(s), + "vc-ram-alias", ram_mr, 0, + memory_region_size(ram_mr)); + memory_region_add_subregion_overlap(&s->videocore.mr[0], 0, + &s->videocore.ram_mr_alias, 1); + peri_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->peripherals), 0); + memory_region_init_alias(&s->videocore.peri_mr_alias, OBJECT(s), + "vc-peripherals-alias", + peri_mr, 0, 16 * MiB); + memory_region_add_subregion_overlap(&s->videocore.mr[0], + BCM2835_VC_PERI_BASE, + &s->videocore.peri_mr_alias, 2); + object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), "sd-bus", &err); if (err) { error_propagate(errp, err); return; } - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, info->peri_base, 1); diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index 7859281e11..f485f20aae 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -36,8 +36,8 @@ typedef struct BCM2835PeripheralState { SysBusDevice parent_obj; /*< public >*/ - MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr; - MemoryRegion ram_alias[4]; + MemoryRegion peri_mr; + MemoryRegion mbox_mr; qemu_irq irq, fiq; BCM2835SystemTimerState systmr; diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 97187f72be..a26bf895a4 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -35,6 +35,11 @@ typedef struct BCM283XState { char *cpu_type; uint32_t enabled_cpus; + struct { + MemoryRegion mr[4]; + MemoryRegion peri_mr_alias; + MemoryRegion ram_mr_alias; + } videocore; ARMCPU cpus[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; From patchwork Thu Oct 17 22:57:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C44113B1 for ; Thu, 17 Oct 2019 23:08:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21FF621D7A for ; Thu, 17 Oct 2019 23:08:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TddYRqK4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 21FF621D7A Authentication-Results: mail.kernel.org; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 07/10] hw/arm/bcm2836: Use per CPU address spaces Date: Fri, 18 Oct 2019 00:57:57 +0200 Message-Id: <20191017225800.6946-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently all CPUs access the main system bus. Let each CPU have his own address space. Before: address-space: cpu-secure-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000003fffffff (prio 0, ram): ram 000000003f000000-000000003fffffff (prio 1, i/o): bcm2835-peripherals 000000003f003000-000000003f00301f (prio 0, i/o): bcm2835-sys-timer 000000003f007000-000000003f007fff (prio 0, i/o): bcm2835-dma 000000003f00b200-000000003f00b3ff (prio 0, i/o): bcm2835-ic 000000003f00b400-000000003f00b43f (prio -1000, i/o): bcm2835-sp804 000000003f00b800-000000003f00bbff (prio 0, i/o): bcm2835-mbox 000000003f100000-000000003f100fff (prio -1000, i/o): bcm2835-cprman 000000003f102000-000000003f102fff (prio -1000, i/o): bcm2835-a2w 000000003f104000-000000003f10400f (prio 0, i/o): bcm2835-rng 000000003f200000-000000003f200fff (prio 0, i/o): bcm2835_gpio 000000003f201000-000000003f201fff (prio 0, i/o): pl011 000000003f202000-000000003f202fff (prio 0, i/o): bcm2835-sdhost 000000003f203000-000000003f2030ff (prio -1000, i/o): bcm2835-i2s 000000003f204000-000000003f20401f (prio -1000, i/o): bcm2835-spi0 000000003f205000-000000003f20501f (prio -1000, i/o): bcm2835-i2c0 000000003f20f000-000000003f20f07f (prio -1000, i/o): bcm2835-otp 000000003f212000-000000003f212007 (prio 0, i/o): bcm2835-thermal 000000003f214000-000000003f2140ff (prio -1000, i/o): bcm2835-spis 000000003f215000-000000003f2150ff (prio 0, i/o): bcm2835-aux 000000003f300000-000000003f3000ff (prio 0, i/o): sdhci 000000003f600000-000000003f6000ff (prio -1000, i/o): bcm2835-smi 000000003f804000-000000003f80401f (prio -1000, i/o): bcm2835-i2c1 000000003f805000-000000003f80501f (prio -1000, i/o): bcm2835-i2c2 000000003f900000-000000003f907fff (prio -1000, i/o): bcm2835-dbus 000000003f910000-000000003f917fff (prio -1000, i/o): bcm2835-ave0 000000003f980000-000000003f980fff (prio -1000, i/o): dwc-usb2 000000003fe00000-000000003fe000ff (prio -1000, i/o): bcm2835-sdramc 000000003fe05000-000000003fe050ff (prio 0, i/o): bcm2835-dma-chan15 0000000040000000-00000000400000ff (prio 0, i/o): bcm2836-control address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000003fffffff (prio 0, ram): ram 000000003f000000-000000003fffffff (prio 1, i/o): bcm2835-peripherals 000000003f003000-000000003f00301f (prio 0, i/o): bcm2835-sys-timer 000000003f007000-000000003f007fff (prio 0, i/o): bcm2835-dma 000000003f00b200-000000003f00b3ff (prio 0, i/o): bcm2835-ic 000000003f00b400-000000003f00b43f (prio -1000, i/o): bcm2835-sp804 000000003f00b800-000000003f00bbff (prio 0, i/o): bcm2835-mbox 000000003f100000-000000003f100fff (prio -1000, i/o): bcm2835-cprman 000000003f102000-000000003f102fff (prio -1000, i/o): bcm2835-a2w 000000003f104000-000000003f10400f (prio 0, i/o): bcm2835-rng 000000003f200000-000000003f200fff (prio 0, i/o): bcm2835_gpio 000000003f201000-000000003f201fff (prio 0, i/o): pl011 000000003f202000-000000003f202fff (prio 0, i/o): bcm2835-sdhost 000000003f203000-000000003f2030ff (prio -1000, i/o): bcm2835-i2s 000000003f204000-000000003f20401f (prio -1000, i/o): bcm2835-spi0 000000003f205000-000000003f20501f (prio -1000, i/o): bcm2835-i2c0 000000003f20f000-000000003f20f07f (prio -1000, i/o): bcm2835-otp 000000003f212000-000000003f212007 (prio 0, i/o): bcm2835-thermal 000000003f214000-000000003f2140ff (prio -1000, i/o): bcm2835-spis 000000003f215000-000000003f2150ff (prio 0, i/o): bcm2835-aux 000000003f300000-000000003f3000ff (prio 0, i/o): sdhci 000000003f600000-000000003f6000ff (prio -1000, i/o): bcm2835-smi 000000003f804000-000000003f80401f (prio -1000, i/o): bcm2835-i2c1 000000003f805000-000000003f80501f (prio -1000, i/o): bcm2835-i2c2 000000003f900000-000000003f907fff (prio -1000, i/o): bcm2835-dbus 000000003f910000-000000003f917fff (prio -1000, i/o): bcm2835-ave0 000000003f980000-000000003f980fff (prio -1000, i/o): dwc-usb2 000000003fe00000-000000003fe000ff (prio -1000, i/o): bcm2835-sdramc 000000003fe05000-000000003fe050ff (prio 0, i/o): bcm2835-dma-chan15 0000000040000000-00000000400000ff (prio 0, i/o): bcm2836-control memory-region: bcm2835-peripherals 000000003f000000-000000003fffffff (prio 1, i/o): bcm2835-peripherals 000000003f003000-000000003f00301f (prio 0, i/o): bcm2835-sys-timer 000000003f007000-000000003f007fff (prio 0, i/o): bcm2835-dma 000000003f00b200-000000003f00b3ff (prio 0, i/o): bcm2835-ic 000000003f00b400-000000003f00b43f (prio -1000, i/o): bcm2835-sp804 000000003f00b800-000000003f00bbff (prio 0, i/o): bcm2835-mbox 000000003f100000-000000003f100fff (prio -1000, i/o): bcm2835-cprman 000000003f102000-000000003f102fff (prio -1000, i/o): bcm2835-a2w 000000003f104000-000000003f10400f (prio 0, i/o): bcm2835-rng 000000003f200000-000000003f200fff (prio 0, i/o): bcm2835_gpio 000000003f201000-000000003f201fff (prio 0, i/o): pl011 000000003f202000-000000003f202fff (prio 0, i/o): bcm2835-sdhost 000000003f203000-000000003f2030ff (prio -1000, i/o): bcm2835-i2s 000000003f204000-000000003f20401f (prio -1000, i/o): bcm2835-spi0 000000003f205000-000000003f20501f (prio -1000, i/o): bcm2835-i2c0 000000003f20f000-000000003f20f07f (prio -1000, i/o): bcm2835-otp 000000003f212000-000000003f212007 (prio 0, i/o): bcm2835-thermal 000000003f214000-000000003f2140ff (prio -1000, i/o): bcm2835-spis 000000003f215000-000000003f2150ff (prio 0, i/o): bcm2835-aux 000000003f300000-000000003f3000ff (prio 0, i/o): sdhci 000000003f600000-000000003f6000ff (prio -1000, i/o): bcm2835-smi 000000003f804000-000000003f80401f (prio -1000, i/o): bcm2835-i2c1 000000003f805000-000000003f80501f (prio -1000, i/o): bcm2835-i2c2 000000003f900000-000000003f907fff (prio -1000, i/o): bcm2835-dbus 000000003f910000-000000003f917fff (prio -1000, i/o): bcm2835-ave0 000000003f980000-000000003f980fff (prio -1000, i/o): dwc-usb2 000000003fe00000-000000003fe000ff (prio -1000, i/o): bcm2835-sdramc 000000003fe05000-000000003fe050ff (prio 0, i/o): bcm2835-dma-chan15 After: address-space: cpu-secure-memory-0 0000000000000000-00000000ffffffff (prio 0, i/o): cpu-bus 0000000000000000-000000003fffffff (prio 1, i/o): alias arm-ram-alias @ram 0000000000000000-000000003fffffff 000000003f000000-000000003fffffff (prio 2, i/o): alias arm-peripherals-alias @bcm2835-peripherals 0000000000000000-0000000000ffffff 0000000040000000-0000000040003fff (prio 2, i/o): alias arm-control-alias @bcm2836-control 0000000000000000-0000000000003fff address-space: cpu-memory-0 0000000000000000-00000000ffffffff (prio 0, i/o): cpu-bus 0000000000000000-000000003fffffff (prio 1, i/o): alias arm-ram-alias @ram 0000000000000000-000000003fffffff 000000003f000000-000000003fffffff (prio 2, i/o): alias arm-peripherals-alias @bcm2835-peripherals 0000000000000000-0000000000ffffff 0000000040000000-0000000040003fff (prio 2, i/o): alias arm-control-alias @bcm2836-control 0000000000000000-0000000000003fff memory-region: bcm2835-peripherals 0000000000000000-0000000000ffffff (prio 0, i/o): bcm2835-peripherals 0000000000003000-000000000000301f (prio 0, i/o): bcm2835-sys-timer 0000000000007000-0000000000007fff (prio 0, i/o): bcm2835-dma 000000000000b200-000000000000b3ff (prio 0, i/o): bcm2835-ic 000000000000b400-000000000000b43f (prio -1000, i/o): bcm2835-sp804 000000000000b800-000000000000bbff (prio 0, i/o): bcm2835-mbox 0000000000100000-0000000000100fff (prio -1000, i/o): bcm2835-cprman 0000000000102000-0000000000102fff (prio -1000, i/o): bcm2835-a2w 0000000000104000-000000000010400f (prio 0, i/o): bcm2835-rng 0000000000200000-0000000000200fff (prio 0, i/o): bcm2835_gpio 0000000000201000-0000000000201fff (prio 0, i/o): pl011 0000000000202000-0000000000202fff (prio 0, i/o): bcm2835-sdhost 0000000000203000-00000000002030ff (prio -1000, i/o): bcm2835-i2s 0000000000204000-000000000020401f (prio -1000, i/o): bcm2835-spi0 0000000000205000-000000000020501f (prio -1000, i/o): bcm2835-i2c0 000000000020f000-000000000020f07f (prio -1000, i/o): bcm2835-otp 0000000000212000-0000000000212007 (prio 0, i/o): bcm2835-thermal 0000000000214000-00000000002140ff (prio -1000, i/o): bcm2835-spis 0000000000215000-00000000002150ff (prio 0, i/o): bcm2835-aux 0000000000300000-00000000003000ff (prio 0, i/o): sdhci 0000000000600000-00000000006000ff (prio -1000, i/o): bcm2835-smi 0000000000804000-000000000080401f (prio -1000, i/o): bcm2835-i2c1 0000000000805000-000000000080501f (prio -1000, i/o): bcm2835-i2c2 0000000000900000-0000000000907fff (prio -1000, i/o): bcm2835-dbus 0000000000910000-0000000000917fff (prio -1000, i/o): bcm2835-ave0 0000000000980000-0000000000980fff (prio -1000, i/o): dwc-usb2 0000000000e00000-0000000000e000ff (prio -1000, i/o): bcm2835-sdramc 0000000000e05000-0000000000e050ff (prio 0, i/o): bcm2835-dma-chan15 Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 38 ++++++++++++++++++++++++++++++++------ hw/arm/raspi.c | 2 -- include/hw/arm/bcm2836.h | 8 +++++++- 3 files changed, 39 insertions(+), 9 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index d712f36052..36742af403 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -70,6 +70,8 @@ static void bcm2836_init(Object *obj) } for (n = 0; n < BCM283X_NCPUS; n++) { + memory_region_init(&s->cpu[n].container_mr, obj, "cpu-bus", 4 * GiB); + object_initialize_child(obj, "cpu[*]", &s->cpus[n], sizeof(s->cpus[n]), info->cpu_type, &error_abort, NULL); } @@ -90,7 +92,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) BCM283XState *s = BCM283X(dev); BCM283XClass *bc = BCM283X_GET_CLASS(dev); const BCM283XInfo *info = bc->info; - MemoryRegion *ram_mr, *peri_mr; + MemoryRegion *ram_mr, *peri_mr, *ctrl_mr; Object *obj; Error *err = NULL; int n; @@ -142,8 +144,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, - info->peri_base, 1); /* bcm2836 interrupt controller (and mailboxes, etc.) */ object_property_set_bool(OBJECT(&s->control), true, "realized", &err); @@ -151,15 +151,41 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } - - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); + ctrl_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->control), 0); for (n = 0; n < BCM283X_NCPUS; n++) { + memory_region_init_alias(&s->cpu[n].ram_mr_alias, OBJECT(s), + "arm-ram-alias", ram_mr, 0, + memory_region_size(ram_mr)); + memory_region_add_subregion_overlap(&s->cpu[n].container_mr, 0, + &s->cpu[n].ram_mr_alias, 1); + + memory_region_init_alias(&s->cpu[n].peri_mr_alias, OBJECT(s), + "arm-peripherals-alias", + peri_mr, 0, 16 * MiB); + memory_region_add_subregion_overlap(&s->cpu[n].container_mr, + info->peri_base, + &s->cpu[n].peri_mr_alias, 2); + + memory_region_init_alias(&s->cpu[n].control_mr_alias, OBJECT(s), + "arm-control-alias", ctrl_mr, + 0, 16 * KiB); + memory_region_add_subregion_overlap(&s->cpu[n].container_mr, + info->ctrl_base, + &s->cpu[n].control_mr_alias, 2); + + object_property_set_link(OBJECT(&s->cpus[n]), + OBJECT(&s->cpu[n].container_mr), + "memory", &err); + if (err) { + error_propagate(errp, err); + return; + } + /* TODO: this should be converted to a property of ARM_CPU */ s->cpus[n].mp_affinity = (info->clusterid << 8) | n; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 615d755879..a12459bc41 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -184,8 +184,6 @@ static void raspi_init(MachineState *machine, int version) /* Allocate and map RAM */ memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", machine->ram_size); - /* FIXME: Remove when we have custom CPU address space support */ - memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0); /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index a26bf895a4..af4c60dbad 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -37,9 +37,15 @@ typedef struct BCM283XState { struct { MemoryRegion mr[4]; - MemoryRegion peri_mr_alias; MemoryRegion ram_mr_alias; + MemoryRegion peri_mr_alias; } videocore; + struct { + MemoryRegion container_mr; + MemoryRegion ram_mr_alias; + MemoryRegion peri_mr_alias; + MemoryRegion control_mr_alias; + } cpu[BCM283X_NCPUS]; ARMCPU cpus[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; From patchwork Thu Oct 17 22:57:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C88141575 for ; Thu, 17 Oct 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 08/10] hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot Date: Fri, 18 Oct 2019 00:57:58 +0200 Message-Id: <20191017225800.6946-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" write_secondary_boot() is used in SMP configurations where the CPU address space might not be the main System Bus. The rom_add_blob_fixed_as() function allow us to specify an address space. Use it to write each boot blob in the corresponding CPU address space. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/raspi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a12459bc41..569d85c11a 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -60,12 +60,14 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 || (BOARDSETUP_ADDR >> 4) >= 0x100); - rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start); + rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start, + arm_boot_address_space(cpu, info)); } static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) { + AddressSpace *as = arm_boot_address_space(cpu, info); /* Unlike the AArch32 version we don't need to call the board setup hook. * The mechanism for doing the spin-table is also entirely different. * We must have four 64-bit fields at absolute addresses @@ -92,10 +94,10 @@ static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) 0, 0, 0, 0 }; - rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start); - rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), - SPINTABLE_ADDR); + rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start, as); + rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), + SPINTABLE_ADDR, as); } static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) From patchwork Thu Oct 17 22:57:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D76F912 for ; Thu, 17 Oct 2019 23:03:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2F0121D7A for ; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 09/10] hw/arm/raspi: Make the board code modular Date: Fri, 18 Oct 2019 00:57:59 +0200 Message-Id: <20191017225800.6946-10-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Our code currently create the raspi2 (based on the BCM2836) and the raspi3 (on the BCM2837). Similarly, the raspi4 is based on the BCM2838. To be able to add the new board, make the current code more modular: - Dynamically fills the 'board-rev' value - Allow DRAM sizes different than 1 GiB Rename the board model name as 'B' since this is the one encoded in the 'board-rev' tag. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/raspi.c | 107 +++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 94 insertions(+), 13 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 569d85c11a..7ccb6ceb4f 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "cpu.h" #include "hw/arm/bcm2836.h" @@ -29,8 +30,67 @@ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ -/* Table of Linux board IDs for different Pi versions */ -static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; +enum BoardIdManufacturer { + M_SONY_UK = 0, + M_EMBEST = 2, +}; + +enum BoardIdChip { + C_BCM2835 = 0, + C_BCM2836 = 1, + C_BCM2837 = 2, +}; + +enum BoardIdType { + T_2B = 0x04, + T_3B = 0x08, +}; + +enum BoardIdRevision { + R_1_0 = 0, + R_1_1 = 1, + R_1_2 = 2, + R_1_3 = 3, +}; + +static const char *processor_typename[] = { + [C_BCM2836] = TYPE_BCM2836, + [C_BCM2837] = TYPE_BCM2837, +}; + +typedef struct BoardInfo BoardInfo; + +struct BoardInfo { + /* Table of Linux board IDs for different Pi versions */ + int board_id; + /* + * Board revision codes: + * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ + */ + struct { + enum BoardIdType type; + enum BoardIdRevision revision; + enum BoardIdChip chip; + enum BoardIdManufacturer manufacturer; + } board_rev; + uint64_t ram_size_min; + uint64_t ram_size_max; +}; + +static const BoardInfo bcm283x_boards[] = { + [2] = { + .board_id = 0xc43, + .board_rev = { T_2B, R_1_1, C_BCM2836, M_EMBEST }, + .ram_size_min = 1 * GiB, + .ram_size_max = 1 * GiB, + }, + [3] = { + .board_id = 0xc44, + .board_rev = { T_3B, R_1_2, C_BCM2837, M_SONY_UK }, + .ram_size_min = 1 * GiB, + .ram_size_max = 1 * GiB, + }, +}; typedef struct RasPiState { BCM283XState soc; @@ -116,7 +176,7 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) static struct arm_boot_info binfo; int r; - binfo.board_id = raspi_boardid[version]; + binfo.board_id = bcm283x_boards[version].board_id; binfo.ram_size = ram_size; binfo.nb_cpus = machine->smp.cpus; @@ -148,7 +208,7 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) * the normal Linux boot process */ if (machine->firmware) { - hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2; + hwaddr firmware_addr = version >= 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2; /* load the firmware image (typically kernel.img) */ r = load_image_targphys(machine->firmware, firmware_addr, ram_size - firmware_addr); @@ -172,16 +232,32 @@ static void raspi_init(MachineState *machine, int version) BlockBackend *blk; BusState *bus; DeviceState *carddev; + char *size_str; + int board_rev; + const char *soc_type; - if (machine->ram_size > 1 * GiB) { + if (machine->ram_size < bcm283x_boards[version].ram_size_min) { + size_str = size_to_str(bcm283x_boards[version].ram_size_min); + error_report("Requested ram size is too small for this machine: " + "minimum is %s", size_str); + g_free(size_str); + exit(1); + } + if (machine->ram_size > bcm283x_boards[version].ram_size_max) { + size_str = size_to_str(bcm283x_boards[version].ram_size_max); error_report("Requested ram size is too large for this machine: " - "maximum is 1GB"); + "maximum is %s", size_str); + g_free(size_str); + exit(1); + } + if (!is_power_of_2(machine->ram_size)) { + error_report("Requested ram size is not a power of 2"); exit(1); } + soc_type = processor_typename[bcm283x_boards[version].board_rev.chip]; object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), - version == 3 ? TYPE_BCM2837 : TYPE_BCM2836, - &error_abort, NULL); + soc_type, &error_abort, NULL); /* Allocate and map RAM */ memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", @@ -192,9 +268,14 @@ static void raspi_init(MachineState *machine, int version) &error_abort); object_property_set_int(OBJECT(&s->soc), machine->smp.cpus, "enabled-cpus", &error_abort); - int board_rev = version == 3 ? 0xa02082 : 0xa21041; - object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", - &error_abort); + + board_rev = ((63 - clz64(machine->ram_size / MiB)) << 20) + | (bcm283x_boards[version].board_rev.manufacturer << 16) + | (bcm283x_boards[version].board_rev.chip << 12) + | (bcm283x_boards[version].board_rev.type << 4) + | (bcm283x_boards[version].board_rev.revision << 0); + object_property_set_int(OBJECT(&s->soc), board_rev, + "board-rev", &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); /* Create and plug in the SD cards */ @@ -221,7 +302,7 @@ static void raspi2_init(MachineState *machine) static void raspi2_machine_init(MachineClass *mc) { - mc->desc = "Raspberry Pi 2"; + mc->desc = "Raspberry Pi 2B"; mc->init = raspi2_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; @@ -243,7 +324,7 @@ static void raspi3_init(MachineState *machine) static void raspi3_machine_init(MachineClass *mc) { - mc->desc = "Raspberry Pi 3"; + mc->desc = "Raspberry Pi 3B"; mc->init = raspi3_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; From patchwork Thu Oct 17 22:58:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11197297 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6373112B for ; Thu, 17 Oct 2019 23:04:29 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BB49221D7A for ; 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[88.21.201.14]) by smtp.gmail.com with ESMTPSA id m18sm3993873wrg.97.2019.10.17.15.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 15:58:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 10/10] hw/arm/highbank: Use AddressSpace when using write_secondary_boot() Date: Fri, 18 Oct 2019 00:58:00 +0200 Message-Id: <20191017225800.6946-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017225800.6946-1-f4bug@amsat.org> References: <20191017225800.6946-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Andrew Baumann , Pekka Enberg , Esteban Bosse , qemu-arm@nongnu.org, Pete Batard , Cleber Rosa , Laurent Bonnans , Cheng Xiang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Clement Deschamps Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" write_secondary_boot() is used in SMP configurations where the CPU address space might not be the main System Bus. The rom_add_blob_fixed_as() function allow us to specify an address space. Use it to write each boot blob in the corresponding CPU address space. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/highbank.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index f1724d6929..518d935fdf 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -78,7 +78,8 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) for (n = 0; n < ARRAY_SIZE(smpboot); n++) { smpboot[n] = tswap32(smpboot[n]); } - rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); + rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR, + arm_boot_address_space(cpu, info)); } static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)