From patchwork Fri Oct 18 15:48:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DA20513BD for ; Fri, 18 Oct 2019 15:46:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BB1F4222C5 for ; Fri, 18 Oct 2019 15:46:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ja3KCBsQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393017AbfJRPqx (ORCPT ); Fri, 18 Oct 2019 11:46:53 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49648 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2409056AbfJRPqR (ORCPT ); Fri, 18 Oct 2019 11:46:17 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkFRe016636; Fri, 18 Oct 2019 10:46:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413575; bh=fdvxbJP1fRre9y4c+tbwQJftQoKadtVF8rlOsxXcNik=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ja3KCBsQ0+h1tbHlNTE5qWgDjVF9gChY6dglqXL/VLGEHdpFKb68UhArTS38Nf+zF QG3FKfRSrZ4BgzOGqhX8FGUlZS5mLeSvO9Kao3yHrvzEKIavkvXN8RbkMU3twULaWD cwLH4jvFPud8wNS0SuSqNPIw8/wPDu8i6Vrz3R/c= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkFg3109005 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:15 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:06 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:06 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAN045642; Fri, 18 Oct 2019 10:46:14 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 1/9] ARM: dts: dra7: add cam clkctrl node Date: Fri, 18 Oct 2019 10:48:41 -0500 Message-ID: <20191018154849.3127-2-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add clkctrl nodes for CAM domain. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 ++++++++++++++ drivers/clk/ti/clk-7xx.c | 19 +++++++++++++++++++ include/dt-bindings/clock/dra7.h | 10 ++++++++++ 3 files changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index d1c2406ec71c..199f8d483f75 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1734,6 +1734,20 @@ }; }; + cam_cm: cam-cm@1000 { + compatible = "ti,omap4-cm"; + reg = <0x1000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x100>; + + cam_clkctrl: cam-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x2c>; + #clock-cells = <2>; + }; + }; + dss_cm: dss-cm@1100 { compatible = "ti,omap4-cm"; reg = <0x1100 0x100>; diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 5dd9cad07542..8f2204a36b51 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -151,6 +151,24 @@ static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = { 0 }, }; +static const char * const dra7_cam_gfclk_mux_parents[] __initconst = { + "l3_iclk_div", + "core_iss_main_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = { + { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { 0 }, +}; + static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, @@ -783,6 +801,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { { 0x4a008c00, dra7_atl_clkctrl_regs }, { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, { 0x4a008e20, dra7_l3instr_clkctrl_regs }, + { 0x4a009020, dra7_cam_clkctrl_regs }, { 0x4a009120, dra7_dss_clkctrl_regs }, { 0x4a009320, dra7_l3init_clkctrl_regs }, { 0x4a0093b0, dra7_pcie_clkctrl_regs }, diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 2b765e579b2a..2c058a534bab 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -34,6 +34,11 @@ #define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) #define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) +/* vip clocks */ +#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) + /* coreaon clocks */ #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) @@ -202,6 +207,11 @@ #define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) #define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) +/* vip clocks */ +#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) + /* coreaon clocks */ #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) From patchwork Fri Oct 18 15:48:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1C6113BD for ; Fri, 18 Oct 2019 15:46:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C3EC1222C6 for ; Fri, 18 Oct 2019 15:46:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Co2TjTHR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502190AbfJRPqT (ORCPT ); Fri, 18 Oct 2019 11:46:19 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46284 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2409052AbfJRPqT (ORCPT ); Fri, 18 Oct 2019 11:46:19 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkGwU120233; Fri, 18 Oct 2019 10:46:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413576; bh=AhKW4zr3y6EnszWY1v1ZvsH1fjzX055dXtF+Ryq9cP0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Co2TjTHRd8/bgq3vBKC1prulo6lCzYTwmoOn3pBY+t411HX9AR5CiB/8TO21Ykrb0 EgdTRS3SOwFgTYx7uWhMTbISiJFBZnvJKfPHpSmwvQmlySFkD9L+r3iZb2+mgwWvSe g80qJ++lgEirJuYd3xQPsSiDzVSCj0vAy/MSG6gA= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkGlh109053 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:16 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:16 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:15 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAO045642; Fri, 18 Oct 2019 10:46:15 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 2/9] ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only Date: Fri, 18 Oct 2019 10:48:42 -0500 Message-ID: <20191018154849.3127-3-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Both CAL and VIP rely on this clock domain. But CAL DPHY require LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active. If only CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK is sourcing the input clock to the DPHY then actual frame capture cannot start as the phy are inactive. So we either have to also enabled VIP1 even if we don't intend on using it or we need to set the CAM domain to use SWSUP only. This patch implements the latter. Signed-off-by: Benoit Parrot --- arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index 3068802824b7..27835c4d1aa9 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = { .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, .wkdep_srcs = cam_wkup_sleep_deps, .sleepdep_srcs = cam_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4per_7xx_clkdm = { From patchwork Fri Oct 18 15:48:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198865 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59380112B for ; Fri, 18 Oct 2019 15:46:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3507A222C6 for ; Fri, 18 Oct 2019 15:46:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VflyZUvX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502263AbfJRPqV (ORCPT ); Fri, 18 Oct 2019 11:46:21 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49658 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2409069AbfJRPqU (ORCPT ); Fri, 18 Oct 2019 11:46:20 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkHkJ016648; Fri, 18 Oct 2019 10:46:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413577; bh=p5em5IRObfpcqp3l0KWyJiTGrR9ie7pRTYi/0m+Xung=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VflyZUvXhATlJZ6PQCSsRB2H7xJyQGp5f4d6CobnvxxxS12HbzjMe22SGv5fpAWy6 5fcabMFNCd8iH2DYssXQnSC1Dsr1ZrQxs3xZ0RVTQbhWEQBHv6JcFbMn1lNUlOHXmc Uswrzwx4PLoiKrwVjyfklZ6G7FPY+qCevF7cs43s= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkHjL128755; Fri, 18 Oct 2019 10:46:17 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:16 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:17 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAP045642; Fri, 18 Oct 2019 10:46:17 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 3/9] ARM: dts: dra7-l4: Add ti-sysc node for CAM Date: Fri, 18 Oct 2019 10:48:43 -0500 Message-ID: <20191018154849.3127-4-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add CAM nodes as a child of l4 interconnect in order for it to probe using ti-sysc. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra7-l4.dtsi | 43 +++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 0917231a20e2..8f5c26a4f7c8 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -4135,27 +4135,58 @@ }; target-module@170000 { /* 0x48970000, ap 21 0a.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x170010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x170000 0x10000>; + status = "disabled"; }; target-module@190000 { /* 0x48990000, ap 23 2e.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x190010 0x4>; + reg-names = "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x190000 0x10000>; + status = "disabled"; }; target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1b0000 0x10000>; + status = "disabled"; }; target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ From patchwork Fri Oct 18 15:48:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4496A19A1 for ; Fri, 18 Oct 2019 15:46:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 25DDE222C9 for ; Fri, 18 Oct 2019 15:46:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oRj+0dNd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404542AbfJRPqq (ORCPT ); Fri, 18 Oct 2019 11:46:46 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49666 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2502233AbfJRPqV (ORCPT ); Fri, 18 Oct 2019 11:46:21 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkIgX016653; Fri, 18 Oct 2019 10:46:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413578; bh=v8OG3LksgH1i+Pb5OuMPKQYp8bn+sVIBG+lclhVp8Ag=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oRj+0dNdqZgFmbLZhvNNHUKddMju3pnW3pBFLrybjkzLw/NgkDDOYclecIhJSHLbN c10HfEpR2efGYm2oub5UqCM6wTSY0oqMUodOANILSwXszzDDiqq2QGoleRiLaBSTbN OlfY9xNDd5Gc8SOZMNQXytQQPTLho2TFiaI3/WAY= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkIJP109094 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:18 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:10 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAQ045642; Fri, 18 Oct 2019 10:46:18 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 4/9] ARM: dts: DRA72: Add CAL dtsi node Date: Fri, 18 Oct 2019 10:48:44 -0500 Message-ID: <20191018154849.3127-5-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org This patch adds the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA72 family of devices. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra72x.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index f5762709c853..29d4c7664e90 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -17,6 +17,49 @@ }; }; +&l4_per2 { + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + cal: cal@0 { + compatible = "ti,dra72-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + syscon-camerrx = <&scm_conf 0xE94>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + &dss { reg = <0x58000000 0x80>, <0x58004054 0x4>, From patchwork Fri Oct 18 15:48:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 02785112B for ; Fri, 18 Oct 2019 15:46:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7095222C6 for ; Fri, 18 Oct 2019 15:46:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="lczfUGmA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505417AbfJRPqX (ORCPT ); Fri, 18 Oct 2019 11:46:23 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:42178 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2505411AbfJRPqW (ORCPT ); Fri, 18 Oct 2019 11:46:22 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkJsH005918; Fri, 18 Oct 2019 10:46:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413579; bh=BvksqVz6iTv8ZZ9PlGARstqOhVwtAPwo8nPnKMMEZfA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lczfUGmAen94j49AIBcT5QEgi9Q4uYtF8AQmt0+pbsLLnkZ+9Jq7YyZaw3mVIkmSY qANXPUTZC0Ez6R4akw+ZqmNLnlETWVvrGSPtZ9BMGZdWLlLhbE6ppWxBCsmph0Gzli DN5wuyTWSX/WOlKgllMfizlCVO6eBciQKx/yJFcM= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkJqF005477 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:19 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:19 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:11 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAR045642; Fri, 18 Oct 2019 10:46:19 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 5/9] arm: dts: dra72-evm-common: Add entries for the CSI2 cameras Date: Fri, 18 Oct 2019 10:48:45 -0500 Message-ID: <20191018154849.3127-6-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add device nodes for CSI2 camera board OV5640. Add the CAL port nodes with the necessary linkage to the ov5640 nodes. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra72-evm-common.dtsi | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 8641a3d7d8ad..e4c01a67f6de 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -187,6 +187,12 @@ gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + clk_ov5640_fixed: clk_ov5640_fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &dra7_pmx_core { @@ -269,6 +275,23 @@ line-name = "vin6_sel_s0"; }; }; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; &uart1 { @@ -580,3 +603,15 @@ &pcie1_rc { status = "okay"; }; + +&cal { + status = "okay"; +}; + +&csi2_0 { + csi2_phy0: endpoint@0 { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; From patchwork Fri Oct 18 15:48:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198861 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F3DE19A1 for ; Fri, 18 Oct 2019 15:46:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F33FC222C6 for ; Fri, 18 Oct 2019 15:46:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jtm+foWE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505518AbfJRPqX (ORCPT ); Fri, 18 Oct 2019 11:46:23 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:46292 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2502173AbfJRPqX (ORCPT ); Fri, 18 Oct 2019 11:46:23 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkKsi120244; Fri, 18 Oct 2019 10:46:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413581; bh=ZDPL8zVH5NOPzH0yuldAxkq1ggOBkCYu24TKtdoM4/s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jtm+foWEiIY9T+K1+XEaLqp56mZ4fXPEtYokCZL5330gXuk8Ytnllbyi29fzaExAu V6pSB6HcJaZ8zTnHtE6kJojVR/wp4eWvq7pc6dcGo9QwyAkyFc5i4SaFEvknJZYK1j 9oSWtwN16Eh50Gc/3j4NW96DsO1uEvRW3ODwtpOo= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkK5W103828 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:20 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:12 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:20 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAS045642; Fri, 18 Oct 2019 10:46:20 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 6/9] arm: dtsi: dra76x: Add CAL dtsi node Date: Fri, 18 Oct 2019 10:48:46 -0500 Message-ID: <20191018154849.3127-7-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA76 family of devices. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra76x.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index cdcba3f561c4..b6f7591bc590 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -41,6 +41,49 @@ }; +&l4_per3 { + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x1b0000 0x4>, + <0x1b0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + + cal: cal@0 { + compatible = "ti,dra76-cal"; + reg = <0x0000 0x400>, + <0x0800 0x40>, + <0x0900 0x40>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1"; + interrupts = ; + syscon-camerrx = <&scm_conf 0x6dc>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + /* MCAN interrupts are hard-wired to irqs 67, 68 */ &crossbar_mpu { ti,irqs-skip = <10 67 68 133 139 140>; From patchwork Fri Oct 18 15:48:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198859 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEDEF112B for ; Fri, 18 Oct 2019 15:46:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 90209222CD for ; Fri, 18 Oct 2019 15:46:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VCXN3DAz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389749AbfJRPqi (ORCPT ); Fri, 18 Oct 2019 11:46:38 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38454 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2505522AbfJRPqY (ORCPT ); Fri, 18 Oct 2019 11:46:24 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkMFo067405; Fri, 18 Oct 2019 10:46:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413582; bh=ijyNp0/kEYQZvQ4u+WUWGhUvE1sdXw4DDj4+j/JH998=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VCXN3DAzncda58LYtLvzEF7QK6rR+oOEusLK01siSwdjz3ABlVAEl/UhadkGoz9Dm yvRKLqEPWORE3wKLIn/B1nXWNToKclL1n6UmC4gz34CFbn2xXhcNFc00G51LvYnpcc +JfUMb7iCQ6NaOVPBCBaAw/QrkaGR/z3XJuI0Fcw= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkMMH005521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:22 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:13 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:13 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAT045642; Fri, 18 Oct 2019 10:46:21 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 7/9] arm: dts: dra76-evm: Add CAL and OV5640 nodes Date: Fri, 18 Oct 2019 10:48:47 -0500 Message-ID: <20191018154849.3127-8-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add device nodes for CSI2 camera board OV5640. Add the CAL port nodes with the necessary linkage to the ov5640 nodes. Signed-off-by: Benoit Parrot --- arch/arm/boot/dts/dra76-evm.dts | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 1fb6f13fb5e2..c9fdf62c68e9 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -116,6 +116,12 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + clk_ov5640_fixed: clk_ov5640_fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &i2c1 { @@ -317,6 +323,27 @@ }; }; +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + &cpu0 { vdd-supply = <&buck10_reg>; }; @@ -447,3 +474,15 @@ max-bitrate = <5000000>; }; }; + +&cal { + status = "okay"; +}; + +&csi2_0 { + csi2_phy0: endpoint@0 { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; From patchwork Fri Oct 18 15:48:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198855 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94D3013BD for ; Fri, 18 Oct 2019 15:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6926C222C6 for ; Fri, 18 Oct 2019 15:46:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YH/fdwR4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406133AbfJRPqc (ORCPT ); Fri, 18 Oct 2019 11:46:32 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38458 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2633634AbfJRPqZ (ORCPT ); Fri, 18 Oct 2019 11:46:25 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkNP9067413; Fri, 18 Oct 2019 10:46:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571413583; bh=tI7h4BaN3NlDalQrh/+Bi4yeNO3NNRokoBjlUSGTQw4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YH/fdwR4lKFtP9D3tTXDV8n1StOm/ATV8PBqAQDp029P+gwIwGMo1zePWx5PYuQXf n6MOASjN7vWZGO4z8Fz8uhId1q5p3XuEtLlw0Gn3jCDx4oGIF/dSynV68kxQ2Gpe47 IsqBaeP+TqVKlyz9hZyXnuGTobaZyGAT2QpGJQdQ= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9IFkNaS103886 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Oct 2019 10:46:23 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 18 Oct 2019 10:46:14 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 18 Oct 2019 10:46:14 -0500 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9IFkDAU045642; Fri, 18 Oct 2019 10:46:22 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 8/9] arm64: dts: k3-am65-main Add CAL node Date: Fri, 18 Oct 2019 10:48:48 -0500 Message-ID: <20191018154849.3127-9-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add CAL dtsi node for AM654 device. Including proper power-domains and clock properties. Signed-off-by: Benoit Parrot --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 799c75fa7981..9bd9a74d5e33 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -516,4 +516,27 @@ dma-coherent; interrupts = ; }; + + cal: cal@6f03000 { + compatible = "ti,am654-cal"; + reg = <0x0 0x06f03000 0x0 0x400>, + <0x0 0x06f03800 0x0 0x40>; + reg-names = "cal_top", + "cal_rx_core0"; + interrupts = ; + syscon-camerrx = <&scm_conf 0x40c0>; + clock-names = "fck"; + clocks = <&k3_clks 2 0>; + power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + }; + }; }; From patchwork Fri Oct 18 15:48:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 11198853 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D11913BD for ; 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Fri, 18 Oct 2019 10:46:24 -0500 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: Rob Herring , , , , Benoit Parrot Subject: [Patch 9/9] arm64: dts: k3-am654-base-board: Add CSI2 OV5640 camera Date: Fri, 18 Oct 2019 10:48:49 -0500 Message-ID: <20191018154849.3127-10-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018154849.3127-1-bparrot@ti.com> References: <20191018154849.3127-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add support for the OV5640 CSI camera: - add the OV5640 nodes - add the CAL node linkage - enable CAL node Signed-off-by: Benoit Parrot --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 1102b84f853d..918601c18f85 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -53,6 +53,12 @@ gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; }; }; + + clk_ov5640_fixed: clk_ov5640_fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &wkup_pmx0 { @@ -184,6 +190,23 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2_phy0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; &main_i2c2 { @@ -280,3 +303,16 @@ &pcie1_ep { status = "disabled"; }; + +&cal { + status = "okay"; +}; + +&csi2_0 { + csi2_phy0: endpoint@0 { + remote-endpoint = <&csi2_cam0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; +