From patchwork Tue Oct 22 17:00:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 11204915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC18E1575 for ; Tue, 22 Oct 2019 17:00:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 906A4214B2 for ; Tue, 22 Oct 2019 17:00:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="QdBmqosX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730363AbfJVRAo (ORCPT ); Tue, 22 Oct 2019 13:00:44 -0400 Received: from mail-eopbgr820087.outbound.protection.outlook.com ([40.107.82.87]:60952 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1732905AbfJVRAo (ORCPT ); Tue, 22 Oct 2019 13:00:44 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=O0WpUY4SLENRBcI9ONpTgIM71eOm3lvh/iC/L/+w6MP6lOiiVZJw89gAHX8G0K1anaxzUFNqPoR/2VLtlnYdcTTVGv2/eWNSsz4mizm4rp6StF1cu5DbaqW/kiIauMIwGTFemy2O9nRAGDkJ1P57v5dwcP8GL0rXZhJFiYPkt4fJTW5zlCLMyAtWwttaWOTOnd7q/Xx0fREc4MfMtPgd+Z+91u983SyS/wctj6qKN9sU4U8FpWq5IGLp70Luic+0zCBrIgBbuLDSP79y2ZgD23bSq6WbOeIusZw2XUY/fZ4qchhijrec1VPtJsdckdQvh5jpyHcK9qQDS0FUOTNAIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OdyptbvHTltRINYT9OFsVx3Oe4pKWTXX/58ZkW6H2Vk=; b=BiWzahQ3NDjOnJMVm6dqkR3nRdlnApN3BVCDm40lttfTC8WcOf22V6hBERQCGTSaHTxuQS/ZY4+kzOKwOy9oSc8vCpm8kntoeRJLRSN13D/th3axU37NqPbYqvGMzFoaAF3KF3yndnNtgvkUOFja4M3E0de0Zb4dpTcbWwOGtyBEZBX2F68lSRHlKOkS17OU2DYQCOZTGx8GngtGsX2xQROKh4HqKECgt1UtnUxOrAnozQSIrEA5Qa3ssGHoAc4mI0MVZGLINFdSNkIQxK/LbVuu4XUc/r4/yPzb+19fmlUqK9MFeshH9lClTeTRPFYRdNn1Yjcw3riMt4HzwL2rXg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OdyptbvHTltRINYT9OFsVx3Oe4pKWTXX/58ZkW6H2Vk=; b=QdBmqosXnCfZYuzRawGfYGn3mEn9j/laNtJPfrM5A16ezRC4jkHcK3MKb0W5NDdWqKxUSfgLDREIR4Y8qLwPaVZe7eez6UHjPoalAsvxHYXuGBlm2HRyYMSMa5c6VOVNZtd8DyUem2Zkruzjs9Cnpjt1RMIWnhkaVDkKoRzQZW8= Received: from MN2PR02CA0010.namprd02.prod.outlook.com (2603:10b6:208:fc::23) by DM6PR02MB6377.namprd02.prod.outlook.com (2603:10b6:5:1d6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2367.24; Tue, 22 Oct 2019 17:00:41 +0000 Received: from CY1NAM02FT036.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e45::204) by MN2PR02CA0010.outlook.office365.com (2603:10b6:208:fc::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2367.20 via Frontend Transport; Tue, 22 Oct 2019 17:00:41 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT036.mail.protection.outlook.com (10.152.75.124) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2367.14 via Frontend Transport; Tue, 22 Oct 2019 17:00:40 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWS-0006Al-4B; Tue, 22 Oct 2019 10:00:40 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp2.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWM-0005DH-S1; Tue, 22 Oct 2019 10:00:34 -0700 Received: from xsj-pvapsmtp01 (smtp-fallback.xilinx.com [149.199.38.66] (may be forged)) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0WZR030509; Tue, 22 Oct 2019 10:00:32 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWJ-00059Z-I4; Tue, 22 Oct 2019 10:00:31 -0700 Received: by ubuntu (Postfix, from userid 13245) id C26F510112A; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 1/6] dt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support Date: Tue, 22 Oct 2019 22:30:17 +0530 Message-Id: <1571763622-29281-2-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--2.613-7.0-31-1 X-imss-scan-details: No--2.613-7.0-31-1;No--2.613-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(346002)(136003)(376002)(189003)(199004)(107886003)(26005)(76176011)(51416003)(6266002)(14444005)(7416002)(305945005)(48376002)(2906002)(4326008)(5660300002)(36756003)(81156014)(8936002)(81166006)(50466002)(8676002)(50226002)(47776003)(106002)(42186006)(446003)(336012)(6666004)(356004)(478600001)(70586007)(186003)(11346002)(486006)(126002)(476003)(2616005)(426003)(16586007)(103686004)(70206006)(316002)(921003)(42866002)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB6377;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fd846e4f-937c-4dbb-6047-08d757115e96 X-MS-TrafficTypeDiagnostic: DM6PR02MB6377: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F5n63usNrYXjfAqdchaP2QBSPHqe+G4x+0YS1YfQbJj8rGwu62csBi0J0+/TcVLRMtMq1sYdVoH6O0muy0g0XG0RfHTnK5YfE3gSaHa7r8qN4ndTwCNbvfTLSvYX3OpEgMK7u2+g2ZcbTkMYQtMl9tl/nhb8ymtkYfDCiO9LQvmBW9hasiI4jTel3YV6Tt4Nmyv0dlRMWZv3VXulw/Bi5woXn4ME1rB7Bo4uyr5BaKkOZYIFAcD1Qdqzm7pmspul7moOFPCtMCptSqjBu+YbJu0queJS9oYlNLgwmnQihJzC/IX+X5m9kF5YSRGmoOp04Mhqt/HPIwSxDcuADt0ewO4eam2AqlOyRrPj0+OtU06H5wC7UPv2lVDukmXF8ofgg0BMN1rhOuqfvA68eksCHo+zwVyrJxhetNw9Mmpg6O7kv/quP3BDbg/2oFDwEawk X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:40.7757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd846e4f-937c-4dbb-6047-08d757115e96 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6377 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver(added in the subsequent commits). Inline with it remove axidma multichannel optional properties i.e xlnx,mcdma and dma-channels from the binding description. Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring --- Changes since RFC: New patch. --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 93b6d96..99d06f9 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -42,7 +42,6 @@ Optional properties for AXI DMA: register as configured in h/w. Takes values {8...26}. If the property is missing or invalid then the default value 23 is used. This is the maximum value that is supported by all IP versions. -- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: @@ -69,8 +68,6 @@ Optional child node properties for VDMA: enabled/disabled in hardware. - xlnx,enable-vert-flip: Tells vertical flip is enabled/disabled in hardware(S2MM path). -Optional child node properties for AXI DMA: --dma-channels: Number of dma channels in child node. Example: ++++++++ From patchwork Tue Oct 22 17:00:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 11204913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 42E831390 for ; Tue, 22 Oct 2019 17:00:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0DAC321783 for ; Tue, 22 Oct 2019 17:00:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="IzmdYdhL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732975AbfJVRAn (ORCPT ); Tue, 22 Oct 2019 13:00:43 -0400 Received: from mail-eopbgr730089.outbound.protection.outlook.com ([40.107.73.89]:18334 "EHLO NAM05-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730363AbfJVRAn (ORCPT ); Tue, 22 Oct 2019 13:00:43 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aBlZtfNwPEGQN4/wRpv8wU0tngcoVhNG85XjK70Toyj38ydwxtjBTTB3/TCJshiULKF7NdB1pbAFesMSc91CSQ3zzfL61er0BBihDN7HGH/IRtCE7tRLXBWX4yZRJnBiWFDhP6B9+RwLzevgp9YFOHRhfT/0cmeAVnmvzWVyniBGuPBWzhgPstj3pFQ/nMJ3/ee3ggbHJ8pGMiVHuAhKZEqoXBzzJqR9GmwkWCuhbwOCK53Gq+0RmmH8pWbjyLENVhfBNgWGUzC79Y6kB7MBw0VvOxzZ9OEKRVL/z/WrLuaWO12XKy2utRGvbn1wVUs5o9WDctChVoZXhZdX1sVtBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZZe1J+kjAxace7Y02lfa3AlwKrWulwj4LpqjO5RicqE=; b=UqUQoB9oo1mErJDvyC95UibPzKQdMbm5NCYW/FZlkAKKuc0BvK8s9IYlm9VnDtGvvTwFM58a6p8r2R1cUKZ4InT+ZCLyx9mmuVpVrvll7TcZKLuXWCbysL4XGy7E/OHCM1si0nA4BvXV9G5uKwyK5piE+N8CGRvwn0cn5lSU4euZpAoihT4oFbiV3MnQ+wtrz17bEKblE4FekCP+ggnetID0oS9jJrOg7GxdVdtT+sRDrlne2a00XUIpbxY7GmltCKyopQyC3EgezjEVZEEyJ1zqf8JZpFykVtLMknXgMhNYSfCF1EcQ7OCiI2Fn04kGwxXkZhLy2waVid+u+InCXQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZZe1J+kjAxace7Y02lfa3AlwKrWulwj4LpqjO5RicqE=; b=IzmdYdhLjnaNK1KUHfMdx63eZGYxgUPid1/QbIb0uje1dcQW6p75LGeJzeFxU9SUQuVIKc19bjIVxTcam7TFHv55s+ZPhRP/Q7+1NtnA9dg8XwFbN5i0kQlUzeGu7Bb5+MMcWq07TmWys03X599MJvZbJpoMw44Sm61omtL0iDU= Received: from BN7PR02CA0004.namprd02.prod.outlook.com (2603:10b6:408:20::17) by DM6PR02MB6236.namprd02.prod.outlook.com (2603:10b6:5:1d1::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.16; Tue, 22 Oct 2019 17:00:39 +0000 Received: from SN1NAM02FT017.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::201) by BN7PR02CA0004.outlook.office365.com (2603:10b6:408:20::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.23 via Frontend Transport; Tue, 22 Oct 2019 17:00:39 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT017.mail.protection.outlook.com (10.152.72.115) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2367.14 via Frontend Transport; Tue, 22 Oct 2019 17:00:39 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWQ-0006Aj-So; Tue, 22 Oct 2019 10:00:38 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp1.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWL-0005CE-L5; Tue, 22 Oct 2019 10:00:33 -0700 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0Wac022056; Tue, 22 Oct 2019 10:00:32 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWJ-00059c-IY; Tue, 22 Oct 2019 10:00:31 -0700 Received: by ubuntu (Postfix, from userid 13245) id C537710112C; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 2/6] dt-bindings: dmaengine: xilinx_dma: Fix formatting and style Date: Tue, 22 Oct 2019 22:30:18 +0530 Message-Id: <1571763622-29281-3-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--5.034-7.0-31-1 X-imss-scan-details: No--5.034-7.0-31-1;No--5.034-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(346002)(136003)(39860400002)(396003)(189003)(199004)(486006)(336012)(26005)(51416003)(8676002)(11346002)(305945005)(107886003)(76176011)(446003)(6266002)(426003)(16586007)(106002)(8936002)(5660300002)(36756003)(4326008)(316002)(50226002)(2906002)(186003)(42186006)(81166006)(81156014)(47776003)(6666004)(48376002)(7416002)(476003)(356004)(50466002)(2616005)(70206006)(70586007)(126002)(478600001)(103686004)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB6236;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4a0f761e-4245-4a11-35ea-08d757115db2 X-MS-TrafficTypeDiagnostic: DM6PR02MB6236: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:549; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hVaasdJe+W7FycCy51iUGGTJnB9Xrinm9H/4UUKFK1ARaVG9zfQsHahVwHAIYgumexXwUuA6wAYBrkeXbOuw1jnT3eL/bJsgPNupJe2tlJePvsiLnHkC4QrC50i7pEqnWu1/V0w68Ke/IJFrqnoSQa1su6WiFgx4GzJOxusFYd37qxq4rNODKHMydWiwcxpLYuwNEXFRd+9eOZL0dqKFLsqTi6CBG14GyE7SX447VXdanfMa9UWQlosMUfkpvbPIi23kmeIw0u1HETRVJxJ6jORQAt5lXzmdwJyXZ5BzjPUd2HiwZYc+vofd2DFujSpUXg1xc4hcNL53ZUIOi9YMtBCOrK+qpI1Ei+Pma5jrnUtumKRwv/bPoWnwBnPZZMstQrkh5BrMgEnh+vBAx2pSVOsUWppZGC74Oldw0Kbx7h8smUptEqTZqMU4Ks25RlSm X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:39.3104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a0f761e-4245-4a11-35ea-08d757115db2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6236 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Trivial formatting(keep compatible string one per line, caps change etc). It doesn't modify the content of the binding. Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring --- Changes since RFC: New patch. Trivial formatting (compatible string one per line) as suggested by Rob in MCDMA RFC series. --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 99d06f9..d4ba1cb 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -12,8 +12,10 @@ Xilinx AXI CDMA engine, it does transfers between memory-mapped source address and a memory-mapped destination address. Required properties: -- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or - "xlnx,axi-cdma-1.00.a"" +- compatible: Should be one of- + "xlnx,axi-vdma-1.00.a" + "xlnx,axi-dma-1.00.a" + "xlnx,axi-cdma-1.00.a" - #dma-cells: Should be <1>, see "dmas" property below - reg: Should contain VDMA registers location and length. - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). @@ -29,7 +31,7 @@ Required properties: "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" For CDMA: Required elements: "s_axi_lite_aclk", "m_axi_aclk" - FOR AXIDMA: + For AXIDMA: Required elements: "s_axi_lite_aclk" Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk" From patchwork Tue Oct 22 17:00:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 11204925 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5E1C1575 for ; Tue, 22 Oct 2019 17:01:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9A127218AE for ; Tue, 22 Oct 2019 17:01:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="GKybovS1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730720AbfJVRBC (ORCPT ); Tue, 22 Oct 2019 13:01:02 -0400 Received: from mail-eopbgr780059.outbound.protection.outlook.com ([40.107.78.59]:60858 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1732886AbfJVRAn (ORCPT ); Tue, 22 Oct 2019 13:00:43 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jx071NEhWr3UJA7tlODqD7P30MvTDZHQgU4D1fY5vDxZtd8KuyNtx87WjLgjxyanG2FXF7UA6eLJ/Fv26NzQg4oLLYpUE2skikJeARprUgHhj1JZ3tbODTTTRP9WwSEFqHLGnGCR5hzldtfFu8KZMdiZGTRow7qC9ZxMUB+e1c9FJz+JRHDssB60S5F6q/8ruNtdi9dj9sUqCXFVMT7F6T//XLrKH0DERecoSs7kik/Ah8cPh2C3FcKRbv190+XzgK4BbEk6redfkt/uqQi8+AufFMyKju5jA+IzwjSLGwkzEXC3NUOlXvCvmeYXsCTOcJJRpNpvj0/JCfXDE7Y6Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ed3I5BZoPRoKWOYjFKhAI5bg7DDua/eE03WhPAIGYrM=; b=dnNvYxsh5lQ9PTMDTNw0ovkLMfrLgWbVaRbOPDH4IMAy8yXb1fkfa3tAsQHBjPnYCMcboOr/1oMVe1VD9BfvComAoecFoHTTCoZN6QYTqAHlgSf4BZrBt7oBTQ2NTDUmOP5tLGwAQqKoFYv7NsN/7R2zkeQVCq7P1HRYS+2d7+kNXLQCM8AWPeHvv1iSanFjClt4Ju49I5H+s6Er2IPMbtwWHY5IavB5EOudoO0OafpKF8sonidw8WhXgFGRZNkH7SCJUZj+W8HUxaKpntwksyaVmNFHO6WGCjlAfv0ShD5XSWp1TFpOSoVSBs7n+zBDS6mYvTk2+xlteq6DgCNc7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ed3I5BZoPRoKWOYjFKhAI5bg7DDua/eE03WhPAIGYrM=; b=GKybovS15aRJD7lFoPv2rim6eNa3YMfpuR7rprFnVRg6s3Mdomdf8vTd8fiD6jALdHP0hYqmiepMuuXJYCqyuD6PuJ4Yc5mjuhY7N5MYigLL9hdy8yL8F16rIom7YWRQwnPR4WVDusL/ZR++FdF1DI/pq9Up5khpyXNgZL0qYkk= Received: from BN7PR02CA0014.namprd02.prod.outlook.com (2603:10b6:408:20::27) by SN4PR0201MB3614.namprd02.prod.outlook.com (2603:10b6:803:46::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.19; Tue, 22 Oct 2019 17:00:41 +0000 Received: from SN1NAM02FT038.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::200) by BN7PR02CA0014.outlook.office365.com (2603:10b6:408:20::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.21 via Frontend Transport; Tue, 22 Oct 2019 17:00:40 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT038.mail.protection.outlook.com (10.152.72.69) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2367.14 via Frontend Transport; Tue, 22 Oct 2019 17:00:40 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWS-0006Ak-0y; Tue, 22 Oct 2019 10:00:40 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp2.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWM-0005D8-OM; Tue, 22 Oct 2019 10:00:34 -0700 Received: from xsj-pvapsmtp01 (mailhub.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0Wo4030513; Tue, 22 Oct 2019 10:00:32 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWJ-00059f-JZ; Tue, 22 Oct 2019 10:00:31 -0700 Received: by ubuntu (Postfix, from userid 13245) id CDE1410112E; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 3/6] dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP Date: Tue, 22 Oct 2019 22:30:19 +0530 Message-Id: <1571763622-29281-4-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--2.053-7.0-31-1 X-imss-scan-details: No--2.053-7.0-31-1;No--2.053-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(39860400002)(136003)(346002)(396003)(189003)(199004)(478600001)(81156014)(186003)(81166006)(8676002)(26005)(2616005)(6266002)(126002)(446003)(107886003)(11346002)(476003)(4326008)(316002)(50466002)(2906002)(16586007)(42186006)(50226002)(106002)(8936002)(36756003)(70586007)(70206006)(6666004)(356004)(76176011)(48376002)(103686004)(14444005)(47776003)(426003)(486006)(305945005)(7416002)(336012)(5660300002)(51416003)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN4PR0201MB3614;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6ea22e8d-3a24-4563-53d8-08d757115e6c X-MS-TrafficTypeDiagnostic: SN4PR0201MB3614: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1775; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v7eAm6BwoA0HZ1h1AAPgAVSIXvErRJHo0OGJjQK59Nyo9EmPX0p1FZTZ7+ZvcvSFhlRBFArLoB+O8XNvovDVmI3yVbDr0r96q6c/LR3cv+26wngxBlinHd5XWRxTUxLqHeXtZg3rq4oz2HoMOSV24si9vulLB4v3VJ4Q7pnr0FPgRF8Mq0jPJBr6nyLfJn4z6eFy0On00akZ6cAWtR06jM8k9Tn3P/7dMV9niDMFrnj2tQJrmdznGpO4t4nhm2gyu78Yx3hgkolD0fAfvotzrFrWWfZEPIXni9trCDTvsVvHYWHOqUDSdpNd8zynEMANEkYlQY+fQveDBFlXc/T1HmHqXazhXjk657UhvXJ6WlriJOYWO3AGSzWU4oi2JPNZ18mxaB94v4ZOfcCjdZlTeNgRovdcvS4lSsS3C1HouRFKfl7jjkTuj0prbYz0JhvV X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:40.4911 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ea22e8d-3a24-4563-53d8-08d757115e6c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0201MB3614 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access (AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides a scatter-gather interface with multiple channel support with independent configuration. Signed-off-by: Radhey Shyam Pandey Reviewed-by: Rob Herring --- Keep compatible string one per line. Suggested by Rob. Reuse the existing xlnx,axi-dma-* channel names. Suggested by Rob. --- .../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index d4ba1cb..325aca5 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -11,11 +11,16 @@ is to receive from the device. Xilinx AXI CDMA engine, it does transfers between memory-mapped source address and a memory-mapped destination address. +Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream +target devices. It can be configured to have up to 16 independent transmit +and receive channels. + Required properties: - compatible: Should be one of- "xlnx,axi-vdma-1.00.a" "xlnx,axi-dma-1.00.a" "xlnx,axi-cdma-1.00.a" + "xlnx,axi-mcdma-1.00.a" - #dma-cells: Should be <1>, see "dmas" property below - reg: Should contain VDMA registers location and length. - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). @@ -31,7 +36,7 @@ Required properties: "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" For CDMA: Required elements: "s_axi_lite_aclk", "m_axi_aclk" - For AXIDMA: + For AXIDMA and MCDMA: Required elements: "s_axi_lite_aclk" Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk" @@ -39,7 +44,7 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. -Optional properties for AXI DMA: +Optional properties for AXI DMA and MCDMA: - xlnx,sg-length-width: Should be set to the width in bits of the length register as configured in h/w. Takes values {8...26}. If the property is missing or invalid then the default value 23 is used. This is the @@ -56,8 +61,8 @@ Required child node properties: For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel". For CDMA: It should be "xlnx,axi-cdma-channel". - For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or - "xlnx,axi-dma-s2mm-channel". + For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" + or "xlnx,axi-dma-s2mm-channel". - interrupts: Should contain per channel VDMA interrupts. - xlnx,datawidth: Should contain the stream data width, take values {32,64...1024}. @@ -70,6 +75,8 @@ Optional child node properties for VDMA: enabled/disabled in hardware. - xlnx,enable-vert-flip: Tells vertical flip is enabled/disabled in hardware(S2MM path). +Optional child node properties for MCDMA: +- dma-channels: Number of dma channels in child node. Example: ++++++++ From patchwork Tue Oct 22 17:00:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 11204919 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 24D731390 for ; Tue, 22 Oct 2019 17:00:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D966C20684 for ; Tue, 22 Oct 2019 17:00:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="mmwQ4HHe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733016AbfJVRAu (ORCPT ); Tue, 22 Oct 2019 13:00:50 -0400 Received: from mail-eopbgr740080.outbound.protection.outlook.com ([40.107.74.80]:35018 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1732905AbfJVRAt (ORCPT ); Tue, 22 Oct 2019 13:00:49 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f1V4ro69sbx9bfcqXMtYOrsG6bBfwIVVcINP4v1aU6YAshe3CDYIZ0oQm0LedyHt78+g6QqWSP7UuqtKh02R9UP5jIdFcyufT1Dt2E2zwUEH3hfPxGQCcK3eY1tcQr+rdVhCsgB10s9U5inpWWpwrik+uHcFX8Mwt8nE1mOeaKKIhO+h84FdLq0WbvwfP3eeLNvGarM/cB0iXNQUSKty6RbFzJuuRXOs/rneKrrzq0V/V9qoahnazZD2prAKWgse6nELWSrQU60c5AWxW4kNxTrWL+yXSnteJlBsJOr8Ok2QGb5Bl43IudNbdb4SqvYH4EXIwTNXx4X0SYBfKu3CwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=STPhDd0jQgFVB0lgoRg+PmMuNGbpy8LPMhupL0SpIik=; b=NkmSNQqvlzNSCufS2PWI6/GxzrkyGNrP7R7lvlSuN/zh3WDAKuUIuEBax5RXseJLP+/5tVw4JtIIfV4iY+m8gutgLLKXwxBq58JtXmwRdoPkB9e4Fzs16QJCX7TScDwDAOnuug3Tpop5TiSgtz2kSlHtYbK97Pxe80niEgddo2Lo9ymtYt1s1Rg3JW2Hy7OX+fObN6HV3WhCpwYcUAbodQkNoCxlOCqjoX1TUbIrfG4tybVX2SkQFFrxBoLtgLZ7T4TLPzpSX1Dq88bmeQA2ItEfoB+F+B5aEuW69AW18b8/IU3Q8u+f/kUqtWBl81HEK+xvo/PbqyO3YRtCOlUSHw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=STPhDd0jQgFVB0lgoRg+PmMuNGbpy8LPMhupL0SpIik=; b=mmwQ4HHeTY2QkhS1wz6Qt9K2qhy5QjNQPyqKjuD98yylDII8hEd2sZmXqlssWONXTUBGsS9mgaNRqUb4V5IcMT/c40ePC3iRke54tWBPjD3WunJ7WWOB2QKvNzkvF1lABbEbuOmlqrXDGlU+/ZR3Ranl8hHNLoIG6qKywkYUXy8= Received: from DM6PR02CA0088.namprd02.prod.outlook.com (2603:10b6:5:1f4::29) by DM6PR02MB5163.namprd02.prod.outlook.com (2603:10b6:5:51::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2347.17; Tue, 22 Oct 2019 17:00:42 +0000 Received: from SN1NAM02FT014.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::208) by DM6PR02CA0088.outlook.office365.com (2603:10b6:5:1f4::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2367.21 via Frontend Transport; Tue, 22 Oct 2019 17:00:42 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT014.mail.protection.outlook.com (10.152.72.106) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2367.14 via Frontend Transport; Tue, 22 Oct 2019 17:00:41 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWT-0006An-Gk; Tue, 22 Oct 2019 10:00:41 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp1.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWO-0005Eb-8S; Tue, 22 Oct 2019 10:00:36 -0700 Received: from xsj-pvapsmtp01 (xsj-pvapsmtp01.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0W9A022062; Tue, 22 Oct 2019 10:00:33 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWJ-00059l-KQ; Tue, 22 Oct 2019 10:00:32 -0700 Received: by ubuntu (Postfix, from userid 13245) id D455B101130; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 4/6] dmaengine: xilinx_dma: Remove axidma multichannel mode support Date: Tue, 22 Oct 2019 22:30:20 +0530 Message-Id: <1571763622-29281-5-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--4.138-7.0-31-1 X-imss-scan-details: No--4.138-7.0-31-1;No--4.138-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(396003)(376002)(136003)(346002)(39860400002)(189003)(199004)(47776003)(50226002)(478600001)(2906002)(48376002)(50466002)(8936002)(103686004)(6266002)(107886003)(356004)(7416002)(106002)(16586007)(486006)(70206006)(42186006)(316002)(336012)(5660300002)(81156014)(305945005)(14444005)(6666004)(36756003)(186003)(51416003)(426003)(26005)(70586007)(11346002)(76176011)(476003)(4326008)(81166006)(2616005)(8676002)(446003)(126002)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB5163;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a455a5fa-fcd4-4e38-e5f7-08d757115f4c X-MS-TrafficTypeDiagnostic: DM6PR02MB5163: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2043; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SyB+nnOQY/5VkwwdENdf7M/F8JmhhWfVufKU2WmEaJxIxll2SNZJy1AD5XETytoIl9WCZBl8XicB7XV9h/qiq75UoL01kONlMFCOr16sU/yAMyrfzO+p7E1wP+KdEhCbU9YOKPKt5aiMo/AqKqbMjHKQ5Ji9NhUmKXntoVTi6TffTXFN31cUykYzYFr0HoOGoiRTp+OV/U9AdB1zNrsYMGIpo0Oc85IoZcZZop4zNyidSHfsZ6xFGVjxIgbdlHGICm+T91oKtez3NDz708bGY2eJ6DpACM0BwWbcqnuGKvQmzHgYoDKdjx9nQ40Oa427/mCTf5qRG6P03YGyPX5lSjzFdE4YE98XSvJThlEgyZaJlKG49rCep/xElpBRA2Oez89MT+Kq0gSlAayW5EkDoCGy/4coxewwlMAQU9Rkzr8= X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:41.9298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a455a5fa-fcd4-4e38-e5f7-08d757115f4c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5163 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver. So inline with it remove axidma multichannel support from from the driver. Signed-off-by: Radhey Shyam Pandey --- Changes since RFC: New patch. --- drivers/dma/xilinx/xilinx_dma.c | 155 +++------------------------------------- 1 file changed, 8 insertions(+), 147 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 41189b6..6d45865 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -116,7 +116,7 @@ #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) /* HW specific definitions */ -#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20 +#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ @@ -170,18 +170,6 @@ #define XILINX_DMA_NUM_DESCS 255 #define XILINX_DMA_NUM_APP_WORDS 5 -/* Multi-Channel DMA Descriptor offsets*/ -#define XILINX_DMA_MCRX_CDESC(x) (0x40 + (x-1) * 0x20) -#define XILINX_DMA_MCRX_TDESC(x) (0x48 + (x-1) * 0x20) - -/* Multi-Channel DMA Masks/Shifts */ -#define XILINX_DMA_BD_HSIZE_MASK GENMASK(15, 0) -#define XILINX_DMA_BD_STRIDE_MASK GENMASK(15, 0) -#define XILINX_DMA_BD_VSIZE_MASK GENMASK(31, 19) -#define XILINX_DMA_BD_TDEST_MASK GENMASK(4, 0) -#define XILINX_DMA_BD_STRIDE_SHIFT 0 -#define XILINX_DMA_BD_VSIZE_SHIFT 19 - /* AXI CDMA Specific Registers/Offsets */ #define XILINX_CDMA_REG_SRCADDR 0x18 #define XILINX_CDMA_REG_DSTADDR 0x20 @@ -218,8 +206,8 @@ struct xilinx_vdma_desc_hw { * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 * @buf_addr: Buffer address @0x08 * @buf_addr_msb: MSB of Buffer address @0x0C - * @mcdma_control: Control field for mcdma @0x10 - * @vsize_stride: Vsize and Stride field for mcdma @0x14 + * @reserved1: Reserved @0x10 + * @reserved2: Reserved @0x14 * @control: Control field @0x18 * @status: Status field @0x1C * @app: APP Fields @0x20 - 0x30 @@ -229,8 +217,8 @@ struct xilinx_axidma_desc_hw { u32 next_desc_msb; u32 buf_addr; u32 buf_addr_msb; - u32 mcdma_control; - u32 vsize_stride; + u32 reserved1; + u32 reserved2; u32 control; u32 status; u32 app[XILINX_DMA_NUM_APP_WORDS]; @@ -346,7 +334,6 @@ struct xilinx_dma_tx_descriptor { * @cyclic_seg_p: Physical allocated segments base for cyclic dma * @start_transfer: Differentiate b/w DMA IP's transfer * @stop_transfer: Differentiate b/w DMA IP's quiesce - * @tdest: TDEST value for mcdma * @has_vflip: S2MM vertical flip */ struct xilinx_dma_chan { @@ -382,7 +369,6 @@ struct xilinx_dma_chan { dma_addr_t cyclic_seg_p; void (*start_transfer)(struct xilinx_dma_chan *chan); int (*stop_transfer)(struct xilinx_dma_chan *chan); - u16 tdest; bool has_vflip; }; @@ -413,7 +399,6 @@ struct xilinx_dma_config { * @dev: Device Structure * @common: DMA device structure * @chan: Driver specific DMA channel - * @mcdma: Specifies whether Multi-Channel is present or not * @flush_on_fsync: Flush on frame sync * @ext_addr: Indicates 64 bit addressing is supported by dma device * @pdev: Platform device structure pointer @@ -432,7 +417,6 @@ struct xilinx_dma_device { struct device *dev; struct dma_device common; struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE]; - bool mcdma; u32 flush_on_fsync; bool ext_addr; struct platform_device *pdev; @@ -1344,53 +1328,23 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } - if (chan->has_sg && !chan->xdev->mcdma) + if (chan->has_sg) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); - if (chan->has_sg && chan->xdev->mcdma) { - if (chan->direction == DMA_MEM_TO_DEV) { - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - head_desc->async_tx.phys); - } else { - if (!chan->tdest) { - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - head_desc->async_tx.phys); - } else { - dma_ctrl_write(chan, - XILINX_DMA_MCRX_CDESC(chan->tdest), - head_desc->async_tx.phys); - } - } - } - xilinx_dma_start(chan); if (chan->err) return; /* Start the transfer */ - if (chan->has_sg && !chan->xdev->mcdma) { + if (chan->has_sg) { if (chan->cyclic) xilinx_write(chan, XILINX_DMA_REG_TAILDESC, chan->cyclic_seg_v->phys); else xilinx_write(chan, XILINX_DMA_REG_TAILDESC, tail_segment->phys); - } else if (chan->has_sg && chan->xdev->mcdma) { - if (chan->direction == DMA_MEM_TO_DEV) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - } else { - if (!chan->tdest) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - } else { - dma_ctrl_write(chan, - XILINX_DMA_MCRX_TDESC(chan->tdest), - tail_segment->phys); - } - } } else { struct xilinx_axidma_tx_segment *segment; struct xilinx_axidma_desc_hw *hw; @@ -2017,90 +1971,6 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( } /** - * xilinx_dma_prep_interleaved - prepare a descriptor for a - * DMA_SLAVE transaction - * @dchan: DMA channel - * @xt: Interleaved template pointer - * @flags: transfer ack flags - * - * Return: Async transaction descriptor on success and NULL on failure - */ -static struct dma_async_tx_descriptor * -xilinx_dma_prep_interleaved(struct dma_chan *dchan, - struct dma_interleaved_template *xt, - unsigned long flags) -{ - struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); - struct xilinx_dma_tx_descriptor *desc; - struct xilinx_axidma_tx_segment *segment; - struct xilinx_axidma_desc_hw *hw; - - if (!is_slave_direction(xt->dir)) - return NULL; - - if (!xt->numf || !xt->sgl[0].size) - return NULL; - - if (xt->frame_size != 1) - return NULL; - - /* Allocate a transaction descriptor. */ - desc = xilinx_dma_alloc_tx_descriptor(chan); - if (!desc) - return NULL; - - chan->direction = xt->dir; - dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); - desc->async_tx.tx_submit = xilinx_dma_tx_submit; - - /* Get a free segment */ - segment = xilinx_axidma_alloc_tx_segment(chan); - if (!segment) - goto error; - - hw = &segment->hw; - - /* Fill in the descriptor */ - if (xt->dir != DMA_MEM_TO_DEV) - hw->buf_addr = xt->dst_start; - else - hw->buf_addr = xt->src_start; - - hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK; - hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) & - XILINX_DMA_BD_VSIZE_MASK; - hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) & - XILINX_DMA_BD_STRIDE_MASK; - hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK; - - /* - * Insert the segment into the descriptor segments - * list. - */ - list_add_tail(&segment->node, &desc->segments); - - - segment = list_first_entry(&desc->segments, - struct xilinx_axidma_tx_segment, node); - desc->async_tx.phys = segment->phys; - - /* For the last DMA_MEM_TO_DEV transfer, set EOP */ - if (xt->dir == DMA_MEM_TO_DEV) { - segment->hw.control |= XILINX_DMA_BD_SOP; - segment = list_last_entry(&desc->segments, - struct xilinx_axidma_tx_segment, - node); - segment->hw.control |= XILINX_DMA_BD_EOP; - } - - return &desc->async_tx; - -error: - xilinx_dma_free_tx_descriptor(chan, desc); - return NULL; -} - -/** * xilinx_dma_terminate_all - Halt the channel and free descriptors * @dchan: Driver specific DMA Channel pointer * @@ -2492,7 +2362,6 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { chan->direction = DMA_MEM_TO_DEV; chan->id = chan_id; - chan->tdest = chan_id; chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ -2509,7 +2378,6 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, "xlnx,axi-dma-s2mm-channel")) { chan->direction = DMA_DEV_TO_MEM; chan->id = chan_id; - chan->tdest = chan_id - xdev->nr_channels; chan->has_vflip = of_property_read_bool(node, "xlnx,enable-vert-flip"); if (chan->has_vflip) { @@ -2597,11 +2465,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, struct device_node *node) { - int ret, i, nr_channels = 1; - - ret = of_property_read_u32(node, "dma-channels", &nr_channels); - if ((ret < 0) && xdev->mcdma) - dev_warn(xdev->dev, "missing dma-channels property\n"); + int i, nr_channels = 1; for (i = 0; i < nr_channels; i++) xilinx_dma_chan_probe(xdev, node, xdev->chan_id++); @@ -2700,7 +2564,6 @@ static int xilinx_dma_probe(struct platform_device *pdev) xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { - xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); if (!of_property_read_u32(node, "xlnx,sg-length-width", &len_width)) { if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || @@ -2765,8 +2628,6 @@ static int xilinx_dma_probe(struct platform_device *pdev) xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; xdev->common.device_prep_dma_cyclic = xilinx_dma_prep_dma_cyclic; - xdev->common.device_prep_interleaved_dma = - xilinx_dma_prep_interleaved; /* Residue calculation is supported by only AXI DMA and CDMA */ xdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; From patchwork Tue Oct 22 17:00:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 11204927 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1A241390 for ; Tue, 22 Oct 2019 17:01:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7551C2084B for ; Tue, 22 Oct 2019 17:01:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="Sacs5uUs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731847AbfJVRBS (ORCPT ); Tue, 22 Oct 2019 13:01:18 -0400 Received: from mail-eopbgr720065.outbound.protection.outlook.com ([40.107.72.65]:65312 "EHLO NAM05-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730768AbfJVRBR (ORCPT ); Tue, 22 Oct 2019 13:01:17 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=V8XcNa+yjyt1MqU8sO4RME5s6YvHBd5mMmJGsWyslk6Zd+GUuYXxUsgm/H5PIWEqrKfSjcjDaiEgP8ThOy05k+wRWU8SUgLklgTAu+R6vQGMivQnVScoBF4VXaIJbNGSLF4oNsVI5dvMCcTzhcvuqFv6fj3vbS8+jBJNPDTmyskSAX8rzympsKCxsxTjrgyutPW0S2amPYjBv2HkyudpBC6iUStrwYoA3FT0ILVK7mPIo+pbsXlM+W8QpTI6REtd8XKqGOsNU+pbfjvmKWyQ5nVila6jUHrS/AqSbIo8dCAyMXXCoYogEh8uzfXEm1gIukCx9sfTxAzZIr1Ly2qbzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WU76ojE5cyfLDJ4NzqiIRVsIPhl67djomZGnU4Ca31w=; b=OMMLPvE3MChqrc8Gz7ZSv50LKYuEDR0+WYGAIeuFBU3aE5fegjTsfayL6rcQXE5gF95yzrdpF0No2UJ/txye4/lxe7ByFhgsgDr+YCbeHANsqQ/Rcirg8Tyigv8+B4g9fWTtQMM5//MGmOgq0TnCnIxmzk7tg9n1VEPd3+2edPpNB4tVmhGhstK7+gHkKj70l0TO3ReJEOmsFlTuNNduFIbNpimxS40T1zVKd/MNHhjINuhJuHM4sgq8rj4nfw7m2hn+AKZgxX+CkjaANE+hcCriFUcdSDUlNGWrJ6dUQ6MvZ/vGnZ4XDLh/SzUcAvo1yczRl1vi4gVNgQn9n6vJSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WU76ojE5cyfLDJ4NzqiIRVsIPhl67djomZGnU4Ca31w=; b=Sacs5uUs9cuRw21FntbXSwRqM6NOzsGN42dgxkxRwalzGoWHs5ZBVR/IEllFZ8MZKsNvQ6Z1nqPNlMFxSHA6Eez4aKYUkhSt7pcB8EKwzxcNE7XxIHSa1uRFrTHI/OpU6FepoxwhGdZrwiE05xpXEvUFW4OwYjByRmTldqrvz7g= Received: from BN7PR02CA0007.namprd02.prod.outlook.com (2603:10b6:408:20::20) by DM6PR02MB5354.namprd02.prod.outlook.com (2603:10b6:5:47::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2367.24; Tue, 22 Oct 2019 17:00:43 +0000 Received: from CY1NAM02FT009.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e45::200) by BN7PR02CA0007.outlook.office365.com (2603:10b6:408:20::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2347.16 via Frontend Transport; Tue, 22 Oct 2019 17:00:43 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT009.mail.protection.outlook.com (10.152.75.12) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2367.14 via Frontend Transport; Tue, 22 Oct 2019 17:00:43 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWU-0006Ap-Ea; Tue, 22 Oct 2019 10:00:42 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp1.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWP-0005GT-1M; Tue, 22 Oct 2019 10:00:37 -0700 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0XNG022072; Tue, 22 Oct 2019 10:00:33 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWK-0005B3-Pg; Tue, 22 Oct 2019 10:00:33 -0700 Received: by ubuntu (Postfix, from userid 13245) id DA455101132; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 5/6] dmaengine: xilinx_dma: Extend dma_config struct to store irq routine handle Date: Tue, 22 Oct 2019 22:30:21 +0530 Message-Id: <1571763622-29281-6-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--5.725-7.0-31-1 X-imss-scan-details: No--5.725-7.0-31-1;No--5.725-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(346002)(396003)(39860400002)(136003)(189003)(199004)(476003)(2616005)(446003)(103686004)(50226002)(478600001)(81156014)(8936002)(81166006)(8676002)(356004)(6666004)(70206006)(70586007)(126002)(486006)(50466002)(11346002)(186003)(5660300002)(14444005)(26005)(336012)(426003)(47776003)(76176011)(6266002)(305945005)(7416002)(107886003)(4326008)(36756003)(106002)(2906002)(48376002)(16586007)(42186006)(316002)(51416003)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB5354;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 63cdd267-7f3f-412b-2891-08d757115ff0 X-MS-TrafficTypeDiagnostic: DM6PR02MB5354: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UD9A4z2kc1lQ+EhzEl7IgGpBvMu6LJSm9Z2jheJTtL8NNliULP8MAKBrLH6HEuB5NXwaqeYsh+Z7ijR6mQw4ykpRD+UKInV7Blnhh+At22oaZbdXmD56aIAACUBeHoQNCal8XXpkMkv3Bww7ZHU/fHgCGE6MoJBagvUgkovm5m9ZYDnTZKPEPo83FtFB81uLyP5BQfaYCWqsjo6T8qmEWPMgCfi2ki/4kUywGI5cnKQQigxOvfZjk5FhclE7atAFsEONh5b3sqyQbU+jDqQrCPDUv2cw6xceZIZpo8Zejy+95qC4/ZmA2PalgiB9Yrqg5HsWMWr2VUJ4WWPwWx9l2vGWHJ9GaXbAO0dUJN2O3VcenCdoXrR6RzbjFGq0T/DFtdG1aihp3v9+qxntSfz1aZ0xrBfr1mkQdq3i/i+/hVIAfg/LzGjFcSnuyzRKvq9K X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:43.0428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63cdd267-7f3f-412b-2891-08d757115ff0 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5354 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Extend dma_config structure to store irq routine handle. It enables runtime handler selection based on xdma_ip_type and serves as preparatory patch for adding MCDMA IP support. Signed-off-by: Radhey Shyam Pandey Suggested-by: Vinod Koul --- Changes since RFC: New patch. It serve as a preparatory patch for MCDMA driver support. --- drivers/dma/xilinx/xilinx_dma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 6d45865..25042a9 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -391,6 +391,7 @@ struct xilinx_dma_config { int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, struct clk **tx_clk, struct clk **txs_clk, struct clk **rx_clk, struct clk **rxs_clk); + irqreturn_t (*irq_handler)(int irq, void *data); }; /** @@ -2402,8 +2403,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, /* Request the interrupt */ chan->irq = irq_of_parse_and_map(node, 0); - err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED, - "xilinx-dma-controller", chan); + err = request_irq(chan->irq, xdev->dma_config->irq_handler, + IRQF_SHARED, "xilinx-dma-controller", chan); if (err) { dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); return err; @@ -2497,16 +2498,19 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, static const struct xilinx_dma_config axidma_config = { .dmatype = XDMA_TYPE_AXIDMA, .clk_init = axidma_clk_init, + .irq_handler = xilinx_dma_irq_handler, }; static const struct xilinx_dma_config axicdma_config = { .dmatype = XDMA_TYPE_CDMA, .clk_init = axicdma_clk_init, + .irq_handler = xilinx_dma_irq_handler, }; static const struct xilinx_dma_config axivdma_config = { .dmatype = XDMA_TYPE_VDMA, .clk_init = axivdma_clk_init, + .irq_handler = xilinx_dma_irq_handler, }; static const struct of_device_id xilinx_dma_of_ids[] = { From patchwork Tue Oct 22 17:00:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 11204921 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCB021575 for ; Tue, 22 Oct 2019 17:00:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C16720684 for ; Tue, 22 Oct 2019 17:00:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="d2B3XSV+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733002AbfJVRAt (ORCPT ); Tue, 22 Oct 2019 13:00:49 -0400 Received: from mail-eopbgr690058.outbound.protection.outlook.com ([40.107.69.58]:51744 "EHLO NAM04-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1733000AbfJVRAs (ORCPT ); Tue, 22 Oct 2019 13:00:48 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NJPa6oV0DmHT2ApzRT0XrdmH4wde6mLCVRYSoU2bTSh0tcDJDyztBm0FSl1qoOpAqvYXHjnnAmr9ozez6DcmWFg5EDTZwSsvTEVxK29x9SdBDttuuf/AlC9AkcmKYeMikNMIAKO0wh93q6oPqeF9ojjxLztTJ8V/vyEouRiA6Q9i5VVLDawf+P+DassTmZT2QgyYtmkIZu0+ILgFEMLxYKgbbGRDwz+1iu0WHzWynaV4GrfN/EM88fUQ4pJOwztvcHFkpDhLDAexSty8KRSgY5hzUaUXd5hP14uKF9bTKa9c0k9940FrPJIIDbuSGmJyo0s8m7cjCXMg7FSElJ44Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=d/9KcTsVK/tmUnZACNYE3qmEQuuyWtAysFtkNZJSDeg=; b=GA0pGecEUp26D5Zc/ZaOGzPVUp1TDJuEZMojN/pQzQnvbJnVreMsjEnjUwXaAXi3in66WloeRr4qvpdHrs52YOMAyYZxtfT4os5d7e1TG9mFMdk9B32RE0F7EKhtuKXqE+yooryLupUmTascozuB2X+6d7FBxkER+XsDZS6zSb+FXKWNk8HtoBmormSNGBK4ishsv0jrYvYIuk6+KftQm/2q07H07fGDbcSJ6goUmNsJ6vPAykHch4ZbDjOSJ8H9Ff3lSq5iL9BIYcNZtK+X/VtDdOxaLRQ/cjQHM1zVC8IEat7Q+xOllvU3t6pQCnrycdIlRQggC/RvNMEyisf3rQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=d/9KcTsVK/tmUnZACNYE3qmEQuuyWtAysFtkNZJSDeg=; b=d2B3XSV+zFTQAmC+56dHJ3/VtRoQDnqfMiHpZQI0fBJZ0p0sPkmACdsq1v53Z/oxsQlE4HAFZqjJ0qVV9ndza9DPC2cgIKr5bJjsFP3NV17TBWLBYaawGjrDvlsWpByLtf0fEDw0rXV9ZjUYiESKoP330uB4j1NJfmW34+s25+k= Received: from CY4PR02CA0013.namprd02.prod.outlook.com (2603:10b6:903:18::23) by BN6PR02MB2801.namprd02.prod.outlook.com (2603:10b6:404:fb::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2367.20; Tue, 22 Oct 2019 17:00:43 +0000 Received: from SN1NAM02FT051.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e44::208) by CY4PR02CA0013.outlook.office365.com (2603:10b6:903:18::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2367.21 via Frontend Transport; Tue, 22 Oct 2019 17:00:43 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by SN1NAM02FT051.mail.protection.outlook.com (10.152.73.103) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.2367.14 via Frontend Transport; Tue, 22 Oct 2019 17:00:42 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWU-0006Ao-AJ; Tue, 22 Oct 2019 10:00:42 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp1.xlnx.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWP-0005GS-00; Tue, 22 Oct 2019 10:00:37 -0700 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0XSm022074; Tue, 22 Oct 2019 10:00:35 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWK-0005B4-Pl; Tue, 22 Oct 2019 10:00:33 -0700 Received: by ubuntu (Postfix, from userid 13245) id DFEC1101134; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 6/6] dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support Date: Tue, 22 Oct 2019 22:30:22 +0530 Message-Id: <1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--5.202-7.0-31-1 X-imss-scan-details: No--5.202-7.0-31-1;No--5.202-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(39860400002)(346002)(396003)(136003)(189003)(199004)(8936002)(446003)(11346002)(48376002)(426003)(336012)(126002)(50226002)(476003)(2906002)(486006)(42186006)(106002)(2616005)(186003)(36756003)(8676002)(81156014)(81166006)(4326008)(14444005)(107886003)(70586007)(6266002)(316002)(26005)(70206006)(103686004)(5660300002)(478600001)(305945005)(50466002)(7416002)(6666004)(16586007)(356004)(51416003)(47776003)(30864003)(76176011)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:BN6PR02MB2801;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2ec76a97-3086-49be-14bc-08d757115fd1 X-MS-TrafficTypeDiagnostic: BN6PR02MB2801: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:525; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3e3UDmyqZPn78imZbu4KUI0gxbEg0VP9I+ymFhSvGhMX+LqGzUr0gjJ1W6eMlpBLJuD6UXcPKeWK/9iLSOYkKQ8POEN1hV/yJFnZPIJ2/2RSlDHlobGA3+680S/DOJfQJuoLtk/s1hv8jbirOpwYQ0xU8xhmxpPJHbdKxN3Rf0YRx6wwqCCiB6se/cd+DN9msa+K9pVhmiqMWBWIPf/nTNeT0RUJtCdJYirTGEEZpddsQuljR+bBLdSCnfnJFUqlFKdqZpkf3ZmHhA5f+fqLcjnDW4ABpsYCUwsrAuoK62EZfB5oMNfu6b5R3mEkac+CHMysEjwuI3ewvjmSS818UJvjs+XP6j8xwUulsDrombm1NAvL5+K9kcUsFWAqjvoaqWzpL8Gw2dw9XEdwWK/R+/YDm1l/3/Gfrxyd0t5/h2ei11IQm6z0Wt1Hpg1x5dEi X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:42.7581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ec76a97-3086-49be-14bc-08d757115fd1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2801 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by: Radhey Shyam Pandey --- Changes since RFC: Mention that xilinx_mcdma_start_transfer is called with lock held. Remove bogus empty lines. Fix xilinx_mcdma_prep_slave_sg indentation. In mcdma slave_sg function merge chan->direction and app word check. Reuse axidma s2mm and mm2 channel nodes. Add MCDA IP description in dma kconfig. Regression fixes. --- drivers/dma/Kconfig | 4 + drivers/dma/xilinx/xilinx_dma.c | 460 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 455 insertions(+), 9 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 59390e8..cc57801 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -655,6 +655,10 @@ config XILINX_DMA destination address. AXI DMA engine provides high-bandwidth one dimensional direct memory access between memory and AXI4-Stream target peripherals. + AXI MCDMA engine provides high-bandwidth direct memory access + between memory and AXI4-Stream target peripherals. It provides + the scatter gather interface with multiple channels independent + configuration support. config XILINX_ZYNQMP_DMA tristate "Xilinx ZynqMP DMA Engine" diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 25042a9..d24d1a2 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -25,6 +25,12 @@ * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory * Access (DMA) between a memory-mapped source address and a memory-mapped * destination address. + * + * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft + * Xilinx IP that provides high-bandwidth direct memory access between + * memory and AXI4-Stream target peripherals. It provides scatter gather + * (SG) interface with multiple channels independent configuration support. + * */ #include @@ -116,7 +122,7 @@ #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) /* HW specific definitions */ -#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 +#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ @@ -179,6 +185,31 @@ #define xilinx_prep_dma_addr_t(addr) \ ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) + +/* AXI MCDMA Specific Registers/Offsets */ +#define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 +#define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 +#define XILINX_MCDMA_CHEN_OFFSET 0x0008 +#define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 +#define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 +#define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 +#define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) +#define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) +#define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) +#define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) + +/* AXI MCDMA Specific Masks/Shifts */ +#define XILINX_MCDMA_COALESCE_SHIFT 16 +#define XILINX_MCDMA_COALESCE_MAX 24 +#define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) +#define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) +#define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) +#define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) +#define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) +#define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) +#define XILINX_MCDMA_BD_EOP BIT(30) +#define XILINX_MCDMA_BD_SOP BIT(31) + /** * struct xilinx_vdma_desc_hw - Hardware Descriptor * @next_desc: Next Descriptor Pointer @0x00 @@ -225,6 +256,30 @@ struct xilinx_axidma_desc_hw { } __aligned(64); /** + * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA + * @next_desc: Next Descriptor Pointer @0x00 + * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 + * @buf_addr: Buffer address @0x08 + * @buf_addr_msb: MSB of Buffer address @0x0C + * @rsvd: Reserved field @0x10 + * @control: Control Information field @0x14 + * @status: Status field @0x18 + * @sideband_status: Status of sideband signals @0x1C + * @app: APP Fields @0x20 - 0x30 + */ +struct xilinx_aximcdma_desc_hw { + u32 next_desc; + u32 next_desc_msb; + u32 buf_addr; + u32 buf_addr_msb; + u32 rsvd; + u32 control; + u32 status; + u32 sideband_status; + u32 app[XILINX_DMA_NUM_APP_WORDS]; +} __aligned(64); + +/** * struct xilinx_cdma_desc_hw - Hardware Descriptor * @next_desc: Next Descriptor Pointer @0x00 * @next_desc_msb: Next Descriptor Pointer MSB @0x04 @@ -271,6 +326,18 @@ struct xilinx_axidma_tx_segment { } __aligned(64); /** + * struct xilinx_aximcdma_tx_segment - Descriptor segment + * @hw: Hardware descriptor + * @node: Node in the descriptor segments list + * @phys: Physical address of segment + */ +struct xilinx_aximcdma_tx_segment { + struct xilinx_aximcdma_desc_hw hw; + struct list_head node; + dma_addr_t phys; +} __aligned(64); + +/** * struct xilinx_cdma_tx_segment - Descriptor segment * @hw: Hardware descriptor * @node: Node in the descriptor segments list @@ -329,11 +396,13 @@ struct xilinx_dma_tx_descriptor { * @ext_addr: Indicates 64 bit addressing is supported by dma channel * @desc_submitcount: Descriptor h/w submitted count * @seg_v: Statically allocated segments base + * @seg_mv: Statically allocated segments base for MCDMA * @seg_p: Physical allocated segments base * @cyclic_seg_v: Statically allocated segment base for cyclic transfers * @cyclic_seg_p: Physical allocated segments base for cyclic dma * @start_transfer: Differentiate b/w DMA IP's transfer * @stop_transfer: Differentiate b/w DMA IP's quiesce + * @tdest: TDEST value for mcdma * @has_vflip: S2MM vertical flip */ struct xilinx_dma_chan { @@ -364,11 +433,13 @@ struct xilinx_dma_chan { bool ext_addr; u32 desc_submitcount; struct xilinx_axidma_tx_segment *seg_v; + struct xilinx_aximcdma_tx_segment *seg_mv; dma_addr_t seg_p; struct xilinx_axidma_tx_segment *cyclic_seg_v; dma_addr_t cyclic_seg_p; void (*start_transfer)(struct xilinx_dma_chan *chan); int (*stop_transfer)(struct xilinx_dma_chan *chan); + u16 tdest; bool has_vflip; }; @@ -378,12 +449,14 @@ struct xilinx_dma_chan { * @XDMA_TYPE_AXIDMA: Axi dma ip. * @XDMA_TYPE_CDMA: Axi cdma ip. * @XDMA_TYPE_VDMA: Axi vdma ip. + * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. * */ enum xdma_ip_type { XDMA_TYPE_AXIDMA = 0, XDMA_TYPE_CDMA, XDMA_TYPE_VDMA, + XDMA_TYPE_AXIMCDMA }; struct xilinx_dma_config { @@ -412,6 +485,7 @@ struct xilinx_dma_config { * @nr_channels: Number of channels DMA device supports * @chan_id: DMA channel identifier * @max_buffer_len: Max buffer length + * @s2mm_index: S2MM channel index */ struct xilinx_dma_device { void __iomem *regs; @@ -430,6 +504,7 @@ struct xilinx_dma_device { u32 nr_channels; u32 chan_id; u32 max_buffer_len; + u32 s2mm_index; }; /* Macros */ @@ -530,6 +605,18 @@ static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, } } +static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, + struct xilinx_aximcdma_desc_hw *hw, + dma_addr_t buf_addr, size_t sg_used) +{ + if (chan->ext_addr) { + hw->buf_addr = lower_32_bits(buf_addr + sg_used); + hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); + } else { + hw->buf_addr = buf_addr + sg_used; + } +} + /* ----------------------------------------------------------------------------- * Descriptors and segments alloc and free */ @@ -603,6 +690,30 @@ xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) return segment; } +/** + * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment + * @chan: Driver specific DMA channel + * + * Return: The allocated segment on success and NULL on failure. + */ +static struct xilinx_aximcdma_tx_segment * +xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) +{ + struct xilinx_aximcdma_tx_segment *segment = NULL; + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + if (!list_empty(&chan->free_seg_list)) { + segment = list_first_entry(&chan->free_seg_list, + struct xilinx_aximcdma_tx_segment, + node); + list_del(&segment->node); + } + spin_unlock_irqrestore(&chan->lock, flags); + + return segment; +} + static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw) { u32 next_desc = hw->next_desc; @@ -614,6 +725,17 @@ static void xilinx_dma_clean_hw_desc(struct xilinx_axidma_desc_hw *hw) hw->next_desc_msb = next_desc_msb; } +static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) +{ + u32 next_desc = hw->next_desc; + u32 next_desc_msb = hw->next_desc_msb; + + memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); + + hw->next_desc = next_desc; + hw->next_desc_msb = next_desc_msb; +} + /** * xilinx_dma_free_tx_segment - Free transaction segment * @chan: Driver specific DMA channel @@ -628,6 +750,20 @@ static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, } /** + * xilinx_mcdma_free_tx_segment - Free transaction segment + * @chan: Driver specific DMA channel + * @segment: DMA transaction segment + */ +static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, + struct xilinx_aximcdma_tx_segment * + segment) +{ + xilinx_mcdma_clean_hw_desc(&segment->hw); + + list_add_tail(&segment->node, &chan->free_seg_list); +} + +/** * xilinx_cdma_free_tx_segment - Free transaction segment * @chan: Driver specific DMA channel * @segment: DMA transaction segment @@ -681,6 +817,7 @@ xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, struct xilinx_vdma_tx_segment *segment, *next; struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; + struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; if (!desc) return; @@ -696,12 +833,18 @@ xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, list_del(&cdma_segment->node); xilinx_cdma_free_tx_segment(chan, cdma_segment); } - } else { + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { list_for_each_entry_safe(axidma_segment, axidma_next, &desc->segments, node) { list_del(&axidma_segment->node); xilinx_dma_free_tx_segment(chan, axidma_segment); } + } else { + list_for_each_entry_safe(aximcdma_segment, aximcdma_next, + &desc->segments, node) { + list_del(&aximcdma_segment->node); + xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); + } } kfree(desc); @@ -770,10 +913,23 @@ static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) chan->cyclic_seg_v, chan->cyclic_seg_p); } - if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) { + if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + spin_lock_irqsave(&chan->lock, flags); + INIT_LIST_HEAD(&chan->free_seg_list); + spin_unlock_irqrestore(&chan->lock, flags); + + /* Free memory that is allocated for BD */ + dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * + XILINX_DMA_NUM_DESCS, chan->seg_mv, + chan->seg_p); + } + + if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && + chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { dma_pool_destroy(chan->desc_pool); chan->desc_pool = NULL; } + } /** @@ -955,6 +1111,30 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) list_add_tail(&chan->seg_v[i].node, &chan->free_seg_list); } + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + /* Allocate the buffer descriptors. */ + chan->seg_mv = dma_alloc_coherent(chan->dev, + sizeof(*chan->seg_mv) * + XILINX_DMA_NUM_DESCS, + &chan->seg_p, GFP_KERNEL); + if (!chan->seg_mv) { + dev_err(chan->dev, + "unable to allocate channel %d descriptors\n", + chan->id); + return -ENOMEM; + } + for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { + chan->seg_mv[i].hw.next_desc = + lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * + ((i + 1) % XILINX_DMA_NUM_DESCS)); + chan->seg_mv[i].hw.next_desc_msb = + upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * + ((i + 1) % XILINX_DMA_NUM_DESCS)); + chan->seg_mv[i].phys = chan->seg_p + + sizeof(*chan->seg_v) * i; + list_add_tail(&chan->seg_mv[i].node, + &chan->free_seg_list); + } } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", chan->dev, @@ -970,7 +1150,8 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) } if (!chan->desc_pool && - (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA)) { + ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && + chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { dev_err(chan->dev, "unable to allocate channel %d descriptor pool\n", chan->id); @@ -1368,6 +1549,76 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) } /** + * xilinx_mcdma_start_transfer - Starts MCDMA transfer + * @chan: Driver specific channel struct pointer + */ +static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) +{ + struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; + struct xilinx_axidma_tx_segment *tail_segment; + u32 reg; + + /* + * lock has been held by calling functions, so we don't need it + * to take it here again. + */ + + if (chan->err) + return; + + if (!chan->idle) + return; + + if (list_empty(&chan->pending_list)) + return; + + head_desc = list_first_entry(&chan->pending_list, + struct xilinx_dma_tx_descriptor, node); + tail_desc = list_last_entry(&chan->pending_list, + struct xilinx_dma_tx_descriptor, node); + tail_segment = list_last_entry(&tail_desc->segments, + struct xilinx_axidma_tx_segment, node); + + reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); + + if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { + reg &= ~XILINX_MCDMA_COALESCE_MASK; + reg |= chan->desc_pendingcount << + XILINX_MCDMA_COALESCE_SHIFT; + } + + reg |= XILINX_MCDMA_IRQ_ALL_MASK; + dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); + + /* Program current descriptor */ + xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), + head_desc->async_tx.phys); + + /* Program channel enable register */ + reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); + reg |= BIT(chan->tdest); + dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); + + /* Start the fetch of BDs for the channel */ + reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); + reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; + dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); + + xilinx_dma_start(chan); + + if (chan->err) + return; + + /* Start the transfer */ + xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), + tail_segment->phys); + + list_splice_tail_init(&chan->pending_list, &chan->active_list); + chan->desc_pendingcount = 0; + chan->idle = false; +} + +/** * xilinx_dma_issue_pending - Issue pending transactions * @dchan: DMA channel */ @@ -1466,6 +1717,74 @@ static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) } /** + * xilinx_mcdma_irq_handler - MCDMA Interrupt handler + * @irq: IRQ number + * @data: Pointer to the Xilinx MCDMA channel structure + * + * Return: IRQ_HANDLED/IRQ_NONE + */ +static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) +{ + struct xilinx_dma_chan *chan = data; + u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; + + if (chan->direction == DMA_DEV_TO_MEM) + ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; + else + ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; + + /* Read the channel id raising the interrupt*/ + chan_sermask = dma_ctrl_read(chan, ser_offset); + chan_id = ffs(chan_sermask); + + if (!chan_id) + return IRQ_NONE; + + if (chan->direction == DMA_DEV_TO_MEM) + chan_offset = chan->xdev->s2mm_index; + + chan_offset = chan_offset + (chan_id - 1); + chan = chan->xdev->chan[chan_offset]; + /* Read the status and ack the interrupts. */ + status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); + if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) + return IRQ_NONE; + + dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), + status & XILINX_MCDMA_IRQ_ALL_MASK); + + if (status & XILINX_MCDMA_IRQ_ERR_MASK) { + dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", + chan, + dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), + dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET + (chan->tdest)), + dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET + (chan->tdest))); + chan->err = true; + } + + if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { + /* + * Device takes too long to do the transfer when user requires + * responsiveness. + */ + dev_dbg(chan->dev, "Inter-packet latency too long\n"); + } + + if (status & XILINX_MCDMA_IRQ_IOC_MASK) { + spin_lock(&chan->lock); + xilinx_dma_complete_descriptor(chan); + chan->idle = true; + chan->start_transfer(chan); + spin_unlock(&chan->lock); + } + + tasklet_schedule(&chan->tasklet); + return IRQ_HANDLED; +} + +/** * xilinx_dma_irq_handler - DMA Interrupt handler * @irq: IRQ number * @data: Pointer to the Xilinx DMA channel structure @@ -1972,6 +2291,104 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( } /** + * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction + * @dchan: DMA channel + * @sgl: scatterlist to transfer to/from + * @sg_len: number of entries in @scatterlist + * @direction: DMA direction + * @flags: transfer ack flags + * @context: APP words of the descriptor + * + * Return: Async transaction descriptor on success and NULL on failure + */ +static struct dma_async_tx_descriptor * +xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, + unsigned int sg_len, + enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); + struct xilinx_dma_tx_descriptor *desc; + struct xilinx_aximcdma_tx_segment *segment = NULL; + u32 *app_w = (u32 *)context; + struct scatterlist *sg; + size_t copy; + size_t sg_used; + unsigned int i; + + if (!is_slave_direction(direction)) + return NULL; + + /* Allocate a transaction descriptor. */ + desc = xilinx_dma_alloc_tx_descriptor(chan); + if (!desc) + return NULL; + + dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); + desc->async_tx.tx_submit = xilinx_dma_tx_submit; + + /* Build transactions using information in the scatter gather list */ + for_each_sg(sgl, sg, sg_len, i) { + sg_used = 0; + + /* Loop until the entire scatterlist entry is used */ + while (sg_used < sg_dma_len(sg)) { + struct xilinx_aximcdma_desc_hw *hw; + + /* Get a free segment */ + segment = xilinx_aximcdma_alloc_tx_segment(chan); + if (!segment) + goto error; + + /* + * Calculate the maximum number of bytes to transfer, + * making sure it is less than the hw limit + */ + copy = min_t(size_t, sg_dma_len(sg) - sg_used, + chan->xdev->max_buffer_len); + hw = &segment->hw; + + /* Fill in the descriptor */ + xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), + sg_used); + hw->control = copy; + + if (chan->direction == DMA_MEM_TO_DEV && app_w) { + memcpy(hw->app, app_w, sizeof(u32) * + XILINX_DMA_NUM_APP_WORDS); + } + + sg_used += copy; + /* + * Insert the segment into the descriptor segments + * list. + */ + list_add_tail(&segment->node, &desc->segments); + } + } + + segment = list_first_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, node); + desc->async_tx.phys = segment->phys; + + /* For the last DMA_MEM_TO_DEV transfer, set EOP */ + if (chan->direction == DMA_MEM_TO_DEV) { + segment->hw.control |= XILINX_MCDMA_BD_SOP; + segment = list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, + node); + segment->hw.control |= XILINX_MCDMA_BD_EOP; + } + + return &desc->async_tx; + +error: + xilinx_dma_free_tx_descriptor(chan, desc); + + return NULL; +} + +/** * xilinx_dma_terminate_all - Halt the channel and free descriptors * @dchan: Driver specific DMA Channel pointer * @@ -2363,6 +2780,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { chan->direction = DMA_MEM_TO_DEV; chan->id = chan_id; + chan->tdest = chan_id; chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ -2379,6 +2797,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, "xlnx,axi-dma-s2mm-channel")) { chan->direction = DMA_DEV_TO_MEM; chan->id = chan_id; + xdev->s2mm_index = xdev->nr_channels; + chan->tdest = chan_id - xdev->nr_channels; chan->has_vflip = of_property_read_bool(node, "xlnx,enable-vert-flip"); if (chan->has_vflip) { @@ -2387,7 +2807,11 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, XILINX_VDMA_ENABLE_VERTICAL_FLIP; } - chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) + chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; + else + chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; + if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; chan->config.park = 1; @@ -2402,7 +2826,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, } /* Request the interrupt */ - chan->irq = irq_of_parse_and_map(node, 0); + chan->irq = irq_of_parse_and_map(node, chan->tdest); err = request_irq(chan->irq, xdev->dma_config->irq_handler, IRQF_SHARED, "xilinx-dma-controller", chan); if (err) { @@ -2413,6 +2837,9 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { chan->start_transfer = xilinx_dma_start_transfer; chan->stop_transfer = xilinx_dma_stop_transfer; + } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + chan->start_transfer = xilinx_mcdma_start_transfer; + chan->stop_transfer = xilinx_dma_stop_transfer; } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { chan->start_transfer = xilinx_cdma_start_transfer; chan->stop_transfer = xilinx_cdma_stop_transfer; @@ -2466,7 +2893,11 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, struct device_node *node) { - int i, nr_channels = 1; + int ret, i, nr_channels = 1; + + ret = of_property_read_u32(node, "dma-channels", &nr_channels); + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) + dev_warn(xdev->dev, "missing dma-channels property\n"); for (i = 0; i < nr_channels; i++) xilinx_dma_chan_probe(xdev, node, xdev->chan_id++); @@ -2501,6 +2932,11 @@ static const struct xilinx_dma_config axidma_config = { .irq_handler = xilinx_dma_irq_handler, }; +static const struct xilinx_dma_config aximcdma_config = { + .dmatype = XDMA_TYPE_AXIMCDMA, + .clk_init = axidma_clk_init, + .irq_handler = xilinx_mcdma_irq_handler, +}; static const struct xilinx_dma_config axicdma_config = { .dmatype = XDMA_TYPE_CDMA, .clk_init = axicdma_clk_init, @@ -2517,6 +2953,7 @@ static const struct of_device_id xilinx_dma_of_ids[] = { { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, + { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config }, {} }; MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); @@ -2567,7 +3004,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) /* Retrieve the DMA engine properties from the device tree */ xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || + xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { if (!of_property_read_u32(node, "xlnx,sg-length-width", &len_width)) { if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || @@ -2640,7 +3078,9 @@ static int xilinx_dma_probe(struct platform_device *pdev) xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; /* Residue calculation is supported by only AXI DMA and CDMA */ xdev->common.residue_granularity = - DMA_RESIDUE_GRANULARITY_SEGMENT; + DMA_RESIDUE_GRANULARITY_SEGMENT; + } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { + xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; } else { xdev->common.device_prep_interleaved_dma = xilinx_vdma_dma_prep_interleaved; @@ -2676,6 +3116,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); + else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) + dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); else dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n");