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Thu, 24 Oct 2019 06:57:22 +0000 Received: from DB7PR04MB4490.eurprd04.prod.outlook.com ([fe80::7804:558a:eef9:cc11]) by DB7PR04MB4490.eurprd04.prod.outlook.com ([fe80::7804:558a:eef9:cc11%7]) with mapi id 15.20.2387.023; Thu, 24 Oct 2019 06:57:22 +0000 From: Peng Fan To: "mturquette@baylibre.com" , "sboyd@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "festevam@gmail.com" , Abel Vesa Subject: [PATCH] clk: imx: imx8mq: fix sys2/3_pll_out_sels Thread-Topic: [PATCH] clk: imx: imx8mq: fix sys2/3_pll_out_sels Thread-Index: AQHVijhIlRv5T5+Fgk+U/4a62CwQtw== Date: Thu, 24 Oct 2019 06:57:21 +0000 Message-ID: <1571900044-22079-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR01CA0046.apcprd01.prod.exchangelabs.com (2603:1096:203:3e::34) To DB7PR04MB4490.eurprd04.prod.outlook.com (2603:10a6:5:36::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR04MB4683; H:DB7PR04MB4490.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: o59luhHqYaavQTq53VNA7uOIeVVzprn4gnTwA++qWGvJ4rCBMH1l6cC7tDg6G3AWA7GfjCk93bt/iKY6l+Bl8NkyTzv17hBYnFsv6DkERoiStMwWfegMHXtj7SBEc6nhmVSkWagtv5X3YXoGWVq4ij0IGJELE83HUkrJjPlAt8YO7CtgJ6frlG52T8a6p1ImBgzFsbu+tgSvGUMDZs1BPu/Y6FdcNc3hGcf0AI34iIztu+1YQA3rBZF76+ek2oYPNh3OQzKEIrJXmAOZtHg2ZIOdey8bkPidrb21W+xx4bFWK34vMsqayUiQwljAkWfmRJfxNozeX/52XUEXNcc0j1rS7oh2PjQ55WSTFss/ugW/O17jNv0I2iX7axRCnBlro3TYNwvN2sJ40h43w57ahHHvxM391AZacnK1Dp+7gMKJ3Dp0FJfECQ6e5cUmdEL4 MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74b9ff3e-2dd2-4bba-cb6a-08d7584f6af6 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Oct 2019 06:57:21.8372 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dPbdvGXamzeFsaUfZbYWWOAkpXDjfeL3aODRpAmyb2vA50v8M/hzqYrAI+Hoat1zYs6lKwaMcHHP9IRrxwsj2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4683 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191023_235726_142658_0383592E X-CRM114-Status: GOOD ( 10.95 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.5.59 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peng Fan , Jacky Bai , Anson Huang , "linux-kernel@vger.kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Leonard Crestez , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Peng Fan The current clk tree shows: osc_25m 9 11 0 25000000 0 0 50000 sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000 sys3_pll_out 1 1 0 25000000 0 0 50000 sys1_pll1_ref_sel 2 2 0 25000000 0 0 50000 sys2_pll_out 6 6 0 1000000000 0 0 50000 It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent, sys2_pll_out use sys1_pll1_ref_sel as parent. According to the current imx_clk_sccg_pll design, it uses both bypass1/2, however set bypass2 as 1 is not correct, because it will make sys[x]_pll_out use wrong parent and might access wrong registers. So correct bypass2 to 0 and fix sys2/3_pll_out_sels. After fix, the tree shows: osc_25m 10 12 0 25000000 0 0 50000 sys3_pll1_ref_sel 1 1 0 25000000 0 0 50000 sys3_pll_out 1 1 0 25000000 0 0 50000 sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000 sys2_pll_out 6 6 0 1000000000 0 0 50000 sys1_pll1_ref_sel 1 1 0 25000000 0 0 50000 sys1_pll_out 5 5 0 800000000 0 0 50000 Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-imx8mq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 05ece7b5da54..e17f0ebfacb0 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", }; -static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", }; -static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", }; +static const char * const sys2_pll_out_sels[] = {"sys2_pll1_ref_sel", }; +static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", }; static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", }; static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", }; @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL); - clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL); - clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL); + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, CLK_IS_CRITICAL); + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL); clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL); clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);