From patchwork Thu Oct 24 16:45:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210255 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F7C313B1 for ; Thu, 24 Oct 2019 16:45:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 277B020659 for ; Thu, 24 Oct 2019 16:45:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 277B020659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9676B6E48E; Thu, 24 Oct 2019 16:45:42 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id E43396E4B0 for ; Thu, 24 Oct 2019 16:45:40 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id p4so26867871wrm.8 for ; Thu, 24 Oct 2019 09:45:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IN+YQnEOyJUS5k1O2xwcjJm7/Rodceth/lgx2YM8Gws=; b=GqyOgTax1e7trC0s84oNeqNTNeJ4mU+Bqk/vN2B/2KY7cOy2eyvXYtscBRAxQfdnnc ECFYr/B0TRoGhBuYIwpytblVWEWU34TMlsFOHa34zl/eLY5CiwgLEcd5pqoHxgvDvdJ8 9XbrNGqs2OfHKRQo3KsfWWjwOetFCrO+mu/EbEGGgzMBXKcwoovYp8ULMs8tLa1RfavJ dn3Sr97dIbqHaaTHpC7fVHi8DRlF9IiVHLMs9nam0fxWUm05m1sGvWPvIDTXx5kx5Nl7 cN4e8SZprAZGfodBSOdpcow310KjyQqNVjiPEhOzuAsyN01qWbBchPJdbFPOiT87ublA 6HNg== X-Gm-Message-State: APjAAAWKa08oQZ4KAsVT+NcG0sD8OPH0Sy4kn5aqBVuhqqIOkUheYu75 wGfQscIgOXVjVXlA4PD9QFI= X-Google-Smtp-Source: APXvYqwAeJKMyLSjXtstNJqix0x6l67WkcLJwRvv30XQzva/DaHCuGReyfFc0aj/heUwuzEbH4su5w== X-Received: by 2002:adf:f90d:: with SMTP id b13mr4588523wrr.316.1571935539407; Thu, 24 Oct 2019 09:45:39 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id r13sm37818229wra.74.2019.10.24.09.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:38 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 01/32] drm/tegra: Add missing kerneldoc for struct drm_dp_link Date: Thu, 24 Oct 2019 18:45:03 +0200 Message-Id: <20191024164534.132764-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IN+YQnEOyJUS5k1O2xwcjJm7/Rodceth/lgx2YM8Gws=; b=hYjszF6NhG//c4hvZIbDA0GvgbAJF8UnSShL2kJUVMVnWx/AKDGV1Y8rejCkDZSHTy MXbxES99xFAwluer9AsNg2buiwlPQKbighBMo5tWpWqdgILpEUQEd75+lypGydnNI3rz 83uX13NDePQd/XRKDc6z62E7xy6O43sH4UTGb4oaxsv1uX4ufXjSzlQSNyrVfb3rhc0y nKiI4ShbizlsozhFyDElpbMpXLeER7StLM0EiCiahookxWBFflCip4Btr1MN6RG7EEne 4ZTwa93a3tpOAcsEIuP205nBbAW5TequGUgr6b2AmRFhl1ISl4DIm4KAgd6ovg1TjeKD 2pSg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The drm_dp_link structure tracks capabilities on the DP link. Add some kerneldoc to explain what each of its fields means. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 88842fd25abf..1cf252e7309a 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -11,6 +11,13 @@ struct drm_dp_aux; #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) +/** + * struct drm_dp_link - DP link capabilities + * @revision: DP specification revision supported on the link + * @rate: maximum clock rate supported on the link + * @num_lanes: maximum number of lanes supported on the link + * @capabilities: bitmask of capabilities supported on the link + */ struct drm_dp_link { unsigned char revision; unsigned int rate; From patchwork Thu Oct 24 16:45:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210257 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 880A214ED for ; Thu, 24 Oct 2019 16:45:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70B4A21D71 for ; Thu, 24 Oct 2019 16:45:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70B4A21D71 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 701888984F; Thu, 24 Oct 2019 16:45:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AB326E4B1 for ; Thu, 24 Oct 2019 16:45:43 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id g7so3593174wmk.4 for ; Thu, 24 Oct 2019 09:45:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5DYjBFdBkh2ExDAy5mIdVeU5TwdGnRp9l6pBdmT3a3c=; b=DB1O8mV/Pk8rJmJzm6siJMNnoVvGptwJhy0QE8mSIQ1OFa5V10rOmMLX50TesYkgI1 8iEp3vwIm95PUB+oblAsaKMMZZHtqBDs1wFKF6tJtuGScLTmU4K7Z2xsJjP6HmK6lbwU rP49MdmJS+4Rt44hFLh34wfguVFtX0Uok2W4b8Op4sli5P6xeZouBNmyn+ktmV4Sqt5e O5P8/1k9oPkaf3yB2IsZrsbPHWbXnwNs8nYgxOwCroRHPRkA8VbpG56PkRfEIbek0tHl gx7I2HG+5sHj5Eo/FaW0B6BtrI44ytDubrM5M5DQ19mlip932twhFVyevl/McaOYq7qW x44A== X-Gm-Message-State: APjAAAWGJZH5Cb4hHCoZfX9HnR61qmk5+7zYvPg4rhlCKnnLNsNmSene bZtOnDCn+KiSXp5IamJDNsj07cg7 X-Google-Smtp-Source: APXvYqwSeJIzZ3He6mdaGu8fUEI1GFMx1cvsK7/HbMJTKLryIrN8fCFQx4VE364WszsLtnqgveVxeA== X-Received: by 2002:a7b:c74a:: with SMTP id w10mr5368725wmk.173.1571935541531; Thu, 24 Oct 2019 09:45:41 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id c189sm3953652wme.24.2019.10.24.09.45.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:40 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 02/32] drm/tegra: dp: Add drm_dp_link_reset() implementation Date: Thu, 24 Oct 2019 18:45:04 +0200 Message-Id: <20191024164534.132764-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5DYjBFdBkh2ExDAy5mIdVeU5TwdGnRp9l6pBdmT3a3c=; b=QQoIImawfuOekh1LfxlRAP4b6eF5hXLjNtWE1GNNfz7nRipP4eaowMSTELRpE0navZ muQr9OVrzQVdbMfdaqtOyQIBD+lh1WbFNMrXBF6CQr6hRyL9BmK4mEqItglK32v64GhY x6MsU1bNN+/+X/xZidb26xcqO12sqT4rn5oz+PoMChVNZaXVbtyo2P5JbE5GtvSmiuuN BpHQ80tBKtpgRxfXGkYyUJn1ZgFIEskEtqmftdviBPcC2L4tsRb3C/v6Q3G/Qs/Fgk3x 8nrFySjTg/JNkG+qVkz12y0jIE681ptcS9VGv3X7Pnqy97H81H/9J696YEeNk9V0EU/q dUOA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Subsequent patches will add non-volatile fields to struct drm_dp_link, so introduce a function to zero out only the volatile fields. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 50ba967ebcbd..c19060b8753a 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -8,6 +8,17 @@ #include "dp.h" +static void drm_dp_link_reset(struct drm_dp_link *link) +{ + if (!link) + return; + + link->revision = 0; + link->rate = 0; + link->num_lanes = 0; + link->capabilities = 0; +} + /** * drm_dp_link_probe() - probe a DisplayPort link for capabilities * @aux: DisplayPort AUX channel @@ -24,7 +35,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) u8 values[3]; int err; - memset(link, 0, sizeof(*link)); + drm_dp_link_reset(link); err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); if (err < 0) From patchwork Thu Oct 24 16:45:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210271 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CE2F14ED for ; Thu, 24 Oct 2019 16:46:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04BE020659 for ; Thu, 24 Oct 2019 16:46:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 04BE020659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 117406E4B3; Thu, 24 Oct 2019 16:46:00 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEAA86E48F for ; Thu, 24 Oct 2019 16:45:45 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id w18so26321758wrt.3 for ; Thu, 24 Oct 2019 09:45:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mmTEcYYOmMVHIgwlChAlJWnry5CbvcEzASf8WlmOdH8=; b=TiHuQFx5+sqiOr28O9VkXLBx/kVSdcCJhEVK4N6nQxh9udp7te+iTbN6RdyVMNmp6l MMjML3sZsKmhRMaW7t2foxywcW2ZfFcQJufyLx+G0O4isk89bTb+DBYWZz4rBWn21DMO noijs9CgXYXv/qEW4GdV8AhNgc5J1SX4ZKCXaWpota8Hrc+8fFwlea0WKxKoIZZmZqpl lsaFj82jVo4IyEDl1EHXazYR/jXh2lSsswRQBNBwYlxHwF5+UqSKYgfC9eoQ/LwvGa6R mq5zzE4aAQNimtKpFf7wzldlriMek+iGesg9OZIjGWcCcDnxrU6Wh/jOBvI07VUZgBbQ ouyQ== X-Gm-Message-State: APjAAAXt6Bl07FEUMNVkcCuwr/0YRJW5kraKceo7iiUe59G6Gb8qJLdS 2nGwlqQaGkCkZJF2FMN7/fY= X-Google-Smtp-Source: APXvYqztzQhFZ0jCrnFjNG5K/u0QloolIVfKSzI5/Asqw55Zi+2J0kMPh5AJXMUmHCD7ibJjy27bPA== X-Received: by 2002:adf:ffc5:: with SMTP id x5mr4759973wrs.93.1571935543980; Thu, 24 Oct 2019 09:45:43 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id d2sm3453994wmd.2.2019.10.24.09.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:42 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 03/32] drm/tegra: dp: Track link capabilities alongside settings Date: Thu, 24 Oct 2019 18:45:05 +0200 Message-Id: <20191024164534.132764-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mmTEcYYOmMVHIgwlChAlJWnry5CbvcEzASf8WlmOdH8=; b=rZMG/4BaNuz8+ClmCKXMj58pw7SG855zvpbJZgbGHdcLErwPuIipT9j7mIW5zzJapT kKPpi6C68hGR7U+OFiXo0rutEu/Hw+MbkOcSYpkAX0Vr3xINuArUvqZIKJ72r9z4dWy6 wWt1wC8Qa4xAB8HjRNjJRyYQoePJXp6x8su3ijlOXKBpl2fkr0KAHXCyIiVULpPk7Njj KVJ5mm+rxKkHvVZQOUKfNAmJuGhtX3NIdjvb9qFxzGepoNqMbvYJjEzMV+RTYserOcpq hwTKKpDDHU/6KzZr5089azRe4dj3DaKOJK1QIPuvV/SfP+kdL8YUvyl4EWMYwv2BgX01 v+Aw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Store capabilities in max_* fields and add separate fields for the currently selected settings. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 16 +++++++++++----- drivers/gpu/drm/tegra/dp.h | 15 ++++++++++----- drivers/gpu/drm/tegra/dpaux.c | 8 ++++---- drivers/gpu/drm/tegra/sor.c | 28 ++++++++++++++-------------- 4 files changed, 39 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index c19060b8753a..e55efd46a7d9 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -14,9 +14,12 @@ static void drm_dp_link_reset(struct drm_dp_link *link) return; link->revision = 0; - link->rate = 0; - link->num_lanes = 0; + link->max_rate = 0; + link->max_lanes = 0; link->capabilities = 0; + + link->rate = 0; + link->lanes = 0; } /** @@ -42,12 +45,15 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) return err; link->revision = values[0]; - link->rate = drm_dp_bw_code_to_link_rate(values[1]); - link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; + link->max_rate = drm_dp_bw_code_to_link_rate(values[1]); + link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; if (values[2] & DP_ENHANCED_FRAME_CAP) link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; + link->rate = link->max_rate; + link->lanes = link->max_lanes; + return 0; } @@ -131,7 +137,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) int err; values[0] = drm_dp_link_rate_to_bw_code(link->rate); - values[1] = link->num_lanes; + values[1] = link->lanes; if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 1cf252e7309a..ec0342d4c95e 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -12,17 +12,22 @@ struct drm_dp_aux; #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) /** - * struct drm_dp_link - DP link capabilities + * struct drm_dp_link - DP link capabilities and configuration * @revision: DP specification revision supported on the link - * @rate: maximum clock rate supported on the link - * @num_lanes: maximum number of lanes supported on the link + * @max_rate: maximum clock rate supported on the link + * @max_lanes: maximum number of lanes supported on the link * @capabilities: bitmask of capabilities supported on the link + * @rate: currently configured link rate + * @lanes: currently configured number of lanes */ struct drm_dp_link { unsigned char revision; - unsigned int rate; - unsigned int num_lanes; + unsigned int max_rate; + unsigned int max_lanes; unsigned long capabilities; + + unsigned int rate; + unsigned int lanes; }; int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 883ed2f025c3..bd3361cea49b 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -849,14 +849,14 @@ int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, if (tp == DP_TRAINING_PATTERN_DISABLE) return 0; - for (i = 0; i < link->num_lanes; i++) + for (i = 0; i < link->lanes; i++) values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | DP_TRAIN_PRE_EMPH_LEVEL_0 | DP_TRAIN_MAX_SWING_REACHED | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, - link->num_lanes); + link->lanes); if (err < 0) return err; @@ -868,13 +868,13 @@ int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, switch (tp) { case DP_TRAINING_PATTERN_1: - if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) + if (!drm_dp_clock_recovery_ok(status, link->lanes)) return -EAGAIN; break; case DP_TRAINING_PATTERN_2: - if (!drm_dp_channel_eq_ok(status, link->num_lanes)) + if (!drm_dp_channel_eq_ok(status, link->lanes)) return -EAGAIN; break; diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 91d5c5041d2c..dca71250d88c 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -650,7 +650,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor, if (err < 0) return err; - for (i = 0, value = 0; i < link->num_lanes; i++) { + for (i = 0, value = 0; i < link->lanes; i++) { unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | SOR_DP_TPG_SCRAMBLER_NONE | SOR_DP_TPG_PATTERN_TRAIN1; @@ -671,7 +671,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor, value |= SOR_DP_SPARE_MACRO_SOR_CLK; tegra_sor_writel(sor, value, SOR_DP_SPARE0); - for (i = 0, value = 0; i < link->num_lanes; i++) { + for (i = 0, value = 0; i < link->lanes; i++) { unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | SOR_DP_TPG_SCRAMBLER_NONE | SOR_DP_TPG_PATTERN_TRAIN2; @@ -686,7 +686,7 @@ static int tegra_sor_dp_train_fast(struct tegra_sor *sor, if (err < 0) return err; - for (i = 0, value = 0; i < link->num_lanes; i++) { + for (i = 0, value = 0; i < link->lanes; i++) { unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | SOR_DP_TPG_SCRAMBLER_GALIOS | SOR_DP_TPG_PATTERN_NONE; @@ -913,11 +913,11 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, u32 num_syms_per_line; unsigned int i; - if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) + if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) return -EINVAL; - output = link_rate * 8 * link->num_lanes; input = pclk * config->bits_per_pixel; + output = link_rate * 8 * link->lanes; if (input >= output) return -ERANGE; @@ -960,7 +960,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, watermark = div_u64(watermark + params.error, f); config->watermark = watermark + (config->bits_per_pixel / 8) + 2; num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * - (link->num_lanes * 8); + (link->lanes * 8); if (config->watermark > 30) { config->watermark = 30; @@ -980,12 +980,12 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) config->hblank_symbols -= 3; - config->hblank_symbols -= 12 / link->num_lanes; + config->hblank_symbols -= 12 / link->lanes; /* compute the number of symbols per vertical blanking interval */ num = (mode->hdisplay - 25) * link_rate; config->vblank_symbols = div_u64(num, pclk); - config->vblank_symbols -= 36 / link->num_lanes + 4; + config->vblank_symbols -= 36 / link->lanes + 4; dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, config->vblank_symbols); @@ -1831,17 +1831,17 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) /* power DP lanes */ value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - if (link.num_lanes <= 2) + if (link.lanes <= 2) value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); else value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; - if (link.num_lanes <= 1) + if (link.lanes <= 1) value &= ~SOR_DP_PADCTL_PD_TXD_1; else value |= SOR_DP_PADCTL_PD_TXD_1; - if (link.num_lanes == 0) + if (link.lanes == 0) value &= ~SOR_DP_PADCTL_PD_TXD_0; else value |= SOR_DP_PADCTL_PD_TXD_0; @@ -1850,7 +1850,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; - value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); + value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes); tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); /* start lane sequencer */ @@ -1907,7 +1907,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) dev_err(sor->dev, "failed to configure eDP link: %d\n", err); rate = drm_dp_link_rate_to_bw_code(link.rate); - lanes = link.num_lanes; + lanes = link.lanes; value = tegra_sor_readl(sor, SOR_CLK_CNTRL); value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; @@ -1925,7 +1925,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) /* disable training pattern generator */ - for (i = 0; i < link.num_lanes; i++) { + for (i = 0; i < link.lanes; i++) { unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | SOR_DP_TPG_SCRAMBLER_GALIOS | SOR_DP_TPG_PATTERN_NONE; From patchwork Thu Oct 24 16:45:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A44913B1 for ; Thu, 24 Oct 2019 16:45:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 02CC720659 for ; Thu, 24 Oct 2019 16:45:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 02CC720659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id l6sm3041725wmg.2.2019.10.24.09.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:44 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 04/32] drm/tegra: dp: Turn link capabilities into booleans Date: Thu, 24 Oct 2019 18:45:06 +0200 Message-Id: <20191024164534.132764-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vuQB447RCY7T9OAh1/C8xr8tJsfjrMuQRccaNwCozL4=; b=giwplgE6Njf9xrIo4JYAkmbD/4cqf5qg7dTt2vsQ6PGNwV6/Id0srPfBRfGuvfHbIJ xTl2Oo3BqO8bZJ0tJJVsPSTyHEUjhUWvz4+5nC+iX5UvHzs+FFU8NkfvO2T4bdrld9Ad rLjabR9tsTaOmfL40m6QmWB1W8/WfvSNmzvPg/9qw2OFFmYZseHY81aJU7afQdAC96Ki JcVV8IAc7dPgEN/eYWJytxdkTITjbBLhPSNg6QwypYgR2d4F8Ij6SOcRHN8i3OQz8jYm Q9gLkYdbjfxFap/fODF4+q1dRkanKd4A1ydhaFNZoWJkDulv6xxnq6JxpIERKDtiv+o2 vNoQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Rather than storing capabilities as flags in an integer, use a separate boolean per capability. This simplifies the code that checks for these capabilities. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 18 +++++++++++++++--- drivers/gpu/drm/tegra/dp.h | 22 +++++++++++++++++++--- drivers/gpu/drm/tegra/sor.c | 4 ++-- 3 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index e55efd46a7d9..e7602fc39a4a 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -8,6 +8,17 @@ #include "dp.h" +static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) +{ + caps->enhanced_framing = false; +} + +void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, + const struct drm_dp_link_caps *src) +{ + dest->enhanced_framing = src->enhanced_framing; +} + static void drm_dp_link_reset(struct drm_dp_link *link) { if (!link) @@ -16,7 +27,8 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->revision = 0; link->max_rate = 0; link->max_lanes = 0; - link->capabilities = 0; + + drm_dp_link_caps_reset(&link->caps); link->rate = 0; link->lanes = 0; @@ -49,7 +61,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; if (values[2] & DP_ENHANCED_FRAME_CAP) - link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; + link->caps.enhanced_framing = true; link->rate = link->max_rate; link->lanes = link->max_lanes; @@ -139,7 +151,7 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) values[0] = drm_dp_link_rate_to_bw_code(link->rate); values[1] = link->lanes; - if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) + if (link->caps.enhanced_framing) values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index ec0342d4c95e..6246f9afb5fe 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -7,16 +7,31 @@ #ifndef DRM_TEGRA_DP_H #define DRM_TEGRA_DP_H 1 +#include + struct drm_dp_aux; -#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) +/** + * struct drm_dp_link_caps - DP link capabilities + */ +struct drm_dp_link_caps { + /** + * @enhanced_framing: + * + * enhanced framing capability (mandatory as of DP 1.2) + */ + bool enhanced_framing; +}; + +void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, + const struct drm_dp_link_caps *src); /** * struct drm_dp_link - DP link capabilities and configuration * @revision: DP specification revision supported on the link * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link - * @capabilities: bitmask of capabilities supported on the link + * @caps: capabilities supported on the link (see &drm_dp_link_caps) * @rate: currently configured link rate * @lanes: currently configured number of lanes */ @@ -24,7 +39,8 @@ struct drm_dp_link { unsigned char revision; unsigned int max_rate; unsigned int max_lanes; - unsigned long capabilities; + + struct drm_dp_link_caps caps; unsigned int rate; unsigned int lanes; diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index dca71250d88c..dd118366455b 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -977,7 +977,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; config->hblank_symbols = div_u64(num, pclk); - if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) + if (link->caps.enhanced_framing) config->hblank_symbols -= 3; config->hblank_symbols -= 12 / link->lanes; @@ -1918,7 +1918,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); - if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) + if (link.caps.enhanced_framing) value |= SOR_DP_LINKCTL_ENHANCED_FRAME; tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); From patchwork Thu Oct 24 16:45:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210269 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FD2F13B1 for ; Thu, 24 Oct 2019 16:46:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 35B8D20659 for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id z15sm25195288wrr.19.2019.10.24.09.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:47 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 05/32] drm/tegra: dp: Probe link using existing parsing helpers Date: Thu, 24 Oct 2019 18:45:07 +0200 Message-Id: <20191024164534.132764-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=abbwhhQgie2zwXLpQrwNZHmhm1e7uRKQChzXAIX90vQ=; b=vXoojypPny2wjvKL3hyDhbkqvgKFOT+etdOa+s8a8OplRP+/bn6EpScpzZFwTv6vLL OojQ16wXU91uAGGQCRFsWL4utnFkBtGbzQwdIQ2A4Hs/OsgcfR44G1BHZFnalxvUAvfz OYe1rrHHoPVeevntjR31NmsQFQBQbuSJg9YzgWFFGXaXWou2amSU7yYfIt0fXbPmewfA qzOVUKYKc2Xc7PSmOdF1zfzNSa96H6344poUNVSSu0FBoGGGZO6iOLdSB/5RBdIjAbKi 6uagfSyySYjK3fuGlBICeDbpu16fMcyIne0Obl/2YE1j456yYWKaxgGIhpzrxg374S1P /rhw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Use existing parsing helpers to probe a DisplayPort link. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index e7602fc39a4a..f9234f66062d 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -47,21 +47,20 @@ static void drm_dp_link_reset(struct drm_dp_link *link) */ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { - u8 values[3]; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; int err; drm_dp_link_reset(link); - err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); + err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); if (err < 0) return err; - link->revision = values[0]; - link->max_rate = drm_dp_bw_code_to_link_rate(values[1]); - link->max_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; + link->revision = dpcd[DP_DPCD_REV]; + link->max_rate = drm_dp_max_link_rate(dpcd); + link->max_lanes = drm_dp_max_lane_count(dpcd); - if (values[2] & DP_ENHANCED_FRAME_CAP) - link->caps.enhanced_framing = true; + link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); link->rate = link->max_rate; link->lanes = link->max_lanes; From patchwork Thu Oct 24 16:45:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB1FF14ED for ; Thu, 24 Oct 2019 16:46:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C363A21D7B for ; Thu, 24 Oct 2019 16:46:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C363A21D7B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 126076E4D2; Thu, 24 Oct 2019 16:46:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id 56CD36E48F for ; Thu, 24 Oct 2019 16:45:52 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id v9so15585163wrq.5 for ; Thu, 24 Oct 2019 09:45:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JHEow/Zl5+7m5KVB2Rml4lhaxLw0XA1AxOO1PkpGdtc=; b=U1blG2ZeWVCS2vLfIrN1fAT8IGGgHakjsW7JV/0+Y/PVUJMtRDDCZJ35Ev6JVqSmpG VZDG8GxsIOV2EDRMnAZqecYvrtYQZ/zgN//3/URDYkWj7gxa5hBeQ01Leu/LyYWEjYBe eDPlvW/QaGdHtkhsy8zZ/P66ngGhM8tCUtSpkai+elW++CP97Qf1FxFckC/MX4twvUxP 2c/ZsBHO8CQB1CBud9osruI39e2crao0wHzgPzN0HKxQM7bYf2VKSsuGLPfgE4gR8Rim 81EZYzlBTj5IZQR/n3ZXqMivl5G36eOTmLRKupxUWs+no8KHqzX+D4TWvyAQ61mOkY4M ZTmA== X-Gm-Message-State: APjAAAUQMSu53GoI4FQ0+GpP+CkhqOYJA1p2lf1OaX3L4Zv/F+QzDuXF JTXwNymykf0XSyeHiRhyS+w= X-Google-Smtp-Source: APXvYqwnrAO1zMBoRxS8dkqIdGXuMX0/xi0kc+5Lq0cTDOs3P869WQW4f/5XMI5t1p6pDADzNyNfSg== X-Received: by 2002:adf:d190:: with SMTP id v16mr4911600wrc.64.1571935550755; Thu, 24 Oct 2019 09:45:50 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id 62sm10661186wre.38.2019.10.24.09.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:49 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 06/32] drm/tegra: dp: Read fast training capability from link Date: Thu, 24 Oct 2019 18:45:08 +0200 Message-Id: <20191024164534.132764-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JHEow/Zl5+7m5KVB2Rml4lhaxLw0XA1AxOO1PkpGdtc=; b=LYgUaVWY/w2p8l5B6g5S0XZNWLGLhSswJGS3no0zLziCxypzsvykd3HXYli8pjBZW1 WhudNHAb+9NBPfo/WcqXxHDgureHA6KYuVLyw2Wt1MwthSyUoeAsx65HTkbz6JQzWouX 9FExQ9Y9KcIwtxYKqO7+lbu7fEclrgmEOHYtFu5rFbBMbcPzNmmJuSGTTaSQ2ubkJ2sc O1JYtZAO3m5tc/7+WM40UxYP+9B3F+Afp02I+xOAompRyFPwEOooqll/W9yZ7p3W8i/X Hn+sEE/riMCwhKLyjgtna6ZBeR5eDhzn3F4QC5eVeSzA8EdsetSwk7m3Z+9nlMBzU7do XYhw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding While probing the DisplayPort link, query the fast training capability. If supported, drivers can use the fast link training sequence instead of the more involved full link training sequence. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 3 +++ drivers/gpu/drm/tegra/dp.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index f9234f66062d..97fc0225483f 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -11,12 +11,14 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; + caps->fast_training = false; } void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, const struct drm_dp_link_caps *src) { dest->enhanced_framing = src->enhanced_framing; + dest->fast_training = src->fast_training; } static void drm_dp_link_reset(struct drm_dp_link *link) @@ -61,6 +63,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->max_lanes = drm_dp_max_lane_count(dpcd); link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); + link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->rate = link->max_rate; link->lanes = link->max_lanes; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 6246f9afb5fe..d6ae477bab5c 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -21,6 +21,13 @@ struct drm_dp_link_caps { * enhanced framing capability (mandatory as of DP 1.2) */ bool enhanced_framing; + + /** + * @fast_training: + * + * AUX CH handshake not required for link training + */ + bool fast_training; }; void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, From patchwork Thu Oct 24 16:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AA8113B1 for ; Thu, 24 Oct 2019 16:46:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52C8A20659 for ; Thu, 24 Oct 2019 16:46:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52C8A20659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 53AC96E49B; Thu, 24 Oct 2019 16:45:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9FE346E48F for ; Thu, 24 Oct 2019 16:45:54 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id z11so3486289wro.11 for ; Thu, 24 Oct 2019 09:45:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W2ba8i6cmLNAVuw9Ax+u8c8Mx7vEOPzpNImQ2Ltx3BU=; b=GWY2swPNu+x7+4+sMSslBbJz/OsvPcLTH9nyY512PgSaEC94pQrI6UShoP/YszNJe0 4Pq/m/bgQu0OjP0g4wzlvRSdCboGSqURZzE441hvyiIq3nYcMBpr1RVXanq4d7jhdkKN l70AzgDqnNFL0FQ2FTjJfFX3Ti05Jm9PUexxErbJLag+CS+HY4NtUp/U/ZeSpi09WKKX /ip4KqxAGkLYfMi9vI62pmLZp0rk3lU0Xifka6iu+JSjc/odn2z0yMc5yu+KcmE4HUQ9 KXI5BipeFJ5M3TyyKc8jcXOw+//lEfdy2eugSOMkdx/VocP+NtY5LYOvSbGWYuMIGB9Z cMBw== X-Gm-Message-State: APjAAAWxAM1pGgboVBtW/Ke4Xu5WWYsd6HL+SplWp9AsqfsjjRD5k4Et KAbkG7o34vJNxSCGifblvwMjXL7i X-Google-Smtp-Source: APXvYqzxAAu40HRGwD/211/4A721vw1pPY68bX60qRMq+Gu+zzY6cblRT/v/7RfYzdUkACAccI9Myw== X-Received: by 2002:a5d:49cf:: with SMTP id t15mr4691068wrs.63.1571935553087; Thu, 24 Oct 2019 09:45:53 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id n1sm31200223wrg.67.2019.10.24.09.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:51 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 07/32] drm/tegra: dp: Read TPS3 capability from sink Date: Thu, 24 Oct 2019 18:45:09 +0200 Message-Id: <20191024164534.132764-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W2ba8i6cmLNAVuw9Ax+u8c8Mx7vEOPzpNImQ2Ltx3BU=; b=k9WJb44yg/elITsDxYJnXcTvdo6WewwN3UuPJc9iOB1Licvzg4FbMNxOVLzfqVPrd7 6YtBLIAosFZE9WAiGJjfPBSOmPvx90IUBe8vXAkcKYfr723hw03CxvIJpDpiaJrdKhF7 K3OAZ2AAof+X8sSSQw+DWZW+7DXT1bum7c9psxevh/w7z35KPtifFHGTQ5dbv+1lg+B0 0SMn1BPvKS5Tw1Hf/Yh+SQMs8iB1N2Pa34oFf1qW6kWhWg0H4bRN+7tohthu/c1qEb5u hOgIyB4a4rgoQ8AbjXDezwqmmzZwp8j6h3KbMDu9P20SV8qJ/HBYHPNe5dFNl1Q9TrJS CGXA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The TPS3 capability can be exposed by DP 1.2 and later sinks if they support the alternative training pattern for channel equalization. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 3 +++ drivers/gpu/drm/tegra/dp.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 97fc0225483f..e22ebab677b9 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -11,6 +11,7 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; + caps->tps3_supported = false; caps->fast_training = false; } @@ -18,6 +19,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, const struct drm_dp_link_caps *src) { dest->enhanced_framing = src->enhanced_framing; + dest->tps3_supported = src->tps3_supported; dest->fast_training = src->fast_training; } @@ -63,6 +65,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->max_lanes = drm_dp_max_lane_count(dpcd); link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); + link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->rate = link->max_rate; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index d6ae477bab5c..999078812943 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -22,6 +22,13 @@ struct drm_dp_link_caps { */ bool enhanced_framing; + /** + * tps3_supported: + * + * training pattern sequence 3 supported for equalization + */ + bool tps3_supported; + /** * @fast_training: * From patchwork Thu Oct 24 16:45:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210267 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13DBC13B1 for ; Thu, 24 Oct 2019 16:46:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F040221906 for ; Thu, 24 Oct 2019 16:46:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F040221906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73C916E4A2; Thu, 24 Oct 2019 16:45:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2ADF86E49B for ; Thu, 24 Oct 2019 16:45:57 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id v6so3287011wmj.0 for ; Thu, 24 Oct 2019 09:45:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N9SI3/7KEnup2lABZq6qRUS5Tek0bF2ZiqM4PxAGcko=; b=S5rUipozM/cV7tBsqfq5sEWhcBLBDS68WUazeBtjM2UmNqV90obRSDUhta6SUYCxRb c9sxsgybP5NLm3sUXKka0P5K8OseuXE4mliRNz+2g5MRMzJR0vLIX7bZyJYH89znAJEp Kc9e0iiMCKLIRIXoVwoeolSH2Z6WldHk7eBO1+3nJU/Crz3RO3DIE5mloJ7mlCfyHrhZ kOKQbSo4JRHQG/8TohDnYh+gfbY9NRN2JxVhcOYpHbSt3HJEFkBqa84Hv5C83Pjfnky3 3z8WYzIkU3Y7Obg8qd7qPqsTz/sfysICgJvd07tBy1ziLurLR3YlHLz+5ePMMOSk3dl/ R3KA== X-Gm-Message-State: APjAAAWfKuaAl0iRiyUkgqr7HjpbOr5uEgOEPd/reEP1L5x2jApbcTS5 jLMilQyuGaSg+JffGUpF8WiMtN8T X-Google-Smtp-Source: APXvYqyv4rA+Hp2xsAFcvJ/wzAlNSBiHkV23Ji4mYrcVhZFeenfluQxWhoiaUWPwAAuh8N2LBeogSg== X-Received: by 2002:a1c:4d14:: with SMTP id o20mr5975598wmh.7.1571935555583; Thu, 24 Oct 2019 09:45:55 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id p17sm22595775wrn.4.2019.10.24.09.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:54 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 08/32] drm/tegra: dp: Read channel coding capability from sink Date: Thu, 24 Oct 2019 18:45:10 +0200 Message-Id: <20191024164534.132764-9-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N9SI3/7KEnup2lABZq6qRUS5Tek0bF2ZiqM4PxAGcko=; b=FEtaRflDCATBZy8YPHJkPoNZVI+yjg+9VjgnqxeMFx6vAZhLUk8mRG8xCoG+d3rNp1 f3VMurZmZPX8x88uMccNkkdt6pmaLN1eDL8FfFsIKr8DcxrZw/0QPQd2xWbgI3Pgg66N D+sZPN7nZA64gJoym+9feP7BEeKm+DdQDlO7HcArGQyY+jIyh0sMJVOI2hYACucjYbsp jghzqa5oel8g7x9wtl5T6fGvdKoUTHU4BpguPWO+txD+e8RFQdEX4mQJ17+xOVJm9Dkq IEX6OPGy9W7qHXurNA3NALVI/QjVSq0IhXeIx/3+5fGiyNbo4lu+WQ0GeB4NSX1D3P93 INYA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Parse from the sink capabilities whether or not it supports ANSI 8B/10B channel coding as specified in ANSI X3.230-1994, clause 11. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 3 +++ drivers/gpu/drm/tegra/dp.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index e22ebab677b9..0bd87cff4575 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -13,6 +13,7 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) caps->enhanced_framing = false; caps->tps3_supported = false; caps->fast_training = false; + caps->channel_coding = false; } void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, @@ -21,6 +22,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, dest->enhanced_framing = src->enhanced_framing; dest->tps3_supported = src->tps3_supported; dest->fast_training = src->fast_training; + dest->channel_coding = src->channel_coding; } static void drm_dp_link_reset(struct drm_dp_link *link) @@ -67,6 +69,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); link->caps.fast_training = drm_dp_fast_training_cap(dpcd); + link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); link->rate = link->max_rate; link->lanes = link->max_lanes; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 999078812943..984dac21568e 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -35,6 +35,13 @@ struct drm_dp_link_caps { * AUX CH handshake not required for link training */ bool fast_training; + + /** + * @channel_coding: + * + * ANSI 8B/10B channel coding capability + */ + bool channel_coding; }; void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, From patchwork Thu Oct 24 16:45:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210275 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AC0C13B1 for ; Thu, 24 Oct 2019 16:46:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 62B3121906 for ; Thu, 24 Oct 2019 16:46:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 62B3121906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 642706E4C1; Thu, 24 Oct 2019 16:46:12 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A8BD6E49A for ; Thu, 24 Oct 2019 16:45:59 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id n7so2776116wmc.3 for ; Thu, 24 Oct 2019 09:45:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lnMOXHki5l5YHT5nhAWPY1kZFjM9Z7XrrlTmxdNtDB8=; b=KnUmaB8upSrs6B9fhz848oRVJ7tVWeL9P47S0pn4oxI2rt+6HuNIffJgItNgnPa4EJ aUo0S+yW4Br6l0lpRGdX59jCP71qCHPn4irYcEJY3zCRgjH1LpOT6Jh+eATeUA7SIPNY uYss1bnSvAZMRboQQBKeNLQJGbxSM+kIXuKW9GmiPV/FNdxENaVkPWjjZn9vEHIbYzCq X2WuIUhWu6BvpP9SjsEyfoa1TJ2PwzPL0Cd7uUHgjJZMBUQjNQaLitYUZvViVhjkAsDg Rqi4L3C5S9Owg9bx1qwt7yzTunpwIx+WGzHeixjC/H2CHipjOHkL81qCwP7CZMtkKjNm PKwA== X-Gm-Message-State: APjAAAWHqczdDdF3Kfwy7yyJgfBO8PndRjsGcu4ccOotBhlWqgZkmA6c WARxdnaOvshZOswpaEikDRc= X-Google-Smtp-Source: APXvYqw+WRepsU1FlsCHgNAsAd5lm7lvHENMKSFTPWEDlyGF4qPLf0sAQvpgB3+/ezT1z1JCgjGw2w== X-Received: by 2002:a7b:c846:: with SMTP id c6mr6040145wml.68.1571935557725; Thu, 24 Oct 2019 09:45:57 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id n1sm31200504wrg.67.2019.10.24.09.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:56 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 09/32] drm/tegra: dp: Read alternate scrambler reset capability from sink Date: Thu, 24 Oct 2019 18:45:11 +0200 Message-Id: <20191024164534.132764-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lnMOXHki5l5YHT5nhAWPY1kZFjM9Z7XrrlTmxdNtDB8=; b=T1gviikxvQIZr4jUM5jOqCz7ZYaO2amBvBHkxQ9hUN7Gei22idMJIbafztcB1cr7xa Leg4mcQR+OYjxmkWE35DlP9bpJzLBz3aLVsW6H68iyWX/y+k1VW9q0SpRlVXiVafD3oX QWuY+IiIpRl0iyqNk2aHiUjMv7krelyaja2UVgCS0Un4+qA9GUQVwTDaTQXoz08p+Kjw xFC1jw3OuusUFT5PeL9u+GUzboK8lc/i72Sn2cwb2zPl6He04UuV3jsD+OKaQDMl9zWg Z2kWEewZqDKvnC5oc01HgDLjauQK9fxc4eABw+JR6R+oakdjBBsWEWyjgLm0W2imCPdA QjGQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Parse from the sink capabilities whether or not the eDP alternate scrambler reset value of 0xfffe is supported. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 5 +++++ drivers/gpu/drm/tegra/dp.h | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 0bd87cff4575..1f48c2190e3b 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -14,6 +14,7 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) caps->tps3_supported = false; caps->fast_training = false; caps->channel_coding = false; + caps->alternate_scrambler_reset = false; } void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, @@ -23,6 +24,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, dest->tps3_supported = src->tps3_supported; dest->fast_training = src->fast_training; dest->channel_coding = src->channel_coding; + dest->alternate_scrambler_reset = src->alternate_scrambler_reset; } static void drm_dp_link_reset(struct drm_dp_link *link) @@ -71,6 +73,9 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); + if (drm_dp_alternate_scrambler_reset_cap(dpcd)) + link->caps.alternate_scrambler_reset = true; + link->rate = link->max_rate; link->lanes = link->max_lanes; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 984dac21568e..45e8ff18ab6a 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -42,6 +42,13 @@ struct drm_dp_link_caps { * ANSI 8B/10B channel coding capability */ bool channel_coding; + + /** + * @alternate_scrambler_reset: + * + * eDP alternate scrambler reset capability + */ + bool alternate_scrambler_reset; }; void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, From patchwork Thu Oct 24 16:45:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12C0A1747 for ; Thu, 24 Oct 2019 16:46:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEEB420659 for ; Thu, 24 Oct 2019 16:46:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EEEB420659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D400D6E4C9; Thu, 24 Oct 2019 16:46:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id 257F06E4BB for ; Thu, 24 Oct 2019 16:46:02 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id q13so21890205wrs.12 for ; Thu, 24 Oct 2019 09:46:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yty/EJuHbPo+sV+vw2W6VylZ7J8vhVAzp70Ulfh9+0w=; b=sH3WyTrPYHhxPQak8qoSkfUrp35mW7SnqTj5B6TEecgllUE+jqcHWtcGzykf3q6ekc AI4iHj9NkgTcyvKNdP7rOA9+3DFqAyu+XnnXy9ZZuDxjCflLXlkd5iD2a+V9Pp1mR++H FnkIlRpYO2AHr/VWFRUP2/Df+lqrargqMj/mF4/uovawya3r5aMCj0NokUDX3xi7CASJ nGnTM75b2waFYVroY3AyWyPipVZbDqUSr9FmX6V78Fzs7yVeaexLNjcxAxC0i8rXhDDg 2rsTTB9QLaJWJMau5gYwWBVhPxlT9FWFZLP/phSGxKVktzpOX6WHxJ1hXXCQQx5g2W6y spsg== X-Gm-Message-State: APjAAAX1ya44gOzGA6R8UVceKNjTSbeMlKnWR3FG6b52meHWd3klg1Om VaGxkWsT2aOuf42q7CcBSik= X-Google-Smtp-Source: APXvYqwCFC6iF6CMbRgp6QF+yXHQtCqN51M4/rI8h1YavptNKwRXtJXI6zlQTsvG9F9hgqpdktAg3A== X-Received: by 2002:adf:a48c:: with SMTP id g12mr4473270wrb.212.1571935559735; Thu, 24 Oct 2019 09:45:59 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id p1sm3658391wmg.11.2019.10.24.09.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:45:58 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 10/32] drm/tegra: dp: Read eDP version from DPCD Date: Thu, 24 Oct 2019 18:45:12 +0200 Message-Id: <20191024164534.132764-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yty/EJuHbPo+sV+vw2W6VylZ7J8vhVAzp70Ulfh9+0w=; b=XhRXcDJ0B/zJO6GUyxCfZStm1mqzsaFnI3qf5hqPARKj4v55F4UNEGAjVr07eQlZTL tDugAZbbwl6PGa3htJmzf3TLaVtra2qQ4c9v7k8rWCo9PaJKp0DXmuidAWxXX2lX9ast i0ohrEAkh/HoQ34k6OO824pIXjXXZP4i9y1HmGkpEgD1EMNdTQvgSGWl+w4PnnSJleFN 6zfA+e2pHLLZH/SUiF3V3iiXVKprW5bVKt8+d5rMmQMc3uL0TYdtMtQdXfLSFKiqqbQC 7z80ZtPNugV3exg1SPmfmqyiNXmsY8U/+cUKVcegxbZur1hMwIzwG3gY6u7W3hGWH9WF FruQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding If the sink supports eDP, read the eDP revision from it's DPCD. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 18 ++++++++++++++++-- drivers/gpu/drm/tegra/dp.h | 2 ++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 1f48c2190e3b..2be0a47ecbec 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -5,9 +5,12 @@ */ #include +#include #include "dp.h" +static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 }; + static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) { caps->enhanced_framing = false; @@ -37,6 +40,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->max_lanes = 0; drm_dp_link_caps_reset(&link->caps); + link->edp = 0; link->rate = 0; link->lanes = 0; @@ -55,7 +59,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) */ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { - u8 dpcd[DP_RECEIVER_CAP_SIZE]; + u8 dpcd[DP_RECEIVER_CAP_SIZE], value; int err; drm_dp_link_reset(link); @@ -73,9 +77,19 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); - if (drm_dp_alternate_scrambler_reset_cap(dpcd)) + if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { link->caps.alternate_scrambler_reset = true; + err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value); + if (err < 0) + return err; + + if (value >= ARRAY_SIZE(drm_dp_edp_revisions)) + DRM_ERROR("unsupported eDP version: %02x\n", value); + else + link->edp = drm_dp_edp_revisions[value]; + } + link->rate = link->max_rate; link->lanes = link->max_lanes; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 45e8ff18ab6a..681cbd0a0094 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -60,6 +60,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) + * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes */ @@ -69,6 +70,7 @@ struct drm_dp_link { unsigned int max_lanes; struct drm_dp_link_caps caps; + unsigned char edp; unsigned int rate; unsigned int lanes; From patchwork Thu Oct 24 16:45:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210291 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B0FF14ED for ; Thu, 24 Oct 2019 16:46:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 325B621A4C for ; Thu, 24 Oct 2019 16:46:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 325B621A4C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23F686E4FB; Thu, 24 Oct 2019 16:46:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D33B6E4BA for ; Thu, 24 Oct 2019 16:46:04 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id r141so3262326wme.4 for ; Thu, 24 Oct 2019 09:46:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eF+YcAgQiBm0mPw0I9xhh8vL6WGqhRLDBDhFt2a9/Oc=; b=fgjRZWNfk4WmQyfzUyjOiwLIiPyiHyZKTS2zjj0FyPsoDWaG0IxsYMQ7tuKslOIFD6 FgT2RN0H7pLt3rXXGRyuDvItduYYA63z1w8FZQ7Cw+rxXktGUgKtY8rdof7KdN6sjj0R Cto8E5BRVsOjhQ6yJErXKzeRO/uKBRnFWlxlEjaL4a5h166cuNylrUa361oy5KkchBRd X2LtGZdJL11Fw6XhjV7X/0pbolkZSycUnJ0s/dnPa3MiBfu06hj30BgB2PcV97ToVJFQ TouemowOBNhnMF8nPIhga19YhtMHuTgmKTg0ohByfbzik+h594XjzNxd/FtLMMoGQR5z K1uA== X-Gm-Message-State: APjAAAU2QlApOUPYbfw9A+k2EyBEVE1jFBp7MwwLvIQ5nxiBWhsbb209 0wT7ZKYNHI+3EnBAFtKyc6gEDuN/ X-Google-Smtp-Source: APXvYqxOgnq4flJoy7BqWhlvmgY1DBITgCFfSAP79ZN7v9S/Q2oJCN4+sXhRdqB3KX2X0POCsolqtQ== X-Received: by 2002:a05:600c:242:: with SMTP id 2mr5550632wmj.73.1571935561964; Thu, 24 Oct 2019 09:46:01 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id l8sm10077273wru.22.2019.10.24.09.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:00 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 11/32] drm/tegra: dp: Read AUX read interval from DPCD Date: Thu, 24 Oct 2019 18:45:13 +0200 Message-Id: <20191024164534.132764-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eF+YcAgQiBm0mPw0I9xhh8vL6WGqhRLDBDhFt2a9/Oc=; b=M6jfENkJo3FjTB+X/IJHkMe4ddP++PDR0rga1S9dy1uyza5fuVQKXcRtgUnVACgKhY sQgRCQB7V6p0YFmecfOpST9/p7EXxpfaxWyFyBRpWeS8iBw8PfvOQoAglILacNQUD+lO PLU3YYhIGL5D6MSxJ7RsBsDi5rWhzIE7XgBFWejgZaTr5ZJwlqBPLyvOLUoTCF5rYCiu hX5IUCfV4tuQhu9odM5FL3ZkIo/5yLTfZbXHwG5XJHS8LYFsvgYmrjWaIVfO8fHGVm3b mu7u41K80lymQ12sjrmx6TuRydFxrJWA6+xSqbud4OrRmEsPybx7Y9EcpmMKvl0ArjCC Arnw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Store the AUX read interval from DPCD, so that it can be used to wait for the durations given in the specification during link training. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dp.h | 11 +++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 2be0a47ecbec..757a0256592f 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -40,6 +40,8 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->max_lanes = 0; drm_dp_link_caps_reset(&link->caps); + link->aux_rd_interval.cr = 0; + link->aux_rd_interval.ce = 0; link->edp = 0; link->rate = 0; @@ -60,6 +62,7 @@ static void drm_dp_link_reset(struct drm_dp_link *link) int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) { u8 dpcd[DP_RECEIVER_CAP_SIZE], value; + unsigned int rd_interval; int err; drm_dp_link_reset(link); @@ -90,6 +93,34 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->edp = drm_dp_edp_revisions[value]; } + /* + * The DPCD stores the AUX read interval in units of 4 ms. There are + * two special cases: + * + * 1) if the TRAINING_AUX_RD_INTERVAL field is 0, the clock recovery + * and channel equalization should use 100 us or 400 us AUX read + * intervals, respectively + * + * 2) for DP v1.4 and above, clock recovery should always use 100 us + * AUX read intervals + */ + rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) { + DRM_DEBUG_KMS("AUX interval %u out of range (max. 4)\n", + rd_interval); + rd_interval = 4; + } + + rd_interval *= 4 * USEC_PER_MSEC; + + if (rd_interval == 0 || link->revision >= DP_DPCD_REV_14) + link->aux_rd_interval.cr = 100; + + if (rd_interval == 0) + link->aux_rd_interval.ce = 400; + link->rate = link->max_rate; link->lanes = link->max_lanes; diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 681cbd0a0094..1fe2d4f45ba3 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -60,6 +60,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @max_rate: maximum clock rate supported on the link * @max_lanes: maximum number of lanes supported on the link * @caps: capabilities supported on the link (see &drm_dp_link_caps) + * @aux_rd_interval: AUX read interval to use for training (in microseconds) * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes @@ -70,6 +71,16 @@ struct drm_dp_link { unsigned int max_lanes; struct drm_dp_link_caps caps; + + /** + * @cr: clock recovery read interval + * @ce: channel equalization read interval + */ + struct { + unsigned int cr; + unsigned int ce; + } aux_rd_interval; + unsigned char edp; unsigned int rate; From patchwork Thu Oct 24 16:45:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210273 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89A4514ED for ; Thu, 24 Oct 2019 16:46:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7214021906 for ; Thu, 24 Oct 2019 16:46:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7214021906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8867A6E4BA; Thu, 24 Oct 2019 16:46:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id C46F86E4BA for ; Thu, 24 Oct 2019 16:46:05 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id g7so3594378wmk.4 for ; Thu, 24 Oct 2019 09:46:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6VLoJyLaTalvPJTjL4ZURLjR521ZUnRyrnLxHevvRaM=; b=cTKQtEuvPmQzxor7nM8k4vtMvwGwPeQ8m14fvihny45l3pu0/1oi2eaEz7E6yFh73p DTQyZEFuMoZWuIZ7YcaLQt9c+XC3iqo5qcB7ZBfRHgAIKZrW62SsFwdiqhAZeLL+jDGl t6HdrPTD2ReNuM5UBQpuxJoT8KTW6kBZ9L1d0xx2UxakMAMLvYTTUXJWIN1kdLrxBLbH WZzD8btrw1jXqdZxHiU8T6UsdQ2difGpSKdqCokQamYDNPXWKz9wsRXq6G8IsQJc9Dn3 D2YVLlK6aSFOf5/wgFRA3IK9lsHkkQOkhJDCnhCveTDdhDOPjAzotJT9jqqXOGuUOvZ0 7/WQ== X-Gm-Message-State: APjAAAWkvkbHCBlvGxWH0Ub/STsP6LYznYfbV0St2dUSLj+PXnmqJuCR rAsU4xwM8Rz+ryy0yLQkMOk= X-Google-Smtp-Source: APXvYqxCTYIc2lo6yAMdPgmEf2fXBJegbWiE+vuDuM6/LyEQ4pIB1jN8pr9bOLLxm3tv/4q5/MdPUQ== X-Received: by 2002:a05:600c:294b:: with SMTP id n11mr5546291wmd.70.1571935563958; Thu, 24 Oct 2019 09:46:03 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id h205sm3542137wmf.35.2019.10.24.09.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:03 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 12/32] drm/tegra: dp: Set channel coding on link configuration Date: Thu, 24 Oct 2019 18:45:14 +0200 Message-Id: <20191024164534.132764-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6VLoJyLaTalvPJTjL4ZURLjR521ZUnRyrnLxHevvRaM=; b=ehcQLQC5E+gvhhTIBrAdm6Wp2/fRl3wMgXLryA6knIosKQs1Na6Bt/uu5kXL7Z6iiW mVWQqcBO99ZsOdf9dgdA77VZli/eOXxbVcSEogQlhRkgXuUpfAEMWBQZqSj9gvOdxTLC qyvrexZMfLD8VSwaEFzMwNuRnhvCV8eFaaVi0/9SIBNXzEvXSjmh0gn+uLDIfGSoRQDD lP0CAyiXbUkAVsoDdzN92q1JYA71izNNQuOgtGtJyG+vZVB9Wj3GyQBToXHkM5m6PJm3 WhasXUy+NPrhNnivV1XTd695MMrSTusHzVwrsmvABp6DIxiUSa4TYYXfbbVA4sCGzcqi pVdg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Make use of ANSI 8B/10B channel coding if the DisplayPort sink supports it. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 757a0256592f..ca287b50fad8 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -203,7 +203,7 @@ int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link) */ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) { - u8 values[2]; + u8 values[2], value; int err; values[0] = drm_dp_link_rate_to_bw_code(link->rate); @@ -216,5 +216,14 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) if (err < 0) return err; + if (link->caps.channel_coding) + value = DP_SET_ANSI_8B10B; + else + value = 0; + + err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value); + if (err < 0) + return err; + return 0; } From patchwork Thu Oct 24 16:45:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8628814ED for ; Thu, 24 Oct 2019 16:46:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A71421929 for ; Thu, 24 Oct 2019 16:46:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6A71421929 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FAE46E4B0; Thu, 24 Oct 2019 16:46:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E73B6E4BA for ; Thu, 24 Oct 2019 16:46:08 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id g24so3592884wmh.5 for ; Thu, 24 Oct 2019 09:46:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v7sIBy+NeFxNLTjK62J325/VvVdEVUMB1reiPu3pIc8=; b=ShH6gxUNIMVXwrw5awm7XMbMTlx8GFLuNBnqZwCLOIU/nmqdmE76iJwjZmZvngVRsL vmpWhWLD+uSJjInS9dLetAANbBU5h/LwX22EsKvFZJBUb7ERY/18n1tnrYQZCDpDa7ps PEree52n5A+Jxh8+flD0tsF2BHSbLQQaO8fkPsxbBfT4ggZoaQR/8uIE3vfqBoktOjTF IOLriEd3/6OZ2wwfHoYJw9Vbm7ubFRSA+Q0JUQLHw23XZUHk4ULhNYA+M5tr9fDo0Fu9 2/ImEUeN7aDBt4iJ7twFc2c0AYRVZr4+BMV8wzDzhGF5gsx+R4/zRsve0qJmfzIdNJHR Q7Tg== X-Gm-Message-State: APjAAAXHeaQ+vk2UG0k0Y79Pa20vSVAyGQqUeYwNwV072KzUDRnnG5iI 6gQcjizcwyK3encwwXnPzY8= X-Google-Smtp-Source: APXvYqzNMQfQSe21eo66v5s9QJVWKaQWzPmmQo+HbPGXpXR1lqS8E7bqjTx+spu0jHtb5iCHVx5TQQ== X-Received: by 2002:a1c:41c1:: with SMTP id o184mr6063460wma.81.1571935565957; Thu, 24 Oct 2019 09:46:05 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id r3sm42193380wre.29.2019.10.24.09.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:05 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 13/32] drm/tegra: dp: Enable alternate scrambler reset when supported Date: Thu, 24 Oct 2019 18:45:15 +0200 Message-Id: <20191024164534.132764-14-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v7sIBy+NeFxNLTjK62J325/VvVdEVUMB1reiPu3pIc8=; b=h2AkK8Fk42hDKnysvCBeOGI1jEnFs/G/r+XJcTwS4ymT5ODIFNyQGWEPknw1kx6V1i QvibakSkAbdHHpT/L0egKH5XsGcX3ntr5VS6QASDLiVIMdWCu/qyhl3VPTjyxxWlZeqC cOq9PCsJoRIxzwcVaEr8zdDrUnLtzWVS6j8cwzry2JAghgu4Mqv195T3aqMefkZXmqOq tuXucWEQY6Bu+nxz1OKB7RiMKmlmG1QvfI2QQgnC41DDD0SnD0WyaFqc99T0fe/TVlVR GmwRL/ZxJxF70qpNaXSAIoTzag4cTjaKdDo3vvHKZp5iXkdpMtg0l5JksOTvwQi8KN8s sTNQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding If the sink is eDP and supports the alternate scrambler reset, enable it. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index ca287b50fad8..638081b568f4 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -225,5 +225,12 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) if (err < 0) return err; + if (link->caps.alternate_scrambler_reset) { + err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, + DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); + if (err < 0) + return err; + } + return 0; } From patchwork Thu Oct 24 16:45:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210279 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5641F1747 for ; Thu, 24 Oct 2019 16:46:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E87821906 for ; Thu, 24 Oct 2019 16:46:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3E87821906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CA496E4BB; Thu, 24 Oct 2019 16:46:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9651A6E4BA for ; Thu, 24 Oct 2019 16:46:09 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id t16so21734004wrr.1 for ; Thu, 24 Oct 2019 09:46:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4lRUdhvbauplkpd4/zSVY6YswIkikfBSoscbfTPm6A=; b=glW70t6vlQTiX+sVTBdT5txLN+OdEv1OyKcHRrR3SUj+k8O9DWcieN2FlNJYoKZn/d AszmGRt9eJt/pBElBNo0dIr5DtGOXTueQLzrFPjLTiNNPNZszUuL6vy15Mc2uW/cnTHG /swo+O4pN7H+VtMXuSevho/694Gx6ItzfmY0xzGQ7FlJPNSytsccQPCcilQ5UsZi5rRx Kd+tKy9DbXtL99cNxl0ARRxKsh/530kNAEdJ+Bt+nf+S/9oxeZEvjCaoUpJZQe68ij7j AyZLdZcr65K1f5k70e4/Yx53VXKPYbRUcoVODqlqxdgpfs1FddEgiDcdeooe/OV5KADs DBqQ== X-Gm-Message-State: APjAAAXsaYtSoaXAP+tIxHsh6l3qB+3UeEq/dzacLKQ2KF8uRGidD003 KAVm8fMDZZ3NhpgnhtntFaIqznQB X-Google-Smtp-Source: APXvYqxghvX8VIL9TX0Ql3qna64+KUMLlY0Ct0J2y1K44HN6eoCXOu8q79Te3MUH6bA+ZQZdaU3Wew== X-Received: by 2002:adf:fe10:: with SMTP id n16mr4995376wrr.288.1571935568004; Thu, 24 Oct 2019 09:46:08 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id u1sm2526372wmc.38.2019.10.24.09.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:06 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 14/32] drm/tegra: dp: Add drm_dp_link_choose() helper Date: Thu, 24 Oct 2019 18:45:16 +0200 Message-Id: <20191024164534.132764-15-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F4lRUdhvbauplkpd4/zSVY6YswIkikfBSoscbfTPm6A=; b=us02LvLyl9MstWWZI+3sQezky6sgukEOfdq9wVIaT3dAjByyV2942Jrzhjtl21DI7w SUnGEzvgbXAhyKIb/D5MaqmUPy4Og9oRmYO9v6WWnbuTEJOUEFH71bzHDoQ/9UTNI+A+ qMUyxyavj3ZnVJzZWilqZbbplLyfy4ltlt2Z40czShEH3HivFXv89kF+VfpeZJMUHC9M 8RrTl77Y304hFn2I5S/5jIr/llCQjd/WU88VBoBDxcWxa2ORcOWgG4BzBtz05nSXDcCD OhFDWpvxExMYgMPxOK6vQwuUzWRLWnjm3Gt8ALkXguSSe1z+ETJajoI+Vm67QEgIa6Uq H9xQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding This helper chooses an appropriate configuration, according to the bitrate requirements of the video mode and the capabilities of the DisplayPort sink. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 55 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dp.h | 5 ++++ 2 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 638081b568f4..e9a5db77a2dc 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -4,6 +4,7 @@ * Copyright (C) 2015 Rob Clark */ +#include #include #include @@ -234,3 +235,57 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) return 0; } + +/** + * drm_dp_link_choose() - choose the lowest possible configuration for a mode + * @link: DRM DP link object + * @mode: DRM display mode + * @info: DRM display information + * + * According to the eDP specification, a source should select a configuration + * with the lowest number of lanes and the lowest possible link rate that can + * match the bitrate requirements of a video mode. However it must ensure not + * to exceed the capabilities of the sink. + * + * Returns: 0 on success or a negative error code on failure. + */ +int drm_dp_link_choose(struct drm_dp_link *link, + const struct drm_display_mode *mode, + const struct drm_display_info *info) +{ + /* available link symbol clock rates */ + static const unsigned int rates[3] = { 162000, 270000, 540000 }; + /* available number of lanes */ + static const unsigned int lanes[3] = { 1, 2, 4 }; + unsigned long requirement, capacity; + unsigned int rate = link->max_rate; + unsigned int i, j; + + /* bandwidth requirement */ + requirement = mode->clock * info->bpc * 3; + + for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { + for (j = 0; j < ARRAY_SIZE(rates) && rates[j] <= rate; j++) { + /* + * Capacity for this combination of lanes and rate, + * factoring in the ANSI 8B/10B encoding. + * + * Link rates in the DRM DP helpers are really link + * symbol frequencies, so a tenth of the actual rate + * of the link. + */ + capacity = lanes[i] * (rates[j] * 10) * 8 / 10; + + if (capacity >= requirement) { + DRM_DEBUG_KMS("using %u lanes at %u kHz (%lu/%lu kbps)\n", + lanes[i], rates[j], requirement, + capacity); + link->lanes = lanes[i]; + link->rate = rates[j]; + return 0; + } + } + } + + return -ERANGE; +} diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index 1fe2d4f45ba3..e07b9a1e43d8 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -9,6 +9,8 @@ #include +struct drm_display_info; +struct drm_display_mode; struct drm_dp_aux; /** @@ -91,5 +93,8 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); +int drm_dp_link_choose(struct drm_dp_link *link, + const struct drm_display_mode *mode, + const struct drm_display_info *info); #endif From patchwork Thu Oct 24 16:45:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3B8714ED for ; Thu, 24 Oct 2019 16:46:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B4CD20679 for ; Thu, 24 Oct 2019 16:46:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B4CD20679 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F00796E4D0; Thu, 24 Oct 2019 16:46:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74A5C6E4C4 for ; Thu, 24 Oct 2019 16:46:12 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id p4so26869590wrm.8 for ; Thu, 24 Oct 2019 09:46:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZmA4CCQ3zKG7QoqtlGNTQGTEdWNG2D4PniESW4LhASE=; b=Eq/y/FezfWRrLnFpIEf3wSlv+jMx3gGSwo4MWfPqmBW4JTaBRZyFBO1WHisLKMzZBx MIVeDjtHoNzWuP7zhB9eQazAF4cZhtNcv23dGQTjQSbAWk51/wwOxTENdpoJoOSexuwz 2O0OlsrxqrB3hGLJZobbXf9ivFHKbL1S63MlH7buZ9pNRNFjF3lwUensL01O2gR7i/UD f/LGWLZ/kqicezFrOnC+4Dgey0nhj9Z62fUiFwbUzTxDYXdN8GDO3CiIiuQpE21ve0qV CFC0kG3ELqgWcUOcb2ua2G2daekCzqJERHBkZW/hQ353GYX0U/POKKz15f590669+dEE y6ag== X-Gm-Message-State: APjAAAVK38oQEsVwwoYTXp0eurDuBrp8XYAzRBm18rI9KnfL1o7EbDVJ HirGTLhjRyf/1XKoltyFh+E= X-Google-Smtp-Source: APXvYqyH/0NeQY+42spVg1z2IjJVsOvpIuMFgks8UGun/fp1nCfAHu/yMIbrC3S2ZU3ULFlM4t72Ug== X-Received: by 2002:adf:9f08:: with SMTP id l8mr4500171wrf.325.1571935570614; Thu, 24 Oct 2019 09:46:10 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id y1sm29072699wrw.6.2019.10.24.09.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:09 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 15/32] drm/tegra: dp: Add support for eDP link rates Date: Thu, 24 Oct 2019 18:45:17 +0200 Message-Id: <20191024164534.132764-16-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZmA4CCQ3zKG7QoqtlGNTQGTEdWNG2D4PniESW4LhASE=; b=MbJRPFT36/d6lD1Yv6VGcEWxYAtG+W2eMU8WZXpifEbv4Ko1LJmKrZHv64DWhwjJ4X Wo6gN06pmq70cRoQwxDA5iEqKx1n/btinPa+hAu5UzZ7/aY8qbfuSfNWSCBckoN3eDwo Yy5UAAa+ou7GnkOoUx4dw1YYodX8lkkiN1oFu4i71s1DSxB3KjAaUXHAdtZzoJkTNsuB Oev+s7myrSfmsF35MTlPB8RiOfznxGsyF4k8kzj8J9WMxa4XR6NUZUudA9D/A2EiJlTk bDIaZVkPDbiwwXkA3x7OcA3+S+DLdnVqqPwwDjJlrW/posDNZVOCNoQUq0eZf+scGyRc zwEw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Parses additional link rates from DPCD if the sink supports eDP 1.4. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 127 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dp.h | 9 +++ 2 files changed, 136 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index e9a5db77a2dc..bcf9df965ef8 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -33,6 +33,8 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, static void drm_dp_link_reset(struct drm_dp_link *link) { + unsigned int i; + if (!link) return; @@ -47,6 +49,111 @@ static void drm_dp_link_reset(struct drm_dp_link *link) link->rate = 0; link->lanes = 0; + + for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++) + link->rates[i] = 0; + + link->num_rates = 0; +} + +/** + * drm_dp_link_add_rate() - add a rate to the list of supported rates + * @link: the link to add the rate to + * @rate: the rate to add + * + * Add a link rate to the list of supported link rates. + * + * Returns: + * 0 on success or one of the following negative error codes on failure: + * - ENOSPC if the maximum number of supported rates has been reached + * - EEXISTS if the link already supports this rate + * + * See also: + * drm_dp_link_remove_rate() + */ +int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate) +{ + unsigned int i, pivot; + + if (link->num_rates == DP_MAX_SUPPORTED_RATES) + return -ENOSPC; + + for (pivot = 0; pivot < link->num_rates; pivot++) + if (rate <= link->rates[pivot]) + break; + + if (pivot != link->num_rates && rate == link->rates[pivot]) + return -EEXIST; + + for (i = link->num_rates; i > pivot; i--) + link->rates[i] = link->rates[i - 1]; + + link->rates[pivot] = rate; + link->num_rates++; + + return 0; +} + +/** + * drm_dp_link_remove_rate() - remove a rate from the list of supported rates + * @link: the link from which to remove the rate + * @rate: the rate to remove + * + * Removes a link rate from the list of supported link rates. + * + * Returns: + * 0 on success or one of the following negative error codes on failure: + * - EINVAL if the specified rate is not among the supported rates + * + * See also: + * drm_dp_link_add_rate() + */ +int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate) +{ + unsigned int i; + + for (i = 0; i < link->num_rates; i++) + if (rate == link->rates[i]) + break; + + if (i == link->num_rates) + return -EINVAL; + + link->num_rates--; + + while (i < link->num_rates) { + link->rates[i] = link->rates[i + 1]; + i++; + } + + return 0; +} + +/** + * drm_dp_link_update_rates() - normalize the supported link rates array + * @link: the link for which to normalize the supported link rates + * + * Users should call this function after they've manually modified the array + * of supported link rates. This function removes any stale entries, compacts + * the array and updates the supported link rate count. Note that calling the + * drm_dp_link_remove_rate() function already does this janitorial work. + * + * See also: + * drm_dp_link_add_rate(), drm_dp_link_remove_rate() + */ +void drm_dp_link_update_rates(struct drm_dp_link *link) +{ + unsigned int i, count = 0; + + for (i = 0; i < link->num_rates; i++) { + if (link->rates[i] != 0) + link->rates[count++] = link->rates[i]; + } + + for (i = count; i < link->num_rates; i++) + link->rates[i] = 0; + + link->num_rates = count; } /** @@ -125,6 +232,26 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->rate = link->max_rate; link->lanes = link->max_lanes; + /* Parse SUPPORTED_LINK_RATES from eDP 1.4 */ + if (link->edp >= 0x14) { + u8 supported_rates[DP_MAX_SUPPORTED_RATES * 2]; + unsigned int i; + u16 rate; + + err = drm_dp_dpcd_read(aux, DP_SUPPORTED_LINK_RATES, + supported_rates, + sizeof(supported_rates)); + if (err < 0) + return err; + + for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++) { + rate = supported_rates[i * 2 + 1] << 8 | + supported_rates[i * 2 + 0]; + + drm_dp_link_add_rate(link, rate * 200); + } + } + return 0; } diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index e07b9a1e43d8..a20ee9f1f1b6 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -66,6 +66,8 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) * @rate: currently configured link rate * @lanes: currently configured number of lanes + * @rates: additional supported link rates in kHz (eDP 1.4) + * @num_rates: number of additional supported link rates (eDP 1.4) */ struct drm_dp_link { unsigned char revision; @@ -87,8 +89,15 @@ struct drm_dp_link { unsigned int rate; unsigned int lanes; + + unsigned long rates[DP_MAX_SUPPORTED_RATES]; + unsigned int num_rates; }; +int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate); +int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate); +void drm_dp_link_update_rates(struct drm_dp_link *link); + int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); From patchwork Thu Oct 24 16:45:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210281 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C51D13B1 for ; Thu, 24 Oct 2019 16:46:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13FEB21A4C for ; Thu, 24 Oct 2019 16:46:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 13FEB21A4C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A8C46E4C4; Thu, 24 Oct 2019 16:46:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3D8026E4BB for ; Thu, 24 Oct 2019 16:46:15 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id c2so21631868wrr.10 for ; Thu, 24 Oct 2019 09:46:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=joZo+BWPZThfhlDpKBzdXgwzEqvhDB4Lk+BS10COeWA=; b=tuIHHnXjYod8ucYdvIgl25Oo230XFJ0ht1Y2VwrfjRMTxRixP2Om5ls1N8wbZNtSQo rk5Lb95G3JVTFZRsTEI39LoucKGiVeAqM5CUimW8TtinOWdBl1SjsLe23F6yg123VtX+ LbtAwGyrka7IfQLZM1fqkzHA/4Ku+/Q+2LyYEIYoGFzOOo1yZg7H++qFUfl2gwI7vL4B UXG2F7U71IndiumisaAA3pXFggxPt8EMzhig+9bTkfP477ffvntJGeBp5AZfyTu/0WNd ZfFxDDnv5Rw3zSuxBvvKtCgszpfUSHKWcBxveNyF5v/20I0mvXUg9DISPjPqPrrdqzPW Brdg== X-Gm-Message-State: APjAAAUkx7/QiAd9f9rFwMu1a1ekaZ4OCr2kQJwBV6I5OYuUlRpnhSIF 5RueCbkAiQgzjjlFYs/X7hQ= X-Google-Smtp-Source: APXvYqwkz9er/GhH6UB4gPyOoVw5v+gKNFltNjnWjyMG0M9HlRp8R3/SfBp1DWCLyUm06LWse8J48A== X-Received: by 2002:a5d:544b:: with SMTP id w11mr4744025wrv.205.1571935573338; Thu, 24 Oct 2019 09:46:13 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id r81sm3058153wme.16.2019.10.24.09.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:11 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 16/32] drm/tegra: dp: Add DisplayPort link training helper Date: Thu, 24 Oct 2019 18:45:18 +0200 Message-Id: <20191024164534.132764-17-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=joZo+BWPZThfhlDpKBzdXgwzEqvhDB4Lk+BS10COeWA=; b=E70YqYgU5PCSYUtPQSiG2KMOz64dncOipa29l7T1Yl/4NJ3pIxIspzO8Yn2XwCt0mQ +W70ldmjgk6pIdGWUm9JD14EW8P2qIM1TZFtgBhJXcYFIF+Ut7ynFfWTmxAtwxQ4Xkb/ lUTosN1bbQTjkUAxwx0mxUxnn2t8T8GNzHsBuCPD79kORmxCjN1JMGZZ77ZcSZpwNfmY HGLPUwnKTMjVjBINQi+zaMmI9OeGTkR9dTNGqCAakLDPke37SEMEKqkacNj8cR+yBiXT vny45FXJ1pujQec3ZKVCRiU6Au9SeZLFrLczeGIkYvykVS3CVL0HUcef/aS8LcI2SWFq zhow== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Add a helper that will perform link training as described in the DisplayPort specification. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 456 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dp.h | 68 ++++++ 2 files changed, 524 insertions(+) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index bcf9df965ef8..5b6765d653b4 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -334,6 +334,14 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) u8 values[2], value; int err; + if (link->ops && link->ops->configure) { + err = link->ops->configure(link); + if (err < 0) { + DRM_ERROR("failed to configure DP link: %d\n", err); + return err; + } + } + values[0] = drm_dp_link_rate_to_bw_code(link->rate); values[1] = link->lanes; @@ -416,3 +424,451 @@ int drm_dp_link_choose(struct drm_dp_link *link, return -ERANGE; } + +/** + * DOC: Link training + * + * These functions contain common logic and helpers to implement DisplayPort + * link training. + */ + +/** + * drm_dp_link_train_init() - initialize DisplayPort link training state + * @train: DisplayPort link training state + */ +void drm_dp_link_train_init(struct drm_dp_link_train *train) +{ + struct drm_dp_link_train_set *request = &train->request; + struct drm_dp_link_train_set *adjust = &train->adjust; + unsigned int i; + + for (i = 0; i < 4; i++) { + request->voltage_swing[i] = 0; + adjust->voltage_swing[i] = 0; + + request->pre_emphasis[i] = 0; + adjust->pre_emphasis[i] = 0; + + request->post_cursor[i] = 0; + adjust->post_cursor[i] = 0; + } + + train->pattern = DP_TRAINING_PATTERN_DISABLE; + train->clock_recovered = false; + train->channel_equalized = false; +} + +static bool drm_dp_link_train_valid(const struct drm_dp_link_train *train) +{ + return train->clock_recovered && train->channel_equalized; +} + +static int drm_dp_link_apply_training(struct drm_dp_link *link) +{ + struct drm_dp_link_train_set *request = &link->train.request; + unsigned int lanes = link->lanes, *vs, *pe, *pc, i; + struct drm_dp_aux *aux = link->aux; + u8 values[4], pattern = 0; + int err; + + err = link->ops->apply_training(link); + if (err < 0) { + DRM_ERROR("failed to apply link training: %d\n", err); + return err; + } + + vs = request->voltage_swing; + pe = request->pre_emphasis; + pc = request->post_cursor; + + /* write currently selected voltage-swing and pre-emphasis levels */ + for (i = 0; i < lanes; i++) + values[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL(vs[i]) | + DP_TRAIN_PRE_EMPHASIS_LEVEL(pe[i]); + + err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, lanes); + if (err < 0) { + DRM_ERROR("failed to set training parameters: %d\n", err); + return err; + } + + /* write currently selected post-cursor level (if supported) */ + if (link->revision >= 0x12 && link->rate == 540000) { + values[0] = values[1] = 0; + + for (i = 0; i < lanes; i++) + values[i / 2] |= DP_LANE_POST_CURSOR(i, pc[i]); + + err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_1_SET2, values, + DIV_ROUND_UP(lanes, 2)); + if (err < 0) { + DRM_ERROR("failed to set post-cursor: %d\n", err); + return err; + } + } + + /* write link pattern */ + if (link->train.pattern != DP_TRAINING_PATTERN_DISABLE) + pattern |= DP_LINK_SCRAMBLING_DISABLE; + + pattern |= link->train.pattern; + + err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern); + if (err < 0) { + DRM_ERROR("failed to set training pattern: %d\n", err); + return err; + } + + return 0; +} + +static void drm_dp_link_train_wait(struct drm_dp_link *link) +{ + unsigned long min = 0; + + switch (link->train.pattern) { + case DP_TRAINING_PATTERN_1: + min = link->aux_rd_interval.cr; + break; + + case DP_TRAINING_PATTERN_2: + case DP_TRAINING_PATTERN_3: + min = link->aux_rd_interval.ce; + break; + + default: + break; + } + + if (min > 0) + usleep_range(min, 2 * min); +} + +static void drm_dp_link_get_adjustments(struct drm_dp_link *link, + u8 status[DP_LINK_STATUS_SIZE]) +{ + struct drm_dp_link_train_set *adjust = &link->train.adjust; + unsigned int i; + + for (i = 0; i < link->lanes; i++) { + adjust->voltage_swing[i] = + drm_dp_get_adjust_request_voltage(status, i) >> + DP_TRAIN_VOLTAGE_SWING_SHIFT; + + adjust->pre_emphasis[i] = + drm_dp_get_adjust_request_pre_emphasis(status, i) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT; + + adjust->post_cursor[i] = + drm_dp_get_adjust_request_post_cursor(status, i); + } +} + +static void drm_dp_link_train_adjust(struct drm_dp_link_train *train) +{ + struct drm_dp_link_train_set *request = &train->request; + struct drm_dp_link_train_set *adjust = &train->adjust; + unsigned int i; + + for (i = 0; i < 4; i++) + if (request->voltage_swing[i] != adjust->voltage_swing[i]) + request->voltage_swing[i] = adjust->voltage_swing[i]; + + for (i = 0; i < 4; i++) + if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) + request->pre_emphasis[i] = adjust->pre_emphasis[i]; + + for (i = 0; i < 4; i++) + if (request->post_cursor[i] != adjust->post_cursor[i]) + request->post_cursor[i] = adjust->post_cursor[i]; +} + +static int drm_dp_link_recover_clock(struct drm_dp_link *link) +{ + u8 status[DP_LINK_STATUS_SIZE]; + int err; + + err = drm_dp_link_apply_training(link); + if (err < 0) + return err; + + drm_dp_link_train_wait(link); + + err = drm_dp_dpcd_read_link_status(link->aux, status); + if (err < 0) { + DRM_ERROR("failed to read link status: %d\n", err); + return err; + } + + if (!drm_dp_clock_recovery_ok(status, link->lanes)) + drm_dp_link_get_adjustments(link, status); + else + link->train.clock_recovered = true; + + return 0; +} + +static int drm_dp_link_clock_recovery(struct drm_dp_link *link) +{ + unsigned int repeat; + int err; + + /* start clock recovery using training pattern 1 */ + link->train.pattern = DP_TRAINING_PATTERN_1; + + for (repeat = 1; repeat < 5; repeat++) { + err = drm_dp_link_recover_clock(link); + if (err < 0) { + DRM_ERROR("failed to recover clock: %d\n", err); + return err; + } + + drm_dp_link_train_adjust(&link->train); + + if (link->train.clock_recovered) + break; + } + + return 0; +} + +static int drm_dp_link_equalize_channel(struct drm_dp_link *link) +{ + struct drm_dp_aux *aux = link->aux; + u8 status[DP_LINK_STATUS_SIZE]; + int err; + + err = drm_dp_link_apply_training(link); + if (err < 0) + return err; + + drm_dp_link_train_wait(link); + + err = drm_dp_dpcd_read_link_status(aux, status); + if (err < 0) { + DRM_ERROR("failed to read link status: %d\n", err); + return err; + } + + if (!drm_dp_clock_recovery_ok(status, link->lanes)) { + DRM_ERROR("clock recovery lost while equalizing channel\n"); + link->train.clock_recovered = false; + return 0; + } + + if (!drm_dp_channel_eq_ok(status, link->lanes)) + drm_dp_link_get_adjustments(link, status); + else + link->train.channel_equalized = true; + + return 0; +} + +static int drm_dp_link_channel_equalization(struct drm_dp_link *link) +{ + unsigned int repeat; + int err; + + /* start channel equalization using pattern 2 or 3 */ + if (link->caps.tps3_supported) + link->train.pattern = DP_TRAINING_PATTERN_3; + else + link->train.pattern = DP_TRAINING_PATTERN_2; + + for (repeat = 1; repeat < 5; repeat++) { + err = drm_dp_link_equalize_channel(link); + if (err < 0) { + DRM_ERROR("failed to equalize channel: %d\n", err); + return err; + } + + drm_dp_link_train_adjust(&link->train); + + if (link->train.channel_equalized) + break; + } + + return 0; +} + +static int drm_dp_link_downgrade(struct drm_dp_link *link) +{ + switch (link->rate) { + case 162000: + return -EINVAL; + + case 270000: + link->rate = 162000; + break; + + case 540000: + link->rate = 270000; + return 0; + } + + return 0; +} + +static void drm_dp_link_train_disable(struct drm_dp_link *link) +{ + int err; + + link->train.pattern = DP_TRAINING_PATTERN_DISABLE; + + err = drm_dp_link_apply_training(link); + if (err < 0) + DRM_ERROR("failed to disable link training: %d\n", err); +} + +static int drm_dp_link_train_full(struct drm_dp_link *link) +{ + int err; + +retry: + DRM_DEBUG_KMS("full-training link: %u lane%s at %u MHz\n", + link->lanes, (link->lanes > 1) ? "s" : "", + link->rate / 100); + + err = drm_dp_link_configure(link->aux, link); + if (err < 0) { + DRM_ERROR("failed to configure DP link: %d\n", err); + return err; + } + + err = drm_dp_link_clock_recovery(link); + if (err < 0) { + DRM_ERROR("clock recovery failed: %d\n", err); + goto out; + } + + if (!link->train.clock_recovered) { + DRM_ERROR("clock recovery failed, downgrading link\n"); + + err = drm_dp_link_downgrade(link); + if (err < 0) + goto out; + + goto retry; + } + + DRM_DEBUG_KMS("clock recovery succeeded\n"); + + err = drm_dp_link_channel_equalization(link); + if (err < 0) { + DRM_ERROR("channel equalization failed: %d\n", err); + goto out; + } + + if (!link->train.channel_equalized) { + DRM_ERROR("channel equalization failed, downgrading link\n"); + + err = drm_dp_link_downgrade(link); + if (err < 0) + goto out; + + goto retry; + } + + DRM_DEBUG_KMS("channel equalization succeeded\n"); + +out: + drm_dp_link_train_disable(link); + return err; +} + +static int drm_dp_link_train_fast(struct drm_dp_link *link) +{ + u8 status[DP_LINK_STATUS_SIZE]; + int err; + + DRM_DEBUG_KMS("fast-training link: %u lane%s at %u MHz\n", + link->lanes, (link->lanes > 1) ? "s" : "", + link->rate / 100); + + err = drm_dp_link_configure(link->aux, link); + if (err < 0) { + DRM_ERROR("failed to configure DP link: %d\n", err); + return err; + } + + /* transmit training pattern 1 for 500 microseconds */ + link->train.pattern = DP_TRAINING_PATTERN_1; + + err = drm_dp_link_apply_training(link); + if (err < 0) + goto out; + + usleep_range(500, 1000); + + /* transmit training pattern 2 or 3 for 500 microseconds */ + if (link->caps.tps3_supported) + link->train.pattern = DP_TRAINING_PATTERN_3; + else + link->train.pattern = DP_TRAINING_PATTERN_2; + + err = drm_dp_link_apply_training(link); + if (err < 0) + goto out; + + usleep_range(500, 1000); + + err = drm_dp_dpcd_read_link_status(link->aux, status); + if (err < 0) { + DRM_ERROR("failed to read link status: %d\n", err); + goto out; + } + + if (!drm_dp_clock_recovery_ok(status, link->lanes)) { + DRM_ERROR("clock recovery failed\n"); + err = -EIO; + } + + if (!drm_dp_channel_eq_ok(status, link->lanes)) { + DRM_ERROR("channel equalization failed\n"); + err = -EIO; + } + +out: + drm_dp_link_train_disable(link); + return err; +} + +/** + * drm_dp_link_train() - perform DisplayPort link training + * @link: a DP link object + * + * Uses the context stored in the DP link object to perform link training. It + * is expected that drivers will call drm_dp_link_probe() to obtain the link + * capabilities before performing link training. + * + * If the sink supports fast link training (no AUX CH handshake) and valid + * training settings are available, this function will try to perform fast + * link training and fall back to full link training on failure. + * + * Returns: 0 on success or a negative error code on failure. + */ +int drm_dp_link_train(struct drm_dp_link *link) +{ + int err; + + if (link->caps.fast_training) { + if (drm_dp_link_train_valid(&link->train)) { + err = drm_dp_link_train_fast(link); + if (err < 0) + DRM_ERROR("fast link training failed: %d\n", + err); + else + return 0; + } else { + DRM_DEBUG_KMS("training parameters not available\n"); + } + } else { + DRM_DEBUG_KMS("fast link training not supported\n"); + } + + err = drm_dp_link_train_full(link); + if (err < 0) + DRM_ERROR("full link training failed: %d\n", err); + + return err; +} diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h index a20ee9f1f1b6..cb12ed0c54e7 100644 --- a/drivers/gpu/drm/tegra/dp.h +++ b/drivers/gpu/drm/tegra/dp.h @@ -12,6 +12,7 @@ struct drm_display_info; struct drm_display_mode; struct drm_dp_aux; +struct drm_dp_link; /** * struct drm_dp_link_caps - DP link capabilities @@ -56,6 +57,55 @@ struct drm_dp_link_caps { void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, const struct drm_dp_link_caps *src); +/** + * struct drm_dp_link_ops - DP link operations + */ +struct drm_dp_link_ops { + /** + * @apply_training: + */ + int (*apply_training)(struct drm_dp_link *link); + + /** + * @configure: + */ + int (*configure)(struct drm_dp_link *link); +}; + +#define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0) +#define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3) +#define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2)) + +/** + * struct drm_dp_link_train_set - link training settings + * @voltage_swing: per-lane voltage swing + * @pre_emphasis: per-lane pre-emphasis + * @post_cursor: per-lane post-cursor + */ +struct drm_dp_link_train_set { + unsigned int voltage_swing[4]; + unsigned int pre_emphasis[4]; + unsigned int post_cursor[4]; +}; + +/** + * struct drm_dp_link_train - link training state information + * @request: currently requested settings + * @adjust: adjustments requested by sink + * @pattern: currently requested training pattern + * @clock_recovered: flag to track if clock recovery has completed + * @channel_equalized: flag to track if channel equalization has completed + */ +struct drm_dp_link_train { + struct drm_dp_link_train_set request; + struct drm_dp_link_train_set adjust; + + unsigned int pattern; + + bool clock_recovered; + bool channel_equalized; +}; + /** * struct drm_dp_link - DP link capabilities and configuration * @revision: DP specification revision supported on the link @@ -92,6 +142,21 @@ struct drm_dp_link { unsigned long rates[DP_MAX_SUPPORTED_RATES]; unsigned int num_rates; + + /** + * @ops: DP link operations + */ + const struct drm_dp_link_ops *ops; + + /** + * @aux: DP AUX channel + */ + struct drm_dp_aux *aux; + + /** + * @train: DP link training state + */ + struct drm_dp_link_train train; }; int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate); @@ -106,4 +171,7 @@ int drm_dp_link_choose(struct drm_dp_link *link, const struct drm_display_mode *mode, const struct drm_display_info *info); +void drm_dp_link_train_init(struct drm_dp_link_train *train); +int drm_dp_link_train(struct drm_dp_link *link); + #endif From patchwork Thu Oct 24 16:45:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2032713B1 for ; Thu, 24 Oct 2019 16:46:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0840621929 for ; Thu, 24 Oct 2019 16:46:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0840621929 Authentication-Results: mail.kernel.org; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id b7sm11010352wrn.53.2019.10.24.09.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:14 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 17/32] drm/tegra: sor: Use DP link training helpers Date: Thu, 24 Oct 2019 18:45:19 +0200 Message-Id: <20191024164534.132764-18-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FwEnjHtFTF7OfFXzKxcCarHlZ61ccQuW3KuS1NZQB7o=; b=g+bw5X7qGub6UzajTmDJyZL1qqTbzRA0r6jrKGWPWSBoyN8AGZ90rmDfkDdkkIvIs2 R7AbTE6y3P7kEm7wEb3XfJok4+n8VFW+KjPFbxeWvW0FTcRrOrO64PfvVJVMjJrorR4f PJrZVpCM1YtghuthN7C1v9JCgl+baRS4Ge1n0apNeMXswK6PRGzazXijj4utZlnTybtv yHceM1oT30n8+vlMc6LBQFXMQvgrx5Hg4OKqcHsMMLd7bMQ2uAfmNMu0ELvxSdneW9Z8 fuoyCaNyRRvEHuRzeDE9ndvNYWQiMxPvS9FlXVuOxny9F+yybh9vFK43losmGXId87HQ n0jg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Make use of the DP link training helpers to implement full and fast link training. While at it, refactor some of the code and remove various code sequences that are not necessary. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dpaux.c | 69 ---- drivers/gpu/drm/tegra/drm.h | 5 - drivers/gpu/drm/tegra/sor.c | 684 +++++++++++++++++++++++----------- drivers/gpu/drm/tegra/sor.h | 2 + 4 files changed, 470 insertions(+), 290 deletions(-) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index bd3361cea49b..622cdf1ad246 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -821,72 +821,3 @@ int drm_dp_aux_disable(struct drm_dp_aux *aux) return 0; } - -int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding) -{ - int err; - - err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, - encoding); - if (err < 0) - return err; - - return 0; -} - -int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, - u8 pattern) -{ - u8 tp = pattern & DP_TRAINING_PATTERN_MASK; - u8 status[DP_LINK_STATUS_SIZE], values[4]; - unsigned int i; - int err; - - err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern); - if (err < 0) - return err; - - if (tp == DP_TRAINING_PATTERN_DISABLE) - return 0; - - for (i = 0; i < link->lanes; i++) - values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | - DP_TRAIN_PRE_EMPH_LEVEL_0 | - DP_TRAIN_MAX_SWING_REACHED | - DP_TRAIN_VOLTAGE_SWING_LEVEL_0; - - err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, - link->lanes); - if (err < 0) - return err; - - usleep_range(500, 1000); - - err = drm_dp_dpcd_read_link_status(aux, status); - if (err < 0) - return err; - - switch (tp) { - case DP_TRAINING_PATTERN_1: - if (!drm_dp_clock_recovery_ok(status, link->lanes)) - return -EAGAIN; - - break; - - case DP_TRAINING_PATTERN_2: - if (!drm_dp_channel_eq_ok(status, link->lanes)) - return -EAGAIN; - - break; - - default: - dev_err(aux->dev, "unsupported training pattern %u\n", tp); - return -EINVAL; - } - - err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0); - if (err < 0) - return err; - - return 0; -} diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6a06d636e930..8b812bb52e5b 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -153,17 +153,12 @@ void tegra_output_connector_destroy(struct drm_connector *connector); void tegra_output_encoder_destroy(struct drm_encoder *encoder); /* from dpaux.c */ -struct drm_dp_link; - struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np); enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux); int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output); int drm_dp_aux_detach(struct drm_dp_aux *aux); int drm_dp_aux_enable(struct drm_dp_aux *aux); int drm_dp_aux_disable(struct drm_dp_aux *aux); -int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding); -int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, - u8 pattern); /* from fb.c */ struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index dd118366455b..636807e047f0 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -383,6 +383,12 @@ struct tegra_sor_soc { unsigned int num_settings; const u8 *xbar_cfg; + const u8 *lane_map; + + const u8 (*voltage_swing)[4][4]; + const u8 (*pre_emphasis)[4][4]; + const u8 (*post_cursor)[4][4]; + const u8 (*tx_pu)[4][4]; }; struct tegra_sor; @@ -413,6 +419,7 @@ struct tegra_sor { u8 xbar_cfg[5]; + struct drm_dp_link link; struct drm_dp_aux *aux; struct drm_info_list *debugfs_files; @@ -598,112 +605,316 @@ static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, return clk; } -static int tegra_sor_dp_train_fast(struct tegra_sor *sor, - struct drm_dp_link *link) +static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) { - unsigned int i; - u8 pattern; + unsigned long timeout; u32 value; - int err; - /* setup lane parameters */ - value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | - SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | - SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | - SOR_LANE_DRIVE_CURRENT_LANE0(0x40); - tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); + /* + * Clear or set the PD_TXD bit corresponding to each lane, depending + * on whether it is used or not. + */ + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | - SOR_LANE_PREEMPHASIS_LANE2(0x0f) | - SOR_LANE_PREEMPHASIS_LANE1(0x0f) | - SOR_LANE_PREEMPHASIS_LANE0(0x0f); - tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); + if (lanes <= 2) + value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | + SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); + else + value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | + SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); + + if (lanes <= 1) + value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); + else + value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); + + if (lanes == 0) + value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); + else + value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); + + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); + + /* start lane sequencer */ + value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | + SOR_LANE_SEQ_CTL_POWER_STATE_UP; + tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) + break; + + usleep_range(250, 1000); + } + + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) + return -ETIMEDOUT; - value = SOR_LANE_POSTCURSOR_LANE3(0x00) | - SOR_LANE_POSTCURSOR_LANE2(0x00) | - SOR_LANE_POSTCURSOR_LANE1(0x00) | - SOR_LANE_POSTCURSOR_LANE0(0x00); - tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); + return 0; +} - /* disable LVDS mode */ - tegra_sor_writel(sor, 0, SOR_LVDS); +static int tegra_sor_power_down_lanes(struct tegra_sor *sor) +{ + unsigned long timeout; + u32 value; + /* power down all lanes */ value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - value |= SOR_DP_PADCTL_TX_PU_ENABLE; - value &= ~SOR_DP_PADCTL_TX_PU_MASK; - value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ + value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | + SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); + /* start lane sequencer */ + value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | + SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; + tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); + + timeout = jiffies + msecs_to_jiffies(250); + + while (time_before(jiffies, timeout)) { + value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) + break; + + usleep_range(25, 100); + } + + if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) + return -ETIMEDOUT; + + return 0; +} + +static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) +{ + u32 value; + + /* pre-charge all used lanes */ value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | - SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; + + if (lanes <= 2) + value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | + SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); + else + value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | + SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); + + if (lanes <= 1) + value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); + else + value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); + + if (lanes == 0) + value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); + else + value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - usleep_range(10, 100); + usleep_range(15, 100); value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); +} - err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); - if (err < 0) - return err; +static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) +{ + u32 mask = 0x08, adj = 0, value; + + /* enable pad calibration logic */ + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); + value &= ~SOR_DP_PADCTL_PAD_CAL_PD; + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); + + value = tegra_sor_readl(sor, sor->soc->regs->pll1); + value |= SOR_PLL1_TMDS_TERM; + tegra_sor_writel(sor, value, sor->soc->regs->pll1); + + while (mask) { + adj |= mask; + + value = tegra_sor_readl(sor, sor->soc->regs->pll1); + value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; + value |= SOR_PLL1_TMDS_TERMADJ(adj); + tegra_sor_writel(sor, value, sor->soc->regs->pll1); - for (i = 0, value = 0; i < link->lanes; i++) { - unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | - SOR_DP_TPG_SCRAMBLER_NONE | - SOR_DP_TPG_PATTERN_TRAIN1; - value = (value << 8) | lane; + usleep_range(100, 200); + + value = tegra_sor_readl(sor, sor->soc->regs->pll1); + if (value & SOR_PLL1_TERM_COMPOUT) + adj &= ~mask; + + mask >>= 1; } - tegra_sor_writel(sor, value, SOR_DP_TPG); + value = tegra_sor_readl(sor, sor->soc->regs->pll1); + value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; + value |= SOR_PLL1_TMDS_TERMADJ(adj); + tegra_sor_writel(sor, value, sor->soc->regs->pll1); - pattern = DP_TRAINING_PATTERN_1; + /* disable pad calibration logic */ + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); + value |= SOR_DP_PADCTL_PAD_CAL_PD; + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); +} - err = drm_dp_aux_train(sor->aux, link, pattern); - if (err < 0) - return err; +static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) +{ + struct tegra_sor *sor = container_of(link, struct tegra_sor, link); + u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; + const struct tegra_sor_soc *soc = sor->soc; + u32 pattern = 0, tx_pu = 0, value; + unsigned int i; - value = tegra_sor_readl(sor, SOR_DP_SPARE0); - value |= SOR_DP_SPARE_SEQ_ENABLE; - value &= ~SOR_DP_SPARE_PANEL_INTERNAL; - value |= SOR_DP_SPARE_MACRO_SOR_CLK; - tegra_sor_writel(sor, value, SOR_DP_SPARE0); + for (value = 0, i = 0; i < link->lanes; i++) { + u8 vs = link->train.request.voltage_swing[i]; + u8 pe = link->train.request.pre_emphasis[i]; + u8 pc = link->train.request.post_cursor[i]; + u8 shift = sor->soc->lane_map[i] << 3; + + voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; + pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; + post_cursor |= soc->post_cursor[pc][vs][pe] << shift; + + if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) + tx_pu = sor->soc->tx_pu[pc][vs][pe]; + + switch (link->train.pattern) { + case DP_TRAINING_PATTERN_DISABLE: + value = SOR_DP_TPG_SCRAMBLER_GALIOS | + SOR_DP_TPG_PATTERN_NONE; + break; + + case DP_TRAINING_PATTERN_1: + value = SOR_DP_TPG_SCRAMBLER_NONE | + SOR_DP_TPG_PATTERN_TRAIN1; + break; + + case DP_TRAINING_PATTERN_2: + value = SOR_DP_TPG_SCRAMBLER_NONE | + SOR_DP_TPG_PATTERN_TRAIN2; + break; - for (i = 0, value = 0; i < link->lanes; i++) { - unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | - SOR_DP_TPG_SCRAMBLER_NONE | - SOR_DP_TPG_PATTERN_TRAIN2; - value = (value << 8) | lane; + case DP_TRAINING_PATTERN_3: + value = SOR_DP_TPG_SCRAMBLER_NONE | + SOR_DP_TPG_PATTERN_TRAIN3; + break; + + default: + return -EINVAL; + } + + if (link->caps.channel_coding) + value |= SOR_DP_TPG_CHANNEL_CODING; + + pattern = pattern << 8 | value; } - tegra_sor_writel(sor, value, SOR_DP_TPG); + tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); + tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); - pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; + if (link->caps.tps3_supported) + tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); - err = drm_dp_aux_train(sor->aux, link, pattern); - if (err < 0) - return err; + tegra_sor_writel(sor, pattern, SOR_DP_TPG); + + value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); + value &= ~SOR_DP_PADCTL_TX_PU_MASK; + value |= SOR_DP_PADCTL_TX_PU_ENABLE; + value |= SOR_DP_PADCTL_TX_PU(tx_pu); + tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); + + usleep_range(20, 100); - for (i = 0, value = 0; i < link->lanes; i++) { - unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | - SOR_DP_TPG_SCRAMBLER_GALIOS | - SOR_DP_TPG_PATTERN_NONE; - value = (value << 8) | lane; + return 0; +} + +static int tegra_sor_dp_link_configure(struct drm_dp_link *link) +{ + struct tegra_sor *sor = container_of(link, struct tegra_sor, link); + unsigned int rate, lanes; + u32 value; + int err; + + rate = drm_dp_link_rate_to_bw_code(link->rate); + lanes = link->lanes; + + /* configure link speed and lane count */ + value = tegra_sor_readl(sor, SOR_CLK_CNTRL); + value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; + value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + + value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); + value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; + value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); + + if (link->caps.enhanced_framing) + value |= SOR_DP_LINKCTL_ENHANCED_FRAME; + + tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); + + usleep_range(400, 1000); + + /* configure load pulse position adjustment */ + value = tegra_sor_readl(sor, sor->soc->regs->pll1); + value &= ~SOR_PLL1_LOADADJ_MASK; + + switch (rate) { + case DP_LINK_BW_1_62: + value |= SOR_PLL1_LOADADJ(0x3); + break; + + case DP_LINK_BW_2_7: + value |= SOR_PLL1_LOADADJ(0x4); + break; + + case DP_LINK_BW_5_4: + value |= SOR_PLL1_LOADADJ(0x6); + break; } - tegra_sor_writel(sor, value, SOR_DP_TPG); + tegra_sor_writel(sor, value, sor->soc->regs->pll1); - pattern = DP_TRAINING_PATTERN_DISABLE; + /* use alternate scrambler reset for eDP */ + value = tegra_sor_readl(sor, SOR_DP_SPARE0); - err = drm_dp_aux_train(sor->aux, link, pattern); - if (err < 0) + if (link->edp == 0) + value &= ~SOR_DP_SPARE_PANEL_INTERNAL; + else + value |= SOR_DP_SPARE_PANEL_INTERNAL; + + tegra_sor_writel(sor, value, SOR_DP_SPARE0); + + err = tegra_sor_power_down_lanes(sor); + if (err < 0) { + dev_err(sor->dev, "failed to power down lanes: %d\n", err); + return err; + } + + /* power up and pre-charge lanes */ + err = tegra_sor_power_up_lanes(sor, lanes); + if (err < 0) { + dev_err(sor->dev, "failed to power up %u lane%s: %d\n", + lanes, (lanes != 1) ? "s" : "", err); return err; + } + + tegra_sor_dp_precharge(sor, lanes); return 0; } +static const struct drm_dp_link_ops tegra_sor_dp_link_ops = { + .apply_training = tegra_sor_dp_link_apply_training, + .configure = tegra_sor_dp_link_configure, +}; + static void tegra_sor_super_update(struct tegra_sor *sor) { tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); @@ -1201,29 +1412,6 @@ static int tegra_sor_power_down(struct tegra_sor *sor) return err; } - value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | - SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); - tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - - /* stop lane sequencer */ - value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | - SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; - tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); - - timeout = jiffies + msecs_to_jiffies(250); - - while (time_before(jiffies, timeout)) { - value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); - if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) - break; - - usleep_range(25, 100); - } - - if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) - return -ETIMEDOUT; - value = tegra_sor_readl(sor, sor->soc->regs->pll2); value |= SOR_PLL2_PORT_POWERDOWN; tegra_sor_writel(sor, value, sor->soc->regs->pll2); @@ -1603,17 +1791,11 @@ static void tegra_sor_edp_disable(struct drm_encoder *encoder) tegra_sor_writel(sor, 0, SOR_STATE1); tegra_sor_update(sor); - /* - * The following accesses registers of the display controller, so make - * sure it's only executed when the output is attached to one. - */ - if (dc) { - value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value &= ~SOR_ENABLE(0); - tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + value &= ~SOR_ENABLE(0); + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); - tegra_dc_commit(dc); - } + tegra_dc_commit(dc); err = tegra_sor_power_down(sor); if (err < 0) @@ -1679,19 +1861,20 @@ static int calc_h_ref_to_sync(const struct drm_display_mode *mode, static void tegra_sor_edp_enable(struct drm_encoder *encoder) { - struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; struct tegra_output *output = encoder_to_output(encoder); struct tegra_dc *dc = to_tegra_dc(encoder->crtc); struct tegra_sor *sor = to_sor(output); struct tegra_sor_config config; struct tegra_sor_state *state; - struct drm_dp_link link; - u8 rate, lanes; + struct drm_display_mode *mode; + struct drm_display_info *info; unsigned int i; - int err = 0; u32 value; + int err; state = to_sor_state(output->connector.state); + mode = &encoder->crtc->state->adjusted_mode; + info = &output->connector.display_info; pm_runtime_get_sync(sor->dev); @@ -1702,7 +1885,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to enable DP: %d\n", err); - err = drm_dp_link_probe(sor->aux, &link); + err = drm_dp_link_probe(sor->aux, &sor->link); if (err < 0) { dev_err(sor->dev, "failed to probe eDP link: %d\n", err); return; @@ -1713,13 +1896,6 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); - memset(&config, 0, sizeof(config)); - config.bits_per_pixel = state->bpc * 3; - - err = tegra_sor_compute_config(sor, mode, &config, &link); - if (err < 0) - dev_err(sor->dev, "failed to compute configuration: %d\n", err); - value = tegra_sor_readl(sor, SOR_CLK_CNTRL); value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; @@ -1828,117 +2004,44 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to set parent clock: %d\n", err); - /* power DP lanes */ - value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - - if (link.lanes <= 2) - value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); - else - value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; - - if (link.lanes <= 1) - value &= ~SOR_DP_PADCTL_PD_TXD_1; - else - value |= SOR_DP_PADCTL_PD_TXD_1; - - if (link.lanes == 0) - value &= ~SOR_DP_PADCTL_PD_TXD_0; - else - value |= SOR_DP_PADCTL_PD_TXD_0; - - tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - - value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); - value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; - value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes); - tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); - - /* start lane sequencer */ - value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | - SOR_LANE_SEQ_CTL_POWER_STATE_UP; - tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); - - while (true) { - value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); - if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) - break; - - usleep_range(250, 1000); - } - - /* set link bandwidth */ - value = tegra_sor_readl(sor, SOR_CLK_CNTRL); - value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; - value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; - tegra_sor_writel(sor, value, SOR_CLK_CNTRL); - - tegra_sor_apply_config(sor, &config); + /* use DP-A protocol */ + value = tegra_sor_readl(sor, SOR_STATE1); + value &= ~SOR_STATE_ASY_PROTOCOL_MASK; + value |= SOR_STATE_ASY_PROTOCOL_DP_A; + tegra_sor_writel(sor, value, SOR_STATE1); - /* enable link */ + /* enable port */ value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); value |= SOR_DP_LINKCTL_ENABLE; - value |= SOR_DP_LINKCTL_ENHANCED_FRAME; tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); - for (i = 0, value = 0; i < 4; i++) { - unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | - SOR_DP_TPG_SCRAMBLER_GALIOS | - SOR_DP_TPG_PATTERN_NONE; - value = (value << 8) | lane; - } - - tegra_sor_writel(sor, value, SOR_DP_TPG); + /* calibrate termination resistance (XXX do this only on HPD) */ + tegra_sor_dp_term_calibrate(sor); - /* enable pad calibration logic */ - value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - value |= SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - - err = drm_dp_link_probe(sor->aux, &link); + err = drm_dp_link_train(&sor->link); if (err < 0) - dev_err(sor->dev, "failed to probe eDP link: %d\n", err); - - err = drm_dp_link_power_up(sor->aux, &link); - if (err < 0) - dev_err(sor->dev, "failed to power up eDP link: %d\n", err); - - err = drm_dp_link_configure(sor->aux, &link); - if (err < 0) - dev_err(sor->dev, "failed to configure eDP link: %d\n", err); - - rate = drm_dp_link_rate_to_bw_code(link.rate); - lanes = link.lanes; - - value = tegra_sor_readl(sor, SOR_CLK_CNTRL); - value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; - value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); - tegra_sor_writel(sor, value, SOR_CLK_CNTRL); - - value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); - value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; - value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); - - if (link.caps.enhanced_framing) - value |= SOR_DP_LINKCTL_ENHANCED_FRAME; - - tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); - - /* disable training pattern generator */ + dev_err(sor->dev, "link training failed: %d\n", err); + else + dev_dbg(sor->dev, "link training succeeded\n"); - for (i = 0; i < link.lanes; i++) { - unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | - SOR_DP_TPG_SCRAMBLER_GALIOS | - SOR_DP_TPG_PATTERN_NONE; - value = (value << 8) | lane; + err = drm_dp_link_power_up(sor->aux, &sor->link); + if (err < 0) { + dev_err(sor->dev, "failed to power up eDP link: %d\n", + err); + return; } - tegra_sor_writel(sor, value, SOR_DP_TPG); + /* compute configuration */ + memset(&config, 0, sizeof(config)); + config.bits_per_pixel = state->bpc * 3; - err = tegra_sor_dp_train_fast(sor, &link); - if (err < 0) - dev_err(sor->dev, "DP fast link training failed: %d\n", err); + err = tegra_sor_compute_config(sor, mode, &config, &sor->link); + if (err < 0) { + dev_err(sor->dev, "failed to compute configuration: %d\n", err); + return; + } - dev_dbg(sor->dev, "fast link training succeeded\n"); + tegra_sor_apply_config(sor, &config); err = tegra_sor_power_up(sor, 250); if (err < 0) @@ -2842,6 +2945,9 @@ static int tegra_sor_init(struct host1x_client *client) connector = DRM_MODE_CONNECTOR_DisplayPort; encoder = DRM_MODE_ENCODER_TMDS; } + + sor->link.ops = &tegra_sor_dp_link_ops; + sor->link.aux = sor->aux; } sor->output.dev = sor->dev; @@ -3042,6 +3148,107 @@ static const struct tegra_sor_regs tegra124_sor_regs = { .dp_padctl2 = 0x73, }; +/* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ +static const u8 tegra124_sor_lane_map[4] = { + 2, 1, 0, 3, +}; + +static const u8 tegra124_sor_voltage_swing[4][4][4] = { + { + { 0x13, 0x19, 0x1e, 0x28 }, + { 0x1e, 0x25, 0x2d, }, + { 0x28, 0x32, }, + { 0x3c, }, + }, { + { 0x12, 0x17, 0x1b, 0x25 }, + { 0x1c, 0x23, 0x2a, }, + { 0x25, 0x2f, }, + { 0x39, } + }, { + { 0x12, 0x16, 0x1a, 0x22 }, + { 0x1b, 0x20, 0x27, }, + { 0x24, 0x2d, }, + { 0x36, }, + }, { + { 0x11, 0x14, 0x17, 0x1f }, + { 0x19, 0x1e, 0x24, }, + { 0x22, 0x2a, }, + { 0x32, }, + }, +}; + +static const u8 tegra124_sor_pre_emphasis[4][4][4] = { + { + { 0x00, 0x09, 0x13, 0x25 }, + { 0x00, 0x0f, 0x1e, }, + { 0x00, 0x14, }, + { 0x00, }, + }, { + { 0x00, 0x0a, 0x14, 0x28 }, + { 0x00, 0x0f, 0x1e, }, + { 0x00, 0x14, }, + { 0x00 }, + }, { + { 0x00, 0x0a, 0x14, 0x28 }, + { 0x00, 0x0f, 0x1e, }, + { 0x00, 0x14, }, + { 0x00, }, + }, { + { 0x00, 0x0a, 0x14, 0x28 }, + { 0x00, 0x0f, 0x1e, }, + { 0x00, 0x14, }, + { 0x00, }, + }, +}; + +static const u8 tegra124_sor_post_cursor[4][4][4] = { + { + { 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, }, + { 0x00, 0x00, }, + { 0x00, }, + }, { + { 0x02, 0x02, 0x04, 0x05 }, + { 0x02, 0x04, 0x05, }, + { 0x04, 0x05, }, + { 0x05, }, + }, { + { 0x04, 0x05, 0x08, 0x0b }, + { 0x05, 0x09, 0x0b, }, + { 0x08, 0x0a, }, + { 0x0b, }, + }, { + { 0x05, 0x09, 0x0b, 0x12 }, + { 0x09, 0x0d, 0x12, }, + { 0x0b, 0x0f, }, + { 0x12, }, + }, +}; + +static const u8 tegra124_sor_tx_pu[4][4][4] = { + { + { 0x20, 0x30, 0x40, 0x60 }, + { 0x30, 0x40, 0x60, }, + { 0x40, 0x60, }, + { 0x60, }, + }, { + { 0x20, 0x20, 0x30, 0x50 }, + { 0x30, 0x40, 0x50, }, + { 0x40, 0x50, }, + { 0x60, }, + }, { + { 0x20, 0x20, 0x30, 0x40, }, + { 0x30, 0x30, 0x40, }, + { 0x40, 0x50, }, + { 0x60, }, + }, { + { 0x20, 0x20, 0x20, 0x40, }, + { 0x30, 0x30, 0x40, }, + { 0x40, 0x40, }, + { 0x60, }, + }, +}; + static const struct tegra_sor_soc tegra124_sor = { .supports_edp = true, .supports_lvds = true, @@ -3050,6 +3257,50 @@ static const struct tegra_sor_soc tegra124_sor = { .regs = &tegra124_sor_regs, .has_nvdisplay = false, .xbar_cfg = tegra124_sor_xbar_cfg, + .lane_map = tegra124_sor_lane_map, + .voltage_swing = tegra124_sor_voltage_swing, + .pre_emphasis = tegra124_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, +}; + +static const u8 tegra132_sor_pre_emphasis[4][4][4] = { + { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x01, 0x0e, 0x1d, }, + { 0x01, 0x13, }, + { 0x00, }, + }, { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x00, 0x0e, 0x1d, }, + { 0x00, 0x13, }, + { 0x00 }, + }, { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x00, 0x0e, 0x1d, }, + { 0x00, 0x13, }, + { 0x00, }, + }, { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x00, 0x0e, 0x1d, }, + { 0x00, 0x13, }, + { 0x00, }, + }, +}; + +static const struct tegra_sor_soc tegra132_sor = { + .supports_edp = true, + .supports_lvds = true, + .supports_hdmi = false, + .supports_dp = false, + .regs = &tegra124_sor_regs, + .has_nvdisplay = false, + .xbar_cfg = tegra124_sor_xbar_cfg, + .lane_map = tegra124_sor_lane_map, + .voltage_swing = tegra124_sor_voltage_swing, + .pre_emphasis = tegra132_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, }; static const struct tegra_sor_regs tegra210_sor_regs = { @@ -3067,18 +3318,20 @@ static const struct tegra_sor_regs tegra210_sor_regs = { .dp_padctl2 = 0x73, }; +static const u8 tegra210_sor_xbar_cfg[5] = { + 2, 1, 0, 3, 4 +}; + static const struct tegra_sor_soc tegra210_sor = { .supports_edp = true, .supports_lvds = false, .supports_hdmi = false, .supports_dp = false, + .regs = &tegra210_sor_regs, .has_nvdisplay = false, - .xbar_cfg = tegra124_sor_xbar_cfg, -}; -static const u8 tegra210_sor_xbar_cfg[5] = { - 2, 1, 0, 3, 4 + .xbar_cfg = tegra210_sor_xbar_cfg, }; static const struct tegra_sor_soc tegra210_sor1 = { @@ -3092,7 +3345,6 @@ static const struct tegra_sor_soc tegra210_sor1 = { .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), .settings = tegra210_sor_hdmi_defaults, - .xbar_cfg = tegra210_sor_xbar_cfg, }; @@ -3134,7 +3386,6 @@ static const struct tegra_sor_soc tegra186_sor1 = { .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), .settings = tegra186_sor_hdmi_defaults, - .xbar_cfg = tegra124_sor_xbar_cfg, }; @@ -3174,6 +3425,7 @@ static const struct of_device_id tegra_sor_of_match[] = { { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, + { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor }, { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, { }, }; diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h index f8efd8be4b7c..5333406c0401 100644 --- a/drivers/gpu/drm/tegra/sor.h +++ b/drivers/gpu/drm/tegra/sor.h @@ -283,10 +283,12 @@ #define SOR_DP_PADCTL_CM_TXD_2 (1 << 6) #define SOR_DP_PADCTL_CM_TXD_1 (1 << 5) #define SOR_DP_PADCTL_CM_TXD_0 (1 << 4) +#define SOR_DP_PADCTL_CM_TXD(x) (1 << (4 + (x))) #define SOR_DP_PADCTL_PD_TXD_3 (1 << 3) #define SOR_DP_PADCTL_PD_TXD_0 (1 << 2) #define SOR_DP_PADCTL_PD_TXD_1 (1 << 1) #define SOR_DP_PADCTL_PD_TXD_2 (1 << 0) +#define SOR_DP_PADCTL_PD_TXD(x) (1 << (0 + (x))) #define SOR_DP_PADCTL1 0x5d From patchwork Thu Oct 24 16:45:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEB5F1747 for ; Thu, 24 Oct 2019 16:46:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 94ECB21906 for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id q12sm2627267wrj.87.2019.10.24.09.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:17 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 18/32] drm/tegra: sor: Hook up I2C-over-AUX to output Date: Thu, 24 Oct 2019 18:45:20 +0200 Message-Id: <20191024164534.132764-19-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t2AaSAVqpbDL04En9DdcntuJXoHrsGRIQaneDm/xPB8=; b=G3twkFZ2mXV/rLLmlkVA04C7g/kJioutmqx7VJWaFEkPh7Bx/z+g3/63gG12vQEYzL lrnuPYLxPkqmK6V8+gRewfRtZgJ5VZQZtE9tNGh77vt3V8wbrL2ZMyTvyyegG9R0a77F TRWbHZp5dfpzBbLZmS3i+g6538kXX2GM08zAM4WQi/tq4JMrmczCA6obAJXlAiMEl/WG olE9mhDzBhdETOOjZHo9ZzvAohsQRKWEGC1L4xaTPH64/LRw1OzvVXbduQSxcyCHUSuX CVhRUUtBFDBSNLjnYEglPnxBO05n27n+jFGpp226y91XKVwas3/7rFq9SgbIgm/yCQ6I 8+sA== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding This is necessary for the output abstraction to retrieve a list of valid modes from the EDID of a connected panel/monitor. This will be useful in conjunction with DisplayPort support that will be added in a subsequent patch, so that the driver can read EDID via the AUX channel. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 636807e047f0..6f979c5fff7b 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3524,6 +3524,8 @@ static int tegra_sor_probe(struct platform_device *pdev) if (!sor->aux) return -EPROBE_DEFER; + + sor->output.ddc = &sor->aux->ddc; } if (!sor->aux) { From patchwork Thu Oct 24 16:45:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4801613B1 for ; Thu, 24 Oct 2019 16:46:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3050421906 for ; Thu, 24 Oct 2019 16:46:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3050421906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 512C66E50B; Thu, 24 Oct 2019 16:46:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id C074B6E4C5 for ; Thu, 24 Oct 2019 16:46:23 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id n7so2777343wmc.3 for ; Thu, 24 Oct 2019 09:46:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ttT3si52DDrLe8rV2q4VCFEdVpWo5U+DWjczyNb5rNc=; b=Ml8BOOdlB5B2zdG7SituUl0zIrO6Bqb845yeMG8b08jD44RQPpto6oGUcAkwGEMtpg ifpK0+k6FG7/QWLktmEPyQQM5BHjKnJ3n09Y8S44qkhcs7KtWjxFaw/I6ab/LT26Jncu 5J+rezhurHVtguZ4MBx/wsymWUhd8T0EEWHMxU2ZNbGxV4IisiZv5x4xgAp0/Y2UkwLM PMd08No99m7A3RAF+jHgh/AkUi/Dfc2ueImUSh2xtPrSshObv29LpU61JTDwpBxgxEoE HYlIKzzCxapgUV2bDUFUJ2ZJqSGL5Xs/st5Xxj1/vur+Cll4rXmkB39irHBLe77JfoSo E0Jg== X-Gm-Message-State: APjAAAXaxjoliILmFiLP/DaK0Dhd2uajYUpSFKwx/szyRgEldwywsLV6 3tPry8Ku8IgkacnxvnrJkAI= X-Google-Smtp-Source: APXvYqzVNNv01TzzHYZ3HhrvpfPbLREUJSHb0h+1SF2prDrc/YOq+hj2nDhyqWK+9K4sdKhH+dtJag== X-Received: by 2002:a1c:6386:: with SMTP id x128mr5633205wmb.41.1571935580516; Thu, 24 Oct 2019 09:46:20 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id y13sm37631421wrg.8.2019.10.24.09.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:19 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 19/32] drm/tegra: sor: Stabilize eDP Date: Thu, 24 Oct 2019 18:45:21 +0200 Message-Id: <20191024164534.132764-20-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ttT3si52DDrLe8rV2q4VCFEdVpWo5U+DWjczyNb5rNc=; b=UNIkA8bpA50Dxy7/OKcXV6PnS6z/MQqhkDXYqura3mEtmgaBM3jKh2X3GDf1T4bd2j Xrtn8qelu9G2lsyx9P1XXmoxaNZ3Tegl6jN3MB8caGCjf+3ilsACNNGhQTjqIErJ8Q/s RyMXuruGhJDecOfI4Eu5AHy2hdVjS7pnSOAgkhD/sQoXmax2DdHFSkrwiKKmOonejw7k kSH0jd5dSzNG7g2lc+MJ4ESZbqIk+gxh9p8ccmSFcPAfr8VIClJ8v7cLcIdo7SUtGIii mgzbF+8pf701SN0Ep+xemEciCPL1Ifl67rS3ZmHDo41CnblX9lbSnuxYQTpqL+cQlxil wYtw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Rework eDP code to correspond more closely to what's documented. This also improves the reliability of modesets. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 138 +++++++++++++----------------------- 1 file changed, 49 insertions(+), 89 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 6f979c5fff7b..2023244ad328 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1878,119 +1878,80 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) pm_runtime_get_sync(sor->dev); - if (output->panel) - drm_panel_prepare(output->panel); + /* switch to safe parent clock */ + err = tegra_sor_set_parent_clock(sor, sor->clk_safe); + if (err < 0) + dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + + err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); + if (err < 0) + dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); + + usleep_range(20, 100); err = drm_dp_aux_enable(sor->aux); if (err < 0) - dev_err(sor->dev, "failed to enable DP: %d\n", err); + dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); err = drm_dp_link_probe(sor->aux, &sor->link); - if (err < 0) { + if (err < 0) dev_err(sor->dev, "failed to probe eDP link: %d\n", err); - return; - } - /* switch to safe parent clock */ - err = tegra_sor_set_parent_clock(sor, sor->clk_safe); + err = drm_dp_link_choose(&sor->link, mode, info); if (err < 0) - dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + dev_err(sor->dev, "failed to choose link: %d\n", err); - value = tegra_sor_readl(sor, SOR_CLK_CNTRL); - value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; - value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; - tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + if (output->panel) + drm_panel_prepare(output->panel); value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_BANDGAP_POWERDOWN; tegra_sor_writel(sor, value, sor->soc->regs->pll2); - usleep_range(20, 100); + + usleep_range(20, 40); value = tegra_sor_readl(sor, sor->soc->regs->pll3); value |= SOR_PLL3_PLL_VDD_MODE_3V3; tegra_sor_writel(sor, value, sor->soc->regs->pll3); - value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | - SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; + value = tegra_sor_readl(sor, sor->soc->regs->pll0); + value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); tegra_sor_writel(sor, value, sor->soc->regs->pll0); value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value |= SOR_PLL2_SEQ_PLLCAPPD; value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; - value |= SOR_PLL2_LVDS_ENABLE; + value |= SOR_PLL2_SEQ_PLLCAPPD; tegra_sor_writel(sor, value, sor->soc->regs->pll2); - value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; - tegra_sor_writel(sor, value, sor->soc->regs->pll1); - - while (true) { - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) - break; - - usleep_range(250, 1000); - } + usleep_range(200, 400); value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; value &= ~SOR_PLL2_PORT_POWERDOWN; tegra_sor_writel(sor, value, sor->soc->regs->pll2); - /* - * power up - */ - - /* set safe link bandwidth (1.62 Gbps) */ value = tegra_sor_readl(sor, SOR_CLK_CNTRL); - value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; - value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; + value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; + value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; tegra_sor_writel(sor, value, SOR_CLK_CNTRL); - /* step 1 */ - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | - SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); - - value = tegra_sor_readl(sor, sor->soc->regs->pll0); - value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; - tegra_sor_writel(sor, value, sor->soc->regs->pll0); - - value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); - value &= ~SOR_DP_PADCTL_PAD_CAL_PD; - tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); - - /* step 2 */ - err = tegra_io_pad_power_enable(sor->pad); - if (err < 0) - dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); - - usleep_range(5, 100); - - /* step 3 */ - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value &= ~SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); + value = tegra_sor_readl(sor, SOR_DP_SPARE0); + /* XXX not in TRM */ + value |= SOR_DP_SPARE_PANEL_INTERNAL; + value |= SOR_DP_SPARE_SEQ_ENABLE; + tegra_sor_writel(sor, value, SOR_DP_SPARE0); - usleep_range(20, 100); + /* XXX not in TRM */ + tegra_sor_writel(sor, 0, SOR_LVDS); - /* step 4 */ value = tegra_sor_readl(sor, sor->soc->regs->pll0); - value &= ~SOR_PLL0_VCOPD; - value &= ~SOR_PLL0_PWR; + value &= ~SOR_PLL0_ICHPMP_MASK; + value &= ~SOR_PLL0_VCOCAP_MASK; + value |= SOR_PLL0_ICHPMP(0x1); + value |= SOR_PLL0_VCOCAP(0x3); + value |= SOR_PLL0_RESISTOR_EXT; tegra_sor_writel(sor, value, sor->soc->regs->pll0); - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); - - usleep_range(200, 1000); - - /* step 5 */ - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value &= ~SOR_PLL2_PORT_POWERDOWN; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); - /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | @@ -2015,7 +1976,6 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) value |= SOR_DP_LINKCTL_ENABLE; tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); - /* calibrate termination resistance (XXX do this only on HPD) */ tegra_sor_dp_term_calibrate(sor); err = drm_dp_link_train(&sor->link); @@ -2025,21 +1985,16 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) dev_dbg(sor->dev, "link training succeeded\n"); err = drm_dp_link_power_up(sor->aux, &sor->link); - if (err < 0) { - dev_err(sor->dev, "failed to power up eDP link: %d\n", - err); - return; - } + if (err < 0) + dev_err(sor->dev, "failed to power up eDP link: %d\n", err); /* compute configuration */ memset(&config, 0, sizeof(config)); config.bits_per_pixel = state->bpc * 3; err = tegra_sor_compute_config(sor, mode, &config, &sor->link); - if (err < 0) { + if (err < 0) dev_err(sor->dev, "failed to compute configuration: %d\n", err); - return; - } tegra_sor_apply_config(sor, &config); @@ -2067,19 +2022,24 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) tegra_sor_update(sor); + err = tegra_sor_power_up(sor, 250); + if (err < 0) + dev_err(sor->dev, "failed to power up SOR: %d\n", err); + + /* attach and wake up */ + err = tegra_sor_attach(sor); + if (err < 0) + dev_err(sor->dev, "failed to attach SOR: %d\n", err); + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); value |= SOR_ENABLE(0); tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); tegra_dc_commit(dc); - err = tegra_sor_attach(sor); - if (err < 0) - dev_err(sor->dev, "failed to attach SOR: %d\n", err); - err = tegra_sor_wakeup(sor); if (err < 0) - dev_err(sor->dev, "failed to enable DC: %d\n", err); + dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); if (output->panel) drm_panel_enable(output->panel); From patchwork Thu Oct 24 16:45:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210297 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B25F13B1 for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id 1sm8264544wrr.16.2019.10.24.09.46.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:21 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 20/32] drm/tegra: sor: Filter eDP rates Date: Thu, 24 Oct 2019 18:45:22 +0200 Message-Id: <20191024164534.132764-21-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B2W0FUjPFjz/awt2KiXk3+qz+ONZRc0nBTwMiyV54YE=; b=Q7lVozVpvsSTvFjEghbOMjRYPRm8HJdTP4vBJd8u6LuWruyy4l/JjXD0mDO4V75JPb KD4qjgDfkz4FRnzJEsFdApLQ88eHvMgjPcggfqoeb2GbHLH92tEzAvc8eQCzZru295bD svNytTmSU+TjO3HzO7H+MPF02EepoF1gMro+cttUch/03GmbLCH3OkeIYlSwYdZVKzdC 42pTM4N0Ws0Y7AFWX5xNx6cFCyVw8e/iroQCQQeP5qg5nk9z+9Y7hW+zhjwfDVV3CPYG N4siyklA0c2LjZsT3j4EL4A1r4wsoEinLmljbD7PQVVLYWnEmIadE84Qz0Q5IkeJ9Qf+ uUNw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The SOR found on Tegra SoCs does not support all the rates potentially advertised by eDP 1.4. Make sure that the rates that are not supported are filtered out. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2023244ad328..9e6a1ab7ef65 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -605,6 +605,30 @@ static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, return clk; } +static void tegra_sor_filter_rates(struct tegra_sor *sor) +{ + struct drm_dp_link *link = &sor->link; + unsigned int i; + + /* Tegra only supports RBR, HBR and HBR2 */ + for (i = 0; i < link->num_rates; i++) { + switch (link->rates[i]) { + case 1620000: + case 2700000: + case 5400000: + break; + + default: + DRM_DEBUG_KMS("link rate %lu kHz not supported\n", + link->rates[i]); + link->rates[i] = 0; + break; + } + } + + drm_dp_link_update_rates(link); +} + static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) { unsigned long timeout; @@ -1897,6 +1921,8 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to probe eDP link: %d\n", err); + tegra_sor_filter_rates(sor); + err = drm_dp_link_choose(&sor->link, mode, info); if (err < 0) dev_err(sor->dev, "failed to choose link: %d\n", err); From patchwork Thu Oct 24 16:45:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3788913B1 for ; Thu, 24 Oct 2019 16:46:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F13121906 for ; Thu, 24 Oct 2019 16:46:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F13121906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32BB76E509; Thu, 24 Oct 2019 16:46:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22CE76E4B0 for ; Thu, 24 Oct 2019 16:46:27 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id o28so26847366wro.7 for ; Thu, 24 Oct 2019 09:46:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q25ZJl137b/SORn0mDotYa8yjt0AhGCjxkBhz1BPsmk=; b=QGOm5tOc1lTFisWmkBCRfPFeu3Rxs4RdcompLY9Q+JU/GFs5dI/Pb11Qr2UCheDpdZ IqWRSjUDM2n1dl2kHjmu1TJtHR+7kNdI80u2ykvZxoQUiMazGFUbAdPs3We/3obb5w2u zTei/F7juzyJy2Iqx513EutRwY1a+/1BTS4QXdcM0yMcptRDr+sZHvH0NAowhFuOIZhl eZyO5bIebPhQB2go/OyHNEaMJn1w9Cz/cQEvfV8DWeONwykuND8ou2tuY6NTfZ/a5YJ8 V9QlNzv6usoYuhHtg0QFgEeI+XQHV9lALt+OFJyQ0ysmTgeG5dcTkKKmpJJFfxeyv2eC UEdA== X-Gm-Message-State: APjAAAWFTRJ63FFLlKkGzM5HA19/TnH40m63GhwInzhTRkeBIQJhF5fW 9tkmRE4YTvTnwmLvci73t25BO9wN X-Google-Smtp-Source: APXvYqxpwKyjyumAN/Hw1VskeeAx/ghYPpNBAPe1IxywObQk5k9tNgcXpXylq5snKnsY9JlQwdUO8Q== X-Received: by 2002:adf:8068:: with SMTP id 95mr2738248wrk.249.1571935584623; Thu, 24 Oct 2019 09:46:24 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id f18sm2489983wmh.43.2019.10.24.09.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:23 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 21/32] drm/tegra: sor: Add DisplayPort support Date: Thu, 24 Oct 2019 18:45:23 +0200 Message-Id: <20191024164534.132764-22-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q25ZJl137b/SORn0mDotYa8yjt0AhGCjxkBhz1BPsmk=; b=LeKAMvsdLdZlQqFxOqzsc+PuhLelqKO+78Zyu9/GYb3/xekpdE8KxIo+bXTeAm3VAn ZKMe/gMBNovmeDD/g/lHVKl+4vLdjsVdIuS04XMTPz1h++ZNt/O3ssWi07LGqRIeNfhM rLIePpdEH2BP2oAvfkyC7cKc0A4F/REFDPTBg8kZs42/QcETjuRu7LqVV292hC00O0SD RT19TfoRu8TVqt6aB1xR4dnEQEcQzJnizDPLhKdfB0CleAgYsy8CVHcHDToZzocRWV4N Zop66RfUYUWhRthD0sQ0EKjOqBoNKAY2Kx6Ee9im+WtbuZJRozcAtJCmbh74wFXNzmB9 IKzw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Add support for regular DisplayPort on Tegra210 and Tegra186. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/dp.c | 10 +- drivers/gpu/drm/tegra/sor.c | 343 +++++++++++++++++++++++++++++++++++- drivers/gpu/drm/tegra/sor.h | 1 + 3 files changed, 348 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 5b6765d653b4..70dfb7d1dec5 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -623,10 +623,10 @@ static int drm_dp_link_clock_recovery(struct drm_dp_link *link) return err; } - drm_dp_link_train_adjust(&link->train); - if (link->train.clock_recovered) break; + + drm_dp_link_train_adjust(&link->train); } return 0; @@ -682,10 +682,10 @@ static int drm_dp_link_channel_equalization(struct drm_dp_link *link) return err; } - drm_dp_link_train_adjust(&link->train); - if (link->train.channel_equalized) break; + + drm_dp_link_train_adjust(&link->train); } return 0; @@ -851,6 +851,8 @@ int drm_dp_link_train(struct drm_dp_link *link) { int err; + drm_dp_link_train_init(&link->train); + if (link->caps.fast_training) { if (drm_dp_link_train_valid(&link->train)) { err = drm_dp_link_train_fast(link); diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 9e6a1ab7ef65..9cf008d7c67b 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -2904,6 +2904,236 @@ static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { .atomic_check = tegra_sor_encoder_atomic_check, }; +static void tegra_sor_dp_disable(struct drm_encoder *encoder) +{ + struct tegra_output *output = encoder_to_output(encoder); + struct tegra_dc *dc = to_tegra_dc(encoder->crtc); + struct tegra_sor *sor = to_sor(output); + u32 value; + int err; + + err = drm_dp_link_power_down(sor->aux, &sor->link); + if (err < 0) + dev_err(sor->dev, "failed to power down link: %d\n", err); + + err = tegra_sor_detach(sor); + if (err < 0) + dev_err(sor->dev, "failed to detach SOR: %d\n", err); + + tegra_sor_writel(sor, 0, SOR_STATE1); + tegra_sor_update(sor); + + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + + if (!sor->soc->has_nvdisplay) + value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); + else + value &= ~SOR_ENABLE(sor->index); + + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + tegra_dc_commit(dc); + + value = tegra_sor_readl(sor, SOR_STATE1); + value &= ~SOR_STATE_ASY_PROTOCOL_MASK; + value &= ~SOR_STATE_ASY_SUBOWNER_MASK; + value &= ~SOR_STATE_ASY_OWNER_MASK; + tegra_sor_writel(sor, value, SOR_STATE1); + tegra_sor_update(sor); + + /* switch to safe parent clock */ + err = tegra_sor_set_parent_clock(sor, sor->clk_safe); + if (err < 0) + dev_err(sor->dev, "failed to set safe clock: %d\n", err); + + err = tegra_sor_power_down(sor); + if (err < 0) + dev_err(sor->dev, "failed to power down SOR: %d\n", err); + + err = tegra_io_pad_power_disable(sor->pad); + if (err < 0) + dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); + + err = drm_dp_aux_disable(sor->aux); + if (err < 0) + dev_err(sor->dev, "failed disable DPAUX: %d\n", err); + + pm_runtime_put(sor->dev); +} + +static void tegra_sor_dp_enable(struct drm_encoder *encoder) +{ + struct tegra_output *output = encoder_to_output(encoder); + struct tegra_dc *dc = to_tegra_dc(encoder->crtc); + struct tegra_sor *sor = to_sor(output); + struct tegra_sor_config config; + struct tegra_sor_state *state; + struct drm_display_mode *mode; + struct drm_display_info *info; + unsigned int i; + u32 value; + int err; + + state = to_sor_state(output->connector.state); + mode = &encoder->crtc->state->adjusted_mode; + info = &output->connector.display_info; + + pm_runtime_get_sync(sor->dev); + + /* switch to safe parent clock */ + err = tegra_sor_set_parent_clock(sor, sor->clk_safe); + if (err < 0) + dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + + err = tegra_io_pad_power_enable(sor->pad); + if (err < 0) + dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); + + usleep_range(20, 100); + + err = drm_dp_aux_enable(sor->aux); + if (err < 0) + dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); + + err = drm_dp_link_probe(sor->aux, &sor->link); + if (err < 0) + dev_err(sor->dev, "failed to probe DP link: %d\n", err); + + err = drm_dp_link_choose(&sor->link, mode, info); + if (err < 0) + dev_err(sor->dev, "failed to choose link: %d\n", err); + + value = tegra_sor_readl(sor, sor->soc->regs->pll2); + value &= ~SOR_PLL2_BANDGAP_POWERDOWN; + tegra_sor_writel(sor, value, sor->soc->regs->pll2); + + usleep_range(20, 40); + + value = tegra_sor_readl(sor, sor->soc->regs->pll3); + value |= SOR_PLL3_PLL_VDD_MODE_3V3; + tegra_sor_writel(sor, value, sor->soc->regs->pll3); + + value = tegra_sor_readl(sor, sor->soc->regs->pll0); + value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); + tegra_sor_writel(sor, value, sor->soc->regs->pll0); + + value = tegra_sor_readl(sor, sor->soc->regs->pll2); + value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; + value |= SOR_PLL2_SEQ_PLLCAPPD; + tegra_sor_writel(sor, value, sor->soc->regs->pll2); + + usleep_range(200, 400); + + value = tegra_sor_readl(sor, sor->soc->regs->pll2); + value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; + value &= ~SOR_PLL2_PORT_POWERDOWN; + tegra_sor_writel(sor, value, sor->soc->regs->pll2); + + value = tegra_sor_readl(sor, SOR_CLK_CNTRL); + value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; + value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); + + usleep_range(200, 400); + + value = tegra_sor_readl(sor, SOR_DP_SPARE0); + /* XXX not in TRM */ + value &= ~SOR_DP_SPARE_PANEL_INTERNAL; + value |= SOR_DP_SPARE_SEQ_ENABLE; + tegra_sor_writel(sor, value, SOR_DP_SPARE0); + + /* XXX not in TRM */ + tegra_sor_writel(sor, 0, SOR_LVDS); + + value = tegra_sor_readl(sor, sor->soc->regs->pll0); + value &= ~SOR_PLL0_ICHPMP_MASK; + value &= ~SOR_PLL0_VCOCAP_MASK; + value |= SOR_PLL0_ICHPMP(0x1); + value |= SOR_PLL0_VCOCAP(0x3); + value |= SOR_PLL0_RESISTOR_EXT; + tegra_sor_writel(sor, value, sor->soc->regs->pll0); + + /* XXX not in TRM */ + for (value = 0, i = 0; i < 5; i++) + value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | + SOR_XBAR_CTRL_LINK1_XSEL(i, i); + + tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); + tegra_sor_writel(sor, value, SOR_XBAR_CTRL); + + /* switch to DP parent clock */ + err = tegra_sor_set_parent_clock(sor, sor->clk_pad); + if (err < 0) { + dev_err(sor->dev, "failed to switch to pad clock: %d\n", err); + return; + } + + err = clk_set_parent(sor->clk, sor->clk_parent); + if (err < 0) { + dev_err(sor->dev, "failed to switch to parent clock: %d\n", err); + return; + } + + /* use DP-A protocol */ + value = tegra_sor_readl(sor, SOR_STATE1); + value &= ~SOR_STATE_ASY_PROTOCOL_MASK; + value |= SOR_STATE_ASY_PROTOCOL_DP_A; + tegra_sor_writel(sor, value, SOR_STATE1); + + /* enable port */ + value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); + value |= SOR_DP_LINKCTL_ENABLE; + tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); + + tegra_sor_dp_term_calibrate(sor); + + err = drm_dp_link_train(&sor->link); + if (err < 0) + dev_err(sor->dev, "link training failed: %d\n", err); + else + dev_dbg(sor->dev, "link training succeeded\n"); + + err = drm_dp_link_power_up(sor->aux, &sor->link); + if (err < 0) + dev_err(sor->dev, "failed to power up DP link: %d\n", err); + + /* compute configuration */ + memset(&config, 0, sizeof(config)); + config.bits_per_pixel = state->bpc * 3; + + err = tegra_sor_compute_config(sor, mode, &config, &sor->link); + if (err < 0) + dev_err(sor->dev, "failed to compute configuration: %d\n", err); + + tegra_sor_apply_config(sor, &config); + tegra_sor_mode_set(sor, mode, state); + tegra_sor_update(sor); + + err = tegra_sor_power_up(sor, 250); + if (err < 0) + dev_err(sor->dev, "failed to power up SOR: %d\n", err); + + /* attach and wake up */ + err = tegra_sor_attach(sor); + if (err < 0) + dev_err(sor->dev, "failed to attach SOR: %d\n", err); + + value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); + value |= SOR_ENABLE(sor->index); + tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); + + tegra_dc_commit(dc); + + err = tegra_sor_wakeup(sor); + if (err < 0) + dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); +} + +static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { + .disable = tegra_sor_dp_disable, + .enable = tegra_sor_dp_enable, + .atomic_check = tegra_sor_encoder_atomic_check, +}; + static int tegra_sor_init(struct host1x_client *client) { struct drm_device *drm = dev_get_drvdata(client->parent); @@ -2930,6 +3160,7 @@ static int tegra_sor_init(struct host1x_client *client) } else if (sor->soc->supports_dp) { connector = DRM_MODE_CONNECTOR_DisplayPort; encoder = DRM_MODE_ENCODER_TMDS; + helpers = &tegra_sor_dp_helpers; } sor->link.ops = &tegra_sor_dp_link_ops; @@ -3115,6 +3346,43 @@ static const struct tegra_sor_ops tegra_sor_hdmi_ops = { .remove = tegra_sor_hdmi_remove, }; +static int tegra_sor_dp_probe(struct tegra_sor *sor) +{ + int err; + + sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); + if (IS_ERR(sor->avdd_io_supply)) + return PTR_ERR(sor->avdd_io_supply); + + err = regulator_enable(sor->avdd_io_supply); + if (err < 0) + return err; + + sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); + if (IS_ERR(sor->vdd_pll_supply)) + return PTR_ERR(sor->vdd_pll_supply); + + err = regulator_enable(sor->vdd_pll_supply); + if (err < 0) + return err; + + return 0; +} + +static int tegra_sor_dp_remove(struct tegra_sor *sor) +{ + regulator_disable(sor->vdd_pll_supply); + regulator_disable(sor->avdd_io_supply); + + return 0; +} + +static const struct tegra_sor_ops tegra_sor_dp_ops = { + .name = "DP", + .probe = tegra_sor_dp_probe, + .remove = tegra_sor_dp_remove, +}; + static const u8 tegra124_sor_xbar_cfg[5] = { 0, 1, 2, 3, 4 }; @@ -3308,6 +3576,10 @@ static const u8 tegra210_sor_xbar_cfg[5] = { 2, 1, 0, 3, 4 }; +static const u8 tegra210_sor_lane_map[4] = { + 0, 1, 2, 3, +}; + static const struct tegra_sor_soc tegra210_sor = { .supports_edp = true, .supports_lvds = false, @@ -3318,6 +3590,11 @@ static const struct tegra_sor_soc tegra210_sor = { .has_nvdisplay = false, .xbar_cfg = tegra210_sor_xbar_cfg, + .lane_map = tegra210_sor_lane_map, + .voltage_swing = tegra124_sor_voltage_swing, + .pre_emphasis = tegra124_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, }; static const struct tegra_sor_soc tegra210_sor1 = { @@ -3332,6 +3609,11 @@ static const struct tegra_sor_soc tegra210_sor1 = { .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), .settings = tegra210_sor_hdmi_defaults, .xbar_cfg = tegra210_sor_xbar_cfg, + .lane_map = tegra210_sor_lane_map, + .voltage_swing = tegra124_sor_voltage_swing, + .pre_emphasis = tegra124_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, }; static const struct tegra_sor_regs tegra186_sor_regs = { @@ -3349,6 +3631,54 @@ static const struct tegra_sor_regs tegra186_sor_regs = { .dp_padctl2 = 0x16a, }; +static const u8 tegra186_sor_voltage_swing[4][4][4] = { + { + { 0x13, 0x19, 0x1e, 0x28 }, + { 0x1e, 0x25, 0x2d, }, + { 0x28, 0x32, }, + { 0x39, }, + }, { + { 0x12, 0x16, 0x1b, 0x25 }, + { 0x1c, 0x23, 0x2a, }, + { 0x25, 0x2f, }, + { 0x37, } + }, { + { 0x12, 0x16, 0x1a, 0x22 }, + { 0x1b, 0x20, 0x27, }, + { 0x24, 0x2d, }, + { 0x35, }, + }, { + { 0x11, 0x14, 0x17, 0x1f }, + { 0x19, 0x1e, 0x24, }, + { 0x22, 0x2a, }, + { 0x32, }, + }, +}; + +static const u8 tegra186_sor_pre_emphasis[4][4][4] = { + { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x01, 0x0e, 0x1d, }, + { 0x01, 0x13, }, + { 0x00, }, + }, { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x00, 0x0e, 0x1d, }, + { 0x00, 0x13, }, + { 0x00 }, + }, { + { 0x00, 0x08, 0x14, 0x24 }, + { 0x00, 0x0e, 0x1d, }, + { 0x00, 0x13, }, + { 0x00, }, + }, { + { 0x00, 0x08, 0x12, 0x24 }, + { 0x00, 0x0e, 0x1d, }, + { 0x00, 0x13, }, + { 0x00, }, + }, +}; + static const struct tegra_sor_soc tegra186_sor = { .supports_edp = false, .supports_lvds = false, @@ -3359,6 +3689,11 @@ static const struct tegra_sor_soc tegra186_sor = { .has_nvdisplay = true, .xbar_cfg = tegra124_sor_xbar_cfg, + .lane_map = tegra124_sor_lane_map, + .voltage_swing = tegra186_sor_voltage_swing, + .pre_emphasis = tegra186_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, }; static const struct tegra_sor_soc tegra186_sor1 = { @@ -3373,6 +3708,11 @@ static const struct tegra_sor_soc tegra186_sor1 = { .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), .settings = tegra186_sor_hdmi_defaults, .xbar_cfg = tegra124_sor_xbar_cfg, + .lane_map = tegra124_sor_lane_map, + .voltage_swing = tegra186_sor_voltage_swing, + .pre_emphasis = tegra186_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, }; static const struct tegra_sor_regs tegra194_sor_regs = { @@ -3530,8 +3870,7 @@ static int tegra_sor_probe(struct platform_device *pdev) sor->ops = &tegra_sor_edp_ops; sor->pad = TEGRA_IO_PAD_LVDS; } else if (sor->soc->supports_dp) { - dev_err(&pdev->dev, "DisplayPort not supported yet\n"); - return -ENODEV; + sor->ops = &tegra_sor_dp_ops; } else { dev_err(&pdev->dev, "unknown (DP) support\n"); return -ENODEV; diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h index 5333406c0401..00e09d5dca30 100644 --- a/drivers/gpu/drm/tegra/sor.h +++ b/drivers/gpu/drm/tegra/sor.h @@ -39,6 +39,7 @@ #define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6) #define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6) #define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6) +#define SOR_STATE_ASY_SUBOWNER_MASK (0x3 << 4) #define SOR_STATE_ASY_OWNER_MASK 0xf #define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0) From patchwork Thu Oct 24 16:45:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4C5C14ED for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id g5sm3596115wmg.12.2019.10.24.09.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:25 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 22/32] drm/tegra: sor: Remove tegra186-sor1 support Date: Thu, 24 Oct 2019 18:45:24 +0200 Message-Id: <20191024164534.132764-23-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NT91ixyOydK7qB96GIPJOfEspuJPPBJ5IFvHC12wAR8=; b=i5ZvW56P9o2vrG223SkKlNPdXMG9zWHHbDYW525HN4gnSUp0eii74knnQ2y/Pm+vGT 4Le1b81W8dEXQl4E8+TYHNX6b+/jQJcc6EQso72skJUHSTd8s4e2mR5ioivA38VVN0nQ WStZKlHF3emj0pIvcqcdlGUA+et2LkbMzZYH2oI191s1rVrapoAc42nApWQ7CeJrQb7K ZxRewovB7f6BzxsRViin2EGNObaxcucUfjbaMeOmOBHuFThI3efhWDBA+s/v/n6Nb/XX 09J8+/lorpSSgqVjboGTqb08EIAUxw98mjBTZB52b4GywsFSJ/9A4MSndZi6MYvclr0L K8Ng== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding It turns out that SOR1 is just another instance of the same block as the SOR0, so there is no need to distinguish them. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 9cf008d7c67b..4e46524f22e3 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3680,23 +3680,6 @@ static const u8 tegra186_sor_pre_emphasis[4][4][4] = { }; static const struct tegra_sor_soc tegra186_sor = { - .supports_edp = false, - .supports_lvds = false, - .supports_hdmi = false, - .supports_dp = true, - - .regs = &tegra186_sor_regs, - .has_nvdisplay = true, - - .xbar_cfg = tegra124_sor_xbar_cfg, - .lane_map = tegra124_sor_lane_map, - .voltage_swing = tegra186_sor_voltage_swing, - .pre_emphasis = tegra186_sor_pre_emphasis, - .post_cursor = tegra124_sor_post_cursor, - .tx_pu = tegra124_sor_tx_pu, -}; - -static const struct tegra_sor_soc tegra186_sor1 = { .supports_edp = false, .supports_lvds = false, .supports_hdmi = true, @@ -3747,7 +3730,6 @@ static const struct tegra_sor_soc tegra194_sor = { static const struct of_device_id tegra_sor_of_match[] = { { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, - { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, From patchwork Thu Oct 24 16:45:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A70B1747 for ; Thu, 24 Oct 2019 16:46:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 031AD21906 for ; Thu, 24 Oct 2019 16:46:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 031AD21906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5059B6E51D; Thu, 24 Oct 2019 16:46:35 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by gabe.freedesktop.org (Postfix) with ESMTPS id B9E7D6E4B0 for ; Thu, 24 Oct 2019 16:46:30 +0000 (UTC) Received: by mail-wr1-x442.google.com with SMTP id w18so26324238wrt.3 for ; Thu, 24 Oct 2019 09:46:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D2UeHNMAu5Kp/NPx+tAQiEXLV+mubgyLK0Vp0oNiIw4=; b=OFxhayJ2OpxbKPMvSYhued0WmKehtRuKdC0WwGLlD4qtVjiFFAgVO/CMPo6VIYXUmm m2QUppQvFrRM79ooEfmzP3rgp8zNt44OP9Ycxz7nQfQHgfTIPaog8WJoeY+8wfRak1KY nG78eDSDfgMlZUxy1b6srcjf+ROWh7yBCTo/79Xkoq0vcT1jANmnKgXwuchnEy2xgphf MU/MtgIsXxMYPFK22ttGpkYHxigfog8fykzy0ZEvabW+xT/Dr6ERRhJXq2i/nMmwX3/5 USWKPYWgrX8NRGbKnnDqFpnvQALujGDjfQyYOL9aYwWhFiVXr7q0EPOI/q6ckIqjQHz8 97pQ== X-Gm-Message-State: APjAAAXBDb8YqeNvqL48xcDGTMgzFc5nAUzZVD16Bd1DyRjWMLVpFQ0+ N/MaVN/Mx7cfTd0bQEC4rAk= X-Google-Smtp-Source: APXvYqzGma/6UYiNaI9+S5cw8bjU4PeFSo4H3FYFriV7jsX8/NdZXwin70oGzSbXfI/jbdfyI0l1nQ== X-Received: by 2002:adf:b219:: with SMTP id u25mr4502900wra.327.1571935589180; Thu, 24 Oct 2019 09:46:29 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id p1sm3659739wmg.11.2019.10.24.09.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:27 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 23/32] drm/tegra: sor: Use correct SOR index on Tegra210 Date: Thu, 24 Oct 2019 18:45:25 +0200 Message-Id: <20191024164534.132764-24-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D2UeHNMAu5Kp/NPx+tAQiEXLV+mubgyLK0Vp0oNiIw4=; b=X9rcVWrs/1mfietCC2Er6ap+BVS2bZF8wpnpbAb+UxfvqyrEPrvT0pmGgLzuLi7iTE xL//lYlvsOAnDFOPFrBHZWhNYLo3PF+Wke7ApVj5xqvkVSbAs7DsP6aJ6bOfxWVGa39i hOCgIF3R3LiLBZfrJJxnWB1NRTN+akgb5dQZ6EtiyXu6HVOLrk5zFryt46fpcyFjPyk6 iBjXn6Y0dca9oW+5vgb4g73Jnaf85320gIZ96QScP2k3+CaHdXZTF1xvOHcDPLb7+OZG MxloX42KS60/VyYHyCBn3qJ0/P6q9ljEv91y4PRJBqSAlgVC64u97AFyh2ZFsuSI7+aC 4FEg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The device tree bindings for the Tegra210 SOR don't require the controller instance to be defined, since the instance can be derived from the compatible string. The index is never used on Tegra210, so we got away with it not getting set. However, subsequent patches will change that, so make sure the proper index is used. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 4e46524f22e3..c7faf088cabc 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3759,6 +3759,11 @@ static int tegra_sor_parse_dt(struct tegra_sor *sor) * earlier */ sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; + } else { + if (sor->soc->supports_edp) + sor->index = 0; + else + sor->index = 1; } err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); From patchwork Thu Oct 24 16:45:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210325 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A9DD14ED for ; Thu, 24 Oct 2019 16:47:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 829D720659 for ; Thu, 24 Oct 2019 16:47:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 829D720659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B31F6E532; Thu, 24 Oct 2019 16:46:54 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id 585216E503 for ; Thu, 24 Oct 2019 16:46:33 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id v9so15587284wrq.5 for ; Thu, 24 Oct 2019 09:46:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J+teLrDmUq/g4c7wc3+RbjUGyVD2T7B6IPhjV4FrY+o=; b=f5br7k/8uS5k52zu6tRdgMK8wdRxL6CICBQ4UTBZsrVMqfo+qxoojr7MMB2GSo2mV3 uA5Fp2cfrprvK/rlz58qMV3WIKyHc6GRbwO4pdJySjuDRzm9yUcBbOMOVjM3k1nb5YVW O32MR0g9Juuo/3D6D3YBKTvzYl0XccQfaf1xYDW3ISP265We63NjggeVVnqcuwfZh4bo ZVCR46mtYXhXVyIoRPPPGkvK9N+jfex5uXCOTJLRhUyYIg1mMpK3oyBVJSblGhsFzs4F PUaIM8h8+hPWg6DN/eOb8qllZA3pNVuqaDqQP8wdV2Mt27PgfEAFSbX4N1qIoXuEcAXb Lefw== X-Gm-Message-State: APjAAAUSJoLPIKU5p7iL6AkMcDS+iUroZQidYcy1PMG0EVoQjfh/N0Tk jpyEeJm2kUO8aTcc6e4p9zVJsn+T X-Google-Smtp-Source: APXvYqxILzNyOiSXsbSp1f4vtgYmepdyNF/ujbe8i31SrmYnTTz3zGzE96FmDDaPMXk7zs4FolzQig== X-Received: by 2002:a5d:638f:: with SMTP id p15mr4963666wru.150.1571935591737; Thu, 24 Oct 2019 09:46:31 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id r1sm19783003wrw.60.2019.10.24.09.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:30 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 24/32] drm/tegra: sor: Implement pad clock for all SOR instances Date: Thu, 24 Oct 2019 18:45:26 +0200 Message-Id: <20191024164534.132764-25-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J+teLrDmUq/g4c7wc3+RbjUGyVD2T7B6IPhjV4FrY+o=; b=NyyAEeonT461+ilpnoe9F3HqNKX94i5GlETWA3k3XcYZKsdNMiUKnSvbP/5deI4iKW ubNd2lZ9FTtDB+me9TNBpM9TiJy4UfNEHxQewT6OlHkvyePtViLsc7DzByadrucAw0kd Hr5fU9cLv0L+o2Pf3mdcnZum/u5tDcmKuVXFmz2+vnidYUhcqdX/IYTTDUiAGSRCEiNT JSHwpRAjc9vl4ppV7Ak0KuUZliyhLF+mgv+X6SsOm2SCkCy43viXwwHozx+G4OLDeRt6 72J7ASNqun16rvb7fu1aHSMD2p38wPvNMPizTqreKikFzsKh46DxFGP+WYzn7jt63gNp IHYg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding So far the pad clock was only needed on the second SOR instance. The clock does exist for all SOR instances, though, so make sure it is always implemented. This prepares for further unification of the code in subsequent patches. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index c7faf088cabc..71a7ed57cb4f 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -522,8 +522,9 @@ static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) return container_of(hw, struct tegra_clk_sor_pad, hw); } -static const char * const tegra_clk_sor_pad_parents[] = { - "pll_d2_out0", "pll_dp" +static const char * const tegra_clk_sor_pad_parents[2][2] = { + { "pll_d_out0", "pll_dp" }, + { "pll_d2_out0", "pll_dp" }, }; static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) @@ -594,8 +595,8 @@ static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, init.name = name; init.flags = 0; - init.parent_names = tegra_clk_sor_pad_parents; - init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents); + init.parent_names = tegra_clk_sor_pad_parents[sor->index]; + init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); init.ops = &tegra_clk_sor_pad_ops; pad->hw.init = &init; @@ -4016,6 +4017,8 @@ static int tegra_sor_probe(struct platform_device *pdev) * pad output clock. */ if (!sor->clk_pad) { + char *name; + err = pm_runtime_get_sync(&pdev->dev); if (err < 0) { dev_err(&pdev->dev, "failed to get runtime PM: %d\n", @@ -4023,8 +4026,13 @@ static int tegra_sor_probe(struct platform_device *pdev) goto remove; } - sor->clk_pad = tegra_clk_sor_pad_register(sor, - "sor1_pad_clkout"); + name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "sor%u_pad_clkout", sor->index); + if (!name) { + err = -ENOMEM; + goto remove; + } + + sor->clk_pad = tegra_clk_sor_pad_register(sor, name); pm_runtime_put(&pdev->dev); } From patchwork Thu Oct 24 16:45:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210323 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE7E21747 for ; Thu, 24 Oct 2019 16:47:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 960C820659 for ; Thu, 24 Oct 2019 16:47:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 960C820659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E9356E525; Thu, 24 Oct 2019 16:46:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB5D96E532 for ; Thu, 24 Oct 2019 16:46:35 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id t16so21735393wrr.1 for ; Thu, 24 Oct 2019 09:46:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iMW1mQmGwhfwXdD0TwS083j3m2VDJ4duIHXhlFj6dGs=; b=Nd+kd+8CMeGFtm+yMDTzM6+SoKIsbUE2G12vFeVm+FvATIv7zQCGyP3FfNGgo5/XbU 8oHdPHU0W/oPuK9RuZ2tUKe5AThfTFqVhkcqin99eBt6ryffxLo1Sr5mnhLesIZy32LO 2na4wl9WEaMYWGnx10pOVEvHweRlvEa9uIpMxKKD0vV/25nY8zIZmSwnLl6jfnHnrddx eLWBsa/i/amf6EDfvx+l+DbLSp4g2pVJ2ytd8BbyzPflQIGm7S1XsYS4mVjBy0lmRuzt 0mKfuP4SXDY4a/WLRp6aLzIAKu7GEIw1qdHrckPbGos/xRJxFjkV+gdLjvaLujNPEgID kdKA== X-Gm-Message-State: APjAAAVA0CoPpYnz9hJtb3etlQp6fNi5ynDyU/Pog/UUgmf/cEyrAhIO 2ayT7OQUw+0U9GIpjJO0AZQ= X-Google-Smtp-Source: APXvYqwVw44G8up3OS83sLFxGoT/QcfUFY9wLUHtHn16GMxo2IjKgwdHCVgeXS2Uo/LjEyJZNWzk+A== X-Received: by 2002:a5d:6787:: with SMTP id v7mr4902264wru.392.1571935593949; Thu, 24 Oct 2019 09:46:33 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id q18sm82168wmk.39.2019.10.24.09.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:32 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 25/32] drm/tegra: sor: Deduplicate connector type detection code Date: Thu, 24 Oct 2019 18:45:27 +0200 Message-Id: <20191024164534.132764-26-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iMW1mQmGwhfwXdD0TwS083j3m2VDJ4duIHXhlFj6dGs=; b=QYhXARciu25ZEWJRn9o+psu9voKzav1JhB48fbUwCZSIaXb/PzD+4Mfx41+4A5yTlu mubvTGZQxcPDOinhWLRLxW3lUyXSYCTo86ITUpw+s0aE2GI2HhBGZnA9wzAEvLExmmEi AgUEdcdNW4dYkMSxEdgCk0P0cxWu9Xzijfo9lHj7c8/fYmZs8J+VaYYFrEt3rWG3H0i/ hFH50c/1xVaOsOGUZ/ItpPjM/JrOBTkqFfxpYkZefFtEiFfEtTPINmXPwhvD7eU6Xa6e /ftBmcMmesrN8ZuGJ/78rtc/FVNDr/6c1CFGyR5CxnxBJF7KjB5EDs3sK1QtPtlwHR4L gYmw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The connector type detection code is duplicated in two places. Keeping both places in sync is an extra maintenance burden that can be avoided by comparing the connector type operations that are set upon the first detection. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 218 ++++++++++++++++++------------------ 1 file changed, 109 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 71a7ed57cb4f..af234d5efbd7 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3135,6 +3135,112 @@ static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { .atomic_check = tegra_sor_encoder_atomic_check, }; +static const struct tegra_sor_ops tegra_sor_edp_ops = { + .name = "eDP", +}; + +static int tegra_sor_hdmi_probe(struct tegra_sor *sor) +{ + int err; + + sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); + if (IS_ERR(sor->avdd_io_supply)) { + dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", + PTR_ERR(sor->avdd_io_supply)); + return PTR_ERR(sor->avdd_io_supply); + } + + err = regulator_enable(sor->avdd_io_supply); + if (err < 0) { + dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", + err); + return err; + } + + sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); + if (IS_ERR(sor->vdd_pll_supply)) { + dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", + PTR_ERR(sor->vdd_pll_supply)); + return PTR_ERR(sor->vdd_pll_supply); + } + + err = regulator_enable(sor->vdd_pll_supply); + if (err < 0) { + dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", + err); + return err; + } + + sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); + if (IS_ERR(sor->hdmi_supply)) { + dev_err(sor->dev, "cannot get HDMI supply: %ld\n", + PTR_ERR(sor->hdmi_supply)); + return PTR_ERR(sor->hdmi_supply); + } + + err = regulator_enable(sor->hdmi_supply); + if (err < 0) { + dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); + return err; + } + + INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); + + return 0; +} + +static int tegra_sor_hdmi_remove(struct tegra_sor *sor) +{ + regulator_disable(sor->hdmi_supply); + regulator_disable(sor->vdd_pll_supply); + regulator_disable(sor->avdd_io_supply); + + return 0; +} + +static const struct tegra_sor_ops tegra_sor_hdmi_ops = { + .name = "HDMI", + .probe = tegra_sor_hdmi_probe, + .remove = tegra_sor_hdmi_remove, +}; + +static int tegra_sor_dp_probe(struct tegra_sor *sor) +{ + int err; + + sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); + if (IS_ERR(sor->avdd_io_supply)) + return PTR_ERR(sor->avdd_io_supply); + + err = regulator_enable(sor->avdd_io_supply); + if (err < 0) + return err; + + sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); + if (IS_ERR(sor->vdd_pll_supply)) + return PTR_ERR(sor->vdd_pll_supply); + + err = regulator_enable(sor->vdd_pll_supply); + if (err < 0) + return err; + + return 0; +} + +static int tegra_sor_dp_remove(struct tegra_sor *sor) +{ + regulator_disable(sor->vdd_pll_supply); + regulator_disable(sor->avdd_io_supply); + + return 0; +} + +static const struct tegra_sor_ops tegra_sor_dp_ops = { + .name = "DP", + .probe = tegra_sor_dp_probe, + .remove = tegra_sor_dp_remove, +}; + static int tegra_sor_init(struct host1x_client *client) { struct drm_device *drm = dev_get_drvdata(client->parent); @@ -3145,7 +3251,7 @@ static int tegra_sor_init(struct host1x_client *client) int err; if (!sor->aux) { - if (sor->soc->supports_hdmi) { + if (sor->ops == &tegra_sor_hdmi_ops) { connector = DRM_MODE_CONNECTOR_HDMIA; encoder = DRM_MODE_ENCODER_TMDS; helpers = &tegra_sor_hdmi_helpers; @@ -3154,11 +3260,11 @@ static int tegra_sor_init(struct host1x_client *client) encoder = DRM_MODE_ENCODER_LVDS; } } else { - if (sor->soc->supports_edp) { + if (sor->ops == &tegra_sor_edp_ops) { connector = DRM_MODE_CONNECTOR_eDP; encoder = DRM_MODE_ENCODER_TMDS; helpers = &tegra_sor_edp_helpers; - } else if (sor->soc->supports_dp) { + } else { connector = DRM_MODE_CONNECTOR_DisplayPort; encoder = DRM_MODE_ENCODER_TMDS; helpers = &tegra_sor_dp_helpers; @@ -3278,112 +3384,6 @@ static const struct host1x_client_ops sor_client_ops = { .exit = tegra_sor_exit, }; -static const struct tegra_sor_ops tegra_sor_edp_ops = { - .name = "eDP", -}; - -static int tegra_sor_hdmi_probe(struct tegra_sor *sor) -{ - int err; - - sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); - if (IS_ERR(sor->avdd_io_supply)) { - dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", - PTR_ERR(sor->avdd_io_supply)); - return PTR_ERR(sor->avdd_io_supply); - } - - err = regulator_enable(sor->avdd_io_supply); - if (err < 0) { - dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", - err); - return err; - } - - sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); - if (IS_ERR(sor->vdd_pll_supply)) { - dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", - PTR_ERR(sor->vdd_pll_supply)); - return PTR_ERR(sor->vdd_pll_supply); - } - - err = regulator_enable(sor->vdd_pll_supply); - if (err < 0) { - dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", - err); - return err; - } - - sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); - if (IS_ERR(sor->hdmi_supply)) { - dev_err(sor->dev, "cannot get HDMI supply: %ld\n", - PTR_ERR(sor->hdmi_supply)); - return PTR_ERR(sor->hdmi_supply); - } - - err = regulator_enable(sor->hdmi_supply); - if (err < 0) { - dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); - return err; - } - - INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); - - return 0; -} - -static int tegra_sor_hdmi_remove(struct tegra_sor *sor) -{ - regulator_disable(sor->hdmi_supply); - regulator_disable(sor->vdd_pll_supply); - regulator_disable(sor->avdd_io_supply); - - return 0; -} - -static const struct tegra_sor_ops tegra_sor_hdmi_ops = { - .name = "HDMI", - .probe = tegra_sor_hdmi_probe, - .remove = tegra_sor_hdmi_remove, -}; - -static int tegra_sor_dp_probe(struct tegra_sor *sor) -{ - int err; - - sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); - if (IS_ERR(sor->avdd_io_supply)) - return PTR_ERR(sor->avdd_io_supply); - - err = regulator_enable(sor->avdd_io_supply); - if (err < 0) - return err; - - sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); - if (IS_ERR(sor->vdd_pll_supply)) - return PTR_ERR(sor->vdd_pll_supply); - - err = regulator_enable(sor->vdd_pll_supply); - if (err < 0) - return err; - - return 0; -} - -static int tegra_sor_dp_remove(struct tegra_sor *sor) -{ - regulator_disable(sor->vdd_pll_supply); - regulator_disable(sor->avdd_io_supply); - - return 0; -} - -static const struct tegra_sor_ops tegra_sor_dp_ops = { - .name = "DP", - .probe = tegra_sor_dp_probe, - .remove = tegra_sor_dp_remove, -}; - static const u8 tegra124_sor_xbar_cfg[5] = { 0, 1, 2, 3, 4 }; From patchwork Thu Oct 24 16:45:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210321 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C9AD13B1 for ; Thu, 24 Oct 2019 16:47:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 352A520659 for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id v128sm4455330wmb.14.2019.10.24.09.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:35 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 26/32] drm/tegra: sor: Support DisplayPort on Tegra194 Date: Thu, 24 Oct 2019 18:45:28 +0200 Message-Id: <20191024164534.132764-27-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZImZ2aYVtus8sIvpoq9U8jJL9U3kFR2rDXns/Vgt5XE=; b=e3YdW4gAuq7BDVpzoPNbRXuhb+yjojW9302LnJrx7BEJmnVsvxyhyMn862RoZBh4Dt 6Q7zCdjSBcg3HpcmYB2xyM85dtwrZCq3YJ33xKRV+tNN1d+6bUswVcodc6xCt+EUA/P9 zaC4p96h7ilg5MKZ4pSjvpTITIkB+DdvQqtWSXse1t4am6BnXkqDMKZivwgeE4F9BS2a B/a6edUlQ0KBnTLS7O8F4UNA75VegUrbnjqZCFAo4ZdITFcPkX5ZoRf3ASCpT6cMvgU9 TFTP3dR3mI4CGCvzZCbqMviWka3w1rDXniT7DPX+3uZ3YFj15RAjedhmQvB5Su0N4ywh SlMw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding Reuse parameters from earlier generations to support DisplayPort on Tegra194. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index af234d5efbd7..fdbd76ec1cf7 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3727,6 +3727,11 @@ static const struct tegra_sor_soc tegra194_sor = { .settings = tegra194_sor_hdmi_defaults, .xbar_cfg = tegra210_sor_xbar_cfg, + .lane_map = tegra124_sor_lane_map, + .voltage_swing = tegra186_sor_voltage_swing, + .pre_emphasis = tegra186_sor_pre_emphasis, + .post_cursor = tegra124_sor_post_cursor, + .tx_pu = tegra124_sor_tx_pu, }; static const struct of_device_id tegra_sor_of_match[] = { From patchwork Thu Oct 24 16:45:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210313 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED38C13B1 for ; Thu, 24 Oct 2019 16:46:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5BF020659 for ; Thu, 24 Oct 2019 16:46:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5BF020659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0C1896E51B; Thu, 24 Oct 2019 16:46:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id 728D66E507 for ; Thu, 24 Oct 2019 16:46:40 +0000 (UTC) Received: by mail-wm1-x343.google.com with SMTP id g24so3594440wmh.5 for ; Thu, 24 Oct 2019 09:46:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cu4ZaTXoU6RcuFW1hTOweUU/CS+vekzJPEEygzQ/x1w=; b=NBsdVXwJyX/ybimr3eFKduHmUQHuqyNQrCG3IqAcEgJ84dUpgh+f3PpsMtaUNR831O WeQq/Nme/vjTIJ049nwYCYzgoCxvw46JlbbIgQKMgOrwtmJNRWwO5i/e860TMTJPUD+m W3BhAjEFagdvVtjlJxMjEOT1W8VTx0Q7Spj3XuCFK0sUUrQ5O4PGT0XBbwjSYMt3XX6d +degL4QVQ2nzsAJpCR8AcROvuvZYhsjxmfmFiYxe1GeYpPlVWCOBC7yK4gGlDJVp1ywr Kb1PnjIDx/P5kXrYrxWf7gyh2NE9VcCLu8xL1jqVWH6YvpEqYG7vfsysaMbZjn/d+559 78Rg== X-Gm-Message-State: APjAAAUMj+gNBhDbKZJBEMSr9W6MkKEBYHgI3J0dLuMFLLPGoX4yNMgA FDikOriU8IK8SQWQiqlqnIc= X-Google-Smtp-Source: APXvYqzYfyl8FGtJ4trA5xN0bWqUzXTku3LpNYYPzDs5/TORC9PUXuZhVK55Zn6eufQ3hXzfzIN9qQ== X-Received: by 2002:a1c:f011:: with SMTP id a17mr5597342wmb.18.1571935598210; Thu, 24 Oct 2019 09:46:38 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id s14sm3185170wmh.18.2019.10.24.09.46.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:37 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 27/32] drm/tegra: sor: Unify clock setup for eDP, HDMI and DP Date: Thu, 24 Oct 2019 18:45:29 +0200 Message-Id: <20191024164534.132764-28-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cu4ZaTXoU6RcuFW1hTOweUU/CS+vekzJPEEygzQ/x1w=; b=E3hc2PdcoligcilS1Kw1X8ZfxWgKwt3Sn8FUwTdkYAO/B+ELfzi2jRgQ3/FVdjbPgC q6DfwU3DGGjZqeqZU+802JCciaFCVi4RZsJLiLc/7G9IiwgI+z+XEda2H+Alw6ku6B3i yzkuFXC3Ql72K+rbQiA+7QnCVq97du+gGp1NqUJA6P1DK2Ul9JRZrAaOYcNwBvow6W1f D+BUvTTxysGS/laJQaNnE/J2qaDJ2fPBsR4P/4oIN+E4xa2Al2lt2xqTzDD2YyCGoyN0 V252QhgP6DpfTSsY8lj9UYqwcX7cnC97/Jc/LTTILTBAE1Pn0iFmZrt2+lrRFM64Uvau eEVQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding With the clocks modelled consistently across SoC generations, the clock setup for eDP, HDMI and DP can now be unified. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 92 ++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index fdbd76ec1cf7..a245bbbd638a 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -527,6 +527,14 @@ static const char * const tegra_clk_sor_pad_parents[2][2] = { { "pll_d2_out0", "pll_dp" }, }; +/* + * Implementing ->set_parent() here isn't really required because the parent + * will be explicitly selected in the driver code via the DP_CLK_SEL mux in + * the SOR_CLK_CNTRL register. This is primarily for compatibility with the + * Tegra186 and later SoC generations where the BPMP implements this clock + * and doesn't expose the mux via the common clock framework. + */ + static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) { struct tegra_clk_sor_pad *pad = to_pad(hw); @@ -1987,10 +1995,36 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); tegra_sor_writel(sor, value, SOR_XBAR_CTRL); - /* switch to DP parent clock */ - err = tegra_sor_set_parent_clock(sor, sor->clk_dp); - if (err < 0) - dev_err(sor->dev, "failed to set parent clock: %d\n", err); + /* + * Switch the pad clock to the DP clock. Note that we cannot actually + * do this because Tegra186 and later don't support clk_set_parent() + * on the sorX_pad_clkout clocks. We already do the equivalent above + * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. + */ +#if 0 + err = clk_set_parent(sor->clk_pad, sor->clk_dp); + if (err < 0) { + dev_err(sor->dev, "failed to select pad parent clock: %d\n", + err); + return; + } +#endif + + /* switch the SOR clock to the pad clock */ + err = tegra_sor_set_parent_clock(sor, sor->clk_pad); + if (err < 0) { + dev_err(sor->dev, "failed to select SOR parent clock: %d\n", + err); + return; + } + + /* switch the output clock to the parent pixel clock */ + err = clk_set_parent(sor->clk, sor->clk_parent); + if (err < 0) { + dev_err(sor->dev, "failed to select output parent clock: %d\n", + err); + return; + } /* use DP-A protocol */ value = tegra_sor_readl(sor, SOR_STATE1); @@ -2661,16 +2695,34 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); tegra_sor_writel(sor, value, SOR_XBAR_CTRL); - /* switch to parent clock */ - err = clk_set_parent(sor->clk, sor->clk_parent); + /* + * Switch the pad clock to the DP clock. Note that we cannot actually + * do this because Tegra186 and later don't support clk_set_parent() + * on the sorX_pad_clkout clocks. We already do the equivalent above + * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. + */ +#if 0 + err = clk_set_parent(sor->clk_pad, sor->clk_dp); if (err < 0) { - dev_err(sor->dev, "failed to set parent clock: %d\n", err); + dev_err(sor->dev, "failed to select pad parent clock: %d\n", + err); return; } +#endif + /* switch the SOR clock to the pad clock */ err = tegra_sor_set_parent_clock(sor, sor->clk_pad); if (err < 0) { - dev_err(sor->dev, "failed to set pad clock: %d\n", err); + dev_err(sor->dev, "failed to select SOR parent clock: %d\n", + err); + return; + } + + /* switch the output clock to the parent pixel clock */ + err = clk_set_parent(sor->clk, sor->clk_parent); + if (err < 0) { + dev_err(sor->dev, "failed to select output parent clock: %d\n", + err); return; } @@ -3061,16 +3113,34 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); tegra_sor_writel(sor, value, SOR_XBAR_CTRL); - /* switch to DP parent clock */ + /* + * Switch the pad clock to the DP clock. Note that we cannot actually + * do this because Tegra186 and later don't support clk_set_parent() + * on the sorX_pad_clkout clocks. We already do the equivalent above + * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. + */ +#if 0 + err = clk_set_parent(sor->clk_pad, sor->clk_parent); + if (err < 0) { + dev_err(sor->dev, "failed to select pad parent clock: %d\n", + err); + return; + } +#endif + + /* switch the SOR clock to the pad clock */ err = tegra_sor_set_parent_clock(sor, sor->clk_pad); if (err < 0) { - dev_err(sor->dev, "failed to switch to pad clock: %d\n", err); + dev_err(sor->dev, "failed to select SOR parent clock: %d\n", + err); return; } + /* switch the output clock to the parent pixel clock */ err = clk_set_parent(sor->clk, sor->clk_parent); if (err < 0) { - dev_err(sor->dev, "failed to switch to parent clock: %d\n", err); + dev_err(sor->dev, "failed to select output parent clock: %d\n", + err); return; } From patchwork Thu Oct 24 16:45:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210319 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 295C313B1 for ; Thu, 24 Oct 2019 16:47:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10D5B20659 for ; Thu, 24 Oct 2019 16:47:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10D5B20659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EB586E524; Thu, 24 Oct 2019 16:46:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 713CC6E503 for ; Thu, 24 Oct 2019 16:46:42 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id v6so3289234wmj.0 for ; Thu, 24 Oct 2019 09:46:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EliCwXDq96B71gmhKQIK2pDZL6FbkUlF5g2UJEA6lCE=; b=Nn6Sfe6aI9sZEzlyl0DRsE4Inx+POW2GciiNjYyuFqAYqYEf/XwviPk/bnAzHOUARE eboGyXbRDBihNY8mbkFAn6a5yQv1VMDIWW/Ty36xBfhjR4e005NjKUg8aLnMggzTb+ec RXiVvdT8kGm2/OPpHIkRsk8T4gfA2teuYQV6EjVMENTSbP4Qvu3Inys+KY2x6LSdstAB 3xlM/N6hIDtFL4DkCYLEHQd0fcKrf4xqUpchBt+2+mS1qFFHN+cfIGqgRg9E/Sp4EYzz S1oEf9B/TNMmcjiKhC4ExTcdH6Ko0yp3KepRATHiTsPteaxF6nAnKQwM5qhx/PuCUEpc LYYg== X-Gm-Message-State: APjAAAVtmm2ccSp3atV8mrtTK5DkqkcxpPSJ5wkaNHc5fsywUt19HBTD ADUSZT5n59qV3Nq0p2La2R8= X-Google-Smtp-Source: APXvYqwvFzod6odWZC+ZmX9rjALdXrLhxe4c2LgwHcJSi6yumP8jY8dCeixhDvAyg/9tgA+Bhh6qzg== X-Received: by 2002:a1c:e08a:: with SMTP id x132mr5862809wmg.146.1571935600543; Thu, 24 Oct 2019 09:46:40 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id 143sm5358801wmb.33.2019.10.24.09.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:39 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 28/32] drm/tegra: sor: Use correct I/O pad for DP Date: Thu, 24 Oct 2019 18:45:30 +0200 Message-Id: <20191024164534.132764-29-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EliCwXDq96B71gmhKQIK2pDZL6FbkUlF5g2UJEA6lCE=; b=EXVxiQWenKVljq3++zs0suyTVv1WnZwcrxL5rHKCjfrrgrf5CqxDirTPmTTi+ULB1e u6+vZmJTzqtn2bHsHMufIYmo8CrifZYgx3Xc4kPjhHIhDuCoYP9xaiwKULZK6J5XZSIT 4TljH/sABEl9N63xWXUhv1v4SyCwOZahkWRKabR9HLn+MKveU2JKCagUFycYfNgTtJDr fIwuNY/jPUf3n+bsAETT3/YJWa6IHPqCSRyWvxkrIEuB8db3wm4a6bd7q1n+0pm3i617 pH7NKBw/HKcZpT/9i0oNnpCbxxEd5uyMPicCsmbiC0IX5FuU8xmhCwF0jbXJIV1I/mCV mPYw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The correct I/O pad needs to be powered up before DP can be used. Make sure the correct default is set for Tegra generations where the I/O pad cannot be derived from the SOR instance. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index a245bbbd638a..bf2e31199166 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -3934,6 +3934,7 @@ static int tegra_sor_probe(struct platform_device *pdev) sor->pad = TEGRA_IO_PAD_LVDS; } else if (sor->soc->supports_dp) { sor->ops = &tegra_sor_dp_ops; + sor->pad = TEGRA_IO_PAD_LVDS; } else { dev_err(&pdev->dev, "unknown (DP) support\n"); return -ENODEV; From patchwork Thu Oct 24 16:45:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210311 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A09DD14ED for ; Thu, 24 Oct 2019 16:46:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8855821906 for ; Thu, 24 Oct 2019 16:46:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8855821906 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3626C6E523; Thu, 24 Oct 2019 16:46:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7FB866E49A for ; Thu, 24 Oct 2019 16:46:45 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id 11so128873wmk.0 for ; Thu, 24 Oct 2019 09:46:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JRd+EeKsrdPkPHAoa/K4vedud6vOnZI24UldnRJuL1o=; b=bmqZGrYEo5qWp1ufJrMZHa4aPObsHVevB9mGcX91D4pNIsUyCE9ASqIKXfeWhJlgk+ 6/h3FODxly4t5PikyM8Tg7mGT38GTBx7cVrsnWlNQzago+qdOLKm0ojwtDpSTcG96Js5 x6AZamoOO4jdU1DXjSI9ui3v3OQKrjcbWIEe4QNkI4fxQPBFjuczG6KPfwuyRObUSY4U 9mPLBN5K+yG8FbpINTzfBI9+1Jsd+NTsvhhAR4M0wYrW3wIEbK9hy31d7f71antgm2Eo vIputHNXG4lwHMT4z+bzHYm/Ul5HfgP9Xgsvn42XQSH0A+mlu0uNwXwowToziL3GTcKf 3hIA== X-Gm-Message-State: APjAAAXRvr3lZuxMqlKQz5a6pE0KKOFBbnYehUxT4Xr8JxOvysOCmBMI kc4CiczNQyRMAoVSRkwrTcZOwU45 X-Google-Smtp-Source: APXvYqxWyKKQZOh8WvkcRPW/UWPlWq4kPtg4dR10MQ56wdE3BdMsocjBWjzg/prv7qySAP192JCkBg== X-Received: by 2002:a7b:c1d1:: with SMTP id a17mr5359295wmj.74.1571935602491; Thu, 24 Oct 2019 09:46:42 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id d4sm33410024wrc.54.2019.10.24.09.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:41 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 29/32] drm/tegra: sor: Unify eDP and DP support Date: Thu, 24 Oct 2019 18:45:31 +0200 Message-Id: <20191024164534.132764-30-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JRd+EeKsrdPkPHAoa/K4vedud6vOnZI24UldnRJuL1o=; b=YMeLv7yawSgBBZoszFFBTVksesBuapiBWzHyCHSZhEu4WMy6aHBQ3Q99lujgQOTSFm V/Y6szr5WZ/SXYN3jfbEOfaustTjZrpRyJoB9FQJ1PLKMH6keA/p/BBF00xlHsKZjCxQ 0Osy9DZDN0XfebYrPCNp8wcGV6vtJ2LrnoR0Km8/teYRQ8drJeg3NWUprZOZUGX4tKlF OmZotQGMGJGm8TXSjB/ceWl5+JtDlLgOxQGBIKSVpM0tzktrPWprq4mu/cbailDEJaBl 0VW6Hs3/plvVHE02KBZ4S2y394P1jEYSTD6wXj8jvS9hhYMEW61mTySBTTZuGvlDfjlS mhAQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The SOR0 on Tegra210 does, contrary to what was previously assumed, in fact support DisplayPort. The difference between SOR0 and SOR1 is that the latter supports audio and HDCP over DP, whereas the former doesn't. The code for eDP and DP is now almost identical and the differences can easily be parameterized based on the presence of a panel. There is no need any longer to duplicate the code. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 421 +++++++----------------------------- 1 file changed, 74 insertions(+), 347 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index bf2e31199166..63831c37ad35 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -371,10 +371,11 @@ struct tegra_sor_regs { }; struct tegra_sor_soc { - bool supports_edp; bool supports_lvds; bool supports_hdmi; bool supports_dp; + bool supports_audio; + bool supports_hdcp; const struct tegra_sor_regs *regs; bool has_nvdisplay; @@ -1806,306 +1807,6 @@ static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { .destroy = tegra_output_encoder_destroy, }; -static void tegra_sor_edp_disable(struct drm_encoder *encoder) -{ - struct tegra_output *output = encoder_to_output(encoder); - struct tegra_dc *dc = to_tegra_dc(encoder->crtc); - struct tegra_sor *sor = to_sor(output); - u32 value; - int err; - - if (output->panel) - drm_panel_disable(output->panel); - - err = tegra_sor_detach(sor); - if (err < 0) - dev_err(sor->dev, "failed to detach SOR: %d\n", err); - - tegra_sor_writel(sor, 0, SOR_STATE1); - tegra_sor_update(sor); - - value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value &= ~SOR_ENABLE(0); - tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); - - tegra_dc_commit(dc); - - err = tegra_sor_power_down(sor); - if (err < 0) - dev_err(sor->dev, "failed to power down SOR: %d\n", err); - - if (sor->aux) { - err = drm_dp_aux_disable(sor->aux); - if (err < 0) - dev_err(sor->dev, "failed to disable DP: %d\n", err); - } - - err = tegra_io_pad_power_disable(sor->pad); - if (err < 0) - dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); - - if (output->panel) - drm_panel_unprepare(output->panel); - - pm_runtime_put(sor->dev); -} - -#if 0 -static int calc_h_ref_to_sync(const struct drm_display_mode *mode, - unsigned int *value) -{ - unsigned int hfp, hsw, hbp, a = 0, b; - - hfp = mode->hsync_start - mode->hdisplay; - hsw = mode->hsync_end - mode->hsync_start; - hbp = mode->htotal - mode->hsync_end; - - pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); - - b = hfp - 1; - - pr_info("a: %u, b: %u\n", a, b); - pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); - - if (a + hsw + hbp <= 11) { - a = 1 + 11 - hsw - hbp; - pr_info("a: %u\n", a); - } - - if (a > b) - return -EINVAL; - - if (hsw < 1) - return -EINVAL; - - if (mode->hdisplay < 16) - return -EINVAL; - - if (value) { - if (b > a && a % 2) - *value = a + 1; - else - *value = a; - } - - return 0; -} -#endif - -static void tegra_sor_edp_enable(struct drm_encoder *encoder) -{ - struct tegra_output *output = encoder_to_output(encoder); - struct tegra_dc *dc = to_tegra_dc(encoder->crtc); - struct tegra_sor *sor = to_sor(output); - struct tegra_sor_config config; - struct tegra_sor_state *state; - struct drm_display_mode *mode; - struct drm_display_info *info; - unsigned int i; - u32 value; - int err; - - state = to_sor_state(output->connector.state); - mode = &encoder->crtc->state->adjusted_mode; - info = &output->connector.display_info; - - pm_runtime_get_sync(sor->dev); - - /* switch to safe parent clock */ - err = tegra_sor_set_parent_clock(sor, sor->clk_safe); - if (err < 0) - dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); - - err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); - if (err < 0) - dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); - - usleep_range(20, 100); - - err = drm_dp_aux_enable(sor->aux); - if (err < 0) - dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); - - err = drm_dp_link_probe(sor->aux, &sor->link); - if (err < 0) - dev_err(sor->dev, "failed to probe eDP link: %d\n", err); - - tegra_sor_filter_rates(sor); - - err = drm_dp_link_choose(&sor->link, mode, info); - if (err < 0) - dev_err(sor->dev, "failed to choose link: %d\n", err); - - if (output->panel) - drm_panel_prepare(output->panel); - - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value &= ~SOR_PLL2_BANDGAP_POWERDOWN; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); - - usleep_range(20, 40); - - value = tegra_sor_readl(sor, sor->soc->regs->pll3); - value |= SOR_PLL3_PLL_VDD_MODE_3V3; - tegra_sor_writel(sor, value, sor->soc->regs->pll3); - - value = tegra_sor_readl(sor, sor->soc->regs->pll0); - value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); - tegra_sor_writel(sor, value, sor->soc->regs->pll0); - - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; - value |= SOR_PLL2_SEQ_PLLCAPPD; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); - - usleep_range(200, 400); - - value = tegra_sor_readl(sor, sor->soc->regs->pll2); - value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; - value &= ~SOR_PLL2_PORT_POWERDOWN; - tegra_sor_writel(sor, value, sor->soc->regs->pll2); - - value = tegra_sor_readl(sor, SOR_CLK_CNTRL); - value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; - value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; - tegra_sor_writel(sor, value, SOR_CLK_CNTRL); - - value = tegra_sor_readl(sor, SOR_DP_SPARE0); - /* XXX not in TRM */ - value |= SOR_DP_SPARE_PANEL_INTERNAL; - value |= SOR_DP_SPARE_SEQ_ENABLE; - tegra_sor_writel(sor, value, SOR_DP_SPARE0); - - /* XXX not in TRM */ - tegra_sor_writel(sor, 0, SOR_LVDS); - - value = tegra_sor_readl(sor, sor->soc->regs->pll0); - value &= ~SOR_PLL0_ICHPMP_MASK; - value &= ~SOR_PLL0_VCOCAP_MASK; - value |= SOR_PLL0_ICHPMP(0x1); - value |= SOR_PLL0_VCOCAP(0x3); - value |= SOR_PLL0_RESISTOR_EXT; - tegra_sor_writel(sor, value, sor->soc->regs->pll0); - - /* XXX not in TRM */ - for (value = 0, i = 0; i < 5; i++) - value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | - SOR_XBAR_CTRL_LINK1_XSEL(i, i); - - tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); - tegra_sor_writel(sor, value, SOR_XBAR_CTRL); - - /* - * Switch the pad clock to the DP clock. Note that we cannot actually - * do this because Tegra186 and later don't support clk_set_parent() - * on the sorX_pad_clkout clocks. We already do the equivalent above - * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. - */ -#if 0 - err = clk_set_parent(sor->clk_pad, sor->clk_dp); - if (err < 0) { - dev_err(sor->dev, "failed to select pad parent clock: %d\n", - err); - return; - } -#endif - - /* switch the SOR clock to the pad clock */ - err = tegra_sor_set_parent_clock(sor, sor->clk_pad); - if (err < 0) { - dev_err(sor->dev, "failed to select SOR parent clock: %d\n", - err); - return; - } - - /* switch the output clock to the parent pixel clock */ - err = clk_set_parent(sor->clk, sor->clk_parent); - if (err < 0) { - dev_err(sor->dev, "failed to select output parent clock: %d\n", - err); - return; - } - - /* use DP-A protocol */ - value = tegra_sor_readl(sor, SOR_STATE1); - value &= ~SOR_STATE_ASY_PROTOCOL_MASK; - value |= SOR_STATE_ASY_PROTOCOL_DP_A; - tegra_sor_writel(sor, value, SOR_STATE1); - - /* enable port */ - value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); - value |= SOR_DP_LINKCTL_ENABLE; - tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); - - tegra_sor_dp_term_calibrate(sor); - - err = drm_dp_link_train(&sor->link); - if (err < 0) - dev_err(sor->dev, "link training failed: %d\n", err); - else - dev_dbg(sor->dev, "link training succeeded\n"); - - err = drm_dp_link_power_up(sor->aux, &sor->link); - if (err < 0) - dev_err(sor->dev, "failed to power up eDP link: %d\n", err); - - /* compute configuration */ - memset(&config, 0, sizeof(config)); - config.bits_per_pixel = state->bpc * 3; - - err = tegra_sor_compute_config(sor, mode, &config, &sor->link); - if (err < 0) - dev_err(sor->dev, "failed to compute configuration: %d\n", err); - - tegra_sor_apply_config(sor, &config); - - err = tegra_sor_power_up(sor, 250); - if (err < 0) - dev_err(sor->dev, "failed to power up SOR: %d\n", err); - - /* CSTM (LVDS, link A/B, upper) */ - value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | - SOR_CSTM_UPPER; - tegra_sor_writel(sor, value, SOR_CSTM); - - /* use DP-A protocol */ - value = tegra_sor_readl(sor, SOR_STATE1); - value &= ~SOR_STATE_ASY_PROTOCOL_MASK; - value |= SOR_STATE_ASY_PROTOCOL_DP_A; - tegra_sor_writel(sor, value, SOR_STATE1); - - tegra_sor_mode_set(sor, mode, state); - - /* PWM setup */ - err = tegra_sor_setup_pwm(sor, 250); - if (err < 0) - dev_err(sor->dev, "failed to setup PWM: %d\n", err); - - tegra_sor_update(sor); - - err = tegra_sor_power_up(sor, 250); - if (err < 0) - dev_err(sor->dev, "failed to power up SOR: %d\n", err); - - /* attach and wake up */ - err = tegra_sor_attach(sor); - if (err < 0) - dev_err(sor->dev, "failed to attach SOR: %d\n", err); - - value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - value |= SOR_ENABLE(0); - tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); - - tegra_dc_commit(dc); - - err = tegra_sor_wakeup(sor); - if (err < 0) - dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); - - if (output->panel) - drm_panel_enable(output->panel); -} - static int tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, @@ -2155,12 +1856,6 @@ tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, return 0; } -static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { - .disable = tegra_sor_edp_disable, - .enable = tegra_sor_edp_enable, - .atomic_check = tegra_sor_encoder_atomic_check, -}; - static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) { u32 value = 0; @@ -2535,9 +2230,9 @@ static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); if (!sor->soc->has_nvdisplay) - value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); - else - value &= ~SOR_ENABLE(sor->index); + value &= ~SOR1_TIMING_CYA; + + value &= ~SOR_ENABLE(sor->index); tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); @@ -2928,9 +2623,9 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); if (!sor->soc->has_nvdisplay) - value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; - else - value |= SOR_ENABLE(sor->index); + value |= SOR1_TIMING_CYA; + + value |= SOR_ENABLE(sor->index); tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); @@ -2965,6 +2660,9 @@ static void tegra_sor_dp_disable(struct drm_encoder *encoder) u32 value; int err; + if (output->panel) + drm_panel_disable(output->panel); + err = drm_dp_link_power_down(sor->aux, &sor->link); if (err < 0) dev_err(sor->dev, "failed to power down link: %d\n", err); @@ -2977,12 +2675,7 @@ static void tegra_sor_dp_disable(struct drm_encoder *encoder) tegra_sor_update(sor); value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); - - if (!sor->soc->has_nvdisplay) - value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); - else - value &= ~SOR_ENABLE(sor->index); - + value &= ~SOR_ENABLE(sor->index); tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); tegra_dc_commit(dc); @@ -3010,6 +2703,9 @@ static void tegra_sor_dp_disable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed disable DPAUX: %d\n", err); + if (output->panel) + drm_panel_unprepare(output->panel); + pm_runtime_put(sor->dev); } @@ -3051,10 +2747,15 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder) if (err < 0) dev_err(sor->dev, "failed to probe DP link: %d\n", err); + tegra_sor_filter_rates(sor); + err = drm_dp_link_choose(&sor->link, mode, info); if (err < 0) dev_err(sor->dev, "failed to choose link: %d\n", err); + if (output->panel) + drm_panel_prepare(output->panel); + value = tegra_sor_readl(sor, sor->soc->regs->pll2); value &= ~SOR_PLL2_BANDGAP_POWERDOWN; tegra_sor_writel(sor, value, sor->soc->regs->pll2); @@ -3083,14 +2784,23 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder) value = tegra_sor_readl(sor, SOR_CLK_CNTRL); value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; - value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; + + if (output->panel) + value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; + else + value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; + tegra_sor_writel(sor, value, SOR_CLK_CNTRL); usleep_range(200, 400); value = tegra_sor_readl(sor, SOR_DP_SPARE0); /* XXX not in TRM */ - value &= ~SOR_DP_SPARE_PANEL_INTERNAL; + if (output->panel) + value |= SOR_DP_SPARE_PANEL_INTERNAL; + else + value &= ~SOR_DP_SPARE_PANEL_INTERNAL; + value |= SOR_DP_SPARE_SEQ_ENABLE; tegra_sor_writel(sor, value, SOR_DP_SPARE0); @@ -3177,6 +2887,19 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder) tegra_sor_apply_config(sor, &config); tegra_sor_mode_set(sor, mode, state); + + if (output->panel) { + /* CSTM (LVDS, link A/B, upper) */ + value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | + SOR_CSTM_UPPER; + tegra_sor_writel(sor, value, SOR_CSTM); + + /* PWM setup */ + err = tegra_sor_setup_pwm(sor, 250); + if (err < 0) + dev_err(sor->dev, "failed to setup PWM: %d\n", err); + } + tegra_sor_update(sor); err = tegra_sor_power_up(sor, 250); @@ -3197,6 +2920,9 @@ static void tegra_sor_dp_enable(struct drm_encoder *encoder) err = tegra_sor_wakeup(sor); if (err < 0) dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); + + if (output->panel) + drm_panel_enable(output->panel); } static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { @@ -3205,10 +2931,6 @@ static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { .atomic_check = tegra_sor_encoder_atomic_check, }; -static const struct tegra_sor_ops tegra_sor_edp_ops = { - .name = "eDP", -}; - static int tegra_sor_hdmi_probe(struct tegra_sor *sor) { int err; @@ -3330,10 +3052,10 @@ static int tegra_sor_init(struct host1x_client *client) encoder = DRM_MODE_ENCODER_LVDS; } } else { - if (sor->ops == &tegra_sor_edp_ops) { + if (sor->output.panel) { connector = DRM_MODE_CONNECTOR_eDP; encoder = DRM_MODE_ENCODER_TMDS; - helpers = &tegra_sor_edp_helpers; + helpers = &tegra_sor_dp_helpers; } else { connector = DRM_MODE_CONNECTOR_DisplayPort; encoder = DRM_MODE_ENCODER_TMDS; @@ -3575,10 +3297,11 @@ static const u8 tegra124_sor_tx_pu[4][4][4] = { }; static const struct tegra_sor_soc tegra124_sor = { - .supports_edp = true, .supports_lvds = true, .supports_hdmi = false, - .supports_dp = false, + .supports_dp = true, + .supports_audio = false, + .supports_hdcp = false, .regs = &tegra124_sor_regs, .has_nvdisplay = false, .xbar_cfg = tegra124_sor_xbar_cfg, @@ -3614,10 +3337,11 @@ static const u8 tegra132_sor_pre_emphasis[4][4][4] = { }; static const struct tegra_sor_soc tegra132_sor = { - .supports_edp = true, .supports_lvds = true, .supports_hdmi = false, - .supports_dp = false, + .supports_dp = true, + .supports_audio = false, + .supports_hdcp = false, .regs = &tegra124_sor_regs, .has_nvdisplay = false, .xbar_cfg = tegra124_sor_xbar_cfg, @@ -3652,10 +3376,11 @@ static const u8 tegra210_sor_lane_map[4] = { }; static const struct tegra_sor_soc tegra210_sor = { - .supports_edp = true, .supports_lvds = false, .supports_hdmi = false, - .supports_dp = false, + .supports_dp = true, + .supports_audio = false, + .supports_hdcp = false, .regs = &tegra210_sor_regs, .has_nvdisplay = false, @@ -3669,10 +3394,11 @@ static const struct tegra_sor_soc tegra210_sor = { }; static const struct tegra_sor_soc tegra210_sor1 = { - .supports_edp = false, .supports_lvds = false, .supports_hdmi = true, .supports_dp = true, + .supports_audio = true, + .supports_hdcp = true, .regs = &tegra210_sor_regs, .has_nvdisplay = false, @@ -3751,10 +3477,11 @@ static const u8 tegra186_sor_pre_emphasis[4][4][4] = { }; static const struct tegra_sor_soc tegra186_sor = { - .supports_edp = false, .supports_lvds = false, .supports_hdmi = true, .supports_dp = true, + .supports_audio = true, + .supports_hdcp = true, .regs = &tegra186_sor_regs, .has_nvdisplay = true, @@ -3785,10 +3512,11 @@ static const struct tegra_sor_regs tegra194_sor_regs = { }; static const struct tegra_sor_soc tegra194_sor = { - .supports_edp = true, .supports_lvds = false, .supports_hdmi = true, .supports_dp = true, + .supports_audio = true, + .supports_hdcp = true, .regs = &tegra194_sor_regs, .has_nvdisplay = true, @@ -3836,7 +3564,7 @@ static int tegra_sor_parse_dt(struct tegra_sor *sor) */ sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; } else { - if (sor->soc->supports_edp) + if (!sor->soc->supports_audio) sor->index = 0; else sor->index = 1; @@ -3929,16 +3657,15 @@ static int tegra_sor_probe(struct platform_device *pdev) return -ENODEV; } } else { - if (sor->soc->supports_edp) { - sor->ops = &tegra_sor_edp_ops; - sor->pad = TEGRA_IO_PAD_LVDS; - } else if (sor->soc->supports_dp) { - sor->ops = &tegra_sor_dp_ops; - sor->pad = TEGRA_IO_PAD_LVDS; - } else { - dev_err(&pdev->dev, "unknown (DP) support\n"); - return -ENODEV; - } + np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); + /* + * No need to keep this around since we only use it as a check + * to see if a panel is connected (eDP) or not (DP). + */ + of_node_put(np); + + sor->ops = &tegra_sor_dp_ops; + sor->pad = TEGRA_IO_PAD_LVDS; } err = tegra_sor_parse_dt(sor); From patchwork Thu Oct 24 16:45:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6491F14ED for ; Thu, 24 Oct 2019 16:46:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C74720659 for ; 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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id d202sm2793119wmd.47.2019.10.24.09.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:43 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 30/32] drm/tegra: sor: Avoid timeouts on unplug events Date: Thu, 24 Oct 2019 18:45:32 +0200 Message-Id: <20191024164534.132764-31-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xnrmAgjd57yL7bQcusoIEkE1OASAQ02Qykb8fz3n31M=; b=MZvBicSw9zipfnsTLsDJjAQ+KeqkoZ0fMDPFBlaj+HgXTCOnugmEXur/eBCIIsyCw4 /ts6A+LhkwqzykJWglYVjSj5RdrSg8WHX4ubiqyi7sxQPuMLxHVQSx/PiNAs/15Epflp nBJkwpsjNeDFSXmsCScMgWHRM4VwPTk096pjfwn5dr55yLDwPJUio3oNDXy3DQ8Vqe7n RyegAq2wyWdH40gOFovFJlVPjxC+cOjHsa0TkUf6m8yVMUb+u2bYGmP9rap5bC1awJOY hJXf63FZVrHHE3L1WZbo2cgOSdi+sECp5G6OLOLmcsUArsCuS6RoDgdMEJ+cKq2j0kg2 wozQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding When the SOR is disabled in DP mode as part of an unplug event, do not attempt to power the DP link down. Powering down the link requires the DPAUX to transmit AUX messages which only works if there's a connected sink. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 63831c37ad35..b81e6d39aa32 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -2663,9 +2663,16 @@ static void tegra_sor_dp_disable(struct drm_encoder *encoder) if (output->panel) drm_panel_disable(output->panel); - err = drm_dp_link_power_down(sor->aux, &sor->link); - if (err < 0) - dev_err(sor->dev, "failed to power down link: %d\n", err); + /* + * Do not attempt to power down a DP link if we're not connected since + * the AUX transactions would just be timing out. + */ + if (output->connector.status != connector_status_disconnected) { + err = drm_dp_link_power_down(sor->aux, &sor->link); + if (err < 0) + dev_err(sor->dev, "failed to power down link: %d\n", + err); + } err = tegra_sor_detach(sor); if (err < 0) From patchwork Thu Oct 24 16:45:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210309 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 37E5214ED for ; Thu, 24 Oct 2019 16:46:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F53221925 for ; Thu, 24 Oct 2019 16:46:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F53221925 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 56EBB6E49A; Thu, 24 Oct 2019 16:46:51 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by gabe.freedesktop.org (Postfix) with ESMTPS id CEB5B6E49A for ; Thu, 24 Oct 2019 16:46:48 +0000 (UTC) Received: by mail-wm1-x342.google.com with SMTP id n7so2778697wmc.3 for ; Thu, 24 Oct 2019 09:46:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WKBeVLYREt15Gh3e8xz+0QmQJOGSqeYITYZf2RyLHbw=; b=njbtZsokKmSyuRfhIpvQqnWMZZpUV0rHVSZoDv0lHfkO5uonAHu08yJkKXRhcViKMc iYKarHNKscz4wp8yorzFmf1ni+O8Q8j8Kw9SgetrkZ0nZBx5n21ETuVUB2hp2PZZk/Pw xYvWM/1YU29UwoxV4ZE7LxTh4w6RExTKir7pGXibvyitM6J7GDGdCPR+Wkx8z8swrfXs rZQ79iwUcagPNORHet+wABIDLeOy8VOikKN8z9hl62q4/aYJ5cFjuBuVfGJltXLGtT0M w7dPZKNbRWPlXDXk7oASIdIRkj6SK/k0BHur02FZsAs+zsR4KDSgHm7r50kLCJxOit5P ASHQ== X-Gm-Message-State: APjAAAU5kLphll9ZBJV4Uf48JgDj8/SZXm31dGWTnNjirxlgJ9EE+7z2 +n9OHsfcdq8bB8CwIJycN24= X-Google-Smtp-Source: APXvYqwRIWbOX1eE2QfXOf7xYJVmFGbmcJHphMcAF60WHywqSwZivxQL4msANSJjxLCMUVoAPPhUlw== X-Received: by 2002:a7b:cc01:: with SMTP id f1mr6132288wmh.113.1571935607081; Thu, 24 Oct 2019 09:46:47 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id c8sm2522429wml.44.2019.10.24.09.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:45 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 31/32] drm/tegra: sor: Extract common audio enabling code Date: Thu, 24 Oct 2019 18:45:33 +0200 Message-Id: <20191024164534.132764-32-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WKBeVLYREt15Gh3e8xz+0QmQJOGSqeYITYZf2RyLHbw=; b=jZ2DuCClUsbZPw3pnaQmSqX6quDGwK0rbHR2dyP+ivScy3u9menmlTQrg/XNJ61hpQ 4kTYwAU4P7hYSd6GtYT7mzJwDNdPvRjY6An4A/OKgORv58TbJPuXID1vH0QqBJchVDSh HJ98PncdOlYPs2kvMXShX8AaQxA7jF5TEXlYranGf6Q/k4e7QPTlIc6P8pT+zTnGFSt/ PG9lgH+oiSrjta0+Pki+OyHPeumM5JQs8mysW+V3So9QbVee3/PcRtwuIH0zr7+K/9iV yrfQoQ9FlGjdLGboB4bME4um5KSIiSDOUlYJSV4C7X5WBN4g7wXALMgKMmjPwv1hudzs 63Qg== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding The code to enable audio support is split into two parts, one being generic for the SOR and another part that is specific whether the SOR is in HDMI mode or in DP mode. Split out the common part in preparation for reusing the code in DP mode. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 43 +++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index b81e6d39aa32..478c001f4453 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -2002,6 +2002,30 @@ static void tegra_sor_audio_unprepare(struct tegra_sor *sor) tegra_sor_writel(sor, 0, SOR_INT_ENABLE); } +static void tegra_sor_audio_enable(struct tegra_sor *sor) +{ + u32 value; + + value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); + + /* select HDA audio input */ + value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); + value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); + + /* inject null samples */ + if (sor->format.channels != 2) + value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; + else + value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; + + value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; + + tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); + + /* enable advertising HBR capability */ + tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); +} + static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) { u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; @@ -2037,24 +2061,7 @@ static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) { u32 value; - value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); - - /* select HDA audio input */ - value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); - value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); - - /* inject null samples */ - if (sor->format.channels != 2) - value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; - else - value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; - - value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; - - tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); - - /* enable advertising HBR capability */ - tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); + tegra_sor_audio_enable(sor); tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); From patchwork Thu Oct 24 16:45:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 11210317 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B1E714ED for ; Thu, 24 Oct 2019 16:47:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7328920659 for ; Thu, 24 Oct 2019 16:47:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7328920659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D3A226E507; Thu, 24 Oct 2019 16:46:51 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by gabe.freedesktop.org (Postfix) with ESMTPS id D72486E49A for ; Thu, 24 Oct 2019 16:46:50 +0000 (UTC) Received: by mail-wr1-x443.google.com with SMTP id o28so26848633wro.7 for ; Thu, 24 Oct 2019 09:46:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oFcPP2oqutBVyEiEACLaC7jQyoj9cZb8X5+nPOqCh7o=; b=JeoCFKAF/aC38+6aNcv2NDxIXJkII0tPnC9/Yz0uFR83TcZNZW6zf4XYzy5ONL/ltn 7bQcSRQR0rdyVCKFRqnK+8tmo9atc3M1w954zqy65FiC3Lje5VgUb/qukOglmdjB2Cwm /E2f5uZ5F2ryhtYbhL3e0RmH92hKNB9KMwJhELs9mrL97RcjePQhoqBYOIZGivMO6gH2 hEnIqQ2+NIKBSqz14AFOv6+zF0d/JwtR1QkoEXUoi5saSjwPXR9N8QRfLsVJf7BPhmx7 YVagy7afyc702Bjbq6TaqvE3XfmU02FofKevwW6JXvxoVMSFK7auPdjhwr7PUkvuK0BI 3ftA== X-Gm-Message-State: APjAAAVGcAfI0wlgXzLr52/FEVJqIfQ/bzxt9fKkjsaSYN8J6l+XNRFb 2NWjnGRDk2RXyp3FMhV8QQE= X-Google-Smtp-Source: APXvYqw1/hZX5WMs4ab63v5HQMWmYw5vlnLln0CGWngX/3ACyBOT0yDMD2mOwJBPkaMVnEh2VWRDBQ== X-Received: by 2002:a5d:6246:: with SMTP id m6mr4947510wrv.262.1571935609360; Thu, 24 Oct 2019 09:46:49 -0700 (PDT) Received: from localhost (p2E5BE2CE.dip0.t-ipconnect.de. [46.91.226.206]) by smtp.gmail.com with ESMTPSA id 1sm8265435wrr.16.2019.10.24.09.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 09:46:48 -0700 (PDT) From: Thierry Reding To: Thierry Reding Subject: [PATCH 32/32] drm/tegra: sor: Introduce audio enable/disable callbacks Date: Thu, 24 Oct 2019 18:45:34 +0200 Message-Id: <20191024164534.132764-33-thierry.reding@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024164534.132764-1-thierry.reding@gmail.com> References: <20191024164534.132764-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oFcPP2oqutBVyEiEACLaC7jQyoj9cZb8X5+nPOqCh7o=; b=TZjKFmQbkbNHnXanxjcWtAgpeaF8KGP7cYtEIFz+T1fl6RXPpBGDum4oB9w0sCVmAd 4ml40spo8rbDQA04LDO7W2onpmI/Ng2S2DgO+f318AVyFfwpOMsENcL0rN1NgeqOfglB 8C5dBKm24qwSsxrNCUhcYzycUGR8D0CpJaICkexJTkTFNaDYgyJRgq7xSZki7ghncePh Ngh6Jr64kkJOrRdAbhTJqsYJ/RCWWFD/sAPpSvBQjcdF+isQ716wcoifti2j8mbNFyME FrBgw30ns3N/3/ylqoIhYZzhj/V/zPgTv9if8RhJQZTaYFjPU6+i4eq5ie+MABjHQxqq Zebw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Thierry Reding In order to support different modes (DP in addition to HDMI), split out the audio setup/teardown into callbacks. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 478c001f4453..615cb319fa8b 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -398,6 +398,8 @@ struct tegra_sor_ops { const char *name; int (*probe)(struct tegra_sor *sor); int (*remove)(struct tegra_sor *sor); + void (*audio_enable)(struct tegra_sor *sor); + void (*audio_disable)(struct tegra_sor *sor); }; struct tegra_sor { @@ -3008,6 +3010,8 @@ static const struct tegra_sor_ops tegra_sor_hdmi_ops = { .name = "HDMI", .probe = tegra_sor_hdmi_probe, .remove = tegra_sor_hdmi_remove, + .audio_enable = tegra_sor_hdmi_audio_enable, + .audio_disable = tegra_sor_hdmi_audio_disable, }; static int tegra_sor_dp_probe(struct tegra_sor *sor) @@ -3616,9 +3620,11 @@ static irqreturn_t tegra_sor_irq(int irq, void *data) tegra_hda_parse_format(format, &sor->format); - tegra_sor_hdmi_audio_enable(sor); + if (sor->ops->audio_enable) + sor->ops->audio_enable(sor); } else { - tegra_sor_hdmi_audio_disable(sor); + if (sor->ops->audio_disable) + sor->ops->audio_disable(sor); } }