From patchwork Sat Oct 26 09:44:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 11213445 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62F8C913 for ; Sat, 26 Oct 2019 09:45:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D2DB2070B for ; Sat, 26 Oct 2019 09:45:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D2DB2070B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=chris-wilson.co.uk Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E47506EC02; Sat, 26 Oct 2019 09:45:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3CBB86EC02 for ; Sat, 26 Oct 2019 09:45:05 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 18973369-1500050 for multiple; Sat, 26 Oct 2019 10:44:22 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sat, 26 Oct 2019 10:44:20 +0100 Message-Id: <20191026094420.8624-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.24.0.rc1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/execlists: Verify context register state before execution X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Check that the context's ring register state still matches our expectations prior to execution. Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 70 ++++++++++++++++++++++++----- 1 file changed, 58 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 16340740139d..24478a1a135d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1154,6 +1154,61 @@ execlists_schedule_out(struct i915_request *rq) i915_request_put(rq); } +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine) +{ + if (INTEL_GEN(engine->i915) >= 12) + return 0x60; + else if (INTEL_GEN(engine->i915) >= 9) + return 0x54; + else if (engine->class == RENDER_CLASS) + return 0x58; + else + return -1; +} + +static void +execlists_check_context(const struct intel_context *ce, + const struct intel_engine_cs *engine) +{ + const struct intel_ring *ring = ce->ring; + u32 *regs = ce->lrc_reg_state; + int x; + + if (regs[CTX_RING_BUFFER_START] != i915_ggtt_offset(ring->vma)) { + pr_err_once("%s: context submitted with incorrect RING_BUFFER_START [%08x], expected %08x\n", + engine->name, + regs[CTX_RING_BUFFER_START], + i915_ggtt_offset(ring->vma)); + regs[CTX_RING_BUFFER_START] = i915_ggtt_offset(ring->vma); + } + + if (regs[CTX_RING_BUFFER_CONTROL] != + (RING_CTL_SIZE(ring->size) | RING_VALID)) { + pr_err_once("%s: context submitted with incorrect RING_BUFFER_CONTROL [%08x], expected %08x\n", + engine->name, + regs[CTX_RING_BUFFER_CONTROL], + (u32)(RING_CTL_SIZE(ring->size) | RING_VALID)); + regs[CTX_RING_BUFFER_CONTROL] = + RING_CTL_SIZE(ring->size) | RING_VALID; + } + + if (regs[CTX_BB_STATE] != RING_BB_PPGTT) { + pr_err_once("%s: context submitted with incorrect BB_STATE [%08x], expected %08x\n", + engine->name, + regs[CTX_BB_STATE], + RING_BB_PPGTT); + regs[CTX_BB_STATE] = RING_BB_PPGTT; + } + + x = lrc_ring_mi_mode(engine); + if (x != -1 && regs[x + 1] & STOP_RING) { + pr_err_once("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n", + engine->name, regs[x + 1]); + regs[x + 1] &= ~STOP_RING; + regs[x + 1] |= STOP_RING << 16; + } +} + static u64 execlists_update_context(const struct i915_request *rq) { struct intel_context *ce = rq->hw_context; @@ -1162,6 +1217,9 @@ static u64 execlists_update_context(const struct i915_request *rq) ce->lrc_reg_state[CTX_RING_TAIL] = intel_ring_set_tail(rq->ring, rq->tail); + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) + execlists_check_context(ce, rq->engine); + /* * Make sure the context image is complete before we submit it to HW. * @@ -2935,18 +2993,6 @@ static void reset_csb_pointers(struct intel_engine_cs *engine) &execlists->csb_status[reset_value]); } -static int lrc_ring_mi_mode(const struct intel_engine_cs *engine) -{ - if (INTEL_GEN(engine->i915) >= 12) - return 0x60; - else if (INTEL_GEN(engine->i915) >= 9) - return 0x54; - else if (engine->class == RENDER_CLASS) - return 0x58; - else - return -1; -} - static void __execlists_reset_reg_state(const struct intel_context *ce, const struct intel_engine_cs *engine) {