From patchwork Sun Oct 27 16:23:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214243 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 369A8112C for ; Sun, 27 Oct 2019 16:24:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1319921D7F for ; Sun, 27 Oct 2019 16:24:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="J0IuqFtZ"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="pCgUOiR/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1319921D7F Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sNNY/dvYkS/13BfRUdbLSET/sXfNhQzcHZ6qUXqkaII=; b=J0IuqFtZoCaD1p J2lIJTMbcNEe2Rgf1SvzIubAlgFBSlU8MOzytdBR7pwWaY4Gbce6Jl/B6SMbGTu5+xrsMcKi8GC4P MrlWlsd9tCMSkPoDf1kW0Is7YiqBbiwK0tOYQV46B5AP988TZ06xKqUff2xDwQ9Dg0pflyTJXXKXO /FLUd3e1utpBWCKa3P2enhb587BE4H0GertSenLc9klF5Bxx3uJrFN6BH9sCoEpMA2H9Jy4rKzMU3 e7F6yAqhB0tC8ceXIhO64Vaww7WzC0p0PHhxLI/tn3saMInHVsKIYXTzFzsM9IY0ht2wPd2f+j1tV 38DgUkyuLLhy2Z+s59Vw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iOlKo-0001XJ-Jl; Sun, 27 Oct 2019 16:24:06 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iOlKQ-0001Cd-Su; Sun, 27 Oct 2019 16:23:44 +0000 Received: by mail-wr1-x443.google.com with SMTP id o28so7375434wro.7; Sun, 27 Oct 2019 09:23:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GWbTlN2rWt2ied7AfeNCro8kNhdCw9BqWl6E/dShDHM=; b=pCgUOiR/1l5Uat1i9ODdivZgGrUR8Pa1WmVT+96e3Io7y6zNE8LiPpSLbneTIFPDpS RhL1RIlEFtXXqBNKZlHkkUOgflEhYPq2hMiZp+ko8yo5lADiImaWyuWsECR3uT6UDOhi tmPjdhrI3bX+bNcTc+oRxSCqEb45PFWrXjBu7TpDXbBarGEudlmDdfx2eLIlOUOcTNaA 5NyA49hZ35RznaDd7fBTq2Y5Hmu2+oM8iIrc2NUO7VOzXrpq1bRx9b3aY60rW7mDSg+f ltmja1byUvCyRGdFdiBdixcM070kcvyClAfl/BkQyLcOWpm0voT5BOXIXtXLPvwzODmz Ed5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GWbTlN2rWt2ied7AfeNCro8kNhdCw9BqWl6E/dShDHM=; b=uUPi4zcqbbdF3njG6tOqAwBVj7SMW3bHVuB7xpUGuTXQiTfyJ4ZuvgpmvourjvjKyp SwKnmlydqFGFU4LxlvVwa7H4w58NGtAIvl+y4Z7QpT+3YD68mAJF7h/d5sSinV++7geD pEX7jUO30CqlaKJ7BUL7mfOCQ8D3QhvKn1eAI9NW0j+ps7MiLQPQoZmAiCn+i/Qf4Z6Z TBO9Aa865e3XLkK08+Fke2zLhe1CGVVJ3e8IMFogjrQ7duO9BipdvBCHI1Kxx5sfDZ34 XgPhfogu5BI49hxPZM/UmZJg2V8gxTXdc7NASVNOtMWBLGWtYlqwK+63345pi8j495cl 627w== X-Gm-Message-State: APjAAAVCwikxtIepZhLbyVTunCVEM+MRRKFPMpk7LJjdbTHOLJtHX9qn pwvhPL9hlOGAPEPsQs3XEk8= X-Google-Smtp-Source: APXvYqwiHWUOdqyOryfoxyoMSXW3biIYINgbbr5FI/oRW27dSCoa7yemhpwRw0z73LhgcDRjGmNbMg== X-Received: by 2002:adf:e403:: with SMTP id g3mr11120841wrm.128.1572193421194; Sun, 27 Oct 2019 09:23:41 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:40 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Subject: [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Date: Sun, 27 Oct 2019 17:23:24 +0100 Message-Id: <20191027162328.1177402-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191027_092342_937459_63D5CF77 X-CRM114-Status: GOOD ( 12.88 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (martin.blumenstingl[at]googlemail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Rob Herring , Martin Blumenstingl , linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by: Rob Herring Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd --- .../clock/amlogic,meson8-ddr-clkc.yaml | 50 +++++++++++++++++++ include/dt-bindings/clock/meson8-ddr-clkc.h | 4 ++ 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml new file mode 100644 index 000000000000..4b8669f870ec --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic DDR Clock Controller Device Tree Bindings + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + enum: + - amlogic,meson8-ddr-clkc + - amlogic,meson8b-ddr-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xtal + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h new file mode 100644 index 000000000000..a8e0fa2987ab --- /dev/null +++ b/include/dt-bindings/clock/meson8-ddr-clkc.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#define DDR_CLKID_DDR_PLL_DCO 0 +#define DDR_CLKID_DDR_PLL 1 From patchwork Sun Oct 27 16:23:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214249 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 92D91913 for ; Sun, 27 Oct 2019 16:24:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BD6E214AF for ; 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[2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:41 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Subject: [PATCH v2 2/5] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Date: Sun, 27 Oct 2019 17:23:25 +0100 Message-Id: <20191027162328.1177402-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191027_092343_905721_C1442FC6 X-CRM114-Status: GOOD ( 17.50 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:341 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (martin.blumenstingl[at]googlemail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/meson8-ddr.c | 152 +++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/meson8-ddr.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 3939f218587a..6eca2a406ee3 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o -obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o +obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c new file mode 100644 index 000000000000..4aefcc5bdaae --- /dev/null +++ b/drivers/clk/meson/meson8-ddr.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic Meson8 DDR clock controller + * + * Copyright (C) 2019 Martin Blumenstingl + */ + +#include + +#include +#include +#include + +#include "clk-regmap.h" +#include "clk-pll.h" + +#define AM_DDR_PLL_CNTL 0x00 +#define AM_DDR_PLL_CNTL1 0x04 +#define AM_DDR_PLL_CNTL2 0x08 +#define AM_DDR_PLL_CNTL3 0x0c +#define AM_DDR_PLL_CNTL4 0x10 +#define AM_DDR_PLL_STS 0x14 +#define DDR_CLK_CNTL 0x18 +#define DDR_CLK_STS 0x1c + +static struct clk_regmap meson8_ddr_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 30, + .width = 1, + }, + .m = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .l = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = AM_DDR_PLL_CNTL, + .shift = 29, + .width = 1, + }, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll_dco", + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap meson8_ddr_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = AM_DDR_PLL_CNTL, + .shift = 16, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll", + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8_ddr_pll_dco.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { + .hws = { + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, + }, + .num = 2, +}; + +static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { + &meson8_ddr_pll_dco, + &meson8_ddr_pll, +}; + +static const struct regmap_config meson8_ddr_clkc_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = DDR_CLK_STS, +}; + +static int meson8_ddr_clkc_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct resource *res; + void __iomem *base; + struct clk_hw *hw; + int ret, i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, + &meson8_ddr_clkc_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* Populate regmap */ + for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++) + meson8_ddr_clk_regmaps[i]->map = regmap; + + /* Register all clks */ + for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { + hw = meson8_ddr_clk_hw_onecell_data.hws[i]; + + ret = devm_clk_hw_register(&pdev->dev, hw); + if (ret) { + dev_err(&pdev->dev, "Clock registration failed\n"); + return ret; + } + } + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + &meson8_ddr_clk_hw_onecell_data); +} + +static const struct of_device_id meson8_ddr_clkc_match_table[] = { + { .compatible = "amlogic,meson8-ddr-clkc" }, + { .compatible = "amlogic,meson8b-ddr-clkc" }, + { /* sentinel */ }, +}; + +static struct platform_driver meson8_ddr_clkc_driver = { + .probe = meson8_ddr_clkc_probe, + .driver = { + .name = "meson8-ddr-clkc", + .of_match_table = meson8_ddr_clkc_match_table, + }, +}; + +builtin_platform_driver(meson8_ddr_clkc_driver); From patchwork Sun Oct 27 16:23:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214253 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C504A112C for ; Sun, 27 Oct 2019 16:24:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A23A321850 for ; Sun, 27 Oct 2019 16:24:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sa10S5Se"; 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[2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:43 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Subject: [PATCH v2 3/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks Date: Sun, 27 Oct 2019 17:23:26 +0100 Message-Id: <20191027162328.1177402-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191027_092345_264253_7158DF55 X-CRM114-Status: GOOD ( 12.05 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:341 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (martin.blumenstingl[at]googlemail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Switch from clk_hw_register to of_clk_hw_register so we can use clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll" and possibly others from the .dtb. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 70ac6755607e..306b809deb49 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3696,7 +3696,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, if (!clk_hw_onecell_data->hws[i]) continue; - ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]); + ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); if (ret) return; } From patchwork Sun Oct 27 16:23:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11214257 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE097112C for ; Sun, 27 Oct 2019 16:25:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EC0E214AF for ; Sun, 27 Oct 2019 16:25:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="W9pQfgd/"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="DJKRsi+4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6EC0E214AF Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bfZLCN5Q3xwslAkNreB++4k//+c3rsAfLdSximeMrTk=; b=W9pQfgd/agGjuq e3qHzLoLeV/FWiUz3QJlsFCK1eLuEF+vGx5lfSE2DKS0Rbp2yc9rfryS4H5rMfX30bSDPzsNUH9UG ZbCtl8ituxLYZZyrjCr0d8FSlFTyqJ/Ix7XcObbT+zHH35tQouF+V7r4oxyG695Gj0Mu41gFiM88M Ju6P9FqD2RsEaE0zzUTbFzUIftV/bzfWmmQ0LYwlKFXyAvfYpZqYoZr7q9QpoIGbjGWnuSamJtqSI QTvA593vBpCqFapsOC0hXgcf+bhFVyXiluRiFcilyFyLf84DU0QyHPcB2ZiZo70vAiTkRGCiLn8yO 78WJsp6wp9tDf3xUh2IQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iOlLg-0002Py-Jp; Sun, 27 Oct 2019 16:25:00 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iOlKU-0001F2-Kf; Sun, 27 Oct 2019 16:23:48 +0000 Received: by mail-wr1-x443.google.com with SMTP id c2so7362685wrr.10; Sun, 27 Oct 2019 09:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FR91Xkho7A58iCTl5ApNx6Gn9blyxo7jlHkr4Z2ufbE=; b=DJKRsi+4xUNfRqEYSANnCE2BCk4qocBMxIHxvNaFwMv+6reNOJ1yDYZzxawhOVKc+u uTJs8mvzJAJRnXdV3PBCK7J+OLejIm0UExJaXQogyWv2+BgWDBWfXTg3kZpu0Jmdk7lG /TyFplsRJQ2IpcuqsNqJKTxyHc9uJ2l/2CiD1tpl4bJ5csKhETxra1ZBvxjQGJGCtawL yOxoKoQ/Qczup8O23yRK//AG/vdy4hLOGN68aA6tPyya/7qZ+H27V1gYV5prUio4nJDb IQWqqg+8jrprGeXqbfvnrir+EWjX38frqDR51u3xD1yBKGVj/PN1HyM3z5ncT5s0Ameu /Thw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FR91Xkho7A58iCTl5ApNx6Gn9blyxo7jlHkr4Z2ufbE=; b=pjO9br1zuHHKGUIwOZyXOMfX4cHO1fVSUCbOf5EaWaYgiq8iXU5b5ddlxBi3YE2L1I RN1sj07KfYZ14dX/m+jvwwe5Y/V5Rm/oWrlGPgrohQ5i1SRfcFYyhxN7Xh5NwUHALUJv g0omjoG6TYaVk9HnVyk39lFroonqrK216Z2oO7EBzZLm98vuawFatXm2/zKIowJ9v5y4 UYwRLMExAy5F3q6ckBe/VfX3K4OhX9T2oKcb9VUmTbfftfSLjJbIMSYyD9eIifg5W03a hLZH3X4caY+WU5i8NgldpX8acuJg/9gKgmxleSYCn+8aNLqB/x9sv8h4XGvq9bPrz0Gi YnIQ== X-Gm-Message-State: APjAAAWaS/hmcQovt4QIgwy1G1Bv4wplxC5YsOL/89QE+tjgvCtn3AKH awk4E43N/F261Nn1vn/6TtA= X-Google-Smtp-Source: APXvYqwYcUCsvwTfCVC8G8QhpTTpc/gHzJpzRKp5RQnLVauGHvqBTZj2iIoo9YjsXmaCQ/Mnq8Vf2g== X-Received: by 2002:a5d:640e:: with SMTP id z14mr11475473wru.311.1572193425067; Sun, 27 Oct 2019 09:23:45 -0700 (PDT) Received: from localhost.localdomain (p200300F133D01300428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:44 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Subject: [PATCH v2 4/5] ARM: dts: meson8: add the DDR clock controller Date: Sun, 27 Oct 2019 17:23:27 +0100 Message-Id: <20191027162328.1177402-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191027_092346_730713_5A3DD6EB X-CRM114-Status: GOOD ( 11.42 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (martin.blumenstingl[at]googlemail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4f59a4c8f036..257c1364864c 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -3,6 +3,7 @@ * Copyright 2014 Carlo Caione */ +#include #include #include #include @@ -195,6 +196,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -455,8 +464,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; }; From patchwork Sun Oct 27 16:23:28 2019 Content-Type: text/plain; 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[2003:f1:33d0:1300:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id 1sm8243299wrr.16.2019.10.27.09.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2019 09:23:45 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, khilman@baylibre.com Subject: [PATCH v2 5/5] ARM: dts: meson8b: add the DDR clock controller Date: Sun, 27 Oct 2019 17:23:28 +0100 Message-Id: <20191027162328.1177402-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> References: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191027_092347_796243_C62CC5B5 X-CRM114-Status: GOOD ( 11.42 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:444 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (martin.blumenstingl[at]googlemail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main (HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the inputs for the audio clock muxes. Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 1934666ff60f..8ac8bdfaf58f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -4,6 +4,7 @@ * Author: Carlo Caione */ +#include #include #include #include @@ -172,6 +173,14 @@ #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; + ddr_clkc: clock-controller@400 { + compatible = "amlogic,meson8b-ddr-clkc"; + reg = <0x400 0x20>; + clocks = <&xtal>; + clock-names = "xtal"; + #clock-cells = <1>; + }; + dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; @@ -434,8 +443,8 @@ &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; };