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client-ip=162.221.158.21; receiver=esa1.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: KVtf7QtyzYyiWs0GAYpC5nrUqnfB4dXBKMCwV3gVdLfq3HTwngGer9fvIsefN38ypIAMzXoz3o 8Z/CCoJjUz0R3+3Hiv6MBzFUDsEdqCuTTxDpMfw3b7WOXqECyL/w/TrW4RpKbYLTq6JXMWFpm7 mGq2oo5SyGELzxWJk53OKLeaBCArOB9R+prPYVtgQQknDfaMg3+yyf/9/BFWKaoqMKW7NNOCnD wwY5SiVOw7xzoSSY32mbc/24R4zb+pZv4B3FL/5YwK0EQcb6ToMdTG683qazTGZjHVG5n7rWQn h1s= X-SBRS: 2.7 X-MesageID: 7606436 X-Ironport-Server: esa1.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.68,240,1569297600"; d="scan'208";a="7606436" From: Andrew Cooper To: Xen-devel Date: Mon, 28 Oct 2019 15:01:51 +0000 Message-ID: <20191028150152.21179-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191028150152.21179-1-andrew.cooper3@citrix.com> References: <20191028150152.21179-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 1/2] x86/vtx: Corrections to BFD93 errata workaround X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Juergen Gross , Kevin Tian , Jan Beulich , Wei Liu , Andrew Cooper , Jun Nakajima , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the time of fixing c/s 20f1976b44, no obvious errata had been published, and BDF14 looked like the most obvious candidate. Subsequently, BDF93 has been published and it is obviously this. The erratum states that LER_TO_LIP is the only affected MSR. The provisional fix in Xen adjusted LER_FROM_LIP, but this is not correct. The FROM MSRs are intended to have TSX metadata, and for steppings with TSX enabled, it will corrupt the value the guest sees, while for parts with TSX disabled, it is redundant with FIXUP_TSX. Drop the LER_FROM_LIP adjustment. Replace BDF14 references with BDF93, drop the redundant 'bdw_erratum_' prefix, and use an Intel vendor check, as other vendors implement VT-x. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Reviewed-by: Kevin Tian --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian CC: Juergen Gross --- xen/arch/x86/hvm/vmx/vmx.c | 45 +++++++++++++++++++++------------------------ 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 535e0384fe..32d289ce06 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2369,7 +2369,7 @@ static void pi_notification_interrupt(struct cpu_user_regs *regs) } static void __init lbr_tsx_fixup_check(void); -static void __init bdw_erratum_bdf14_fixup_check(void); +static void __init bdf93_fixup_check(void); const struct hvm_function_table * __init start_vmx(void) { @@ -2438,7 +2438,7 @@ const struct hvm_function_table * __init start_vmx(void) setup_vmcs_dump(); lbr_tsx_fixup_check(); - bdw_erratum_bdf14_fixup_check(); + bdf93_fixup_check(); return &vmx_function_table; } @@ -2722,11 +2722,11 @@ enum #define LBR_MSRS_INSERTED (1u << 0) #define LBR_FIXUP_TSX (1u << 1) -#define LBR_FIXUP_BDF14 (1u << 2) -#define LBR_FIXUP_MASK (LBR_FIXUP_TSX | LBR_FIXUP_BDF14) +#define LBR_FIXUP_BDF93 (1u << 2) +#define LBR_FIXUP_MASK (LBR_FIXUP_TSX | LBR_FIXUP_BDF93) static bool __read_mostly lbr_tsx_fixup_needed; -static bool __read_mostly bdw_erratum_bdf14_fixup_needed; +static bool __read_mostly bdf93_fixup_needed; static uint32_t __read_mostly lbr_from_start; static uint32_t __read_mostly lbr_from_end; static uint32_t __read_mostly lbr_lastint_from; @@ -2763,11 +2763,18 @@ static void __init lbr_tsx_fixup_check(void) } } -static void __init bdw_erratum_bdf14_fixup_check(void) +static void __init bdf93_fixup_check(void) { - /* Broadwell E5-2600 v4 processors need to work around erratum BDF14. */ - if ( boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 79 ) - bdw_erratum_bdf14_fixup_needed = true; + /* + * Broadwell erratum BDF93: + * + * Reads from MSR_LER_TO_LIP (MSR 1DEH) may return values for bits[63:61] + * that are not equal to bit[47]. Attempting to context switch this value + * may cause a #GP. Software should sign extend the MSR. + */ + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && + boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x4f ) + bdf93_fixup_needed = true; } static int is_last_branch_msr(u32 ecx) @@ -3128,8 +3135,8 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) v->arch.hvm.vmx.lbr_flags |= LBR_MSRS_INSERTED; if ( lbr_tsx_fixup_needed ) v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_TSX; - if ( bdw_erratum_bdf14_fixup_needed ) - v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_BDF14; + if ( bdf93_fixup_needed ) + v->arch.hvm.vmx.lbr_flags |= LBR_FIXUP_BDF93; } __vmwrite(GUEST_IA32_DEBUGCTL, msr_content); @@ -4148,20 +4155,10 @@ static void sign_extend_msr(struct vcpu *v, u32 msr, int type) entry->data = canonicalise_addr(entry->data); } -static void bdw_erratum_bdf14_fixup(void) +static void bdf93_fixup(void) { struct vcpu *curr = current; - /* - * Occasionally, on certain Broadwell CPUs MSR_IA32_LASTINTTOIP has - * been observed to have the top three bits corrupted as though the - * MSR is using the LBR_FORMAT_EIP_FLAGS_TSX format. This is - * incorrect and causes a vmentry failure -- the MSR should contain - * an offset into the current code segment. This is assumed to be - * erratum BDF14. Fix up MSR_IA32_LASTINT{FROM,TO}IP by - * sign-extending into bits 48:63. - */ - sign_extend_msr(curr, MSR_IA32_LASTINTFROMIP, VMX_MSR_GUEST); sign_extend_msr(curr, MSR_IA32_LASTINTTOIP, VMX_MSR_GUEST); } @@ -4171,8 +4168,8 @@ static void lbr_fixup(void) if ( curr->arch.hvm.vmx.lbr_flags & LBR_FIXUP_TSX ) lbr_tsx_fixup(); - if ( curr->arch.hvm.vmx.lbr_flags & LBR_FIXUP_BDF14 ) - bdw_erratum_bdf14_fixup(); + if ( curr->arch.hvm.vmx.lbr_flags & LBR_FIXUP_BDF93 ) + bdf93_fixup(); } /* Returns false if the vmentry has to be restarted */ From patchwork Mon Oct 28 15:01:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 11215697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B7B113BD for ; Mon, 28 Oct 2019 15:03:30 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 179B021479 for ; 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client-ip=162.221.158.21; receiver=esa3.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="Andrew.Cooper3@citrix.com"; x-conformance=sidf_compatible; x-record-type="v=spf1"; x-record-text="v=spf1 ip4:209.167.231.154 ip4:178.63.86.133 ip4:195.66.111.40/30 ip4:85.115.9.32/28 ip4:199.102.83.4 ip4:192.28.146.160 ip4:192.28.146.107 ip4:216.52.6.88 ip4:216.52.6.188 ip4:162.221.158.21 ip4:162.221.156.83 ip4:168.245.78.127 ~all" Received-SPF: None (esa3.hc3370-68.iphmx.com: no sender authenticity information available from domain of postmaster@mail.citrix.com) identity=helo; client-ip=162.221.158.21; receiver=esa3.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: jGwBE8Borhxy1cWf/L7wpVn71ez8VLCW6x8PnYL/mpaH0IPURvtBge1GKqTgh9ibCf46M4KnK6 //p6FQhO3BoeanAiBCax6VfISB25ZLfP2/AfeFt5weUhkiSWTsx9SGi3muU45TXSYyE34c66sj PF9cMCiAPQhzrKjZo9p/DyLurE9uZJeRvd3E5g2ntF5XUAg1q11PVA1mbWEAIi/Rcd9UJXfHtJ xs66z4t/PitzH3Z1DSDca3N7b3QIknROJZfQHYB8O26vtjXVIBemVpWrOE/hgXGofnx6FWYwMo WQg= X-SBRS: 2.7 X-MesageID: 7507028 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.68,240,1569297600"; d="scan'208";a="7507028" From: Andrew Cooper To: Xen-devel Date: Mon, 28 Oct 2019 15:01:52 +0000 Message-ID: <20191028150152.21179-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20191028150152.21179-1-andrew.cooper3@citrix.com> References: <20191028150152.21179-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH 2/2] x86/vtx: Fixes to Haswell/Broadwell LBR TSX errata X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Juergen Gross , Kevin Tian , Jan Beulich , Wei Liu , Andrew Cooper , Jun Nakajima , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Cross reference and list each errata, now that they are published. These errata are specific to Haswell/Broadwell. They should have model and vendor checks, as Intel isn't the only vendor to implement VT-x. All affected models use the same MSR indicies, so these can be hard coded rather than looking up and storing constant values. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Reviewed-by: Kevin Tian --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monné CC: Jun Nakajima CC: Kevin Tian CC: Juergen Gross --- xen/arch/x86/hvm/vmx/vmx.c | 63 +++++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 28 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 32d289ce06..f20ee94f9e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2583,14 +2583,6 @@ static int vmx_cr_access(cr_access_qual_t qual) return X86EMUL_OKAY; } -/* This defines the layout of struct lbr_info[] */ -#define LBR_LASTINT_FROM_IDX 0 -#define LBR_LASTINT_TO_IDX 1 -#define LBR_LASTBRANCH_TOS_IDX 2 -#define LBR_LASTBRANCH_FROM_IDX 3 -#define LBR_LASTBRANCH_TO_IDX 4 -#define LBR_LASTBRANCH_INFO 5 - static const struct lbr_info { u32 base, count; } p4_lbr[] = { @@ -2727,40 +2719,50 @@ enum static bool __read_mostly lbr_tsx_fixup_needed; static bool __read_mostly bdf93_fixup_needed; -static uint32_t __read_mostly lbr_from_start; -static uint32_t __read_mostly lbr_from_end; -static uint32_t __read_mostly lbr_lastint_from; static void __init lbr_tsx_fixup_check(void) { - bool tsx_support = cpu_has_hle || cpu_has_rtm; uint64_t caps; uint32_t lbr_format; - /* Fixup is needed only when TSX support is disabled ... */ - if ( tsx_support ) + /* + * HSM182, HSD172, HSE117, BDM127, BDD117, BDF85, BDE105: + * + * On processors that do not support Intel Transactional Synchronization + * Extensions (Intel TSX) (CPUID.07H.EBX bits 4 and 11 are both zero), + * writes to MSR_LASTBRANCH_x_FROM_IP (MSR 680H to 68FH) may #GP unless + * bits[62:61] are equal to bit[47]. + * + * Software should sign the MSRs. + * + * Experimentally, MSR_LER_FROM_LIP (1DDH) is similarly impacted, so is + * fixed up as well. + */ + if ( cpu_has_hle || cpu_has_rtm || + boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || + boot_cpu_data.x86 != 6 || + (boot_cpu_data.x86_model != 0x3c && /* HSM182, HSD172 - 4th gen Core */ + boot_cpu_data.x86_model != 0x3f && /* HSE117 - Xeon E5 v3 */ + boot_cpu_data.x86_model != 0x45 && /* HSM182 - 4th gen Core */ + boot_cpu_data.x86_model != 0x46 && /* HSM182, HSD172 - 4th gen Core (GT3) */ + boot_cpu_data.x86_model != 0x3d && /* BDM127 - 5th gen Core */ + boot_cpu_data.x86_model != 0x47 && /* BDD117 - 5th gen Core (GT3) */ + boot_cpu_data.x86_model != 0x4f && /* BDF85 - Xeon E5-2600 v4 */ + boot_cpu_data.x86_model != 0x56) ) /* BDE105 - Xeon D-1500 */ return; + /* + * Fixup is needed only when TSX support is disabled and the address + * format of LBR includes TSX bits 61:62 + */ if ( !cpu_has_pdcm ) return; rdmsrl(MSR_IA32_PERF_CAPABILITIES, caps); lbr_format = caps & MSR_IA32_PERF_CAP_LBR_FORMAT; - /* ... and the address format of LBR includes TSX bits 61:62 */ if ( lbr_format == LBR_FORMAT_EIP_FLAGS_TSX ) - { - const struct lbr_info *lbr = last_branch_msr_get(); - - if ( lbr == NULL ) - return; - - lbr_lastint_from = lbr[LBR_LASTINT_FROM_IDX].base; - lbr_from_start = lbr[LBR_LASTBRANCH_FROM_IDX].base; - lbr_from_end = lbr_from_start + lbr[LBR_LASTBRANCH_FROM_IDX].count; - lbr_tsx_fixup_needed = true; - } } static void __init bdf93_fixup_check(void) @@ -4133,8 +4135,12 @@ static void lbr_tsx_fixup(void) struct vmx_msr_entry *msr_area = curr->arch.hvm.vmx.msr_area; struct vmx_msr_entry *msr; - if ( (msr = vmx_find_msr(curr, lbr_from_start, VMX_MSR_GUEST)) != NULL ) + if ( (msr = vmx_find_msr(curr, MSR_P4_LASTBRANCH_0_FROM_LIP, + VMX_MSR_GUEST)) != NULL ) { + unsigned int lbr_from_end = + MSR_P4_LASTBRANCH_0_FROM_LIP + NUM_MSR_P4_LASTBRANCH_FROM_TO; + /* * Sign extend into bits 61:62 while preserving bit 63 * The loop relies on the fact that MSR array is sorted. @@ -4143,7 +4149,8 @@ static void lbr_tsx_fixup(void) msr->data |= ((LBR_FROM_SIGNEXT_2MSB & msr->data) << 2); } - if ( (msr = vmx_find_msr(curr, lbr_lastint_from, VMX_MSR_GUEST)) != NULL ) + if ( (msr = vmx_find_msr(curr, MSR_IA32_LASTINTFROMIP, + VMX_MSR_GUEST)) != NULL ) msr->data |= ((LBR_FROM_SIGNEXT_2MSB & msr->data) << 2); }