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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c6sm4382210pfj.59.2019.10.31.10.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2019 10:58:36 -0700 (PDT) From: Mathieu Poirier To: corbet@lwn.net Subject: [PATCH 1/4] coresight: etm4x: docs: Update ABI doc for new sysfs name scheme. Date: Thu, 31 Oct 2019 11:58:31 -0600 Message-Id: <20191031175834.17548-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191031175834.17548-1-mathieu.poirier@linaro.org> References: <20191031175834.17548-1-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191031_105838_243397_C1A1B6F5 X-CRM114-Status: GOOD ( 11.97 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:42f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Mike Leach Recent updates to CoreSight drivers have changed the component naming schema used in sysfs. This updates the ABI document to reflect the new naming schema. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../testing/sysfs-bus-coresight-devices-etm4x | 136 +++++++++--------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 36258bc1b473..9290010e973e 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -1,4 +1,4 @@ -What: /sys/bus/coresight/devices/.etm/enable_source +What: /sys/bus/coresight/devices/etm/enable_source Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. of coresight components linking the source to the sink is configured and managed automatically by the coresight framework. -What: /sys/bus/coresight/devices/.etm/cpu +What: /sys/bus/coresight/devices/etm/cpu Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) The CPU this tracing entity is associated with. -What: /sys/bus/coresight/devices/.etm/nr_pe_cmp +What: /sys/bus/coresight/devices/etm/nr_pe_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of PE comparator inputs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_addr_cmp +What: /sys/bus/coresight/devices/etm/nr_addr_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of address comparator pairs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_cntr +What: /sys/bus/coresight/devices/etm/nr_cntr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of counters that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_ext_inp +What: /sys/bus/coresight/devices/etm/nr_ext_inp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates how many external inputs are implemented. -What: /sys/bus/coresight/devices/.etm/numcidc +What: /sys/bus/coresight/devices/etm/numcidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of Context ID comparators that are available for tracing. -What: /sys/bus/coresight/devices/.etm/numvmidc +What: /sys/bus/coresight/devices/etm/numvmidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of VMID comparators that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nrseqstate +What: /sys/bus/coresight/devices/etm/nrseqstate Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of sequencer states that are implemented. -What: /sys/bus/coresight/devices/.etm/nr_resource +What: /sys/bus/coresight/devices/etm/nr_resource Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of resource selection pairs that are available for tracing. -What: /sys/bus/coresight/devices/.etm/nr_ss_cmp +What: /sys/bus/coresight/devices/etm/nr_ss_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. -What: /sys/bus/coresight/devices/.etm/reset +What: /sys/bus/coresight/devices/etm/reset Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (W) Cancels all configuration on a trace unit and set it back to its boot configuration. -What: /sys/bus/coresight/devices/.etm/mode +What: /sys/bus/coresight/devices/etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -91,302 +91,302 @@ Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. -What: /sys/bus/coresight/devices/.etm/pe +What: /sys/bus/coresight/devices/etm/pe Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which PE to trace. -What: /sys/bus/coresight/devices/.etm/event +What: /sys/bus/coresight/devices/etm/event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. -What: /sys/bus/coresight/devices/.etm/event_instren +What: /sys/bus/coresight/devices/etm/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the behavior of the events in bank 0 to 3. -What: /sys/bus/coresight/devices/.etm/event_ts +What: /sys/bus/coresight/devices/etm/event_ts Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the insertion of global timestamps in the trace streams. -What: /sys/bus/coresight/devices/.etm/syncfreq +What: /sys/bus/coresight/devices/etm/syncfreq Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls how often trace synchronization requests occur. -What: /sys/bus/coresight/devices/.etm/cyc_threshold +What: /sys/bus/coresight/devices/etm/cyc_threshold Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Sets the threshold value for cycle counting. -What: /sys/bus/coresight/devices/.etm/bb_ctrl +What: /sys/bus/coresight/devices/etm/bb_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. -What: /sys/bus/coresight/devices/.etm/event_vinst +What: /sys/bus/coresight/devices/etm/event_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls instruction trace filtering. -What: /sys/bus/coresight/devices/.etm/s_exlevel_vinst +What: /sys/bus/coresight/devices/etm/s_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/.etm/ns_exlevel_vinst +What: /sys/bus/coresight/devices/etm/ns_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/.etm/addr_idx +What: /sys/bus/coresight/devices/etm/addr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which address comparator or pair (of comparators) to work with. -What: /sys/bus/coresight/devices/.etm/addr_instdatatype +What: /sys/bus/coresight/devices/etm/addr_instdatatype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls what type of comparison the trace unit performs. -What: /sys/bus/coresight/devices/.etm/addr_single +What: /sys/bus/coresight/devices/etm/addr_single Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup single address comparator values. -What: /sys/bus/coresight/devices/.etm/addr_range +What: /sys/bus/coresight/devices/etm/addr_range Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Used to setup address range comparator values. -What: /sys/bus/coresight/devices/.etm/seq_idx +What: /sys/bus/coresight/devices/etm/seq_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which sequensor. -What: /sys/bus/coresight/devices/.etm/seq_state +What: /sys/bus/coresight/devices/etm/seq_state Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Use this to set, or read, the sequencer state. -What: /sys/bus/coresight/devices/.etm/seq_event +What: /sys/bus/coresight/devices/etm/seq_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer state to a specific state. -What: /sys/bus/coresight/devices/.etm/seq_reset_event +What: /sys/bus/coresight/devices/etm/seq_reset_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. -What: /sys/bus/coresight/devices/.etm/cntr_idx +What: /sys/bus/coresight/devices/etm/cntr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which counter unit to work with. -What: /sys/bus/coresight/devices/.etm/cntrldvr +What: /sys/bus/coresight/devices/etm/cntrldvr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) This sets or returns the reload count value of the specific counter. -What: /sys/bus/coresight/devices/.etm/cntr_val +What: /sys/bus/coresight/devices/etm/cntr_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) This sets or returns the current count value of the specific counter. -What: /sys/bus/coresight/devices/.etm/cntr_ctrl +What: /sys/bus/coresight/devices/etm/cntr_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the operation of the selected counter. -What: /sys/bus/coresight/devices/.etm/res_idx +What: /sys/bus/coresight/devices/etm/res_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which resource selection unit to work with. -What: /sys/bus/coresight/devices/.etm/res_ctrl +What: /sys/bus/coresight/devices/etm/res_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Controls the selection of the resources in the trace unit. -What: /sys/bus/coresight/devices/.etm/ctxid_idx +What: /sys/bus/coresight/devices/etm/ctxid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which context ID comparator to work with. -What: /sys/bus/coresight/devices/.etm/ctxid_pid +What: /sys/bus/coresight/devices/etm/ctxid_pid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Get/Set the context ID comparator value to trigger on. -What: /sys/bus/coresight/devices/.etm/ctxid_masks +What: /sys/bus/coresight/devices/etm/ctxid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/.etm/vmid_idx +What: /sys/bus/coresight/devices/etm/vmid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Select which virtual machine ID comparator to work with. -What: /sys/bus/coresight/devices/.etm/vmid_val +What: /sys/bus/coresight/devices/etm/vmid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Get/Set the virtual machine ID comparator value to trigger on. -What: /sys/bus/coresight/devices/.etm/vmid_masks +What: /sys/bus/coresight/devices/etm/vmid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/.etm/mgmt/trcoslsr +What: /sys/bus/coresight/devices/etm/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the OS Lock Status Register (0x304). The value it taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpdcr +What: /sys/bus/coresight/devices/etm/mgmt/trcpdcr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Power Down Control Register (0x310). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpdsr +What: /sys/bus/coresight/devices/etm/mgmt/trcpdsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Power Down Status Register (0x314). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trclsr +What: /sys/bus/coresight/devices/etm/mgmt/trclsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the SW Lock Status Register (0xFB4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcauthstatus +What: /sys/bus/coresight/devices/etm/mgmt/trcauthstatus Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Authentication Status Register (0xFB8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcdevid +What: /sys/bus/coresight/devices/etm/mgmt/trcdevid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcdevtype +What: /sys/bus/coresight/devices/etm/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Device Type Register (0xFCC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr0 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID0 Register (0xFE0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr1 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID1 Register (0xFE4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr2 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID2 Register (0xFE8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr3 +What: /sys/bus/coresight/devices/etm/mgmt/trcpidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/mgmt/trcconfig +What: /sys/bus/coresight/devices/etm/mgmt/trcconfig Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier Description: (R) Print the content of the trace configuration register (0x010) as currently set by SW. -What: /sys/bus/coresight/devices/.etm/mgmt/trctraceid +What: /sys/bus/coresight/devices/etm/mgmt/trctraceid Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier Description: (R) Print the content of the trace ID register (0x040). -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr0 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr1 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr2 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -394,7 +394,7 @@ Description: (R) Returns the maximum size of the data value, data address, VMID, context ID and instuction address in the trace unit (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr3 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -403,42 +403,42 @@ Description: (R) Returns the value associated with various resources architecture specification for more details (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr4 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr4 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns how many resources the trace unit supports (0x1F0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr5 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr5 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns how many resources the trace unit supports (0x1F4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr8 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr8 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the maximum speculation depth of the instruction trace stream. (0x180). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr9 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr9 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the number of P0 right-hand keys that the trace unit can use (0x184). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr10 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr10 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Returns the number of P1 right-hand keys that the trace unit can use (0x188). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr11 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr11 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -446,7 +446,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the trace unit can use (0x18C). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr12 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr12 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier @@ -454,7 +454,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that the trace unit can use (0x190). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/.etm/trcidr/trcidr13 +What: /sys/bus/coresight/devices/etm/trcidr/trcidr13 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier From patchwork Thu Oct 31 17:58:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 11221677 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5861314E5 for ; Thu, 31 Oct 2019 17:58:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E5662080F for ; Thu, 31 Oct 2019 17:58:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="CG3giz99"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ATidlEjE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2E5662080F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=3+lTqq2HhsqzJgqapvk8Gz4KbcWkhSBv22DBeAJ3bRY=; b=CG3giz99MPigHUS+JoWJMzsUC0 oF8sejDGb8aFYSpVgbQotOS5P61kA8kS5TG2lyCDe+qEZEI+FT7GsnQPYvB6YoD4giHQ6Ud6sjLj/ MJ8P/m0IUckeGdpPN3tSKIlw13V+6nFQgMChp6tCfkrnkhRQerJpGFadv1Jx7dZggu+dwbKM4MTe7 0ZrQyr6wiBBKZ5Wor2o4MjJMlR2ohADWuDaM7YuVaQo8GUoF6RpAcHXXt8m61//dhH54+tY+u14SV OkKtWtc5NZzXjQ4NtY3n8Er7Krp/lA2wVFl6CkkvE9NLj+vGs5MEx3k080r96UJkATNsTvWG39NF+ lksRoXDg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iQEif-0008IP-L3; Thu, 31 Oct 2019 17:58:49 +0000 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iQEiU-00088S-A1 for linux-arm-kernel@lists.infradead.org; Thu, 31 Oct 2019 17:58:39 +0000 Received: by mail-pf1-x441.google.com with SMTP id q26so4855415pfn.11 for ; Thu, 31 Oct 2019 10:58:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/ws48OPfYIJsP3hLi0od0xxVO+NdaAYQZFQkL5nisiM=; b=ATidlEjEqD00UPJarL+ncmaSsGAlcuIP8YB2LTb+0EVSJWNqesZQj6dFeAV7iSzX91 BvzrjMRoTBs2lfTwKEYXe1AaDvKWhphMavrmAx2ZYd0y/qHStcqHTKuY9klBNyRDp0j3 q2YmpFczqJajz69+imTNDU0LtX4QTyHZXLV6dtzD+Ya50UY7DaX8YXNtRWGQaBopGBsx s8AtgTZTQZnO7FZ+f7A9fbcxsCQUnsTIY5Ba3i+Gxs/cfmQvb7hxQu035hpAq+jaakyJ 4Vo1yK6PH210LLJPYdll0hlBzeYvNDkd3//aqYIpb++z5Xwas2SMkC0E0aBx9AUuY7Rx Sbnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/ws48OPfYIJsP3hLi0od0xxVO+NdaAYQZFQkL5nisiM=; b=quYr6wPhZwWsYxTPyHcv/o7boYSjtqavMzEkA9ulE3Nu5+gx1f/HTq/eeyzQhCCC3k 34Ex5kb65LZHh5viABGHaDorf3bo5O+pslNggsMOTYQfdGhw0t8/k+kdAaUU537aPCns 4LvdVY2Idz9fBoUjQP0y7ZNzBJNGsRs3jzYd29bZd8P4i8F3x7aLeE6dAWQrXMDF9HY3 4+pWVaCfJT4g294Em+5YKIhb0sNakEkTAi8X1FczPx9s/S7xcMDC8fMyzStEiDD+kCpT YlVmnGYyzbIYe79GqlG3+qLvkJy98AuZ111V6CE+OYLxJDU44KqdqMb9tygqjU8MhpWN rm9w== X-Gm-Message-State: APjAAAWyKrrx/jGh6gS2IgU7ww/Gbtu7BjLqtFCAfBmM9nyWf5gyhk9x Vy0fBizozrUeFjUvbv3HaRkbRG3t9yA= X-Google-Smtp-Source: APXvYqxQs8ZQ5Ruv/C9/lnpJ42h8VwAa6x+pIpe8aXf0grM0GwA7KunaMBdVfcWHB/0EeZDApjFciA== X-Received: by 2002:a63:65c6:: with SMTP id z189mr7889040pgb.433.1572544717693; Thu, 31 Oct 2019 10:58:37 -0700 (PDT) Received: from xps15.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id c6sm4382210pfj.59.2019.10.31.10.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2019 10:58:37 -0700 (PDT) From: Mathieu Poirier To: corbet@lwn.net Subject: [PATCH 2/4] coresight: etm4x: docs: Update ABI doc for new sysfs etm4 attributes Date: Thu, 31 Oct 2019 11:58:32 -0600 Message-Id: <20191031175834.17548-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191031175834.17548-1-mathieu.poirier@linaro.org> References: <20191031175834.17548-1-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191031_105838_347164_DDC3D05C X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Mike Leach This updates the ABI document to reflect recent additions to the ETM4.X driver sysfs interface. Signed-off-by: Mike Leach [Updated Date and KernelVersion fields] Reviewed-by: Mathieu Poirier --- .../testing/sysfs-bus-coresight-devices-etm4x | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 9290010e973e..614874e2cf53 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -282,6 +282,53 @@ Contact: Mathieu Poirier Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). +What: /sys/bus/coresight/devices/etm/addr_exlevel_s_ns +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (RW) Set the Exception Level matching bits for secure and + non-secure exception levels. + +What: /sys/bus/coresight/devices/etm/vinst_pe_cmp_start_stop +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (RW) Access the start stop control register for PE input + comparators. + +What: /sys/bus/coresight/devices/etm/addr_cmp_view +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (R) Print the current settings for the selected address + comparator. + +What: /sys/bus/coresight/devices/etm/sshot_idx +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (RW) Select the single shot control register to access. + +What: /sys/bus/coresight/devices/etm/sshot_ctrl +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (RW) Access the selected single shot control register. + +What: /sys/bus/coresight/devices/etm/sshot_status +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (R) Print the current value of the selected single shot + status register. + +What: /sys/bus/coresight/devices/etm/sshot_pe_ctrl +Date: December 2019 +KernelVersion: 5.5 +Contact: Mathieu Poirier +Description: (RW) Access the selected single show PE comparator control + register. + What: /sys/bus/coresight/devices/etm/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 From patchwork Thu Oct 31 17:58:33 2019 Content-Type: text/plain; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c6sm4382210pfj.59.2019.10.31.10.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2019 10:58:38 -0700 (PDT) From: Mathieu Poirier To: corbet@lwn.net Subject: [PATCH 3/4] coresight: docs: Create common sub-directory for coresight trace. Date: Thu, 31 Oct 2019 11:58:33 -0600 Message-Id: <20191031175834.17548-4-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191031175834.17548-1-mathieu.poirier@linaro.org> References: <20191031175834.17548-1-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191031_105839_704533_141D12A0 X-CRM114-Status: GOOD ( 13.76 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Mike Leach There are two files in the Documentation/trace directory relating to coresight, with more to follow, so create a Documentation/trace/coresight directory and move existing files there. Fixup index to reference new location. Update MAINTAINERS to reference this sub-directory rather than the individual files. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../trace/{ => coresight}/coresight-cpu-debug.rst | 0 Documentation/trace/{ => coresight}/coresight.rst | 2 +- Documentation/trace/coresight/index.rst | 9 +++++++++ Documentation/trace/index.rst | 3 +-- MAINTAINERS | 3 +-- 5 files changed, 12 insertions(+), 5 deletions(-) rename Documentation/trace/{ => coresight}/coresight-cpu-debug.rst (100%) rename Documentation/trace/{ => coresight}/coresight.rst (99%) create mode 100644 Documentation/trace/coresight/index.rst diff --git a/Documentation/trace/coresight-cpu-debug.rst b/Documentation/trace/coresight/coresight-cpu-debug.rst similarity index 100% rename from Documentation/trace/coresight-cpu-debug.rst rename to Documentation/trace/coresight/coresight-cpu-debug.rst diff --git a/Documentation/trace/coresight.rst b/Documentation/trace/coresight/coresight.rst similarity index 99% rename from Documentation/trace/coresight.rst rename to Documentation/trace/coresight/coresight.rst index 72f4b7ef1bad..a566719f8e7e 100644 --- a/Documentation/trace/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -489,7 +489,7 @@ interface provided for that purpose by the generic STM API:: crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0 root@genericarmv8:~# -Details on how to use the generic STM API can be found here [#second]_. +Details on how to use the generic STM API can be found here:- :doc:`../stm` [#second]_. .. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm diff --git a/Documentation/trace/coresight/index.rst b/Documentation/trace/coresight/index.rst new file mode 100644 index 000000000000..8d31b155a87c --- /dev/null +++ b/Documentation/trace/coresight/index.rst @@ -0,0 +1,9 @@ +============================== +CoreSight - ARM Hardware Trace +============================== + +.. toctree:: + :maxdepth: 2 + :glob: + + * diff --git a/Documentation/trace/index.rst b/Documentation/trace/index.rst index b7891cb1ab4d..04acd277c5f6 100644 --- a/Documentation/trace/index.rst +++ b/Documentation/trace/index.rst @@ -23,5 +23,4 @@ Linux Tracing Technologies intel_th stm sys-t - coresight - coresight-cpu-debug + coresight/index diff --git a/MAINTAINERS b/MAINTAINERS index 296de2b51c83..f903160b507c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1608,8 +1608,7 @@ R: Suzuki K Poulose L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/hwtracing/coresight/* -F: Documentation/trace/coresight.rst -F: Documentation/trace/coresight-cpu-debug.rst +F: Documentation/trace/coresight/* F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* From patchwork Thu Oct 31 17:58:34 2019 Content-Type: text/plain; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id c6sm4382210pfj.59.2019.10.31.10.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2019 10:58:39 -0700 (PDT) From: Mathieu Poirier To: corbet@lwn.net Subject: [PATCH 4/4] coresight: etm4x: docs: Adds detailed document for programming etm4x. Date: Thu, 31 Oct 2019 11:58:34 -0600 Message-Id: <20191031175834.17548-5-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191031175834.17548-1-mathieu.poirier@linaro.org> References: <20191031175834.17548-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191031_105841_917983_75F1A0AB X-CRM114-Status: GOOD ( 16.47 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Mike Leach Add in detailed programmers reference for users wanting to program the CoreSight ETM 4.x driver using sysfs. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../coresight/coresight-etm4x-reference.rst | 798 ++++++++++++++++++ 1 file changed, 798 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.rst diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst new file mode 100644 index 000000000000..b64d9a9c79df --- /dev/null +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst @@ -0,0 +1,798 @@ +=============================================== +ETMv4 sysfs linux driver programming reference. +=============================================== + + :Author: Mike Leach + :Date: October 11th, 2019 + +Supplement to existing ETMv4 driver documentation. + +Sysfs files and directories +--------------------------- + +Root: ``/sys/bus/coresight/devices/etm`` + + +The following paragraphs explain the association between sysfs files and the +ETMv4 registers that they effect. Note the register names are given without +the ‘TRC’ prefix. + +---- + +:File: ``mode`` (rw) +:Trace Registers: {CONFIGR + others} +:Notes: + Bit select trace features. See ‘mode’ section below. Bits + in this will cause equivalent programming of trace config and + other registers to enable the features requested. + +:Syntax & eg: + ``echo bitfield > mode`` + + bitfield up to 32 bits setting trace features. + +:Example: + ``$> echo 0x012 > mode`` + +---- + +:File: ``reset`` (wo) +:Trace Registers: All +:Notes: + Reset all programming to trace nothing / no logic programmed. + +:Syntax: + ``echo 1 > reset`` + +---- + +:File: ``enable_source`` (wo) +:Trace Registers: PRGCTLR, All hardware regs. +:Notes: + - > 0 : Programs up the hardware with the current values held in the driver + and enables trace. + + - = 0 : disable trace hardware. + +:Syntax: + ``echo 1 > enable_source`` + +---- + +:File: ``cpu`` (ro) +:Trace Registers: None. +:Notes: + CPU ID that this ETM is attached to. + +:Example: + ``$> cat cpu`` + + ``$> 0`` + +---- + +:File: ``addr_idx`` (rw) +:Trace Registers: None. +:Notes: + Virtual register to index address comparator and range + features. Set index for first of the pair in a range. + +:Syntax: + ``echo idx > addr_idx`` + + Where idx < nr_addr_cmp x 2 + +---- + +:File: ``addr_range`` (rw) +:Trace Registers: ACVR[idx, idx+1], VIIECTLR +:Notes: + Pair of addresses for a range selected by addr_idx. Include + / exclude according to the optional parameter, or if omitted + uses the current ‘mode’ setting. Select comparator range in + control register. Error if index is odd value. + +:Depends: ``mode, addr_idx`` +:Syntax: + ``echo addr1 addr2 [exclude] > addr_range`` + + Where addr1 and addr2 define the range and addr1 < addr2. + + Optional exclude value:- + + - 0 for include + - 1 for exclude. +:Example: + ``$> echo 0x0000 0x2000 0 > addr_range`` + +---- + +:File: ``addr_single`` (rw) +:Trace Registers: ACVR[idx] +:Notes: + Set a single address comparator according to addr_idx. This + is used if the address comparator is used as part of event + generation logic etc. + +:Depends: ``addr_idx`` +:Syntax: + ``echo addr1 > addr_single`` + +---- + +:File: ``addr_start`` (rw) +:Trace Registers: ACVR[idx], VISSCTLR +:Notes: + Set a trace start address comparator according to addr_idx. + Select comparator in control register. + +:Depends: ``addr_idx`` +:Syntax: + ``echo addr1 > addr_start`` + +---- + +:File: ``addr_stop`` (rw) +:Trace Registers: ACVR[idx], VISSCTLR +:Notes: + Set a trace stop address comparator according to addr_idx. + Select comparator in control register. + +:Depends: ``addr_idx`` +:Syntax: + ``echo addr1 > addr_stop`` + +---- + +:File: ``addr_context`` (rw) +:Trace Registers: ACATR[idx,{6:4}] +:Notes: + Link context ID comparator to address comparator addr_idx + +:Depends: ``addr_idx`` +:Syntax: + ``echo ctxt_idx > addr_context`` + + Where ctxt_idx is the index of the linked context id / vmid + comparator. + +---- + +:File: ``addr_ctxtype`` (rw) +:Trace Registers: ACATR[idx,{3:2}] +:Notes: + Input value string. Set type for linked context ID comparator + +:Depends: ``addr_idx`` +:Syntax: + ``echo type > addr_ctxtype`` + + Type one of {all, vmid, ctxid, none} +:Example: + ``$> echo ctxid > addr_ctxtype`` + +---- + +:File: ``addr_exlevel_s_ns`` (rw) +:Trace Registers: ACATR[idx,{14:8}] +:Notes: + Set the ELx secure and non-secure matching bits for the + selected address comparator + +:Depends: ``addr_idx`` +:Syntax: + ``echo val > addr_exlevel_s_ns`` + + val is a 7 bit value for exception levels to exclude. Input + value shifted to correct bits in register. +:Example: + ``$> echo 0x4F > addr_exlevel_s_ns`` + +---- + +:File: ``addr_instdatatype`` (rw) +:Trace Registers: ACATR[idx,{1:0}] +:Notes: + Set the comparator address type for matching. Driver only + supports setting instruction address type. + +:Depends: ``addr_idx`` + +---- + +:File: ``addr_cmp_view`` (ro) +:Trace Registers: ACVR[idx, idx+1], ACATR[idx], VIIECTLR +:Notes: + Read the currently selected address comparator. If part of + address range then display both addresses. + +:Depends: ``addr_idx`` +:Syntax: + ``cat addr_cmp_view`` +:Example: + ``$> cat addr_cmp_view`` + + ``addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00)`` + +---- + +:File: ``nr_addr_cmp`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of address comparator pairs + +---- + +:File: ``sshot_idx`` (rw) +:Trace Registers: None +:Notes: + Select single shot register set. + +---- + +:File: ``sshot_ctrl`` (rw) +:Trace Registers: SSCCR[idx] +:Notes: + Access a single shot comparator control register. + +:Depends: ``sshot_idx`` +:Syntax: + ``echo val > sshot_ctrl`` + + Writes val into the selected control register. + +---- + +:File: ``sshot_status`` (ro) +:Trace Registers: SSCSR[idx] +:Notes: + Read a single shot comparator status register + +:Depends: ``sshot_idx`` +:Syntax: + ``cat sshot_status`` + + Read status. +:Example: + ``$> cat sshot_status`` + + ``0x1`` + +---- + +:File: ``sshot_pe_ctrl`` (rw) +:Trace Registers: SSPCICR[idx] +:Notes: + Access a single shot PE comparator input control register. + +:Depends: ``sshot_idx`` +:Syntax: + ``echo val > sshot_pe_ctrl`` + + Writes val into the selected control register. + +---- + +:File: ``ns_exlevel_vinst`` (rw) +:Trace Registers: VICTLR{23:20} +:Notes: + Program non-secure exception level filters. Set / clear NS + exception filter bits. Setting ‘1’ excludes trace from the + exception level. + +:Syntax: + ``echo bitfield > ns_exlevel_viinst`` + + Where bitfield contains bits to set clear for EL0 to EL2 +:Example: + ``%> echo 0x4 > ns_exlevel_viinst`` + + Excludes EL2 NS trace. + +---- + +:File: ``vinst_pe_cmp_start_stop`` (rw) +:Trace Registers: VIPCSSCTLR +:Notes: + Access PE start stop comparator input control registers + +---- + +:File: ``bb_ctrl`` (rw) +:Trace Registers: BBCTLR +:Notes: + Define ranges that Branch Broadcast will operate in. + Default (0x0) is all addresses. + +:Depends: BB enabled. + +---- + +:File: ``cyc_threshold`` (rw) +:Trace Registers: CCCTLR +:Notes: + Set the threshold for which cycle counts will be emitted. + Error if attempt to set below minimum defined in IDR3, masked + to width of valid bits. + +:Depends: CC enabled. + +---- + +:File: ``syncfreq`` (rw) +:Trace Registers: SYNCPR +:Notes: + Set trace synchronisation period. Power of 2 value, 0 (off) + or 8-20. Driver defaults to 12 (every 4096 bytes). + +---- + +:File: ``cntr_idx`` (rw) +:Trace Registers: none +:Notes: + Select the counter to access + +:Syntax: + ``echo idx > cntr_idx`` + + Where idx < nr_cntr + +---- + +:File: ``cntr_ctrl`` (rw) +:Trace Registers: CNTCTLR[idx] +:Notes: + Set counter control value. + +:Depends: ``cntr_idx`` +:Syntax: + ``echo val > cntr_ctrl`` + + Where val is per ETMv4 spec. + +---- + +:File: ``cntrldvr`` (rw) +:Trace Registers: CNTRLDVR[idx] +:Notes: + Set counter reload value. + +:Depends: ``cntr_idx`` +:Syntax: + ``echo val > cntrldvr`` + + Where val is per ETMv4 spec. + +---- + +:File: ``nr_cntr`` (ro) +:Trace Registers: From IDR5 + +:Notes: + Number of counters implemented. + +---- + +:File: ``ctxid_idx`` (rw) +:Trace Registers: None +:Notes: + Select the context ID comparator to access + +:Syntax: + ``echo idx > ctxid_idx`` + + Where idx < numcidc + +---- + +:File: ``ctxid_pid`` (rw) +:Trace Registers: CIDCVR[idx] +:Notes: + Set the context ID comparator value + +:Depends: ``ctxid_idx`` + +---- + +:File: ``ctxid_masks`` (rw) +:Trace Registers: CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> +:Notes: + Pair of values to set the byte masks for 1-8 context ID + comparators. Automatically clears masked bytes to 0 in CID + value registers. + +:Syntax: + ``echo m3m2m1m0 [m7m6m5m4] > ctxid_masks`` + + 32 bit values made up of mask bytes, where mN represents a + byte mask value for Context ID comparator N. + + Second value not required on systems that have fewer than 4 + context ID comparators + +---- + +:File: ``numcidc`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of Context ID comparators + +---- + +:File: ``vmid_idx`` (rw) +:Trace Registers: None +:Notes: + Select the VM ID comparator to access. + +:Syntax: + ``echo idx > vmid_idx`` + + Where idx <  numvmidc + +---- + +:File: ``vmid_val`` (rw) +:Trace Registers: VMIDCVR[idx] +:Notes: + Set the VM ID comparator value + +:Depends: ``vmid_idx`` + +---- + +:File: ``vmid_masks`` (rw) +:Trace Registers: VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> +:Notes: + Pair of values to set the byte masks for 1-8 VM ID comparators. + Automatically clears masked bytes to 0 in VMID value registers. + +:Syntax: + ``echo m3m2m1m0 [m7m6m5m4] > vmid_masks`` + + Where mN represents a byte mask value for VMID comparator N. + Second value not required on systems that have fewer than 4 + VMID comparators. + +---- + +:File: ``numvmidc`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of VMID comparators + +---- + +:File: ``res_idx`` (rw) +:Trace Registers: None. +:Notes: + Select the resource selector control to access. Must be 2 or + higher as selectors 0 and 1 are hardwired. + +:Syntax: + ``echo idx > res_idx`` + + Where 2 <= idx < nr_resource x 2 + +---- + +:File: ``res_ctrl`` (rw) +:Trace Registers: RSCTLR[idx] +:Notes: + Set resource selector control value. Value per ETMv4 spec. + +:Depends: ``res_idx`` +:Syntax: + ``echo val > res_cntr`` + + Where val is per ETMv4 spec. + +---- + +:File: ``nr_resource`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of resource selector pairs + +---- + +:File: ``event`` (rw) +:Trace Registers: EVENTCTRL0R +:Notes: + Set up to 4 implemented event fields. + +:Syntax: + ``echo ev3ev2ev1ev0 > event`` + + Where evN is an 8 bit event field. Up to 4 event fields make up the + 32-bit input value. Number of valid fields is implementation dependent, + defined in IDR0. + +---- + +:File: ``event_instren`` (rw) +:Trace Registers: EVENTCTRL1R +:Notes: + Choose events which insert event packets into trace stream. + +:Depends: EVENTCTRL0R +:Syntax: + ``echo bitfield > event_instren`` + + Where bitfield is up to 4 bits according to number of event fields. + +---- + +:File: ``event_ts`` (rw) +:Trace Registers: TSCTLR +:Notes: + Set the event that will generate timestamp requests. + +:Depends: ``TS activated`` +:Syntax: + ``echo evfield > event_ts`` + + Where evfield is an 8 bit event selector. + +---- + +:File: ``seq_idx`` (rw) +:Trace Registers: None +:Notes: + Sequencer event register select - 0 to 2 + +---- + +:File: ``seq_state`` (rw) +:Trace Registers: SEQSTR +:Notes: + Sequencer current state - 0 to 3. + +---- + +:File: ``seq_event`` (rw) +:Trace Registers: SEQEVR[idx] +:Notes: + State transition event registers + +:Depends: ``seq_idx`` +:Syntax: + ``echo evBevF > seq_event`` + + Where evBevF is a 16 bit value made up of two event selectors, + + - evB : back + - evF : forwards. + +---- + +:File: ``seq_reset_event`` (rw) +:Trace Registers: SEQRSTEVR +:Notes: + Sequencer reset event + +:Syntax: + ``echo evfield > seq_reset_event`` + + Where evfield is an 8 bit event selector. + +---- + +:File: ``nrseqstate`` (ro) +:Trace Registers: From IDR5 +:Notes: + Number of sequencer states (0 or 4) + +---- + +:File: ``nr_pe_cmp`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of PE comparator inputs + +---- + +:File: ``nr_ext_inp`` (ro) +:Trace Registers: From IDR5 +:Notes: + Number of external inputs + +---- + +:File: ``nr_ss_cmp`` (ro) +:Trace Registers: From IDR4 +:Notes: + Number of Single Shot control registers + +---- + +*Note:* When programming any address comparator the driver will tag the +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag +is set, then only the values can be changed using the same sysfs file / type +used to program it. + +Thus:: + + % echo 0 > addr_idx ; select address comparator 0 + % echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0, 1. + % echo 0x2000 > addr_start ; error as comparator 0 is a range comparator + % echo 2 > addr_idx ; select address comparator 2 + % echo 0x2000 > addr_start ; this is OK as comparator 2 is unused. + % echo 0x3000 > addr_stop ; error as comparator 2 set as start address. + % echo 2 > addr_idx ; select address comparator 3 + % echo 0x3000 > addr_stop ; this is OK + +To remove programming on all the comparators (and all the other hardware) use +the reset parameter:: + + % echo 1 > reset + + + +The ‘mode’ sysfs parameter. +--------------------------- + +This is a bitfield selection parameter that sets the overall trace mode for the +ETM. The table below describes the bits, using the defines from the driver +source file, along with a description of the feature these represent. Many +features are optional and therefore dependent on implementation in the +hardware. + +Bit assignments shown below:- + +---- + +**bit (0):** + ETM_MODE_EXCLUDE + +**description:** + This is the default value for the include / exclude function when + setting address ranges. Set 1 for exclude range. When the mode + parameter is set this value is applied to the currently indexed + address range. + + +**bit (4):** + ETM_MODE_BB + +**description:** + Set to enable branch broadcast if supported in hardware [IDR0]. + + +**bit (5):** + ETMv4_MODE_CYCACC + +**description:** + Set to enable cycle accurate trace if supported [IDR0]. + + +**bit (6):** + ETMv4_MODE_CTXID + +**description:** + Set to enable context ID tracing if supported in hardware [IDR2]. + + +**bit (7):** + ETM_MODE_VMID + +**description:** + Set to enable virtual machine ID tracing if supported [IDR2]. + + +**bit (11):** + ETMv4_MODE_TIMESTAMP + +**description:** + Set to enable timestamp generation if supported [IDR0]. + + +**bit (12):** + ETM_MODE_RETURNSTACK +**description:** + Set to enable trace return stack use if supported [IDR0]. + + +**bit (13-14):** + ETM_MODE_QELEM(val) + +**description:** + ‘val’ determines level of Q element support enabled if + implemented by the ETM [IDR0] + + +**bit (19):** + ETM_MODE_ATB_TRIGGER + +**description:** + Set to enable the ATBTRIGGER bit in the event control register + [EVENTCTLR1] if supported [IDR5]. + + +**bit (20):** + ETM_MODE_LPOVERRIDE + +**description:** + Set to enable the LPOVERRIDE bit in the event control register + [EVENTCTLR1], if supported [IDR5]. + + +**bit (21):** + ETM_MODE_ISTALL_EN + +**description:** + Set to enable the ISTALL bit in the stall control register + [STALLCTLR] + + +**bit (23):** + ETM_MODE_INSTPRIO + +**description:** + Set to enable the INSTPRIORITY bit in the stall control register + [STALLCTLR] , if supported [IDR0]. + + +**bit (24):** + ETM_MODE_NOOVERFLOW + +**description:** + Set to enable the NOOVERFLOW bit in the stall control register + [STALLCTLR], if supported [IDR3]. + + +**bit (25):** + ETM_MODE_TRACE_RESET + +**description:** + Set to enable the TRCRESET bit in the viewinst control register + [VICTLR] , if supported [IDR3]. + + +**bit (26):** + ETM_MODE_TRACE_ERR + +**description:** + Set to enable the TRCCTRL bit in the viewinst control register + [VICTLR]. + + +**bit (27):** + ETM_MODE_VIEWINST_STARTSTOP + +**description:** + Set the initial state value of the ViewInst start / stop logic + in the viewinst control register [VICTLR] + + +**bit (30):** + ETM_MODE_EXCL_KERN + +**description:** + Set default trace setup to exclude kernel mode trace (see note a) + + +**bit (31):** + ETM_MODE_EXCL_USER + +**description:** + Set default trace setup to exclude user space trace (see note a) + +---- + +*Note a)* On startup the ETM is programmed to trace the complete address space +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to +set EL exclude bits for NS state in either user space (EL0) or kernel space +(EL1) in the address range comparator. (the default setting excludes all +secure EL, and NS EL2) + +Once the reset parameter has been used, and/or custom programming has been +implemented - using these bits will result in the EL bits for address +comparator 0 being set in the same way. + +*Note b)* Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with +data trace. As A-profile data trace is architecturally prohibited in ETMv4, +these have been omitted here. Possible uses could be where a kernel has +support for control of R or M profile infrastructure as part of a heterogeneous +system. + +Bits 17, 28-29 are unused.