From patchwork Fri Nov 1 06:31:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 11222411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F48F1515 for ; Fri, 1 Nov 2019 06:31:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 669DB208E3 for ; Fri, 1 Nov 2019 06:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725936AbfKAGbc (ORCPT ); Fri, 1 Nov 2019 02:31:32 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:38780 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725798AbfKAGbc (ORCPT ); Fri, 1 Nov 2019 02:31:32 -0400 X-IronPort-AV: E=Sophos;i="5.68,254,1569250800"; d="scan'208";a="30388548" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 01 Nov 2019 15:31:30 +0900 Received: from localhost.localdomain (unknown [10.166.17.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C03A340104DD; Fri, 1 Nov 2019 15:31:30 +0900 (JST) From: Yoshihiro Shimoda To: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, stable@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 1/2] Revert "PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" Date: Fri, 1 Nov 2019 15:31:29 +0900 Message-Id: <1572589890-8903-2-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572589890-8903-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1572589890-8903-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This reverts commit 175cc093888ee74a17c4dd5f99ba9a6bc86de5be. The commit description/code don't follow the manual accurately, it's difficult to understand. So, this patch reverts the commit. Fixes: 175cc093888e ("PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" Cc: Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/pcie-rcar.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index 0dadccb..40d8c54 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -91,7 +91,6 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 -#define MACCTLR_RESERVED BIT(0) #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -614,8 +613,6 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); - rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); - /* Finish initialization - establish a PCI Express link */ rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); @@ -1238,7 +1235,6 @@ static int rcar_pcie_resume_noirq(struct device *dev) return 0; /* Re-establish the PCIe link */ - rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0); rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); return rcar_pcie_wait_for_dl(pcie); } From patchwork Fri Nov 1 06:31:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 11222419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 960FC1515 for ; Fri, 1 Nov 2019 06:31:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 715C5208CB for ; Fri, 1 Nov 2019 06:31:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726618AbfKAGbd (ORCPT ); Fri, 1 Nov 2019 02:31:33 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:16533 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726454AbfKAGbd (ORCPT ); Fri, 1 Nov 2019 02:31:33 -0400 X-IronPort-AV: E=Sophos;i="5.68,254,1569250800"; d="scan'208";a="30602187" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 01 Nov 2019 15:31:30 +0900 Received: from localhost.localdomain (unknown [10.166.17.210]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id CD70640104DC; Fri, 1 Nov 2019 15:31:30 +0900 (JST) From: Yoshihiro Shimoda To: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, stable@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v2 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence Date: Fri, 1 Nov 2019 15:31:30 +0900 Message-Id: <1572589890-8903-3-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572589890-8903-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1572589890-8903-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org According to the R-Car Gen2/3 manual, "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT". To avoid unexpected behaviors, this patch fixes it. Note that the SPCHG bit of MACCTLR register description said "Only writing 1 is valid and writing 0 is invalid" but this "invalid" means "ignored", not "prohibited". So, any documentation conflict doesn't exist about writing the MACCTLR register. Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver") Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()") Cc: # v5.2+ Signed-off-by: Yoshihiro Shimoda Reported-by: Eugeniu Rosca Reviewed-by: Eugeniu Rosca --- drivers/pci/controller/pcie-rcar.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c index 40d8c54..d470ab8 100644 --- a/drivers/pci/controller/pcie-rcar.c +++ b/drivers/pci/controller/pcie-rcar.c @@ -91,6 +91,7 @@ #define LINK_SPEED_2_5GTS (1 << 16) #define LINK_SPEED_5_0GTS (2 << 16) #define MACCTLR 0x011058 +#define MACCTLR_INIT_VAL 0x80ff0000 #define SPEED_CHANGE BIT(24) #define SCRAMBLE_DISABLE BIT(27) #define PMSR 0x01105c @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); + /* Finish initialization - establish a PCI Express link */ rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev) return 0; /* Re-establish the PCIe link */ + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); return rcar_pcie_wait_for_dl(pcie); }