From patchwork Fri Nov 1 16:37:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: thermal-bot for Julien Panis X-Patchwork-Id: 11223417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 482B214DB for ; Fri, 1 Nov 2019 16:37:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F7EB217D9 for ; Fri, 1 Nov 2019 16:37:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729026AbfKAQhr (ORCPT ); Fri, 1 Nov 2019 12:37:47 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:60104 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727626AbfKAQhq (ORCPT ); Fri, 1 Nov 2019 12:37:46 -0400 Received: from [5.158.153.53] (helo=tip-bot2.lab.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iQZve-0002yY-9u; Fri, 01 Nov 2019 17:37:38 +0100 Received: from [127.0.1.1] (localhost [IPv6:::1]) by tip-bot2.lab.linutronix.de (Postfix) with ESMTP id DC4B91C0315; Fri, 1 Nov 2019 17:37:37 +0100 (CET) Date: Fri, 01 Nov 2019 16:37:37 -0000 From: "tip-bot2 for Tony Luck" Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: ras/core] x86/mce: Add Xeon Icelake to list of CPUs that support PPIN Cc: Tony Luck , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , "linux-edac" , Thomas Gleixner , "x86-ml" , Ingo Molnar , Borislav Petkov , linux-kernel@vger.kernel.org In-Reply-To: <20191028163719.19708-1-tony.luck@intel.com> References: <20191028163719.19708-1-tony.luck@intel.com> MIME-Version: 1.0 Message-ID: <157262625753.29376.16645566147052348797.tip-bot2@tip-bot2> X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The following commit has been merged into the ras/core branch of tip: Commit-ID: dc6b025de95bcd22ff37c4fabb022ec8a027abf1 Gitweb: https://git.kernel.org/tip/dc6b025de95bcd22ff37c4fabb022ec8a027abf1 Author: Tony Luck AuthorDate: Mon, 28 Oct 2019 09:37:19 -07:00 Committer: Borislav Petkov CommitterDate: Fri, 01 Nov 2019 17:29:36 +01:00 x86/mce: Add Xeon Icelake to list of CPUs that support PPIN New CPU model, same MSRs to control and read the inventory number. Signed-off-by: Tony Luck Signed-off-by: Borislav Petkov Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: linux-edac Cc: Thomas Gleixner Cc: x86-ml Link: https://lkml.kernel.org/r/20191028163719.19708-1-tony.luck@intel.com --- arch/x86/kernel/cpu/mce/intel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 68a1d25..e270d07 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -484,6 +484,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: