From patchwork Tue Nov 5 21:25:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11228755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AE59139A for ; Tue, 5 Nov 2019 21:25:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3CAA121929 for ; Tue, 5 Nov 2019 21:25:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="qsHpgIcG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729985AbfKEVZh (ORCPT ); Tue, 5 Nov 2019 16:25:37 -0500 Received: from mail-eopbgr680076.outbound.protection.outlook.com ([40.107.68.76]:15246 "EHLO NAM04-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729976AbfKEVZh (ORCPT ); Tue, 5 Nov 2019 16:25:37 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SDOLt9GGp4T0AU9m9ux0B4sIyMha04S7zuHk50o8vZL9/N6NwAGtgN+lfBIv5Exp+xhbnP5QeY/MlkOgvpS6VqlOqrEqvxNUO1RNNzkerUJEPLoltnXo+1UQ9vz1o+//c9U0MQ4hvmTuRPVM58wONz5OPW3n+Tn8gWCiPn4Rx52GdNXpM27y218zAzgp56HiPTNO5D87JS0ds5E18oeXDPPNx0PgmshMlNEWzTCimJPDLZizi1yBTTcslBXUoFv+HdSXx0yjfEy8pNqonsK4mvl75rUsXBWBk8l1Q9c6TlqPP9/ibxA6odDISpg8VYyiRdztEA6+BN4CyttC/8Yz/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UHaVTCAPAa2PXuzAYcJxBwSPmQecCgZXVdVUs4LVvF0=; b=kcnCd1ajDKo9gVHRE/Sy90anVKf6fZifKrvgKWPgoX4WIZWk0BK+8FUsoRr6BIYsjDOaBL3SWOLkn0WIwsnYiYywM8wVtzmHpiRXYn7aEXvmRoQ9vdIWxi3HR0RfmTu6MeC8OF8wbFvxCpNjtcFgYVbasFcfv52Nc67lyVdURXZ/faX7PIpVFg4ei1u77rfXecLS+ounty4vFR5Iu/kGEQQfT5OVfl1JlWgKef/23NAIKYxu93mfksxn3iXp9wpU34/AKKTbCPkfNiXY5HgEe5whPmIqiSK6y4/zWKssqiRvj6a/9MaAB6CamMdfyyB4aoV8hagPmMrzseMMKA4taw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UHaVTCAPAa2PXuzAYcJxBwSPmQecCgZXVdVUs4LVvF0=; b=qsHpgIcG6lMqZSQ4C3gfoHyORO1w0UNB7y96WH3dg2i84qemj4kuxuFUoG4jS4sz1mmcg04V7cfuIlIUJFC7YYCT0G7vaFTzRCh4KAqZdigymynININPZq7e9I2XbLKJZj2Lri+vgQJXRa7ppaNkpyn7IaW53mi5Z0RgHMhzTXE= Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB1195.namprd12.prod.outlook.com (10.168.240.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2408.24; Tue, 5 Nov 2019 21:25:32 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::c5a3:6a2e:8699:1999]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::c5a3:6a2e:8699:1999%6]) with mapi id 15.20.2408.024; Tue, 5 Nov 2019 21:25:32 +0000 From: "Moger, Babu" To: "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "sean.j.christopherson@intel.com" , "vkuznets@redhat.com" , "wanpengli@tencent.com" , "jmattson@google.com" CC: "x86@kernel.org" , "joro@8bytes.org" , "Moger, Babu" , "luto@kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "nayna@linux.ibm.com" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "ebiederm@xmission.com" , "ricardo.neri-calderon@linux.intel.com" , "bshanks@codeweavers.com" Subject: [PATCH v3 1/2] x86/Kconfig: Rename UMIP config parameter Thread-Topic: [PATCH v3 1/2] x86/Kconfig: Rename UMIP config parameter Thread-Index: AQHVlB+O3ASEuWoCTkuU8z7yyrBiRA== Date: Tue, 5 Nov 2019 21:25:32 +0000 Message-ID: <157298912544.17462.2018334793891409521.stgit@naples-babu.amd.com> References: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> In-Reply-To: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN6PR04CA0059.namprd04.prod.outlook.com (2603:10b6:805:2a::36) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: f1b24793-9b72-4653-0924-08d76236b06a x-ms-traffictypediagnostic: DM5PR12MB1195: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; x-forefront-prvs: 0212BDE3BE x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(376002)(366004)(136003)(346002)(199004)(189003)(2201001)(54906003)(110136005)(8676002)(7416002)(103116003)(305945005)(81156014)(81166006)(66946007)(478600001)(25786009)(66556008)(64756008)(99286004)(66476007)(7736002)(316002)(26005)(2501003)(3846002)(102836004)(52116002)(6116002)(6436002)(6506007)(386003)(86362001)(66446008)(8936002)(2906002)(76176011)(14454004)(71200400001)(71190400001)(446003)(256004)(6512007)(476003)(486006)(186003)(4326008)(11346002)(14444005)(5660300002)(6486002)(66066001)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR12MB1195;H:DM5PR12MB2471.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: ClSbpkyoYOR8wv0hOslz+teUZvAaJ0bhbL1mAd/teMgxh4jPhn+muqf7IvBt/MB8AVjhZx/7rzk3wNBVTnvJcx8bnXzUSeoHRYB8kEMsMMWKEaFlLFv1ucYDavJZpBzcBxlzcYF4YrX6kSmAdCFWZo4P7laEebnnx4w5qwpB8rGQEI5zfJfbVRHAfZLxPWCVKDD/FybvamVJpoZMOuWgYnMWJU2W0ztnEy32wlQsm2ioMW0XexLak2Fq2g5L4He4YbQwvtNSntSkB5hUu2Yti+NlZuRecHm5ZSKIdoyRFWufqR5N+F1YQZmkh5lUNQgezlrofL/kOdiV4LwY0c/PHUOeCeOBkScZjlLo/2xaKovHR4FWL4B4+iS64xBRx8h0lLN9FckzjKypD6P4hhVEDtqnLNLuytDIWHlqgKjNC20yhrSrTvSaHLUV6CA2yhCO Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f1b24793-9b72-4653-0924-08d76236b06a X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2019 21:25:32.6178 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: e0feHaupNd+ZncqL/7giuXPSjEoF7LB9RTQgGcVk3ySvPm9S+mfW/oEfmg125hyN X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1195 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD 2nd generation EPYC processors support the UMIP (User-Mode Instruction Prevention) feature. So, rename X86_INTEL_UMIP to generic X86_UMIP and modify the text to cover both Intel and AMD. Signed-off-by: Babu Moger --- arch/x86/Kconfig | 10 +++++----- arch/x86/include/asm/disabled-features.h | 2 +- arch/x86/include/asm/umip.h | 4 ++-- arch/x86/kernel/Makefile | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d6e1faa28c58..b7fb285d7c0f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1880,13 +1880,13 @@ config X86_SMAP If unsure, say Y. -config X86_INTEL_UMIP +config X86_UMIP def_bool y - depends on CPU_SUP_INTEL - prompt "Intel User Mode Instruction Prevention" if EXPERT + depends on CPU_SUP_INTEL || CPU_SUP_AMD + prompt "User Mode Instruction Prevention" if EXPERT ---help--- - The User Mode Instruction Prevention (UMIP) is a security - feature in newer Intel processors. If enabled, a general + User Mode Instruction Prevention (UMIP) is a security + feature in newer x86 processors. If enabled, a general protection fault is issued if the SGDT, SLDT, SIDT, SMSW or STR instructions are executed in user mode. These instructions unnecessarily expose information about the hardware state. diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index a5ea841cc6d2..8e1d0bb46361 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -22,7 +22,7 @@ # define DISABLE_SMAP (1<<(X86_FEATURE_SMAP & 31)) #endif -#ifdef CONFIG_X86_INTEL_UMIP +#ifdef CONFIG_X86_UMIP # define DISABLE_UMIP 0 #else # define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) diff --git a/arch/x86/include/asm/umip.h b/arch/x86/include/asm/umip.h index db43f2a0d92c..aeed98c3c9e1 100644 --- a/arch/x86/include/asm/umip.h +++ b/arch/x86/include/asm/umip.h @@ -4,9 +4,9 @@ #include #include -#ifdef CONFIG_X86_INTEL_UMIP +#ifdef CONFIG_X86_UMIP bool fixup_umip_exception(struct pt_regs *regs); #else static inline bool fixup_umip_exception(struct pt_regs *regs) { return false; } -#endif /* CONFIG_X86_INTEL_UMIP */ +#endif /* CONFIG_X86_UMIP */ #endif /* _ASM_X86_UMIP_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 3578ad248bc9..52ce1e239525 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -134,7 +134,7 @@ obj-$(CONFIG_EFI) += sysfb_efi.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_TRACING) += tracepoint.o obj-$(CONFIG_SCHED_MC_PRIO) += itmt.o -obj-$(CONFIG_X86_INTEL_UMIP) += umip.o +obj-$(CONFIG_X86_UMIP) += umip.o obj-$(CONFIG_UNWINDER_ORC) += unwind_orc.o obj-$(CONFIG_UNWINDER_FRAME_POINTER) += unwind_frame.o From patchwork Tue Nov 5 21:25:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11228761 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5ACF7139A for ; Tue, 5 Nov 2019 21:26:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3745321A4A for ; Tue, 5 Nov 2019 21:26:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="PYifDBxB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730011AbfKEV0Y (ORCPT ); Tue, 5 Nov 2019 16:26:24 -0500 Received: from mail-eopbgr680062.outbound.protection.outlook.com ([40.107.68.62]:50242 "EHLO NAM04-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1730043AbfKEV0X (ORCPT ); Tue, 5 Nov 2019 16:26:23 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I9VPUSTXqT5SSZAdrG4Xv6H7wq5wwCgWhgQX+V7jUg2y9WAKMBu7ZW6cnnWi4+TXYoYaHBTeJ61OT2KAuMsbGAPtOiiHisxwY1gAct4KIDK5HNDllkw33cJAfTJH8reVTMzQPt3X5sMzAJYcUWtw8i/0EZPUG/MHNWcQ/Ras3bottNSogRCrChf8KWTB+sxBSvxcmoiqki44guIId8gLVnvZw6n5lYcnYQ6GXuHMoQKPpKgl/ZFJ0dJ6PFkqkKM2LO2Lic3aADVzZQRT8i7YO26VgvZaIOOl0F1V4mUwzUMnuE6xOloom6kaFdeugUT/FrKPNt8u6wmJ5JiKw9ZYfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MCF7XV2nMLJby4hgGhIpf8CSZOgeFjSmWD8Y3Du8mQo=; b=k7SJxh+CcetEEnerA8fkCTJ08d9ti0LCxRqbbaSD1CzQ40K+a1E6ljGdLplc18mJTC6k1WbMqAC+DcLzPQY+vzx9pxIl4z9cf+HaeKb6Vu0aRj+1+Ky4S/RjX70p7b4C0pQbJNhVjvAuWlDuA98SwqVH3Eg7fnJjWPMQrTLK+SWXN8zBwGxt2nLrOVtE/WFzqXGr0SqHmhd9U0Y6NGwVfAipW8oOb3D8MauExn1g3MeOLl16cjUL0PWdQdUZ6Op9Pjt8BSEaToM6EoB6afZin+U6Bo1Utkit9R7xm7qcXKbbRUhsoh53ip5wG9u05y95yzarAyaUaAzYU4DmaNF3zw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MCF7XV2nMLJby4hgGhIpf8CSZOgeFjSmWD8Y3Du8mQo=; b=PYifDBxBTnaYf8UYOSq4a+I6xwlOsgBjhgkSMYx87Iam9jjAnHNOOLv4LVOhbPykR4ToeoVTCNCeObjOwQpLW6SR72nZbk79cCmY3DY7scXtpIBuZv6COCQbc0ghPe5Rqm07WB52e4vE7YacUWIUr4m2druk/+3rXPmnWVYXdJk= Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB1195.namprd12.prod.outlook.com (10.168.240.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2408.24; Tue, 5 Nov 2019 21:25:40 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::c5a3:6a2e:8699:1999]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::c5a3:6a2e:8699:1999%6]) with mapi id 15.20.2408.024; Tue, 5 Nov 2019 21:25:40 +0000 From: "Moger, Babu" To: "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "sean.j.christopherson@intel.com" , "vkuznets@redhat.com" , "wanpengli@tencent.com" , "jmattson@google.com" CC: "x86@kernel.org" , "joro@8bytes.org" , "Moger, Babu" , "luto@kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "nayna@linux.ibm.com" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "zohar@linux.ibm.com" , "yamada.masahiro@socionext.com" , "ebiederm@xmission.com" , "ricardo.neri-calderon@linux.intel.com" , "bshanks@codeweavers.com" Subject: [PATCH v3 2/2] x86/umip: Update the comments to cover generic x86 processors Thread-Topic: [PATCH v3 2/2] x86/umip: Update the comments to cover generic x86 processors Thread-Index: AQHVlB+SCjh4NAufykaxQBgEbCDhKg== Date: Tue, 5 Nov 2019 21:25:40 +0000 Message-ID: <157298913784.17462.12654728938970637305.stgit@naples-babu.amd.com> References: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> In-Reply-To: <157298900783.17462.2778215498449243912.stgit@naples-babu.amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0401CA0011.namprd04.prod.outlook.com (2603:10b6:803:21::21) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Babu.Moger@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 509a3f88-56e2-475c-3961-08d76236b4db x-ms-traffictypediagnostic: DM5PR12MB1195: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; x-forefront-prvs: 0212BDE3BE x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(376002)(366004)(136003)(346002)(199004)(189003)(2201001)(54906003)(110136005)(8676002)(7416002)(103116003)(305945005)(81156014)(81166006)(66946007)(478600001)(25786009)(66556008)(64756008)(99286004)(66476007)(7736002)(316002)(26005)(2501003)(3846002)(102836004)(52116002)(6116002)(6436002)(6506007)(386003)(86362001)(66446008)(8936002)(15650500001)(2906002)(76176011)(14454004)(71200400001)(71190400001)(446003)(256004)(6512007)(476003)(486006)(186003)(4326008)(11346002)(14444005)(5660300002)(6486002)(66066001)(41533002)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR12MB1195;H:DM5PR12MB2471.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: I+u+d79jUFisN2RQFOBONPb3+T9DF/HJGCU0KUkn84+UGiI8j6nbJLT3LjsCda522JFnIggrELevJYXig61WV3vSWf7oAR6GqLr35OLoxZMzmwtrHwOcKcFOQJQBajeHaDvp+iMfqy2OC4/nzMr1eh8x8/qNDqpbcpF8leE/2O3A218gRXgnCfNTxy0XKC9RGJ+pJiozuEGFvM5o8SqAUWe7oPq2eDupLKPZIE3uvbhkImKTEKlobJom8ZC7B9+q1zzBJeSnHC624FanQg8fs/5z4lqbPFyEmfd5Xcxs3NmKOxzps/6LFLlkarPjmB5Ogaf3jcXSRGV0YHYu56NZZDT8blQu8Xbyf+OZ7+n9lbFiOvc4A1AV4GaVq01iLsaYaWBaK1WHJDBBwPRpK7VbbXJ/AUGSbn8u5eR6RUUd21k+eWJeodYdKFH98Fah76JL Content-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 509a3f88-56e2-475c-3961-08d76236b4db X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2019 21:25:40.0295 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Oo9pSPkhWyfKskTEFYlzYIpRvIPQqtAv+9AcKVJPEktNKSMRdG+y/v70S3S35o9F X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1195 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD 2nd generation EPYC processors also support UMIP feature. Update the comments to cover generic x86 processors. Signed-off-by: Babu Moger --- arch/x86/kernel/umip.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c index 548fefed71ee..8ccef6c495dc 100644 --- a/arch/x86/kernel/umip.c +++ b/arch/x86/kernel/umip.c @@ -1,6 +1,6 @@ /* - * umip.c Emulation for instruction protected by the Intel User-Mode - * Instruction Prevention feature + * umip.c Emulation for instruction protected by the User-Mode Instruction + * Prevention feature * * Copyright (c) 2017, Intel Corporation. * Ricardo Neri @@ -18,10 +18,10 @@ /** DOC: Emulation for User-Mode Instruction Prevention (UMIP) * - * The feature User-Mode Instruction Prevention present in recent Intel - * processor prevents a group of instructions (SGDT, SIDT, SLDT, SMSW and STR) - * from being executed with CPL > 0. Otherwise, a general protection fault is - * issued. + * User-Mode Instruction Prevention is a security feature present in recent + * x86 processors that, when enabled, prevents a group of instructions (SGDT, + * SIDT, SLDT, SMSW and STR) from being run in user mode by issuing a general + * protection fault if the instruction is executed with CPL > 0. * * Rather than relaying to the user space the general protection fault caused by * the UMIP-protected instructions (in the form of a SIGSEGV signal), it can be