From patchwork Mon Sep 17 19:07:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 10603293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 301C014DA for ; Mon, 17 Sep 2018 19:07:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 242F12948D for ; Mon, 17 Sep 2018 19:07:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1880729725; Mon, 17 Sep 2018 19:07:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI, USER_IN_DEF_DKIM_WL autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2F392948D for ; Mon, 17 Sep 2018 19:07:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728354AbeIRAgQ (ORCPT ); Mon, 17 Sep 2018 20:36:16 -0400 Received: from mail-io1-f74.google.com ([209.85.166.74]:55771 "EHLO mail-io1-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728317AbeIRAgQ (ORCPT ); Mon, 17 Sep 2018 20:36:16 -0400 Received: by mail-io1-f74.google.com with SMTP id m15-v6so19351341ioj.22 for ; Mon, 17 Sep 2018 12:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:message-id:mime-version:subject:from:to:cc; bh=qllcHIYXBqiYBg4I7sVPAG+SLUtsBCRp7wSplP92U3s=; b=ZlpHcUT4Iw2w63Yr5toALonmGvJaYFOsG7CmCSz8PQOgNZK4qIYxKzsAZ4mCCWmFq6 WBOvE2e0av3ro6CqJcSXKRNv3i54E8Hpu43I1WB9MRAwhmSpcjoJ1bDTREREJpD8g7Pr u6ZhQOilRBJc1RqaF9cYpfLELegviULMNhLmEVOLmFb1dbMgnBeKz8ufVCMm/p1ppWtJ QlLCdI0k0QUPx0VcXLCQNv39xdce1DOVeLdXYoM2JlF5T2UbtcIbfjAtEdXwkoJufPru mk2MAcElUcIVkc8wgnUb91FFIKtFmQnAEasG/Mj4NfITqZe1MGH3NqlwTIlwXhYNce3e YDgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=qllcHIYXBqiYBg4I7sVPAG+SLUtsBCRp7wSplP92U3s=; b=O4K1H4r6/ii3SWup8yuKb2WYX2TY5hkBraSm8oBrDIYsyIZZOZT6Vl7lk8zOiVK2OE IfUBIw/WfMUnPpOqdf9h6R57xVpJzIbGsG9qD+wdtSa/BvHBdQ0tvscqXIkH+E4Cr1ZO FI4Xo3wWksVlq7h8Xgxd5KzIvgRJvDuF62qv8vSkpxG15hq7xMqIof+FqS6KO3QsiQL2 cv75svWn7uEmQRv9uVhzGEB3rKZnzRS3l40YhnlmxWTRIdANKGzdDEracX6JbXM9n8t5 CIzOXpl5cgziIARuiq8932v7hn3WlzDJvKlgpwO8hEHRjLiP2EHms9KA5aGxGm+RVl+k uW/A== X-Gm-Message-State: APzg51A7lxPqm9vX7ZEFjx5B7IT7ObjaPe/F1Ia/zdG+u5C6CYt+zm4P u9L9+Ej/yyUf3EvWb69/0+mvqDLBID5xfup3eFXaqg1TjqJoc0hFXy3kcIL103X69jeSDMLAuPO 6d8+wjAw59qdqMmsr/d2nISPOlJc20gdxGrXk7g614uB8//hQOo4tNA5Ttm6ZKg4= X-Google-Smtp-Source: ANB0VdYqyGnKl6zmS94RNBaBJAnbUk558LL023+TukHh32Ah0HBOVEVPjfIPwED80hdgzesoVu82B+iHRS6NSw== X-Received: by 2002:a24:552:: with SMTP id 79-v6mr12154654itl.16.1537211255783; Mon, 17 Sep 2018 12:07:35 -0700 (PDT) Date: Mon, 17 Sep 2018 12:07:20 -0700 Message-Id: <20180917190720.156906-1-jmattson@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.19.0.397.gdd90340f6a-goog Subject: [PATCH] KVM: nVMX: L0 should emulate instructions for L2 From: Jim Mattson To: kvm@vger.kernel.org Cc: Jim Mattson Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When L0 enumerates support for an instruction not supported by the physical CPU, it must emulate that instruction for L2 as well as for L1. Take MOVBE, for example. If hardware reports that CPUID.1:ECX.MOVBE[bit 22] is clear, but L0 sets the bit when emulating CPUID for L1, then L0 is obligated to intercept #UD and emulate the MOVBE instruction for L1. Furthermore, L0 is also obligated to intercept #UD and emulate the MOVBE instruction for L2. Even if L1 chooses to intercept #UD, L0 must be prepared to decode the instruction and emulate MOVBE before deciding to reflect the #UD VM-exit to L1. Rewriting the wrong hypercall instruction with the correct hypercall instruction is not as clear-cut. One could argue that this is a property of a kvm virtual CPU, and that L0 should always do it. However, to avoid surprises, I've preserved the existing behavior (right or wrong). Signed-off-by: Jim Mattson --- arch/x86/kvm/vmx.c | 2 ++ arch/x86/kvm/x86.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 533a327372c8..c9d8ab3ce56e 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -9649,6 +9649,8 @@ static bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason) else if (is_breakpoint(intr_info) && vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) return false; + else if (is_invalid_opcode(intr_info)) + return false; return vmcs12->exception_bitmap & (1u << (intr_info & INTR_INFO_VECTOR_MASK)); case EXIT_REASON_EXTERNAL_INTERRUPT: diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 542f6315444d..212067531050 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6876,6 +6876,12 @@ static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) char instruction[3]; unsigned long rip = kvm_rip_read(vcpu); + if (is_guest_mode(vcpu)) { + ctxt->exception.vector = UD_VECTOR; + ctxt->exception.error_code_valid = false; + return X86EMUL_PROPAGATE_FAULT; + } + kvm_x86_ops->patch_hypercall(vcpu, instruction); return emulator_write_emulated(ctxt, rip, instruction, 3,