From patchwork Wed Nov 6 21:45:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Saenz Julienne X-Patchwork-Id: 11231205 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 404B41986 for ; Wed, 6 Nov 2019 21:46:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A427217D7 for ; Wed, 6 Nov 2019 21:46:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="UBVBPE0x" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A427217D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2T3cYqtRwlvgYC8Jx6KKmSGTBeCD8D5C5HP1YbaegXo=; b=UBVBPE0xz8q+th Cv8ZF5S+lSzqBcn3SEk0lO1fL77Msg4wlP6LiC2jHv1cBApjb0Gjp/9q+JgwlnVtwKDJGp30Bh57g nezJ+HWCyAkFU0GfM1RLeneTIuADb5phoSi2mdR9L3sEdRJP/lYnLoGdTDy6niDpvgq6vicuZNzmG +5WZelBrOs7JabDn3UaAf91EeYq0a/E+lUVcwrksGGo/iqL2xs3Ass6uqTWfyt6NltY/4n6f4qtbO W365Lreo2WMvqjSSNgp+TgW5jekFYXzrfOXQqi4l/z2mFrPBjzn6I4uYEFaBd9Sn7bpZrljDQA/6b 9sU80OAPAS2DS5280VQw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST7r-0005ZK-0s; Wed, 06 Nov 2019 21:46:03 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST7c-0005MT-4u; Wed, 06 Nov 2019 21:45:50 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id CC0CCAE35; Wed, 6 Nov 2019 21:45:46 +0000 (UTC) From: Nicolas Saenz Julienne To: Andrew Murray , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Bjorn Helgaas Subject: [PATCH 1/4] dt-bindings: pci: add bindings for brcmstb's PCIe device Date: Wed, 6 Nov 2019 22:45:23 +0100 Message-Id: <20191106214527.18736-2-nsaenzjulienne@suse.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106214527.18736-1-nsaenzjulienne@suse.de> References: <20191106214527.18736-1-nsaenzjulienne@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_134548_475350_54673225 X-CRM114-Status: GOOD ( 13.09 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , f.fainelli@gmail.com, phil@raspberrypi.org, linux-kernel@vger.kernel.org, Rob Herring , mbrugger@suse.com, wahrenst@gmx.net, james.quinlan@broadcom.com, Nicolas Saenz Julienne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jim Quinlan The DT bindings description of the brcmstb PCIe device is described. This node can only be used for now on the Raspberry Pi 4. This was based on Jim's original submission[1], converted to yaml and adapted to the RPi4 case. [1] https://patchwork.kernel.org/patch/10605937/ Signed-off-by: Jim Quinlan Co-developed-by: Nicolas Saenz Julienne Signed-off-by: Nicolas Saenz Julienne --- .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml new file mode 100644 index 000000000000..0b81c26f8568 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Brcmstb PCIe Host Controller Device Tree Bindings + +maintainers: + - Nicolas Saenz Julienne + +properties: + compatible: + const: brcm,bcm2711-pcie # The Raspberry Pi 4 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: PCIe host controller + - description: builtin MSI controller + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + - const: pcie + - const: msi + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: true + + interrupt-map: true + + ranges: true + + dma-ranges: true + + clocks: + maxItems: 1 + + clock-names: + items: + - const: sw_pcie + + msi-controller: + description: Identifies the node as an MSI controller. + type: boolean + + msi-parent: + description: MSI controller the device is capable of using. + $ref: /schemas/types.yaml#/definitions/phandle + + linux,pci-domain: + description: PCI domain ID. Should be unique for each host controller. + $ref: /schemas/types.yaml#/definitions/uint32 + + brcm,enable-ssc: + description: Indicates usage of spread-spectrum clocking. + type: boolean + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - ranges + - dma-ranges + - linux,pci-domain + +additionalProperties: false + +examples: + - | + #include + #include + + scb { + #address-cells = <2>; + #size-cells = <1>; + pcie0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&pcie0>; + msi-controller; + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + linux,pci-domain = <0>; + brcm,enable-ssc; + }; + }; From patchwork Wed Nov 6 21:45:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Saenz Julienne X-Patchwork-Id: 11231209 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62A8F13BD for ; Wed, 6 Nov 2019 21:46:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3EB48217D7 for ; Wed, 6 Nov 2019 21:46:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FPeYj5js" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3EB48217D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HP8zLdJ2z6m6/B+DWbXUk+LkE6TMyThJl79I/HhBJ8g=; b=FPeYj5jsfazvwa dbinW8o2DiJniK1SoSGY9jZDQwTBbKJTAmtNrplRRseSseyFGzP8mXGG/k8JiT+ndhsq3X74+oaNz xrg05JTd1Glp9tfJS5KPB6G6Dh6ND10S8drkhmtofp+VoHCdoiZjMJJ12/i2EY3JANv7bPljk2zOJ TApOsoGQtMZ3CV8MbBa7mNGfFPYxtx9C2+0xLcl5zTJ8pDVRPL2rWf0NuoBph1jYabVaK6LDZ9vPL YgPGAaS49jbmx8IKlD5WknjOpAP2YJdvEjSlpFYAarep/K4U6XcV2me5dD8olO5m19qQqNOZzzSs/ ZTlOn1xRy+6BFGV5+bgw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST82-0005rN-Gx; Wed, 06 Nov 2019 21:46:14 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST7e-0005NN-4n; Wed, 06 Nov 2019 21:45:51 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id D2C5EB3F6; Wed, 6 Nov 2019 21:45:48 +0000 (UTC) From: Nicolas Saenz Julienne To: Andrew Murray , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland , Eric Anholt , Stefan Wahren Subject: [PATCH 2/4] ARM: dts: bcm2711: Enable PCIe controller Date: Wed, 6 Nov 2019 22:45:24 +0100 Message-Id: <20191106214527.18736-3-nsaenzjulienne@suse.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106214527.18736-1-nsaenzjulienne@suse.de> References: <20191106214527.18736-1-nsaenzjulienne@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_134550_347750_F42ED7DA X-CRM114-Status: GOOD ( 12.02 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f.fainelli@gmail.com, phil@raspberrypi.org, linux-kernel@vger.kernel.org, mbrugger@suse.com, james.quinlan@broadcom.com, Nicolas Saenz Julienne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies XHCI USB 3.0 controller. Signed-off-by: Nicolas Saenz Julienne --- arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index a9d84e28f245..c7b2e7b57da6 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -288,6 +288,53 @@ arm,cpu-registers-not-fw-configured; }; + scb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, + <0x6 0x00000000 0x6 0x00000000 0x40000000>; + + pcie_0: pcie@7d500000 { + compatible = "brcm,bcm2711-pcie"; + reg = <0x0 0x7d500000 0x9310>; + msi-controller; + msi-parent = <&pcie_0>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + linux,pci-domain = <0>; + brcm,enable-ssc; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gicv2 GIC_SPI 144 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gicv2 GIC_SPI 145 + IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gicv2 GIC_SPI 146 + IRQ_TYPE_LEVEL_HIGH>; + + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 + 0x0 0x04000000>; + /* + * The wrapper around the PCIe block has a bug + * preventing it from accessing beyond the first 3GB of + * memory. As the bus DMA mask is rounded up to the + * closest power of two of the dma-range size, we're + * forced to set the limit at 2GB. This can be + * harmlessly changed in the future once the DMA code + * handles non power of two DMA limits. + */ + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 + 0x0 0x80000000>; + }; + }; + cpus: cpus { #address-cells = <1>; #size-cells = <0>; From patchwork Wed Nov 6 21:45:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Saenz Julienne X-Patchwork-Id: 11231211 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EB8713BD for ; Wed, 6 Nov 2019 21:46:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5E554217D7 for ; Wed, 6 Nov 2019 21:46:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="diZlsov7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5E554217D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tOpF6qEuF18Oovp0k1X9hKNcj3bsW/9R+K3a3uEkC1E=; b=diZlsov7Rh7HOg FcWok55jeWA1pZMjOeKLPkaDyiwVil9g/W5mslVOtGiihiulePzLmjBJsZT2etNncRhCVpXRKPWlD 5R7mSxZoti2NugIwsC7N4gbrL58AzySy9soDBFciK/1LZ/N3TcwS7Q4AZ8SxPo4G724+2Y1DSsald IFXJwjHpaRZLb1N9MwfzKS4pBz1rjLXUVlDoe2rBkwJEzspS0mr1sG1aqz9TPjiF2DK8j3kkhPw5B PUpkAkEr21VFGh+jlsJIo7eAQMNNSiAr6F3zM3VQ20lTpWcncNRJx32UZyk7ca8CJb2WQan9tAh49 0D6l3szorbkJVUV3ivJw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST8E-00065b-Kr; Wed, 06 Nov 2019 21:46:26 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST7f-0005OT-9X; Wed, 06 Nov 2019 21:45:55 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id F27A4AED5; Wed, 6 Nov 2019 21:45:49 +0000 (UTC) From: Nicolas Saenz Julienne To: Andrew Murray , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Florian Fainelli Subject: [PATCH 3/4] PCI: brcmstb: add Broadcom STB PCIe host controller driver Date: Wed, 6 Nov 2019 22:45:25 +0100 Message-Id: <20191106214527.18736-4-nsaenzjulienne@suse.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106214527.18736-1-nsaenzjulienne@suse.de> References: <20191106214527.18736-1-nsaenzjulienne@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_134551_649270_25D49653 X-CRM114-Status: GOOD ( 22.07 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mbrugger@suse.com, phil@raspberrypi.org, linux-kernel@vger.kernel.org, wahrenst@gmx.net, james.quinlan@broadcom.com, Bjorn Helgaas , Nicolas Saenz Julienne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jim Quinlan This commit adds the basic Broadcom STB PCIe controller. Missing is the ability to process MSI. This functionality is added in a subsequent commit. The PCIe block contains an MDIO interface. This is a local interface only accessible by the PCIe controller. It cannot be used or shared by any other HW. As such, the small amount of code for this controller is included in this driver as there is little upside to put it elsewhere. This is based on Jim's original submission[1] but adapted and tailored specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for the rest of the brcmstb family will soon follow once we get support for multiple dma-ranges in dma/direct. [1] https://patchwork.kernel.org/patch/10605959/ Signed-off-by: Jim Quinlan Co-developed-by: Nicolas Saenz Julienne Signed-off-by: Nicolas Saenz Julienne --- drivers/pci/controller/Kconfig | 12 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++ 3 files changed, 986 insertions(+) create mode 100644 drivers/pci/controller/pcie-brcmstb.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index f5de9119e8d3..8b3aae91d8af 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -281,6 +281,18 @@ config VMD To compile this driver as a module, choose M here: the module will be called vmd. +config PCIE_BRCMSTB + bool "Broadcom Brcmstb PCIe host controller" + depends on ARCH_BRCMSTB || BMIPS_GENERIC + depends on OF + depends on SOC_BRCMSTB + default ARCH_BRCMSTB || BMIPS_GENERIC + help + Say Y here to enable PCIe host controller support for + Broadcom Settop Box SOCs. A Broadcom SOC will may have + multiple host controllers as opposed to a single host + controller with multiple ports. + config PCI_HYPERV_INTERFACE tristate "Hyper-V PCI Interface" depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64 diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index a2a22c9d91af..3fc0b0cf5b5b 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c new file mode 100644 index 000000000000..880ec11d06a1 --- /dev/null +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -0,0 +1,973 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2009 - 2019 Broadcom */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ +#define BRCM_PCIE_CAP_REGS 0x00ac + +/* + * Broadcom Settop Box PCIe Register Offsets. The names are from + * the chip's RDB and we use them here so that a script can correlate + * this code and the RDB to prevent discrepancies. + */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c +#define PCIE_RC_DL_MDIO_ADDR 0x1100 +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 +#define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c +#define PCIE_MISC_PCIE_CTRL 0x4064 +#define PCIE_MISC_PCIE_STATUS 0x4068 +#define PCIE_MISC_REVISION 0x406c +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 +#define PCIE_INTR2_CPU_BASE 0x4300 + +/* + * Broadcom Settop Box PCIe Register Field shift and mask info. The + * names are from the chip's RDB and we use them here so that a script + * can correlate this code and the RDB to prevent discrepancies. + */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2 +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000 +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16 +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0 +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0 +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0 +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2 +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6 +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0 + +#define BRCM_NUM_PCIE_OUT_WINS 0x4 +#define BRCM_MAX_SCB 0x4 + +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL + +#define BURST_SIZE_128 0 +#define BURST_SIZE_256 1 +#define BURST_SIZE_512 2 + +/* Offsets from PCIE_INTR2_CPU_BASE */ +#define STATUS 0x0 +#define SET 0x4 +#define CLR 0x8 +#define MASK_STATUS 0xc +#define MASK_SET 0x10 +#define MASK_CLR 0x14 + +#define PCIE_BUSNUM_SHIFT 20 +#define PCIE_SLOT_SHIFT 15 +#define PCIE_FUNC_SHIFT 12 + +#if defined(__BIG_ENDIAN) +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */ +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */ +#else +#define DATA_ENDIAN 0 +#define MMIO_ENDIAN 0 +#endif + +#define MDIO_PORT0 0x0 +#define MDIO_DATA_MASK 0x7fffffff +#define MDIO_DATA_SHIFT 0x0 +#define MDIO_PORT_MASK 0xf0000 +#define MDIO_PORT_SHIFT 0x16 +#define MDIO_REGAD_MASK 0xffff +#define MDIO_REGAD_SHIFT 0x0 +#define MDIO_CMD_MASK 0xfff00000 +#define MDIO_CMD_SHIFT 0x14 +#define MDIO_CMD_READ 0x1 +#define MDIO_CMD_WRITE 0x0 +#define MDIO_DATA_DONE_MASK 0x80000000 +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) +#define SSC_REGS_ADDR 0x1100 +#define SET_ADDR_OFFSET 0x1f +#define SSC_CNTL_OFFSET 0x2 +#define SSC_CNTL_OVRD_EN_MASK 0x8000 +#define SSC_CNTL_OVRD_EN_SHIFT 0xf +#define SSC_CNTL_OVRD_VAL_MASK 0x4000 +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe +#define SSC_STATUS_OFFSET 0x1 +#define SSC_STATUS_SSC_MASK 0x400 +#define SSC_STATUS_SSC_SHIFT 0xa +#define SSC_STATUS_PLL_LOCK_MASK 0x800 +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb + +#define IDX_ADDR(pcie) \ + ((pcie)->reg_offsets[EXT_CFG_INDEX]) +#define DATA_ADDR(pcie) \ + ((pcie)->reg_offsets[EXT_CFG_DATA]) +#define PCIE_RGR1_SW_INIT_1(pcie) \ + ((pcie)->reg_offsets[RGR1_SW_INIT_1]) + +enum { + RGR1_SW_INIT_1, + EXT_CFG_INDEX, + EXT_CFG_DATA, +}; + +enum { + RGR1_SW_INIT_1_INIT_MASK, + RGR1_SW_INIT_1_INIT_SHIFT, + RGR1_SW_INIT_1_PERST_MASK, + RGR1_SW_INIT_1_PERST_SHIFT, +}; + +enum pcie_type { + BCM2711, +}; + +struct brcm_window { + dma_addr_t pcie_addr; + phys_addr_t cpu_addr; + dma_addr_t size; +}; + +/* Internal PCIe Host Controller Information.*/ +struct brcm_pcie { + struct device *dev; + void __iomem *base; + int irq; + struct clk *clk; + struct pci_bus *root_bus; + struct device_node *dn; + int id; + bool suspended; + bool ssc; + int gen; + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS]; + unsigned int rev; + const int *reg_offsets; + const int *reg_field_info; + enum pcie_type type; +}; + +struct pcie_cfg_data { + const int *reg_field_info; + const int *offsets; + const enum pcie_type type; +}; + +static const int pcie_reg_field_info[] = { + [RGR1_SW_INIT_1_INIT_MASK] = 0x2, + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1, +}; + +static const int pcie_offset_bcm2711[] = { + [RGR1_SW_INIT_1] = 0x9210, + [EXT_CFG_INDEX] = 0x9000, + [EXT_CFG_DATA] = 0x8000, +}; + +static const struct pcie_cfg_data bcm2711_cfg = { + .reg_field_info = pcie_reg_field_info, + .offsets = pcie_offset_bcm2711, + .type = BCM2711, +}; + +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, + int where); + +static struct pci_ops brcm_pcie_ops = { + .map_bus = brcm_pcie_map_conf, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +#define bcm_readl(a) readl(a) +#define bcm_writel(d, a) writel(d, a) +#define bcm_readw(a) readw(a) +#define bcm_writew(d, a) writew(d, a) + +/* These macros extract/insert fields to host controller's register set. */ +#define RD_FLD(base, reg, field) \ + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT) +#define WR_FLD(base, reg, field, val) \ + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val) +#define WR_FLD_RB(base, reg, field, val) \ + wr_fld_rb((base) + reg, reg##_##field##_MASK, \ + reg##_##field##_SHIFT, val) +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \ + wr_fld((base) + reg + (off), reg##_##field##_MASK, \ + reg##_##field##_SHIFT, val) +#define EXTRACT_FIELD(val, reg, field) \ + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT) +#define INSERT_FIELD(val, reg, field, field_val) \ + (((val) & ~reg##_##field##_MASK) | \ + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT))) + +static u32 rd_fld(void __iomem *p, u32 mask, int shift) +{ + return (bcm_readl(p) & mask) >> shift; +} + +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val) +{ + u32 reg = bcm_readl(p); + + reg = (reg & ~mask) | ((val << shift) & mask); + bcm_writel(reg, p); +} + +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val) +{ + wr_fld(p, mask, shift, val); + (void)bcm_readl(p); +} + +static const char *link_speed_to_str(int s) +{ + switch (s) { + case 1: + return "2.5"; + case 2: + return "5.0"; + case 3: + return "8.0"; + default: + break; + } + return "???"; +} + +/* + * The roundup_pow_of_two() from log2.h invokes + * __roundup_pow_of_two(unsigned long), but we really need a + * such a function to take a native u64 since unsigned long + * is 32 bits on some configurations. So we provide this helper + * function below. + */ +static u64 roundup_pow_of_two_64(u64 n) +{ + return 1ULL << fls64(n - 1); +} + +/* + * This is to convert the size of the inbound "BAR" region to the + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE + */ +int encode_ibar_size(u64 size) +{ + int log2_in = ilog2(size); + + if (log2_in >= 12 && log2_in <= 15) + /* Covers 4KB to 32KB (inclusive) */ + return (log2_in - 12) + 0x1c; + else if (log2_in >= 16 && log2_in <= 37) + /* Covers 64KB to 32GB, (inclusive) */ + return log2_in - 15; + /* Something is awry so disable */ + return 0; +} + +static u32 mdio_form_pkt(int port, int regad, int cmd) +{ + u32 pkt = 0; + + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK; + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK; + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK; + + return pkt; +} + +/* negative return value indicates error */ +static int mdio_read(void __iomem *base, u8 port, u8 regad) +{ + int tries; + u32 data; + + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ), + base + PCIE_RC_DL_MDIO_ADDR); + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR); + + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA); + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { + udelay(10); + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA); + } + + return MDIO_RD_DONE(data) + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT + : -EIO; +} + +/* negative return value indicates error */ +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata) +{ + int tries; + u32 data; + + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE), + base + PCIE_RC_DL_MDIO_ADDR); + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR); + bcm_writel(MDIO_DATA_DONE_MASK | wrdata, + base + PCIE_RC_DL_MDIO_WR_DATA); + + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA); + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { + udelay(10); + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA); + } + + return MDIO_WT_DONE(data) ? 0 : -EIO; +} + +/* + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative + * return value indicates error. + */ +static int set_ssc(void __iomem *base) +{ + int tmp; + u16 wrdata; + int pll, ssc; + + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR); + if (tmp < 0) + return tmp; + + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET); + if (tmp < 0) + return tmp; + + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1); + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1); + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata); + if (tmp < 0) + return tmp; + + usleep_range(1000, 2000); + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET); + if (tmp < 0) + return tmp; + + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC); + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK); + + return (ssc && pll) ? 0 : -EIO; +} + +/* Limits operation to a specific generation (1, 2, or 3) */ +static void set_gen(void __iomem *base, int gen) +{ + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); + + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); + + lnkctl2 = (lnkctl2 & ~0xf) | gen; + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); +} + +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + unsigned int win, phys_addr_t cpu_addr, + dma_addr_t pcie_addr, dma_addr_t size) +{ + void __iomem *base = pcie->base; + phys_addr_t cpu_addr_mb, limit_addr_mb; + u32 tmp; + + /* Set the base of the pcie_addr window */ + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN, + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8)); + bcm_writel(upper_32_bits(pcie_addr), + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8)); + + cpu_addr_mb = cpu_addr >> 20; + limit_addr_mb = (cpu_addr + size - 1) >> 20; + + /* Write the addr base low register */ + WR_FLD_WITH_OFFSET(base, (win * 4), + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT, + BASE, cpu_addr_mb); + /* Write the addr limit low register */ + WR_FLD_WITH_OFFSET(base, (win * 4), + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT, + LIMIT, limit_addr_mb); + + /* Write the cpu addr high register */ + tmp = (u32)(cpu_addr_mb >> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS); + WR_FLD_WITH_OFFSET(base, (win * 8), + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI, + BASE, tmp); + /* Write the cpu limit high register */ + tmp = (u32)(limit_addr_mb >> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS); + WR_FLD_WITH_OFFSET(base, (win * 8), + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI, + LIMIT, tmp); +} + +/* Configuration space read/write support */ +static int cfg_index(int busnr, int devfn, int reg) +{ + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT) + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT) + | (busnr << PCIE_BUSNUM_SHIFT) + | (reg & ~3); +} + +/* The controller is capable of serving in both RC and EP roles */ +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS); + + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT); +} + +static bool brcm_pcie_link_up(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS); + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE); + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP); + + return (dla && plu) ? true : false; +} + +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct brcm_pcie *pcie = bus->sysdata; + void __iomem *base = pcie->base; + int idx; + + /* Accesses to the RC go right to the RC registers if slot==0 */ + if (pci_is_root_bus(bus)) + return PCI_SLOT(devfn) ? NULL : base + where; + + /* For devices, write to the config space index register */ + idx = cfg_index(bus->number, devfn, 0); + bcm_writel(idx, pcie->base + IDX_ADDR(pcie)); + return base + DATA_ADDR(pcie) + where; +} + +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, + unsigned int val) +{ + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT]; + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK]; + + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val); +} + +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, + unsigned int val) +{ + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), + PCIE_RGR1_SW_INIT_1_PERST_MASK, + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val); +} + +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, + u64 *rc_bar2_size, + u64 *rc_bar2_offset) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + struct device *dev = pcie->dev; + struct resource_entry *entry; + u64 total_mem_size = 0; + + *rc_bar2_offset = -1; + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + /* + * We're promissed the RC will provide a contiguous view of + * memory to downstream devices. We can then infer the + * rc_bar2_offset from the lower avaiable dma-range offset. + */ + if (entry->offset < *rc_bar2_offset) + *rc_bar2_offset = entry->offset; + + total_mem_size += entry->res->end - entry->res->start + 1; + } + + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size); + + /* + * Validate the results: + * + * The PCIe host controller by design must set the inbound viewport to + * be a contiguous arrangement of all of the system's memory. In + * addition, its size mut be a power of two. To further complicate + * matters, the viewport must start on a pcie-address that is aligned + * on a multiple of its size. If a portion of the viewport does not + * represent system memory -- e.g. 3GB of memory requires a 4GB + * viewport -- we can map the outbound memory in or after 3GB and even + * though the viewport will overlap the outbound memory the controller + * will know to send outbound memory downstream and everything else + * upstream. + * + * For example: + * + * - The best-case scenario, memory up to 3GB, is to place the inbound + * region in the first 4GB of pcie-space, as some legacy devices can + * only address 32bits. We would also like to put the MSI under 4GB + * as well, since some devices require a 32bit MSI target address. + * + * - If the system memory is 4GB or larger we cannot start the inbound + * region at location 0 (since we have to allow some space for + * outbound memory @ 3GB). So instead it will start at the 1x + * multiple of its size + */ + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size || + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) { + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", + *rc_bar2_size, *rc_bar2_offset); + return -EINVAL; + } + + return 0; +} + +static int brcm_pcie_setup(struct brcm_pcie *pcie) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + u64 rc_bar2_offset, rc_bar2_size; + void __iomem *base = pcie->base; + struct resource_entry *entry; + unsigned int scb_size_val; + struct resource *res; + int num_out_wins = 0; + u32 tmp; + int i, j, ret, limit; + u16 nlw, cls, lnksta; + bool ssc_good = false; + struct device *dev = pcie->dev; + + /* Reset the bridge */ + brcm_pcie_bridge_sw_init_set(pcie, 1); + + usleep_range(100, 200); + + /* Take the bridge out of reset */ + brcm_pcie_bridge_sw_init_set(pcie, 0); + + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0); + /* Wait for SerDes to be stable */ + usleep_range(100, 200); + + /* Grab the PCIe hw revision number */ + tmp = bcm_readl(base + PCIE_MISC_REVISION); + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN); + + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1); + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1); + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, + BURST_SIZE_128); + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL); + + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, + &rc_bar2_offset); + if (ret) + return ret; + + tmp = lower_32_bits(rc_bar2_offset); + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE, + encode_ibar_size(rc_bar2_size)); + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); + bcm_writel(upper_32_bits(rc_bar2_offset), + base + PCIE_MISC_RC_BAR2_CONFIG_HI); + + scb_size_val = rc_bar2_size ? + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val); + + /* disable the PCIe->GISB memory window (RC_BAR1) */ + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0); + + /* disable the PCIe->SCB memory window (RC_BAR3) */ + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0); + + if (!pcie->suspended) { + /* clear any interrupts we find on boot */ + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR); + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR); + } + + /* Mask all interrupts since we are not handling any yet */ + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET); + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET); + + if (pcie->gen) + set_gen(base, pcie->gen); + + /* Unassert the fundamental reset */ + brcm_pcie_perst_set(pcie, 0); + + /* + * Give the RC/EP time to wake up, before trying to configure RC. + * Intermittently check status for link-up, up to a total of 100ms + * when we don't know if the device is there, and up to 1000ms if + * we do know the device is there. + */ + limit = pcie->suspended ? 1000 : 100; + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie); + j += i, i = i * 2) + msleep(i + j > limit ? limit - j : i); + + if (!brcm_pcie_link_up(pcie)) { + dev_info(dev, "link down\n"); + return -ENODEV; + } + + if (!brcm_pcie_rc_mode(pcie)) { + dev_err(dev, "PCIe misconfigured; is in EP mode\n"); + return -EINVAL; + } + + resource_list_for_each_entry(entry, &bridge->windows) { + res = entry->res; + + if (resource_type(res) != IORESOURCE_MEM) + continue; + + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) { + dev_err(pcie->dev, "too many outbound wins\n"); + return -EINVAL; + } + + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, + res->start - entry->offset, + res->end - res->start + 1); + num_out_wins++; + } + + /* + * For config space accesses on the RC, show the right class for + * a PCIe-PCIe bridge (the default setting is to be EP mode). + */ + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400); + + if (pcie->ssc) { + ret = set_ssc(base); + if (ret == 0) + ssc_good = true; + else + dev_err(dev, "failed attempt to enter ssc mode\n"); + } + + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); + cls = lnksta & PCI_EXP_LNKSTA_CLS; + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls), + nlw, ssc_good ? "(SSC)" : "(!SSC)"); + + /* PCIe->SCB endian mode for BAR */ + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */ + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, + ENDIAN_MODE_BAR2, DATA_ENDIAN); + + /* + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. + */ + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1); + + return 0; +} + +/* L23 is a low-power PCIe link state */ +static void enter_l23(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + int l23, i; + + /* assert request for L23 */ + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1); + + /* Wait up to 30 msec for L23 */ + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23); + for (i = 0; i < 15 && !l23; i++) { + usleep_range(2000, 2400); + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23); + } + + if (!l23) + dev_err(pcie->dev, "failed to enter L23\n"); +} + +static void turn_off(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + + if (brcm_pcie_link_up(pcie)) + enter_l23(pcie); + /* Assert fundamental reset */ + brcm_pcie_perst_set(pcie, 1); + /* Deassert request for L23 in case it was asserted */ + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0); + /* Turn off SerDes */ + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1); + /* Shutdown PCIe bridge */ + brcm_pcie_bridge_sw_init_set(pcie, 1); +} + +static int brcm_pcie_suspend(struct device *dev) +{ + struct brcm_pcie *pcie = dev_get_drvdata(dev); + + turn_off(pcie); + clk_disable_unprepare(pcie->clk); + pcie->suspended = true; + + return 0; +} + +static int brcm_pcie_resume(struct device *dev) +{ + struct brcm_pcie *pcie = dev_get_drvdata(dev); + void __iomem *base; + int ret; + + base = pcie->base; + clk_prepare_enable(pcie->clk); + + /* Take bridge out of reset so we can access the SerDes reg */ + brcm_pcie_bridge_sw_init_set(pcie, 0); + + /* Turn on SerDes */ + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0); + /* Wait for SerDes to be stable */ + usleep_range(100, 200); + + ret = brcm_pcie_setup(pcie); + if (ret) + return ret; + + pcie->suspended = false; + + return 0; +} + +static void _brcm_pcie_remove(struct brcm_pcie *pcie) +{ + turn_off(pcie); + clk_disable_unprepare(pcie->clk); + clk_put(pcie->clk); +} + +static int brcm_pcie_remove(struct platform_device *pdev) +{ + struct brcm_pcie *pcie = platform_get_drvdata(pdev); + + pci_stop_root_bus(pcie->root_bus); + pci_remove_root_bus(pcie->root_bus); + _brcm_pcie_remove(pcie); + + return 0; +} + +static const struct of_device_id brcm_pcie_match[] = { + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, + {}, +}; +MODULE_DEVICE_TABLE(of, brcm_pcie_match); + +static int brcm_pcie_probe(struct platform_device *pdev) +{ + struct device_node *dn = pdev->dev.of_node; + const struct of_device_id *of_id; + const struct pcie_cfg_data *data; + struct resource *res; + int ret; + struct brcm_pcie *pcie; + void __iomem *base; + struct pci_host_bridge *bridge; + struct pci_bus *child; + + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); + if (!bridge) + return -ENOMEM; + + pcie = pci_host_bridge_priv(bridge); + + of_id = of_match_node(brcm_pcie_match, dn); + if (!of_id) { + dev_err(&pdev->dev, "failed to look up compatible string\n"); + return -EINVAL; + } + + data = of_id->data; + pcie->reg_offsets = data->offsets; + pcie->reg_field_info = data->reg_field_info; + pcie->type = data->type; + pcie->dn = dn; + pcie->dev = &pdev->dev; + + /* We use the domain number as our controller number */ + pcie->id = of_get_pci_domain_nr(dn); + if (pcie->id < 0) + return pcie->id; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pcie->clk = of_clk_get_by_name(dn, "sw_pcie"); + if (IS_ERR(pcie->clk)) { + dev_err(&pdev->dev, "could not get clock\n"); + pcie->clk = NULL; + } + pcie->base = base; + + ret = of_pci_get_max_link_speed(dn); + pcie->gen = (ret < 0) ? 0 : ret; + + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc"); + + ret = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (ret == 0) + /* keep going, as we don't use this intr yet */ + dev_warn(pcie->dev, "cannot get PCIe interrupt\n"); + else + pcie->irq = ret; + + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows, + &bridge->dma_ranges, NULL); + if (ret) + return ret; + + ret = clk_prepare_enable(pcie->clk); + if (ret) { + dev_err(&pdev->dev, "could not enable clock\n"); + return ret; + } + + ret = brcm_pcie_setup(pcie); + if (ret) + goto fail; + + bridge->dev.parent = &pdev->dev; + bridge->busnr = 0; + bridge->ops = &brcm_pcie_ops; + bridge->sysdata = pcie; + bridge->map_irq = of_irq_parse_and_map_pci; + bridge->swizzle_irq = pci_common_swizzle; + + ret = pci_scan_root_bus_bridge(bridge); + if (ret < 0) { + dev_err(pcie->dev, "Scanning root bridge failed\n"); + goto fail; + } + + pci_assign_unassigned_bus_resources(bridge->bus); + list_for_each_entry(child, &bridge->bus->children, node) + pcie_bus_configure_settings(child); + pci_bus_add_devices(bridge->bus); + platform_set_drvdata(pdev, pcie); + pcie->root_bus = bridge->bus; + + return 0; + +fail: + _brcm_pcie_remove(pcie); + return ret; +} + +static const struct dev_pm_ops brcm_pcie_pm_ops = { + .suspend_noirq = brcm_pcie_suspend, + .resume_noirq = brcm_pcie_resume, +}; + +static struct platform_driver brcm_pcie_driver = { + .probe = brcm_pcie_probe, + .remove = brcm_pcie_remove, + .driver = { + .name = "brcm-pcie", + .owner = THIS_MODULE, + .of_match_table = brcm_pcie_match, + .pm = &brcm_pcie_pm_ops, + }, +}; + +module_platform_driver(brcm_pcie_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver"); +MODULE_AUTHOR("Broadcom"); From patchwork Wed Nov 6 21:45:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Saenz Julienne X-Patchwork-Id: 11231213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 245351575 for ; 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bh=/KTEC69AkqyO1YmOpvr23Gd5MTG6tR8iu+4wDEg22yI=; b=YWZDJiLVF6T5gg E4e3cefs/QIqPBaB1Fala5SzoPPwZmY2OuZFooaeXbmUymKhS7wHLzxQ7Fo3bQFrj650gRWMIdizs Jyu6tNSa5AK56aGLr2xGDekP6SOTQlNv2sXgr1bFSK38LHUEGkOR2SBoY2iyf9o7SLrdiZrcEUug4 F4PZl99vKa3Pj/08DW1ldG4yTxe5muwCAMdOFuiLaCDS75ZqjThr6qK/Z+/dfXIw2fm1RyDl83rbj NP1IBcLj0pGOgZAUNFE58NYdSJIjsJlwra0t3CoALH+9/6bo/tv24CpSlZW/9Tvfgc9YTzI0VUuNg 38BIBBvM3y4GJmp8UZ8A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST8U-0006Oj-Fq; Wed, 06 Nov 2019 21:46:42 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iST7g-0005PZ-FH; Wed, 06 Nov 2019 21:45:55 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 1B9EEAE35; Wed, 6 Nov 2019 21:45:51 +0000 (UTC) From: Nicolas Saenz Julienne To: Andrew Murray , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , Florian Fainelli Subject: [PATCH 4/4] PCI: brcmstb: add MSI capability Date: Wed, 6 Nov 2019 22:45:26 +0100 Message-Id: <20191106214527.18736-5-nsaenzjulienne@suse.de> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106214527.18736-1-nsaenzjulienne@suse.de> References: <20191106214527.18736-1-nsaenzjulienne@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_134552_821960_6AACD68E X-CRM114-Status: GOOD ( 25.53 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mbrugger@suse.com, phil@raspberrypi.org, linux-kernel@vger.kernel.org, wahrenst@gmx.net, james.quinlan@broadcom.com, Bjorn Helgaas , Nicolas Saenz Julienne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jim Quinlan This commit adds MSI to the Broadcom STB PCIe host controller. It does not add MSIX since that functionality is not in the HW. The MSI controller is physically located within the PCIe block, however, there is no reason why the MSI controller could not be moved elsewhere in the future. Since the internal Brcmstb MSI controller is intertwined with the PCIe controller, it is not its own platform device but rather part of the PCIe platform device. This is based on Jim's original submission[1] with some slight changes regarding how pcie->msi_target_addr is decided. [1] https://patchwork.kernel.org/patch/10605955/ Signed-off-by: Jim Quinlan Co-developed-by: Nicolas Saenz Julienne Signed-off-by: Nicolas Saenz Julienne --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-brcmstb.c | 333 +++++++++++++++++++++++++- 2 files changed, 332 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 8b3aae91d8af..99b972ad3f2f 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -284,7 +284,7 @@ config VMD config PCIE_BRCMSTB bool "Broadcom Brcmstb PCIe host controller" depends on ARCH_BRCMSTB || BMIPS_GENERIC - depends on OF + depends on OF && PCI_MSI depends on SOC_BRCMSTB default ARCH_BRCMSTB || BMIPS_GENERIC help diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 880ec11d06a1..26053e69b95f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright (C) 2009 - 2019 Broadcom */ +#include #include #include #include @@ -8,11 +9,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -46,6 +49,9 @@ #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c +#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 +#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 +#define PCIE_MISC_MSI_DATA_CONFIG 0x404c #define PCIE_MISC_PCIE_CTRL 0x4064 #define PCIE_MISC_PCIE_STATUS 0x4068 #define PCIE_MISC_REVISION 0x406c @@ -54,6 +60,7 @@ #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_INTR2_CPU_BASE 0x4300 +#define PCIE_MSI_INTR2_BASE 0x4500 /* * Broadcom Settop Box PCIe Register Field shift and mask info. The @@ -114,6 +121,8 @@ #define BRCM_NUM_PCIE_OUT_WINS 0x4 #define BRCM_MAX_SCB 0x4 +#define BRCM_INT_PCI_MSI_NR 32 +#define BRCM_PCIE_HW_REV_33 0x0303 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL @@ -199,6 +208,33 @@ struct brcm_window { dma_addr_t size; }; +struct brcm_msi { + struct device *dev; + void __iomem *base; + struct device_node *dn; + struct irq_domain *msi_domain; + struct irq_domain *inner_domain; + struct mutex lock; /* guards the alloc/free operations */ + u64 target_addr; + int irq; + + /* intr_base is the base pointer for interrupt status/set/clr regs */ + void __iomem *intr_base; + + /* intr_legacy_mask indicates how many bits are MSI interrupts */ + u32 intr_legacy_mask; + + /* + * intr_legacy_offset indicates bit position of MSI_01. It is + * to map the register bit position to a hwirq that starts at 0. + */ + u32 intr_legacy_offset; + + /* used indicates which MSI interrupts have been alloc'd */ + unsigned long used; + unsigned int rev; +}; + /* Internal PCIe Host Controller Information.*/ struct brcm_pcie { struct device *dev; @@ -211,7 +247,10 @@ struct brcm_pcie { bool suspended; bool ssc; int gen; + u64 msi_target_addr; struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS]; + struct brcm_msi *msi; + bool msi_internal; unsigned int rev; const int *reg_offsets; const int *reg_field_info; @@ -477,6 +516,267 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, LIMIT, tmp); } +static struct irq_chip brcm_msi_irq_chip = { + .name = "Brcm_MSI", + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static struct msi_domain_info brcm_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX), + .chip = &brcm_msi_irq_chip, +}; + +static void brcm_pcie_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct brcm_msi *msi; + unsigned long status, virq; + u32 mask, bit, hwirq; + struct device *dev; + + chained_irq_enter(chip, desc); + msi = irq_desc_get_handler_data(desc); + mask = msi->intr_legacy_mask; + dev = msi->dev; + + while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) { + for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) { + /* clear the interrupt */ + bcm_writel(1 << bit, msi->intr_base + CLR); + + /* Account for legacy interrupt offset */ + hwirq = bit - msi->intr_legacy_offset; + + virq = irq_find_mapping(msi->inner_domain, hwirq); + if (virq) { + if (msi->used & (1 << hwirq)) + generic_handle_irq(virq); + else + dev_info(dev, "unhandled MSI %d\n", + hwirq); + } else { + /* Unknown MSI, just clear it */ + dev_dbg(dev, "unexpected MSI\n"); + } + } + } + chained_irq_exit(chip, desc); +} + +static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct brcm_msi *msi = irq_data_get_irq_chip_data(data); + u32 temp; + + msg->address_lo = lower_32_bits(msi->target_addr); + msg->address_hi = upper_32_bits(msi->target_addr); + temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG); + msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq; +} + +static int brcm_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip brcm_msi_bottom_irq_chip = { + .name = "Brcm_MSI", + .irq_compose_msi_msg = brcm_compose_msi_msg, + .irq_set_affinity = brcm_msi_set_affinity, +}; + +static int brcm_msi_alloc(struct brcm_msi *msi) +{ + int bit, hwirq; + + mutex_lock(&msi->lock); + bit = ~msi->used ? ffz(msi->used) : -1; + + if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) { + msi->used |= (1 << bit); + hwirq = bit - msi->intr_legacy_offset; + } else { + hwirq = -ENOSPC; + } + + mutex_unlock(&msi->lock); + return hwirq; +} + +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) +{ + mutex_lock(&msi->lock); + msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset)); + mutex_unlock(&msi->lock); +} + +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct brcm_msi *msi = domain->host_data; + int hwirq; + + hwirq = brcm_msi_alloc(msi); + + if (hwirq < 0) + return hwirq; + + irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq, + &brcm_msi_bottom_irq_chip, domain->host_data, + handle_simple_irq, NULL, NULL); + return 0; +} + +static void brcm_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct brcm_msi *msi = irq_data_get_irq_chip_data(d); + + brcm_msi_free(msi, d->hwirq); +} + +static void brcm_msi_set_regs(struct brcm_msi *msi) +{ + u32 data_val, msi_lo, msi_hi; + + if (msi->rev >= BRCM_PCIE_HW_REV_33) { + /* + * ffe0 -- least sig 5 bits are 0 indicating 32 msgs + * 6540 -- this is our arbitrary unique data value + */ + data_val = 0xffe06540; + } else { + /* + * fff8 -- least sig 3 bits are 0 indicating 8 msgs + * 6540 -- this is our arbitrary unique data value + */ + data_val = 0xfff86540; + } + + /* + * Make sure we are not masking MSIs. Note that MSIs can be masked, + * but that occurs on the PCIe EP device + */ + bcm_writel(0xffffffff & msi->intr_legacy_mask, + msi->intr_base + MASK_CLR); + + msi_lo = lower_32_bits(msi->target_addr); + msi_hi = upper_32_bits(msi->target_addr); + /* + * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI + * enable, which we set to 1. + */ + bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); + bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); + bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); +} + +static const struct irq_domain_ops msi_domain_ops = { + .alloc = brcm_irq_domain_alloc, + .free = brcm_irq_domain_free, +}; + +static int brcm_allocate_domains(struct brcm_msi *msi) +{ + struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn); + struct device *dev = msi->dev; + + msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR, + &msi_domain_ops, msi); + if (!msi->inner_domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + msi->msi_domain = pci_msi_create_irq_domain(fwnode, + &brcm_msi_domain_info, + msi->inner_domain); + if (!msi->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(msi->inner_domain); + return -ENOMEM; + } + + return 0; +} + +static void brcm_free_domains(struct brcm_msi *msi) +{ + irq_domain_remove(msi->msi_domain); + irq_domain_remove(msi->inner_domain); +} + +static void brcm_msi_remove(struct brcm_pcie *pcie) +{ + struct brcm_msi *msi = pcie->msi; + + if (!msi) + return; + irq_set_chained_handler(msi->irq, NULL); + irq_set_handler_data(msi->irq, NULL); + brcm_free_domains(msi); +} + +static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) +{ + struct brcm_msi *msi; + int irq, ret; + struct device *dev = pcie->dev; + + irq = irq_of_parse_and_map(dev->of_node, 1); + if (irq <= 0) { + dev_err(dev, "cannot map msi intr\n"); + return -ENODEV; + } + + msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); + if (!msi) + return -ENOMEM; + + msi->dev = dev; + msi->base = pcie->base; + msi->rev = pcie->rev; + msi->dn = pcie->dn; + msi->target_addr = pcie->msi_target_addr; + msi->irq = irq; + + ret = brcm_allocate_domains(msi); + if (ret) + return ret; + + irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); + + if (msi->rev >= BRCM_PCIE_HW_REV_33) { + msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; + /* + * This version of PCIe hw has only 32 intr bits + * starting at bit position 0. + */ + msi->intr_legacy_mask = 0xffffffff; + msi->intr_legacy_offset = 0x0; + msi->used = 0x0; + + } else { + msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; + /* + * This version of PCIe hw has only 8 intr bits starting + * at bit position 24. + */ + msi->intr_legacy_mask = 0xff000000; + msi->intr_legacy_offset = 24; + msi->used = 0x00ffffff; + } + + brcm_msi_set_regs(msi); + pcie->msi = msi; + + return 0; +} + /* Configuration space read/write support */ static int cfg_index(int busnr, int devfn, int reg) { @@ -643,6 +943,18 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) if (ret) return ret; + /* + * We ideally want the MSI target address to be located in the 32bit + * addressable memory area. Some devices might depend on it. This is + * possible either when the inbound window is located above the lower + * 4GB or when the inbound and outbound areas fit in the lower 4GB of + * memory. + */ + if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) <= SZ_4G) + pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; + else + pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; + tmp = lower_32_bits(rc_bar2_offset); tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE, encode_ibar_size(rc_bar2_size)); @@ -816,6 +1128,9 @@ static int brcm_pcie_resume(struct device *dev) if (ret) return ret; + if (pcie->msi && pcie->msi_internal) + brcm_msi_set_regs(pcie->msi); + pcie->suspended = false; return 0; @@ -823,6 +1138,7 @@ static int brcm_pcie_resume(struct device *dev) static void _brcm_pcie_remove(struct brcm_pcie *pcie) { + brcm_msi_remove(pcie); turn_off(pcie); clk_disable_unprepare(pcie->clk); clk_put(pcie->clk); @@ -847,7 +1163,7 @@ MODULE_DEVICE_TABLE(of, brcm_pcie_match); static int brcm_pcie_probe(struct platform_device *pdev) { - struct device_node *dn = pdev->dev.of_node; + struct device_node *dn = pdev->dev.of_node, *msi_dn; const struct of_device_id *of_id; const struct pcie_cfg_data *data; struct resource *res; @@ -923,6 +1239,20 @@ static int brcm_pcie_probe(struct platform_device *pdev) if (ret) goto fail; + msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0); + /* Use the internal MSI if no msi-parent property */ + if (!msi_dn) + msi_dn = pcie->dn; + + if (pci_msi_enabled() && msi_dn == pcie->dn) { + ret = brcm_pcie_enable_msi(pcie); + if (ret) + dev_err(pcie->dev, + "probe of internal MSI failed: %d)", ret); + else + pcie->msi_internal = true; + } + bridge->dev.parent = &pdev->dev; bridge->busnr = 0; bridge->ops = &brcm_pcie_ops; @@ -944,7 +1274,6 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->root_bus = bridge->bus; return 0; - fail: _brcm_pcie_remove(pcie); return ret;