From patchwork Tue Sep 18 01:45:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 10603655 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C8FC615E8 for ; Tue, 18 Sep 2018 01:50:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA04E2A71F for ; Tue, 18 Sep 2018 01:50:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE3B42A722; Tue, 18 Sep 2018 01:50:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F4F52A71F for ; Tue, 18 Sep 2018 01:50:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728579AbeIRHUH (ORCPT ); Tue, 18 Sep 2018 03:20:07 -0400 Received: from vsp-unauthed02.binero.net ([195.74.38.227]:63128 "EHLO vsp-unauthed02.binero.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726990AbeIRHUH (ORCPT ); Tue, 18 Sep 2018 03:20:07 -0400 X-Halon-ID: 1de2fd83-bae5-11e8-ab18-005056917a89 Authorized-sender: niklas@soderlund.pp.se Received: from bismarck.berto.se (unknown [89.233.230.99]) by bin-vsp-out-01.atm.binero.net (Halon) with ESMTPA id 1de2fd83-bae5-11e8-ab18-005056917a89; Tue, 18 Sep 2018 03:49:45 +0200 (CEST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Kieran Bingham , Laurent Pinchart , Jacopo Mondi , linux-media@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 1/3] i2c: adv748x: store number of CSI-2 lanes described in device tree Date: Tue, 18 Sep 2018 03:45:07 +0200 Message-Id: <20180918014509.6394-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> References: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The adv748x CSI-2 transmitters TXA and TXB can use different number of lines to transmit data on. In order to be able configure the device correctly this information need to be parsed from device tree and stored in each TX private data structure. TXA supports 1, 2 and 4 lanes while TXB supports 1 lane. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart --- drivers/media/i2c/adv748x/adv748x-core.c | 49 ++++++++++++++++++++++++ drivers/media/i2c/adv748x/adv748x.h | 1 + 2 files changed, 50 insertions(+) diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c index 85c027bdcd56748d..a93f8ea89a228474 100644 --- a/drivers/media/i2c/adv748x/adv748x-core.c +++ b/drivers/media/i2c/adv748x/adv748x-core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "adv748x.h" @@ -561,11 +562,54 @@ void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state, sd->entity.ops = &adv748x_media_ops; } +static int adv748x_parse_csi2_lanes(struct adv748x_state *state, + unsigned int port, + struct device_node *ep) +{ + struct v4l2_fwnode_endpoint vep; + unsigned int num_lanes; + int ret; + + if (port != ADV748X_PORT_TXA && port != ADV748X_PORT_TXB) + return 0; + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &vep); + if (ret) + return ret; + + num_lanes = vep.bus.mipi_csi2.num_data_lanes; + + if (vep.base.port == ADV748X_PORT_TXA) { + if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { + adv_err(state, "TXA: Invalid number (%d) of lanes\n", + num_lanes); + return -EINVAL; + } + + state->txa.num_lanes = num_lanes; + adv_dbg(state, "TXA: using %d lanes\n", state->txa.num_lanes); + } + + if (vep.base.port == ADV748X_PORT_TXB) { + if (num_lanes != 1) { + adv_err(state, "TXB: Invalid number (%d) of lanes\n", + num_lanes); + return -EINVAL; + } + + state->txb.num_lanes = num_lanes; + adv_dbg(state, "TXB: using %d lanes\n", state->txb.num_lanes); + } + + return 0; +} + static int adv748x_parse_dt(struct adv748x_state *state) { struct device_node *ep_np = NULL; struct of_endpoint ep; bool found = false; + int ret; for_each_endpoint_of_node(state->dev->of_node, ep_np) { of_graph_parse_endpoint(ep_np, &ep); @@ -589,6 +633,11 @@ static int adv748x_parse_dt(struct adv748x_state *state) state->endpoints[ep.port] = ep_np; found = true; + + /* Store number of CSI-2 lanes used for TXA and TXB. */ + ret = adv748x_parse_csi2_lanes(state, ep.port, ep_np); + if (ret) + return ret; } return found ? 0 : -ENODEV; diff --git a/drivers/media/i2c/adv748x/adv748x.h b/drivers/media/i2c/adv748x/adv748x.h index c9016acaba34aff2..88ad06a3045c5427 100644 --- a/drivers/media/i2c/adv748x/adv748x.h +++ b/drivers/media/i2c/adv748x/adv748x.h @@ -78,6 +78,7 @@ struct adv748x_csi2 { struct adv748x_state *state; struct v4l2_mbus_framefmt format; unsigned int page; + unsigned int num_lanes; struct media_pad pads[ADV748X_CSI2_NR_PADS]; struct v4l2_ctrl_handler ctrl_hdl; From patchwork Tue Sep 18 01:45:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 10603661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13032161F for ; Tue, 18 Sep 2018 01:50:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 03E632A6F8 for ; Tue, 18 Sep 2018 01:50:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ECBE02A722; Tue, 18 Sep 2018 01:50:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 860AF2A6F8 for ; Tue, 18 Sep 2018 01:50:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728590AbeIRHUI (ORCPT ); Tue, 18 Sep 2018 03:20:08 -0400 Received: from bin-mail-out-06.binero.net ([195.74.38.229]:34042 "EHLO bin-mail-out-06.binero.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726990AbeIRHUI (ORCPT ); Tue, 18 Sep 2018 03:20:08 -0400 X-Halon-ID: 1e626d97-bae5-11e8-ab18-005056917a89 Authorized-sender: niklas@soderlund.pp.se Received: from bismarck.berto.se (unknown [89.233.230.99]) by bin-vsp-out-01.atm.binero.net (Halon) with ESMTPA id 1e626d97-bae5-11e8-ab18-005056917a89; Tue, 18 Sep 2018 03:49:45 +0200 (CEST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Kieran Bingham , Laurent Pinchart , Jacopo Mondi , linux-media@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 2/3] i2c: adv748x: configure number of lanes used for TXA CSI-2 transmitter Date: Tue, 18 Sep 2018 03:45:08 +0200 Message-Id: <20180918014509.6394-3-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> References: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The driver fixed the TXA CSI-2 transmitter in 4-lane mode while it could operate using 1-, 2- and 4-lanes. Update the driver to support all modes the hardware does. The driver make use of large tables of static register/value writes when configuring the hardware, some writing to undocumented registers. Instead of creating 3 sets of the register tables for the different modes catch when the register containing NUM_LANES[2:0] is written to and inject the correct number of lanes. Signed-off-by: Niklas Söderlund --- drivers/media/i2c/adv748x/adv748x-core.c | 38 +++++++++++++++++++----- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c index a93f8ea89a228474..9a82cdf301bccb41 100644 --- a/drivers/media/i2c/adv748x/adv748x-core.c +++ b/drivers/media/i2c/adv748x/adv748x-core.c @@ -207,13 +207,23 @@ static int adv748x_write_regs(struct adv748x_state *state, const struct adv748x_reg_value *regs) { int ret; + u8 value; while (regs->page != ADV748X_PAGE_EOR) { if (regs->page == ADV748X_PAGE_WAIT) { msleep(regs->value); } else { + value = regs->value; + + /* + * Register 0x00 in TXA needs to bei injected with + * the number of CSI-2 lanes used to transmitt. + */ + if (regs->page == ADV748X_PAGE_TXA && regs->reg == 0x00) + value = (value & ~7) | state->txa.num_lanes; + ret = adv748x_write(state, regs->page, regs->reg, - regs->value); + value); if (ret < 0) { adv_err(state, "Error regs page: 0x%02x reg: 0x%02x\n", @@ -233,14 +243,18 @@ static int adv748x_write_regs(struct adv748x_state *state, static const struct adv748x_reg_value adv748x_power_up_txa_4lane[] = { - {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ - {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x80}, /* Enable n-lane MIPI */ + {ADV748X_PAGE_TXA, 0x00, 0xa0}, /* Set Auto DPHY Timing */ {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ - {ADV748X_PAGE_TXA, 0x00, 0x24 },/* Power-up CSI-TX */ + + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x20 },/* Power-up CSI-TX */ + {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */ {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ @@ -253,7 +267,10 @@ static const struct adv748x_reg_value adv748x_power_down_txa_4lane[] = { {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0x1e, 0x00}, /* ADI Required Write */ - {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ + + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x80}, /* Enable n-lane MIPI */ + {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_TXA, 0xc1, 0x3b}, /* ADI Required Write */ @@ -399,8 +416,10 @@ static const struct adv748x_reg_value adv748x_init_txa_4lane[] = { /* Outputs Enabled */ {ADV748X_PAGE_IO, 0x10, 0xa0}, /* Enable 4-lane CSI Tx & Pixel Port */ - {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ - {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x80}, /* Enable n-lane MIPI */ + {ADV748X_PAGE_TXA, 0x00, 0xa0}, /* Set Auto DPHY Timing */ + {ADV748X_PAGE_TXA, 0xdb, 0x10}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xd6, 0x07}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xc4, 0x0a}, /* ADI Required Write */ @@ -412,7 +431,10 @@ static const struct adv748x_reg_value adv748x_init_txa_4lane[] = { {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ - {ADV748X_PAGE_TXA, 0x00, 0x24 },/* Power-up CSI-TX */ + + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x20 },/* Power-up CSI-TX */ + {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */ {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ From patchwork Tue Sep 18 01:45:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 10603665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B142115E8 for ; Tue, 18 Sep 2018 01:50:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A38232A6F8 for ; Tue, 18 Sep 2018 01:50:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 97F0A2A721; Tue, 18 Sep 2018 01:50:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F23E32A6F8 for ; Tue, 18 Sep 2018 01:50:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728592AbeIRHUK (ORCPT ); Tue, 18 Sep 2018 03:20:10 -0400 Received: from bin-mail-out-06.binero.net ([195.74.38.229]:30472 "EHLO bin-mail-out-06.binero.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726974AbeIRHUK (ORCPT ); Tue, 18 Sep 2018 03:20:10 -0400 X-Halon-ID: 1eeb9bc8-bae5-11e8-ab18-005056917a89 Authorized-sender: niklas@soderlund.pp.se Received: from bismarck.berto.se (unknown [89.233.230.99]) by bin-vsp-out-01.atm.binero.net (Halon) with ESMTPA id 1eeb9bc8-bae5-11e8-ab18-005056917a89; Tue, 18 Sep 2018 03:49:46 +0200 (CEST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Kieran Bingham , Laurent Pinchart , Jacopo Mondi , linux-media@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 3/3] i2c: adv748x: fix typo in comment for TXB CSI-2 transmitter power down Date: Tue, 18 Sep 2018 03:45:09 +0200 Message-Id: <20180918014509.6394-4-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> References: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fix copy-and-past error in comment for TXB CSI-2 transmitter power down sequence. Signed-off-by: Niklas Söderlund Reviewed-by: Kieran Bingham Reviewed-by: Laurent Pinchart --- drivers/media/i2c/adv748x/adv748x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c index 9a82cdf301bccb41..86cb38f4d7cc11c6 100644 --- a/drivers/media/i2c/adv748x/adv748x-core.c +++ b/drivers/media/i2c/adv748x/adv748x-core.c @@ -299,7 +299,7 @@ static const struct adv748x_reg_value adv748x_power_down_txb_1lane[] = { {ADV748X_PAGE_TXB, 0x31, 0x82}, /* ADI Required Write */ {ADV748X_PAGE_TXB, 0x1e, 0x00}, /* ADI Required Write */ - {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 4-lane MIPI */ + {ADV748X_PAGE_TXB, 0x00, 0x81}, /* Enable 1-lane MIPI */ {ADV748X_PAGE_TXB, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_TXB, 0xc1, 0x3b}, /* ADI Required Write */