From patchwork Mon Nov 11 01:40:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11236411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA7551390 for ; Mon, 11 Nov 2019 01:44:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A29C1206DF for ; Mon, 11 Nov 2019 01:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726845AbfKKBo1 (ORCPT ); Sun, 10 Nov 2019 20:44:27 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:55648 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726754AbfKKBo1 (ORCPT ); Sun, 10 Nov 2019 20:44:27 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 07E0995406B7BB897352; Mon, 11 Nov 2019 09:44:21 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Mon, 11 Nov 2019 09:44:14 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , CC: , Subject: [RESEND PATCH v21 1/6] hw/arm/virt: Introduce a RAS machine option Date: Mon, 11 Nov 2019 09:40:43 +0800 Message-ID: <20191111014048.21296-2-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> References: <20191111014048.21296-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Dongjiu Geng RAS Virtualization feature is not supported now, so add a RAS machine option and disable it by default. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng Reviewed-by: Peter Maydell --- hw/arm/virt.c | 23 +++++++++++++++++++++++ include/hw/arm/virt.h | 1 + 2 files changed, 24 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2607..ea0fbf82be 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1819,6 +1819,20 @@ static void virt_set_its(Object *obj, bool value, Error **errp) vms->its = value; } +static bool virt_get_ras(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->ras; +} + +static void virt_set_ras(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->ras = value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -2122,6 +2136,15 @@ static void virt_instance_init(Object *obj) "Valid values are none and smmuv3", NULL); + /* Default disallows RAS instantiation */ + vms->ras = false; + object_property_add_bool(obj, "ras", virt_get_ras, + virt_set_ras, NULL); + object_property_set_description(obj, "ras", + "Set on/off to enable/disable " + "RAS instantiation", + NULL); + vms->irqmap = a15irqmap; virt_flash_create(vms); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 0b41083e9d..989785f2f7 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -122,6 +122,7 @@ typedef struct { bool highmem_ecam; bool its; bool virt; + bool ras; int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; From patchwork Mon Nov 11 01:40:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11236415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 408F613BD for ; Mon, 11 Nov 2019 01:44:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FFBD204EC for ; Mon, 11 Nov 2019 01:44:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726885AbfKKBo3 (ORCPT ); Sun, 10 Nov 2019 20:44:29 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:55736 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726819AbfKKBo2 (ORCPT ); Sun, 10 Nov 2019 20:44:28 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 426AE30996FC53ACBCA1; Mon, 11 Nov 2019 09:44:26 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Mon, 11 Nov 2019 09:44:15 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , CC: , Subject: [RESEND PATCH v21 2/6] docs: APEI GHES generation and CPER record description Date: Mon, 11 Nov 2019 09:40:44 +0800 Message-ID: <20191111014048.21296-3-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> References: <20191111014048.21296-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Dongjiu Geng Add APEI/GHES detailed design document Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng Reviewed-by: Michael S. Tsirkin --- docs/specs/acpi_hest_ghes.rst | 95 +++++++++++++++++++++++++++++++++++ docs/specs/index.rst | 1 + 2 files changed, 96 insertions(+) create mode 100644 docs/specs/acpi_hest_ghes.rst diff --git a/docs/specs/acpi_hest_ghes.rst b/docs/specs/acpi_hest_ghes.rst new file mode 100644 index 0000000000..348825f9d3 --- /dev/null +++ b/docs/specs/acpi_hest_ghes.rst @@ -0,0 +1,95 @@ +APEI tables generating and CPER record +====================================== + +.. + Copyright (c) 2019 HUAWEI TECHNOLOGIES CO., LTD. + + This work is licensed under the terms of the GNU GPL, version 2 or later. + See the COPYING file in the top-level directory. + +Design Details +-------------- + +:: + + etc/acpi/tables etc/hardware_errors + ==================== ========================================== + + +--------------------------+ +-----------------------+ + | | HEST | | address | +--------------+ + | +--------------------------+ | registers | | Error Status | + | | GHES1 | | +---------------------+ | Data Block 1 | + | +--------------------------+ +--------->| |error_block_address1 |----------->| +------------+ + | | ................. | | | +---------------------+ | | CPER | + | | error_status_address-----+-+ +------->| |error_block_address2 |--------+ | | CPER | + | | ................. | | | +---------------------+ | | | .... | + | | read_ack_register--------+-+ | | | .............. | | | | CPER | + | | read_ack_preserve | | | +-----------------------+ | | +------------+ + | | read_ack_write | | | +----->| |error_block_addressN |------+ | | Error Status | + + +--------------------------+ | | | | +---------------------+ | | | Data Block 2 | + | | GHES2 | +-+-+----->| |read_ack_register1 | | +-->| +------------+ + + +--------------------------+ | | | +---------------------+ | | | CPER | + | | ................. | | | +--->| |read_ack_register2 | | | | CPER | + | | error_status_address-----+---+ | | | +---------------------+ | | | .... | + | | ................. | | | | | ............. | | | | CPER | + | | read_ack_register--------+-----+-+ | +---------------------+ | +-+------------+ + | | read_ack_preserve | | +->| |read_ack_registerN | | | |.......... | + | | read_ack_write | | | | +---------------------+ | | +------------+ + + +--------------------------| | | | | Error Status | + | | ............... | | | | | Data Block N | + + +--------------------------+ | | +---->| +------------+ + | | GHESN | | | | | CPER | + + +--------------------------+ | | | | CPER | + | | ................. | | | | | .... | + | | error_status_address-----+-----+ | | | CPER | + | | ................. | | +-+------------+ + | | read_ack_register--------+---------+ + | | read_ack_preserve | + | | read_ack_write | + + +--------------------------+ + +(1) QEMU generates the ACPI HEST table. This table goes in the current + "etc/acpi/tables" fw_cfg blob. Each error source has different + notification types. + +(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU + also needs to populate this blob. The "etc/hardware_errors" fw_cfg blob + contains an address registers table and an Error Status Data Block table. + +(3) The address registers table contains N Error Block Address entries + and N Read Ack Register entries. The size for each entry is 8-byte. + The Error Status Data Block table contains N Error Status Data Block + entries. The size for each entry is 4096(0x1000) bytes. The total size + for the "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes. + N is the number of the kinds of hardware error sources. + +(4) QEMU generates the ACPI linker/loader script for the firmware. The + firmware pre-allocates memory for "etc/acpi/tables", "etc/hardware_errors" + and copies blob contents there. + +(5) QEMU generates N ADD_POINTER commands, which patch addresses in the + "error_status_address" fields of the HEST table with a pointer to the + corresponding "address registers" in the "etc/hardware_errors" blob. + +(6) QEMU generates N ADD_POINTER commands, which patch addresses in the + "read_ack_register" fields of the HEST table with a pointer to the + corresponding "address registers" in the "etc/hardware_errors" blob. + +(7) QEMU generates N ADD_POINTER commands for the firmware, which patch + addresses in the "error_block_address" fields with a pointer to the + respective "Error Status Data Block" in the "etc/hardware_errors" blob. + +(8) QEMU defines a third and write-only fw_cfg blob which is called + "etc/hardware_errors_addr". Through that blob, the firmware can send back + the guest-side allocation addresses to QEMU. The "etc/hardware_errors_addr" + blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER command + for the firmware. The firmware will write back the start address of + "etc/hardware_errors" blob to the fw_cfg file "etc/hardware_errors_addr". + +(9) When QEMU gets a SIGBUS from the kernel, QEMU formats the CPER right into + guest memory, and then injects platform specific interrupt (in case of + arm/virt machine it's Synchronous External Abort) as a notification which + is necessary for notifying the guest. + +(10) This notification (in virtual hardware) will be handled by the guest + kernel, guest APEI driver will read the CPER which is recorded by QEMU and + do the recovery. diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 984ba44029..3019b9c976 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -13,3 +13,4 @@ Contents: ppc-xive ppc-spapr-xive acpi_hw_reduced_hotplug + acpi_hest_ghes From patchwork Mon Nov 11 01:40:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11236419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 708511390 for ; Mon, 11 Nov 2019 01:44:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46699204EC for ; Mon, 11 Nov 2019 01:44:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726910AbfKKBob (ORCPT ); Sun, 10 Nov 2019 20:44:31 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6179 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726847AbfKKBoa (ORCPT ); Sun, 10 Nov 2019 20:44:30 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 1E058652FFE76F211A73; Mon, 11 Nov 2019 09:44:26 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Mon, 11 Nov 2019 09:44:16 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , CC: , Subject: [RESEND PATCH v21 3/6] ACPI: Add APEI GHES table generation support Date: Mon, 11 Nov 2019 09:40:45 +0800 Message-ID: <20191111014048.21296-4-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> References: <20191111014048.21296-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Dongjiu Geng This patch implements APEI GHES Table generation via fw_cfg blobs. Now it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards, we can extend the supported types if needed. For the CPER section, currently it is memory section because kernel mainly wants userspace to handle the memory errors. This patch follows the spec ACPI 6.2 to build the Hardware Error Source table. For more detailed information, please refer to document: docs/specs/acpi_hest_ghes.rst Suggested-by: Laszlo Ersek Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng Reviewed-by: Michael S. Tsirkin --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Kconfig | 4 + hw/acpi/Makefile.objs | 1 + hw/acpi/acpi_ghes.c | 267 ++++++++++++++++++++++++++++++++ hw/acpi/aml-build.c | 2 + hw/arm/virt-acpi-build.c | 12 ++ include/hw/acpi/acpi_ghes.h | 56 +++++++ include/hw/acpi/aml-build.h | 1 + 8 files changed, 344 insertions(+) create mode 100644 hw/acpi/acpi_ghes.c create mode 100644 include/hw/acpi/acpi_ghes.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 1f2e0e7fde..5722f3130e 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -40,3 +40,4 @@ CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_SEMIHOSTING=y +CONFIG_ACPI_APEI=y diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index 12e3f1e86e..ed8c34d238 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -23,6 +23,10 @@ config ACPI_NVDIMM bool depends on ACPI +config ACPI_APEI + bool + depends on ACPI + config ACPI_PCI bool depends on ACPI && PCI diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 655a9c1973..84474b0ca8 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -5,6 +5,7 @@ common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o +common-obj-$(CONFIG_ACPI_APEI) += acpi_ghes.o common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o common-obj-$(CONFIG_ACPI_HW_REDUCED) += generic_event_device.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c new file mode 100644 index 0000000000..42c00ff3d3 --- /dev/null +++ b/hw/acpi/acpi_ghes.c @@ -0,0 +1,267 @@ +/* + * Support for generating APEI tables and recording CPER for Guests + * + * Copyright (c) 2019 HUAWEI TECHNOLOGIES CO., LTD. + * + * Author: Dongjiu Geng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/acpi_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +#define ACPI_GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define ACPI_GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +/* + * The size of Address field in Generic Address Structure. + * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure. + */ +#define ACPI_GHES_ADDRESS_SIZE 8 + +/* The max size in bytes for one error block */ +#define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 + +/* + * Now only support ARMv8 SEA notification type error source + */ +#define ACPI_GHES_ERROR_SOURCE_COUNT 1 + +/* + * Generic Hardware Error Source version 2 + */ +#define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 + +/* + * | +--------------------------+ 0 + * | | Header | + * | +--------------------------+ 40---+- + * | | ................. | | + * | | error_status_address-----+ 60 | + * | | ................. | | + * | | read_ack_register--------+ 104 92 + * | | read_ack_preserve | | + * | | read_ack_write | | + * + +--------------------------+ 132--+- + * + * From above GHES definition, the error status address offset is 60; + * the Read Ack Register offset is 104, the whole size of GHESv2 is 92 + */ + +/* The error status address offset in GHES */ +#define ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(start_addr, n) (start_addr + \ + 60 + offsetof(struct AcpiGenericAddress, address) + n * 92) + +/* The Read Ack Register offset in GHES */ +#define ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, n) (start_addr +\ + 104 + offsetof(struct AcpiGenericAddress, address) + n * 92) + +typedef struct AcpiGhesState { + uint64_t ghes_addr_le; +} AcpiGhesState; + +/* + * Hardware Error Notification + * ACPI 4.0: 17.3.2.7 Hardware Error Notification + */ +static void acpi_ghes_build_notify(GArray *table, const uint8_t type) +{ + /* Type */ + build_append_int_noprefix(table, type, 1); + /* + * Length: + * Total length of the structure in bytes + */ + build_append_int_noprefix(table, 28, 1); + /* Configuration Write Enable */ + build_append_int_noprefix(table, 0, 2); + /* Poll Interval */ + build_append_int_noprefix(table, 0, 4); + /* Vector */ + build_append_int_noprefix(table, 0, 4); + /* Switch To Polling Threshold Value */ + build_append_int_noprefix(table, 0, 4); + /* Switch To Polling Threshold Window */ + build_append_int_noprefix(table, 0, 4); + /* Error Threshold Value */ + build_append_int_noprefix(table, 0, 4); + /* Error Threshold Window */ + build_append_int_noprefix(table, 0, 4); +} + +/* Build table for the hardware error fw_cfg blob */ +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker) +{ + int i, error_status_block_offset; + + /* + * | +--------------------------+ + * | | error_block_address | + * | | .......... | + * | +--------------------------+ + * | | read_ack_register | + * | | ........... | + * | +--------------------------+ + * | | Error Status Data Block | + * | | ........ | + * | +--------------------------+ + */ + + /* Build error_block_address */ + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + build_append_int_noprefix(hardware_errors, 0, ACPI_GHES_ADDRESS_SIZE); + } + + /* Build read_ack_register */ + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + /* + * Initialize the value of read_ack_register to 1, so GHES can be + * writeable in the first time. + * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2 + * (GHESv2 - Type 10) + */ + build_append_int_noprefix(hardware_errors, 1, ACPI_GHES_ADDRESS_SIZE); + } + + /* Generic Error Status Block offset in the hardware error fw_cfg blob */ + error_status_block_offset = hardware_errors->len; + + /* Build Error Status Data Block */ + build_append_int_noprefix(hardware_errors, 0, + ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT); + + /* Allocate guest memory for the hardware error fw_cfg blob */ + bios_linker_loader_alloc(linker, ACPI_GHES_ERRORS_FW_CFG_FILE, + hardware_errors, 1, false); + + for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + /* + * Patch the address of Error Status Data Block into + * the error_block_address of hardware_errors fw_cfg blob + */ + bios_linker_loader_add_pointer(linker, + ACPI_GHES_ERRORS_FW_CFG_FILE, ACPI_GHES_ADDRESS_SIZE * i, + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, + error_status_block_offset + i * ACPI_GHES_MAX_RAW_DATA_LENGTH); + } + + /* + * Write the address of hardware_errors fw_cfg blob into the + * hardware_errors_addr fw_cfg blob. + */ + bios_linker_loader_write_pointer(linker, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, + 0, ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, 0); +} + +/* Build Hardware Error Source Table */ +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_errors, + BIOSLinker *linker) +{ + uint32_t hest_start = table_data->len; + uint32_t source_id = 0; + + /* Hardware Error Source Table header*/ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + /* Error Source Count */ + build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4); + + /* + * Type: + * Generic Hardware Error Source version 2(GHESv2 - Type 10) + */ + build_append_int_noprefix(table_data, ACPI_GHES_SOURCE_GENERIC_ERROR_V2, 2); + /* + * Source Id + * Once we support more than one hardware error sources, we need to + * increase the value of this field. + */ + build_append_int_noprefix(table_data, source_id, 2); + /* Related Source Id */ + build_append_int_noprefix(table_data, 0xffff, 2); + /* Flags */ + build_append_int_noprefix(table_data, 0, 1); + /* Enabled */ + build_append_int_noprefix(table_data, 1, 1); + + /* Number of Records To Pre-allocate */ + build_append_int_noprefix(table_data, 1, 4); + /* Max Sections Per Record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max Raw Data Length */ + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Error Status Address */ + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */, 0); + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, + ACPI_GHES_ERROR_STATUS_ADDRESS_OFFSET(hest_start, source_id), + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, + source_id * ACPI_GHES_ADDRESS_SIZE); + + /* + * Notification Structure + * Now only enable ARMv8 SEA notification type + */ + acpi_ghes_build_notify(table_data, ACPI_GHES_NOTIFY_SEA); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, ACPI_GHES_MAX_RAW_DATA_LENGTH, 4); + + /* + * Read Ack Register + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source + * version 2 (GHESv2 - Type 10) + */ + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */, 0); + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, + ACPI_GHES_READ_ACK_REGISTER_ADDRESS_OFFSET(hest_start, 0), + ACPI_GHES_ADDRESS_SIZE, ACPI_GHES_ERRORS_FW_CFG_FILE, + (ACPI_GHES_ERROR_SOURCE_COUNT + source_id) * ACPI_GHES_ADDRESS_SIZE); + + /* + * Read Ack Preserve + * We only provide the first bit in Read Ack Register to OSPM to write + * while the other bits are preserved. + */ + build_append_int_noprefix(table_data, ~0x1ULL, 8); + /* Read Ack Write */ + build_append_int_noprefix(table_data, 0x1, 8); + + build_header(linker, table_data, (void *)(table_data->data + hest_start), + "HEST", table_data->len - hest_start, 1, NULL, "GHES"); +} + +static AcpiGhesState ges; +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t size = 2 * ACPI_GHES_ADDRESS_SIZE + ACPI_GHES_MAX_RAW_DATA_LENGTH; + size_t request_block_size = ACPI_GHES_ERROR_SOURCE_COUNT * size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, ACPI_GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + request_block_size); + + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 2c3702b882..3681ec6e3d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1578,6 +1578,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data = g_array_new(false, true /* clear */, 1); tables->tcpalog = g_array_new(false, true /* clear */, 1); tables->vmgenid = g_array_new(false, true /* clear */, 1); + tables->hardware_errors = g_array_new(false, true /* clear */, 1); tables->linker = bios_linker_loader_init(); } @@ -1588,6 +1589,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } /* diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 4cd50175e0..1b1fd273e4 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -48,6 +48,7 @@ #include "sysemu/reset.h" #include "kvm_arm.h" #include "migration/vmstate.h" +#include "hw/acpi/acpi_ghes.h" #define ARM_SPI_BASE 32 @@ -825,6 +826,13 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); + if (vms->ras) { + acpi_add_table(table_offsets, tables_blob); + acpi_ghes_build_error_table(tables->hardware_errors, tables->linker); + acpi_ghes_build_hest(tables_blob, tables->hardware_errors, + tables->linker); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -942,6 +950,10 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data, acpi_data_len(tables.tcpalog)); + if (vms->ras) { + acpi_ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + } + build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h new file mode 100644 index 0000000000..cb62ec9c7b --- /dev/null +++ b/include/hw/acpi/acpi_ghes.h @@ -0,0 +1,56 @@ +/* + * Support for generating APEI tables and recording CPER for Guests + * + * Copyright (c) 2019 HUAWEI TECHNOLOGIES CO., LTD. + * + * Author: Dongjiu Geng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +/* + * Values for Hardware Error Notification Type field + */ +enum AcpiGhesNotifyType { + ACPI_GHES_NOTIFY_POLLED = 0, /* Polled */ + ACPI_GHES_NOTIFY_EXTERNAL = 1, /* External Interrupt */ + ACPI_GHES_NOTIFY_LOCAL = 2, /* Local Interrupt */ + ACPI_GHES_NOTIFY_SCI = 3, /* SCI */ + ACPI_GHES_NOTIFY_NMI = 4, /* NMI */ + ACPI_GHES_NOTIFY_CMCI = 5, /* CMCI, ACPI 5.0: 18.3.2.7, Table 18-290 */ + ACPI_GHES_NOTIFY_MCE = 6, /* MCE, ACPI 5.0: 18.3.2.7, Table 18-290 */ + /* GPIO-Signal, ACPI 6.0: 18.3.2.7, Table 18-332 */ + ACPI_GHES_NOTIFY_GPIO = 7, + /* ARMv8 SEA, ACPI 6.1: 18.3.2.9, Table 18-345 */ + ACPI_GHES_NOTIFY_SEA = 8, + /* ARMv8 SEI, ACPI 6.1: 18.3.2.9, Table 18-345 */ + ACPI_GHES_NOTIFY_SEI = 9, + /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */ + ACPI_GHES_NOTIFY_GSIV = 10, + /* Software Delegated Exception, ACPI 6.2: 18.3.2.9, Table 18-383 */ + ACPI_GHES_NOTIFY_SDEI = 11, + ACPI_GHES_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */ +}; + +void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); + +void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker); +void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +#endif diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index de4a406568..8f13620701 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -220,6 +220,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; From patchwork Mon Nov 11 01:40:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11236423 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F80A13BD for ; Mon, 11 Nov 2019 01:44:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 77F37206DF for ; Mon, 11 Nov 2019 01:44:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726953AbfKKBoe (ORCPT ); Sun, 10 Nov 2019 20:44:34 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6178 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726824AbfKKBoe (ORCPT ); Sun, 10 Nov 2019 20:44:34 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 15A30E704D2DBB69064B; Mon, 11 Nov 2019 09:44:26 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Mon, 11 Nov 2019 09:44:17 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , CC: , Subject: [RESEND PATCH v21 4/6] KVM: Move hwpoison page related functions into kvm-all.c Date: Mon, 11 Nov 2019 09:40:46 +0800 Message-ID: <20191111014048.21296-5-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> References: <20191111014048.21296-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Dongjiu Geng kvm_hwpoison_page_add() and kvm_unpoison_all() will both be used by X86 and ARM platforms, so moving them into "accel/kvm/kvm-all.c" to avoid duplicate code. For architectures that don't use the poison-list functionality the reset handler will harmlessly do nothing, so let's register the kvm_unpoison_all() function in the generic kvm_init() function. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng Reviewed-by: Peter Maydell --- accel/kvm/kvm-all.c | 36 ++++++++++++++++++++++++++++++++++++ include/sysemu/kvm_int.h | 12 ++++++++++++ target/i386/kvm.c | 36 ------------------------------------ 3 files changed, 48 insertions(+), 36 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 140b0bd8f6..f45096d5a0 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -41,6 +41,7 @@ #include "hw/irq.h" #include "sysemu/sev.h" #include "sysemu/balloon.h" +#include "sysemu/reset.h" #include "hw/boards.h" @@ -856,6 +857,39 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension) return ret; } +typedef struct HWPoisonPage { + ram_addr_t ram_addr; + QLIST_ENTRY(HWPoisonPage) list; +} HWPoisonPage; + +static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = + QLIST_HEAD_INITIALIZER(hwpoison_page_list); + +static void kvm_unpoison_all(void *param) +{ + HWPoisonPage *page, *next_page; + + QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { + QLIST_REMOVE(page, list); + qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); + g_free(page); + } +} + +void kvm_hwpoison_page_add(ram_addr_t ram_addr) +{ + HWPoisonPage *page; + + QLIST_FOREACH(page, &hwpoison_page_list, list) { + if (page->ram_addr == ram_addr) { + return; + } + } + page = g_new(HWPoisonPage, 1); + page->ram_addr = ram_addr; + QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); +} + static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size) { #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) @@ -2031,6 +2065,8 @@ static int kvm_init(MachineState *ms) goto err; } + qemu_register_reset(kvm_unpoison_all, NULL); + if (machine_kernel_irqchip_allowed(ms)) { kvm_irqchip_create(ms, s); } diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h index ac2d1f8b56..c660a70c51 100644 --- a/include/sysemu/kvm_int.h +++ b/include/sysemu/kvm_int.h @@ -42,4 +42,16 @@ void kvm_memory_listener_register(KVMState *s, KVMMemoryListener *kml, AddressSpace *as, int as_id); void kvm_set_max_memslot_size(hwaddr max_slot_size); + +/** + * kvm_hwpoison_page_add: + * + * Parameters: + * @ram_addr: the address in the RAM for the poisoned page + * + * Add a poisoned page to the list + * + * Return: None. + */ +void kvm_hwpoison_page_add(ram_addr_t ram_addr); #endif diff --git a/target/i386/kvm.c b/target/i386/kvm.c index bfd09bd441..d8f2507a8d 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -24,7 +24,6 @@ #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm_int.h" -#include "sysemu/reset.h" #include "sysemu/runstate.h" #include "kvm_i386.h" #include "hyperv.h" @@ -521,40 +520,6 @@ uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) } } - -typedef struct HWPoisonPage { - ram_addr_t ram_addr; - QLIST_ENTRY(HWPoisonPage) list; -} HWPoisonPage; - -static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list = - QLIST_HEAD_INITIALIZER(hwpoison_page_list); - -static void kvm_unpoison_all(void *param) -{ - HWPoisonPage *page, *next_page; - - QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { - QLIST_REMOVE(page, list); - qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); - g_free(page); - } -} - -static void kvm_hwpoison_page_add(ram_addr_t ram_addr) -{ - HWPoisonPage *page; - - QLIST_FOREACH(page, &hwpoison_page_list, list) { - if (page->ram_addr == ram_addr) { - return; - } - } - page = g_new(HWPoisonPage, 1); - page->ram_addr = ram_addr; - QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); -} - static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, int *max_banks) { @@ -2157,7 +2122,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s) fprintf(stderr, "e820_add_entry() table is full\n"); return ret; } - qemu_register_reset(kvm_unpoison_all, NULL); shadow_mem = machine_kvm_shadow_mem(ms); if (shadow_mem != -1) { From patchwork Mon Nov 11 01:40:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11236417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D078415AB for ; Mon, 11 Nov 2019 01:44:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D130204EC for ; Mon, 11 Nov 2019 01:44:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726889AbfKKBo3 (ORCPT ); Sun, 10 Nov 2019 20:44:29 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6180 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726754AbfKKBo3 (ORCPT ); Sun, 10 Nov 2019 20:44:29 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 26D6ED92E432D6C92DF2; Mon, 11 Nov 2019 09:44:26 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Mon, 11 Nov 2019 09:44:18 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , CC: , Subject: [RESEND PATCH v21 5/6] target-arm: kvm64: handle SIGBUS signal from kernel or KVM Date: Mon, 11 Nov 2019 09:40:47 +0800 Message-ID: <20191111014048.21296-6-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> References: <20191111014048.21296-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Dongjiu Geng Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type, translates the host VA delivered by host to guest PA, then fills this PA to guest APEI GHES memory, then notifies guest according to the SIGBUS type. When guest accesses the poisoned memory, it will generate a Synchronous External Abort(SEA). Then host kernel gets an APEI notification and calls memory_failure() to unmapped the affected page in stage 2, finally returns to guest. Guest continues to access the PG_hwpoison page, it will trap to KVM as stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to Qemu, Qemu records this error address into guest APEI GHES memory and notifes guest using Synchronous-External-Abort(SEA). In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function in which we can setup the type of exception and the syndrome information. When switching to guest, the target vcpu will jump to the synchronous external abort vector table entry. The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is not valid and hold an UNKNOWN value. These values will be set to KVM register structures through KVM_SET_ONE_REG IOCTL. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng Reviewed-by: Michael S. Tsirkin --- hw/acpi/acpi_ghes.c | 297 ++++++++++++++++++++++++++++++++++++ include/hw/acpi/acpi_ghes.h | 4 + include/sysemu/kvm.h | 3 +- target/arm/cpu.h | 4 + target/arm/helper.c | 2 +- target/arm/internals.h | 5 +- target/arm/kvm64.c | 64 ++++++++ target/arm/tlb_helper.c | 2 +- target/i386/cpu.h | 2 + 9 files changed, 377 insertions(+), 6 deletions(-) diff --git a/hw/acpi/acpi_ghes.c b/hw/acpi/acpi_ghes.c index 42c00ff3d3..f5b54990c0 100644 --- a/hw/acpi/acpi_ghes.c +++ b/hw/acpi/acpi_ghes.c @@ -39,6 +39,34 @@ /* The max size in bytes for one error block */ #define ACPI_GHES_MAX_RAW_DATA_LENGTH 0x1000 +/* + * The total size of Generic Error Data Entry + * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data, + * Table 18-343 Generic Error Data Entry + */ +#define ACPI_GHES_DATA_LENGTH 72 + +/* + * The memory section CPER size, + * UEFI 2.6: N.2.5 Memory Error Section + */ +#define ACPI_GHES_MEM_CPER_LENGTH 80 + +/* + * Masks for block_status flags + */ +#define ACPI_GEBS_UNCORRECTABLE 1 + +/* + * Values for error_severity field + */ +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + /* * Now only support ARMv8 SEA notification type error source */ @@ -49,6 +77,16 @@ */ #define ACPI_GHES_SOURCE_GENERIC_ERROR_V2 10 +#define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ + {{{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ + ((b) >> 8) & 0xff, (b) & 0xff, \ + ((c) >> 8) & 0xff, (c) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } } + +#define UEFI_CPER_SEC_PLATFORM_MEM \ + UUID_BE(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83, \ + 0xED, 0x7C, 0x83, 0xB1) + /* * | +--------------------------+ 0 * | | Header | @@ -77,6 +115,174 @@ typedef struct AcpiGhesState { uint64_t ghes_addr_le; } AcpiGhesState; +/* + * Total size for Generic Error Status Block + * ACPI 6.2: 18.3.2.7.1 Generic Error Data, + * Table 18-380 Generic Error Status Block + */ +#define ACPI_GHES_GESB_SIZE 20 +/* The offset of Data Length in Generic Error Status Block */ +#define ACPI_GHES_GESB_DATA_LENGTH_OFFSET 12 + +/* + * Record the value of data length for each error status block to avoid getting + * this value from guest. + */ +static uint32_t acpi_ghes_data_length[ACPI_GHES_ERROR_SOURCE_COUNT]; + +/* + * Generic Error Data Entry + * ACPI 6.1: 18.3.2.7.1 Generic Error Data + */ +static void acpi_ghes_generic_error_data(GArray *table, QemuUUID section_type, + uint32_t error_severity, uint16_t revision, + uint8_t validation_bits, uint8_t flags, + uint32_t error_data_length, QemuUUID fru_id, + uint8_t *fru_text, uint64_t time_stamp) +{ + QemuUUID uuid_le; + + /* Section Type */ + uuid_le = qemu_uuid_bswap(section_type); + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); + + /* Error Severity */ + build_append_int_noprefix(table, error_severity, 4); + /* Revision */ + build_append_int_noprefix(table, revision, 2); + /* Validation Bits */ + build_append_int_noprefix(table, validation_bits, 1); + /* Flags */ + build_append_int_noprefix(table, flags, 1); + /* Error Data Length */ + build_append_int_noprefix(table, error_data_length, 4); + + /* FRU Id */ + uuid_le = qemu_uuid_bswap(fru_id); + g_array_append_vals(table, uuid_le.data, ARRAY_SIZE(uuid_le.data)); + + /* FRU Text */ + g_array_append_vals(table, fru_text, 20); + /* Timestamp */ + build_append_int_noprefix(table, time_stamp, 8); +} + +/* + * Generic Error Status Block + * ACPI 6.1: 18.3.2.7.1 Generic Error Data + */ +static void acpi_ghes_generic_error_status(GArray *table, uint32_t block_status, + uint32_t raw_data_offset, uint32_t raw_data_length, + uint32_t data_length, uint32_t error_severity) +{ + /* Block Status */ + build_append_int_noprefix(table, block_status, 4); + /* Raw Data Offset */ + build_append_int_noprefix(table, raw_data_offset, 4); + /* Raw Data Length */ + build_append_int_noprefix(table, raw_data_length, 4); + /* Data Length */ + build_append_int_noprefix(table, data_length, 4); + /* Error Severity */ + build_append_int_noprefix(table, error_severity, 4); +} + +/* UEFI 2.6: N.2.5 Memory Error Section */ +static void acpi_ghes_build_append_mem_cper(GArray *table, + uint64_t error_physical_addr) +{ + /* + * Memory Error Record + */ + + /* Validation Bits */ + build_append_int_noprefix(table, + (1UL << 14) | /* Type Valid */ + (1UL << 1) /* Physical Address Valid */, + 8); + /* Error Status */ + build_append_int_noprefix(table, 0, 8); + /* Physical Address */ + build_append_int_noprefix(table, error_physical_addr, 8); + /* Skip all the detailed information normally found in such a record */ + build_append_int_noprefix(table, 0, 48); + /* Memory Error Type */ + build_append_int_noprefix(table, 0 /* Unknown error */, 1); + /* Skip all the detailed information normally found in such a record */ + build_append_int_noprefix(table, 0, 7); +} + +static int acpi_ghes_record_mem_error(uint64_t error_block_address, + uint64_t error_physical_addr, + uint32_t data_length) +{ + GArray *block; + uint64_t current_block_length; + /* Memory Error Section Type */ + QemuUUID mem_section_id_le = UEFI_CPER_SEC_PLATFORM_MEM; + QemuUUID fru_id = {}; + uint8_t fru_text[20] = {}; + + /* + * Generic Error Status Block + * | +---------------------+ + * | | block_status | + * | +---------------------+ + * | | raw_data_offset | + * | +---------------------+ + * | | raw_data_length | + * | +---------------------+ + * | | data_length | + * | +---------------------+ + * | | error_severity | + * | +---------------------+ + */ + block = g_array_new(false, true /* clear */, 1); + + /* The current whole length of the generic error status block */ + current_block_length = ACPI_GHES_GESB_SIZE + data_length; + + /* This is the length if adding a new generic error data entry*/ + data_length += ACPI_GHES_DATA_LENGTH; + data_length += ACPI_GHES_MEM_CPER_LENGTH; + + /* + * Check whether it will run out of the preallocated memory if adding a new + * generic error data entry + */ + if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return ACPI_GHES_CPER_FAIL; + } + + /* Build the new generic error status block header */ + acpi_ghes_generic_error_status(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE), + 0, 0, cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE)); + + /* Write back above generic error status block header to guest memory */ + cpu_physical_memory_write(error_block_address, block->data, + block->len); + + /* Add a new generic error data entry */ + + data_length = block->len; + /* Build this new generic error data entry header */ + acpi_ghes_generic_error_data(block, mem_section_id_le, + cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300), 0, 0, + cpu_to_le32(ACPI_GHES_MEM_CPER_LENGTH), fru_id, fru_text, 0); + + /* Build the memory section CPER for above new generic error data entry */ + acpi_ghes_build_append_mem_cper(block, error_physical_addr); + + /* Write back above this new generic error data entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + block->data + data_length, block->len - data_length); + + g_array_free(block, true); + + return ACPI_GHES_CPER_OK; +} + /* * Hardware Error Notification * ACPI 4.0: 17.3.2.7 Hardware Error Notification @@ -265,3 +471,94 @@ void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, NULL, &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); } + +bool acpi_ghes_record_errors(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr, read_ack_register_addr, read_ack_register = 0; + int loop = 0; + uint64_t start_addr = le64_to_cpu(ges.ghes_addr_le); + bool ret = ACPI_GHES_CPER_FAIL; + uint8_t source_id; + const uint8_t error_source_id[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0, 0xff, 0xff, 0xff}; + + /* + * | +---------------------+ ges.ghes_addr_le + * | |error_block_address0 | + * | +---------------------+ --+-- + * | | ............. | ACPI_GHES_ADDRESS_SIZE + * | +---------------------+ --+-- + * | |error_block_addressN | + * | +---------------------+ + * | | read_ack_register0 | + * | +---------------------+ --+-- + * | | ............. | ACPI_GHES_ADDRESS_SIZE + * | +---------------------+ --+-- + * | | read_ack_registerN | + * | +---------------------+ --+-- + * | | CPER | | + * | | .... | ACPI_GHES_MAX_RAW_DATA_LENGT + * | | CPER | | + * | +---------------------+ --+-- + * | | .......... | + * | +---------------------+ + * | | CPER | + * | | .... | + * | | CPER | + * | +---------------------+ + */ + if (physical_address && notify < ACPI_GHES_NOTIFY_RESERVED) { + /* Find and check the source id for this new CPER */ + source_id = error_source_id[notify]; + if (source_id != 0xff) { + start_addr += source_id * ACPI_GHES_ADDRESS_SIZE; + } else { + goto out; + } + + cpu_physical_memory_read(start_addr, &error_block_addr, + ACPI_GHES_ADDRESS_SIZE); + + read_ack_register_addr = start_addr + + ACPI_GHES_ERROR_SOURCE_COUNT * ACPI_GHES_ADDRESS_SIZE; +retry: + cpu_physical_memory_read(read_ack_register_addr, + &read_ack_register, ACPI_GHES_ADDRESS_SIZE); + + /* zero means OSPM does not acknowledge the error */ + if (!read_ack_register) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("OSPM does not acknowledge previous error," + " so can not record CPER for current error, forcibly" + " acknowledge previous error to avoid blocking next time" + " CPER record! Exit"); + read_ack_register = 1; + cpu_physical_memory_write(read_ack_register_addr, + &read_ack_register, ACPI_GHES_ADDRESS_SIZE); + } + } else { + if (error_block_addr) { + read_ack_register = 0; + /* + * Clear the Read Ack Register, OSPM will write it to 1 when + * acknowledge this error. + */ + cpu_physical_memory_write(read_ack_register_addr, + &read_ack_register, ACPI_GHES_ADDRESS_SIZE); + ret = acpi_ghes_record_mem_error(error_block_addr, + physical_address, acpi_ghes_data_length[source_id]); + if (ret == ACPI_GHES_CPER_OK) { + acpi_ghes_data_length[source_id] += + (ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH); + } + } + } + } + +out: + return ret; +} diff --git a/include/hw/acpi/acpi_ghes.h b/include/hw/acpi/acpi_ghes.h index cb62ec9c7b..8e3c5b879e 100644 --- a/include/hw/acpi/acpi_ghes.h +++ b/include/hw/acpi/acpi_ghes.h @@ -24,6 +24,9 @@ #include "hw/acpi/bios-linker-loader.h" +#define ACPI_GHES_CPER_OK 1 +#define ACPI_GHES_CPER_FAIL 0 + /* * Values for Hardware Error Notification Type field */ @@ -53,4 +56,5 @@ void acpi_ghes_build_hest(GArray *table_data, GArray *hardware_error, void acpi_ghes_build_error_table(GArray *hardware_errors, BIOSLinker *linker); void acpi_ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool acpi_ghes_record_errors(uint32_t notify, uint64_t error_physical_addr); #endif diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 9d143282bc..321ead8115 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -378,8 +378,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id); /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */ unsigned long kvm_arch_vcpu_id(CPUState *cpu); -#ifdef TARGET_I386 -#define KVM_HAVE_MCE_INJECTION 1 +#ifdef KVM_HAVE_MCE_INJECTION void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d844ea21d8..c4fe6ccc63 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -28,6 +28,10 @@ /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) +#ifdef TARGET_AARCH64 +#define KVM_HAVE_MCE_INJECTION 1 +#endif + #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 diff --git a/target/arm/helper.c b/target/arm/helper.c index 63815fc4cf..a9ce97efb1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3005,7 +3005,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * Report exception with ESR indicating a fault due to a * translation table walk for a cache maintenance instruction. */ - syn = syn_data_abort_no_iss(current_el == target_el, + syn = syn_data_abort_no_iss(current_el == target_el, 0, fi.ea, 1, fi.s1ptw, 1, fsc); env->exception.vaddress = value; env->exception.fsr = fsr; diff --git a/target/arm/internals.h b/target/arm/internals.h index f5313dd3d4..28b8451d6d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -451,13 +451,14 @@ static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; } -static inline uint32_t syn_data_abort_no_iss(int same_el, +static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, int ea, int cm, int s1ptw, int wnr, int fsc) { return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; + | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; } static inline uint32_t syn_data_abort_with_iss(int same_el, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 28f6db57d5..c7b7653d3f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -28,6 +28,8 @@ #include "kvm_arm.h" #include "hw/boards.h" #include "internals.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/acpi_ghes.h" static bool have_guest_debug; @@ -710,6 +712,30 @@ int kvm_arm_cpreg_level(uint64_t regidx) return KVM_PUT_RUNTIME_STATE; } +/* Callers must hold the iothread mutex lock */ +static void kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + CPUClass *cc = CPU_GET_CLASS(c); + uint32_t esr; + bool same_el; + + c->exception_index = EXCP_DATA_ABORT; + env->exception.target_el = 1; + + /* + * Set the DFSC to synchronous external abort and set FnV to not valid, + * this will tell guest the FAR_ELx is UNKNOWN for this abort. + */ + same_el = arm_current_el(env) == env->exception.target_el; + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); + + env->exception.syndrome = esr; + + cc->do_interrupt(c); +} + #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) @@ -1036,6 +1062,44 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); + + if (acpi_enabled && addr && + object_property_get_bool(qdev_get_machine(), "ras", NULL)) { + ram_addr = qemu_ram_addr_from_host(addr); + if (ram_addr != RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { + kvm_hwpoison_page_add(ram_addr); + /* + * Asynchronous signal will be masked by main thread, so + * only handle synchronous signal. + */ + if (code == BUS_MCEERR_AR) { + kvm_cpu_synchronize_state(c); + if (ACPI_GHES_CPER_FAIL != + acpi_ghes_record_errors(ACPI_GHES_NOTIFY_SEA, paddr)) { + kvm_inject_arm_sea(c); + } else { + fprintf(stderr, "failed to record the error\n"); + } + } + return; + } + fprintf(stderr, "Hardware memory error for memory used by " + "QEMU itself instead of guest system!\n"); + } + + if (code == BUS_MCEERR_AR) { + fprintf(stderr, "Hardware memory error!\n"); + exit(1); + } +} + /* C6.6.29 BRK instruction */ static const uint32_t brk_insn = 0xd4200000; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 5feb312941..499672ebbc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -33,7 +33,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * ISV field. */ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { - syn = syn_data_abort_no_iss(same_el, + syn = syn_data_abort_no_iss(same_el, 0, ea, 0, s1ptw, is_write, fsc); } else { /* diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5352c9ff55..f75a210f96 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -29,6 +29,8 @@ /* The x86 has a strong memory model with some store-after-load re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#define KVM_HAVE_MCE_INJECTION 1 + /* Maximum instruction code size */ #define TARGET_MAX_INSN_SIZE 16 From patchwork Mon Nov 11 01:40:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiang Zheng X-Patchwork-Id: 11236421 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF1D913BD for ; Mon, 11 Nov 2019 01:44:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8C6D9204EC for ; Mon, 11 Nov 2019 01:44:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726871AbfKKBo2 (ORCPT ); Sun, 10 Nov 2019 20:44:28 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:6177 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726789AbfKKBo1 (ORCPT ); Sun, 10 Nov 2019 20:44:27 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 0D7E8820CD7FDC4E85F3; Mon, 11 Nov 2019 09:44:26 +0800 (CST) Received: from HGHY4Z004218071.china.huawei.com (10.133.224.57) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Mon, 11 Nov 2019 09:44:20 +0800 From: Xiang Zheng To: , , , , , , , , , , , , , , , , CC: , Subject: [RESEND PATCH v21 6/6] MAINTAINERS: Add APCI/APEI/GHES entries Date: Mon, 11 Nov 2019 09:40:48 +0800 Message-ID: <20191111014048.21296-7-zhengxiang9@huawei.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20191111014048.21296-1-zhengxiang9@huawei.com> References: <20191111014048.21296-1-zhengxiang9@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.224.57] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Dongjiu Geng I and Xiang are willing to review the APEI-related patches and volunteer as the reviewers for the APEI/GHES part. Signed-off-by: Dongjiu Geng Signed-off-by: Xiang Zheng --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 325e67a04e..043f7a928e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1414,6 +1414,15 @@ F: tests/bios-tables-test.c F: tests/acpi-utils.[hc] F: tests/data/acpi/ +ACPI/APEI/GHES +R: Dongjiu Geng +R: Xiang Zheng +L: qemu-arm@nongnu.org +S: Maintained +F: hw/acpi/acpi_ghes.c +F: include/hw/acpi/acpi_ghes.h +F: docs/specs/acpi_hest_ghes.rst + ppc4xx M: David Gibson L: qemu-ppc@nongnu.org