From patchwork Mon Nov 11 20:54:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5026017E6 for ; Mon, 11 Nov 2019 20:57:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A1232173B for ; Mon, 11 Nov 2019 20:57:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="d+MjqgYB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727097AbfKKU5M (ORCPT ); Mon, 11 Nov 2019 15:57:12 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:33636 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726965AbfKKU5L (ORCPT ); Mon, 11 Nov 2019 15:57:11 -0500 Received: by mail-lj1-f193.google.com with SMTP id t5so15343944ljk.0; Mon, 11 Nov 2019 12:57:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r/nohohxRUMshQs6j2Da0FE/YxPnOOD2XZg9k5AEvZQ=; b=d+MjqgYBlvBJrc8Jcf9CovJLPhwry8+7PcJUP1QHms45xANHtVvgvfA1MPXW7UiZf9 4HHKtv8oLg07p2QWVAoUTeTlpBq7jSRBERkmz+1dv8xLGTV8/LQk0K5eywhm3CCb+IX0 wpUV6tFH6yVahbVBg40rAVhli206TPnnVHHWcUHqC6L5VDQzljHWhW6HKzCZVC3keVYk DkS27rRbx3/ZOtRfG1pgNShnZfEgtj9MV1t8tuNr4RNWF6ewnUqwVKxwj1qw9qTJzE5f HoktscE6hPFCShDTGjf+5h+jcoTh/X9dMPZ5fxvNeCEDk9LhjEQtNZR1FFcdbikIBDUr uRww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r/nohohxRUMshQs6j2Da0FE/YxPnOOD2XZg9k5AEvZQ=; b=qJWXlsVNbm53CqZhmNtQCTB0PNxzrsgCGwyPRabi3KfmQuOUwVszvsBzjQj6cqinVa eREp83f0PnZeopzdrb30v5s6HfA5sdE8nai5klJOoOY/6xHgSCce8ychEzBejUtEzTKN IYoyY3Ku9/EryIpHC448KcaG9KesWbazQITda83N0v9K2cMpCS68++0FwtXGiAKbtk+Q UOdlstEhnzq6oOuWWmGforqr8ON+3ox3P9qQoG/WTktxPMCKicHnJP8tE9srpTURg8If iRZW6otzvhHmPyYLYmLyT8ZX+6C1nfJw1gr357vVRh+c7SFoV97zueAosRjk63NZdc7h KTdA== X-Gm-Message-State: APjAAAUwfYPOiVsi1xiTvzaw+sNwDL56/jTEDPALItRMREUlEERt61W7 bzIxtey/uebfwoTa5UhjWGo= X-Google-Smtp-Source: APXvYqxBEnhUVWw2j4RDVZgbbw9rwVz2nRII/o0f5IQFygcvvF5m+16VRHTvWD289iiuNEvRC74FyA== X-Received: by 2002:a2e:94d6:: with SMTP id r22mr17340469ljh.7.1573505827793; Mon, 11 Nov 2019 12:57:07 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:07 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/10] clk: tegra: Add custom CCLK implementation Date: Mon, 11 Nov 2019 23:54:10 +0300 Message-Id: <20191111205419.16768-2-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-super-cclk.c | 178 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 11 +- 3 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index df966ca06788..f04b490f5416 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -14,6 +14,7 @@ obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-super-cclk.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c new file mode 100644 index 000000000000..7bcb9e8d0860 --- /dev/null +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on clk-super.c + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Based on older tegra20-cpufreq driver by Colin Cross + * Copyright (C) 2010 Google, Inc. + * + * Author: Dmitry Osipenko + * Copyright (C) 2019 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLLP_INDEX 4 +#define PLLX_INDEX 8 + +#define SUPER_CDIV_ENB BIT(31) + +static u8 cclk_super_get_parent(struct clk_hw *hw) +{ + return tegra_clk_super_ops.get_parent(hw); +} + +static int cclk_super_set_parent(struct clk_hw *hw, u8 index) +{ + return tegra_clk_super_ops.set_parent(hw, index); +} + +static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); +} + +static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (cclk_super_get_parent(hw) == PLLX_INDEX) + return parent_rate; + + return tegra_clk_super_ops.recalc_rate(hw, parent_rate); +} + +static int cclk_super_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *pllp_hw = clk_hw_get_parent_by_index(hw, PLLP_INDEX); + struct clk_hw *pllx_hw = clk_hw_get_parent_by_index(hw, PLLX_INDEX); + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + unsigned long pllp_rate; + long rate = req->rate; + + if (WARN_ON_ONCE(!pllp_hw || !pllx_hw)) + return -EINVAL; + + /* + * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. + * PLLX will be disabled in this case, saving some power. + */ + pllp_rate = clk_hw_get_rate(pllp_hw); + + if (rate <= pllp_rate) { + if (super->flags & TEGRA20_SUPER_CLK) + rate = pllp_rate; + else + rate = tegra_clk_super_ops.round_rate(hw, rate, + &pllp_rate); + + req->best_parent_rate = pllp_rate; + req->best_parent_hw = pllp_hw; + req->rate = rate; + } else { + rate = clk_hw_round_rate(pllx_hw, rate); + req->best_parent_rate = rate; + req->best_parent_hw = pllx_hw; + req->rate = rate; + } + + if (WARN_ON_ONCE(rate <= 0)) + return -EINVAL; + + return 0; +} + +static const struct clk_ops tegra_cclk_super_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .set_rate = cclk_super_set_rate, + .recalc_rate = cclk_super_recalc_rate, + .determine_rate = cclk_super_determine_rate, +}; + +static const struct clk_ops tegra_cclk_super_mux_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .determine_rate = cclk_super_determine_rate, +}; + +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock) +{ + struct tegra_clk_super_mux *super; + struct clk *clk; + struct clk_init_data init; + u32 val; + + super = kzalloc(sizeof(*super), GFP_KERNEL); + if (!super) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + super->reg = reg; + super->lock = lock; + super->width = 4; + super->flags = clk_super_flags; + super->hw.init = &init; + + if (super->flags & TEGRA20_SUPER_CLK) { + init.ops = &tegra_cclk_super_mux_ops; + } else { + init.ops = &tegra_cclk_super_ops; + + super->frac_div.reg = reg + 4; + super->frac_div.shift = 16; + super->frac_div.width = 8; + super->frac_div.frac_width = 1; + super->frac_div.lock = lock; + super->div_ops = &tegra_clk_frac_div_ops; + } + + /* + * Tegra30+ has the following CPUG clock topology: + * + * +---+ +-------+ +-+ +-+ +-+ + * PLLP+->+ +->+DIVIDER+->+0| +-------->+0| ------------->+0| + * | | +-------+ | | | +---+ | | | | | + * PLLC+->+MUX| | +->+ | S | | +->+ | +->+CPU + * ... | | | | | | K | | | | +-------+ | | + * PLLX+->+-->+------------>+1| +->+ I +->+1| +->+ DIV2 +->+1| + * +---+ +++ | P | +++ |SKIPPER| +++ + * ^ | P | ^ +-------+ ^ + * | | E | | | + * PLLX_SEL+--+ | R | | OVERHEAT+--+ + * +---+ | + * | + * SUPER_CDIV_ENB+--+ + * + * Tegra20 is similar, but simpler. It doesn't have the divider and + * thermal DIV2 skipper. + * + * At least for now we're not going to use clock-skipper, hence let's + * ensure that it is disabled. + */ + val = readl_relaxed(reg + 4); + val &= ~SUPER_CDIV_ENB; + writel_relaxed(val, reg + 4); + + clk = clk_register(NULL, &super->hw); + if (IS_ERR(clk)) + kfree(super); + + return clk; +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 416a6b09f6a3..ee35a847df08 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -729,8 +729,10 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates * that this is LP cluster clock. * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5 - * super mux parent using PLLP branches. To use PLLP branches to CPU, need - * to configure additional bit PLLP_OUT_CPU in the clock registers. + * super mux parent using PLLP branches. To use PLLP branches to CPU, need + * to configure additional bit PLLP_OUT_CPU in the clock registers. + * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super + * clocks, it only has a clock-skipper. */ struct tegra_clk_super_mux { struct clk_hw hw; @@ -748,6 +750,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) #define TEGRA210_CPU_CLK BIT(1) +#define TEGRA20_SUPER_CLK BIT(2) extern const struct clk_ops tegra_clk_super_ops; struct clk *tegra_clk_register_super_mux(const char *name, @@ -758,6 +761,10 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Mon Nov 11 20:54:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CAE015AB for ; Mon, 11 Nov 2019 20:57:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EEE4121E6F for ; Mon, 11 Nov 2019 20:57:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ePuXH4N1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727143AbfKKU5N (ORCPT ); Mon, 11 Nov 2019 15:57:13 -0500 Received: from mail-lf1-f67.google.com ([209.85.167.67]:46358 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727069AbfKKU5N (ORCPT ); Mon, 11 Nov 2019 15:57:13 -0500 Received: by mail-lf1-f67.google.com with SMTP id o65so7271367lff.13; Mon, 11 Nov 2019 12:57:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y0gNszD0ptBgrgfqARNo4dCfpARXgUJI1xW2pH1mNqQ=; b=ePuXH4N1diUNfpdEHjC9xzRvSYlc1Z2ire9MqkX4ns2BE2JVkJTu5JWE6LFVtNjQZ+ Oe5balXFPDLkGxD62J0RPKxuqHFURPpCvSnoMI27YBKIOOMGKkTBR+CuD3kcK9vgp3Vd inUP8Y2tXOP7ejLmvaC4Vf+aSNX459QAvlWts7UEY2lS0eWFv++8+EQN9jjfQF1/yllF zZMFovb+jCS3nUcpXAotQ6BusRdzxDR/yCx4oqGxlOdL11Lru723/S2rWv3e63SxorkE 7g+Bzy591ZIjYbHXpWLPDSaCWsjgQXaOm8s0/ubsUYD6JiU/PAOgSRn0xBPeXPI+lHmq MoSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y0gNszD0ptBgrgfqARNo4dCfpARXgUJI1xW2pH1mNqQ=; b=rv+/V3OC20T2OWohMEZ4ZhiIRe3z3AJEzrCmIHkHOBjuD80J6TiO9DUxi80A0xGLKu 0RdpCGIBWP0IRlIwwPFG65GgbB6JPfyEjUBjwmQaXWYlv5hpKHrcI9STyCNgP1pdFbVE SpolOMTBFU7cD7OjPXWZtrevUSz/BDjA5GYNsBSp6xFfALhmQGANm/78WaTlCOvJ39uH T/rpsnc2YGbyIRHzRo1fEjvfkjT1RQCqA8Jp4Nh7mnHMwxv7XFtAgTs4Ae7rmlBrujQl TR9cKYU3vMuj2UotqVVlxDxvxTn2IwbF9bKW2SLeOib1jM/nWYnePMlBmfkuc+7MU9vN 7fwg== X-Gm-Message-State: APjAAAVd0fLl8ABo2uyo8ZcDzEpm5YpTG2QqxOL3x0R53yU4soa639vx 2bX6Cz2230XJeXKH5EEfUTM= X-Google-Smtp-Source: APXvYqzEsLhupYbrzzQr5Cy19ftT2seWidKiJlHrMOknEraImZcfvcmPrtB6SJXzm0t+AwCTUfkAdg== X-Received: by 2002:ac2:5097:: with SMTP id f23mr16777817lfm.90.1573505828934; Mon, 11 Nov 2019 12:57:08 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:08 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/10] clk: tegra: pll: Add pre/post rate-change hooks Date: Mon, 11 Nov 2019 23:54:11 +0300 Message-Id: <20191111205419.16768-3-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 12 +++++++++++- drivers/clk/tegra/clk.h | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 531c2b3d814e..0b212cf2e794 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, state = clk_pll_is_enabled(hw); + if (state && pll->params->pre_rate_change) { + ret = pll->params->pre_rate_change(); + if (WARN_ON(ret)) + return ret; + } + _get_pll_mnp(pll, &old_cfg); if (state && pll->params->defaults_set && pll->params->dyn_ramp && (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { ret = pll->params->dyn_ramp(pll, cfg); if (!ret) - return 0; + goto done; } if (state) { @@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, pll_clk_start_ss(pll); } +done: + if (state && pll->params->post_rate_change) + pll->params->post_rate_change(); + return ret; } diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ee35a847df08..fa18bef914af 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -266,6 +266,10 @@ struct tegra_clk_pll; * disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. + * @pre_rate_change: Callback which is invoked just before changing + * PLL's rate. + * @post_rate_change: Callback which is invoked right after changing + * PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -342,6 +346,8 @@ struct tegra_clk_pll_params { void (*set_defaults)(struct tegra_clk_pll *pll); int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg); + int (*pre_rate_change)(void); + void (*post_rate_change)(void); }; #define TEGRA_PLL_USE_LOCK BIT(0) From patchwork Mon Nov 11 20:54:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2873815AB for ; Mon, 11 Nov 2019 20:57:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0676521783 for ; Mon, 11 Nov 2019 20:57:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZkINMQoi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727028AbfKKU5r (ORCPT ); Mon, 11 Nov 2019 15:57:47 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:39254 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726916AbfKKU5M (ORCPT ); Mon, 11 Nov 2019 15:57:12 -0500 Received: by mail-lf1-f68.google.com with SMTP id j14so2365790lfk.6; Mon, 11 Nov 2019 12:57:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pG9lXccv0oOEUJTH/gOp3aikTwBYEJL3+x/Tztb4ZXo=; b=ZkINMQoiT/jCLcB/Il6D7tp13igrBaOrQmFWZ/9dIP4MutQdUT2AKJpNyQTyZ5Q5EW rMnGETQBf/e5bo95mmdlVyUooaNbYYWwuERpY36dfI6JdPcuoLUozMspHwxJIiShTcpC 0FIALRAq/js8RsbEDZItkDJLSnPRqsqkgyvx2Xl9YB0KSoKe0s6xdWLPdXOrietuKXBQ M5jlXvHTu0YB+6FqnBI40Si87W/93go0tnzNasghoUzmZtUoGx7j0K/4HQNdSwOKJYBh XhCvstrYDjEwVUQ2p7OXxMPsKvDDh+qshYgEqwG+lIVq59uNL+tR8JHM6aZV0eN7msjA nyaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pG9lXccv0oOEUJTH/gOp3aikTwBYEJL3+x/Tztb4ZXo=; b=ElwESIv2iYkLveEkmHxrXvozyR05LYhDT8159G6BHnEOJKP7V854kZMhvDij3k0td+ /gEU1Mb89mfPC+tkFUd8c5FrDBtfComsSUPO+uC9d1BacnsW3FLhbTLPQxfozx9CRdUI YnDydh6t1XdrG3XDt6cqDOBVVlIBAZYbuU6Q1P6TNMjYMNiwW0EiXTdHlnwQrKpcM22j AL+7KvmQasE9zMUn4GawI31wo0G+zvP7RHSz/CTK100sTpHhqm7cOZ19a9neubdiEVyb Nz3FYZvJLr1xq2HSCvwtyrA5TYlwG2tGoaY6vEMEcopT8flC4Bs8D1VUOi2BFiSydZWR wFnA== X-Gm-Message-State: APjAAAW5F5fz4hBMX4iTPY1fDzXt7qh32Mx7S2jaIwJwimj+/0X07qUk Rk707WpRWuliIJuH42G1L/YikiD7 X-Google-Smtp-Source: APXvYqyTLvaW2jX9fnIpBh+CACwUJYXd1X6vSzrQ2vWpCHoS0b+gPFRz9R5AOCf5ttzmw8HybM0GZA== X-Received: by 2002:a19:ae02:: with SMTP id f2mr7206530lfc.54.1573505830112; Mon, 11 Nov 2019 12:57:10 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:09 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/10] clk: tegra: cclk: Add helpers for handling PLLX rate changes Date: Mon, 11 Nov 2019 23:54:12 +0300 Message-Id: <20191111205419.16768-4-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 7bcb9e8d0860..a03119c30456 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,9 @@ #define SUPER_CDIV_ENB BIT(31) +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; + static u8 cclk_super_get_parent(struct clk_hw *hw) { return tegra_clk_super_ops.get_parent(hw); @@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, struct clk_init_data init; u32 val; + if (WARN_ON(cclk_super)) + return ERR_PTR(-EBUSY); + super = kzalloc(sizeof(*super), GFP_KERNEL); if (!super) return ERR_PTR(-ENOMEM); @@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk = clk_register(NULL, &super->hw); if (IS_ERR(clk)) kfree(super); + else + cclk_super = super; return clk; } + +int tegra_cclk_pre_pllx_rate_change(void) +{ + if (IS_ERR_OR_NULL(cclk_super)) + return -EINVAL; + + if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX) + cclk_on_pllx = true; + else + cclk_on_pllx = false; + + /* + * CPU needs to be temporarily re-parented away from PLLX if PLLX + * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. + */ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX); + + return 0; +} + +void tegra_cclk_post_pllx_rate_change(void) +{ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fa18bef914af..0afe28f4372b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change(void); +void tegra_cclk_post_pllx_rate_change(void); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Mon Nov 11 20:54:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237753 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3973B17E6 for ; Mon, 11 Nov 2019 20:57:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 178E321783 for ; Mon, 11 Nov 2019 20:57:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QU7GT4Gn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727196AbfKKU5Q (ORCPT ); Mon, 11 Nov 2019 15:57:16 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:37999 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727148AbfKKU5P (ORCPT ); Mon, 11 Nov 2019 15:57:15 -0500 Received: by mail-lf1-f66.google.com with SMTP id q28so10976142lfa.5; Mon, 11 Nov 2019 12:57:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CbLJtKoWfGlhZ2yYzvSNqEKgjc0Cow8QnHrPe+s4dKk=; b=QU7GT4Gn4qhqAjo+x7iJ2aVKPQoxU2QNQTAbTOzCbEaWc8mvrRV5YLJ537xB7tCBjI 5OgNdEUqKVEZYOuXglKODAY4Nn/smNHy7u2yoiO37Ua9pKo3dXXgDoMTRYL9RM4ETCqt CI1ehLDJjGpUy4tAiKq9WlC/YdePFA02h4n9j3bTvGJGyJR0HWXlWMylIrklLwfBN8Ef 1Le3Qz50U1i64dor4sGIAcdpNbUbM7LZzAlJwaRhI3n/luzmBqc391ovuLSMqOMtmWEI HGi+UmBz/rdyJEKJXmLw0E4UJjW8KLMpC+gKayxvIn41SUYrTMEoA2Uhy7aeHtvEaO2U ylyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CbLJtKoWfGlhZ2yYzvSNqEKgjc0Cow8QnHrPe+s4dKk=; b=ZI2VUyj7niqFksiaiwsPP/BcW6a5YLAyDwL8StUif10Yy/Rz44lghfjtGMzKJLBHf7 M19RCGiDOsbV39OI4v5YigTK5nn3C6bGoP7M/syyLHsu+FeVHwMV32ta6dh25cDiAALI zezYTAdbyIjDE3/SxcUnJpcP+WOuH9nUan4GmVJsM9KHa9JeK/0HR07RE3U9O0oOT0DH BYbG3Iyzgd/cvRkmTZmOHPsa8Quy3cW2qhSCyyOjO7lunlG+7X4zuYyzH/kyJAC9TWW7 j1Dr0x/PiZGQtaIgKCXFXcoz1T/GraTfhiLzREvdco+WeFrUPORTF5Bdrh3883VTqggs o38Q== X-Gm-Message-State: APjAAAXjIyrT5sfQt4xz8sqwwYiyWnGqOxU3MjDuyBuQ4EV9TUHZb/XW 1iDuDcGmVvr40IF15SmshyQ= X-Google-Smtp-Source: APXvYqzZeL6DOiXbgybhMH87aKuaIctavA3yanUheLeZSqDTvQPBpkJpcdJM8kBBvfGaJyzqDjLalg== X-Received: by 2002:a19:911c:: with SMTP id t28mr16229971lfd.84.1573505831297; Mon, 11 Nov 2019 12:57:11 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:10 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/10] clk: tegra20: Use custom CCLK implementation Date: Mon, 11 Nov 2019 23:54:13 +0300 Message-Id: <20191111205419.16768-5-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 4d8222f5c638..eb821666ca61 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params = { @@ -704,9 +706,10 @@ static void tegra20_super_clk_init(void) struct clk *clk; /* CCLK */ - clk = tegra_clk_register_super_mux("cclk", cclk_parents, + clk = tegra_clk_register_super_cclk("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, - clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, + NULL); clks[TEGRA20_CLK_CCLK] = clk; /* SCLK */ From patchwork Mon Nov 11 20:54:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2825715AB for ; Mon, 11 Nov 2019 20:57:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 04A372084F for ; Mon, 11 Nov 2019 20:57:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JN4lPrst" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727238AbfKKU5R (ORCPT ); Mon, 11 Nov 2019 15:57:17 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:41282 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727128AbfKKU5O (ORCPT ); Mon, 11 Nov 2019 15:57:14 -0500 Received: by mail-lf1-f65.google.com with SMTP id j14so10951755lfb.8; Mon, 11 Nov 2019 12:57:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oZXgBiZ7YOkoGyisWeubyUkOPcMd11xlE2xTsIL1hcs=; b=JN4lPrste717s/4AQdu1jc1YIYNtZXuqu5CWkhLocrAQX9wq1Z9uWmTwoPG3n0KTDd 2RnHc82t6mkhZVFE2o2Jdy6YiFfJcqlBhyynKaDmjSRlBWJ2j+gDC59FWpCtMl6Ff5f7 vwwnbetoVoQgl98Jwp/bT8OwArU3ewDOVum4hKLf/OmfETeFjH649L9ctPpk21FcfDTB HoagzqDt+LmEsLwBzxwd8Qif+T5zWId5zfj5vGQqbdZ6ZcB3XbVeNcByhQ1EOWFzPvfF vf4iDSD/AL1OMEzEfJbLyhmhKqgYD5SVgxWUHv3x7jvWfeodCf/5mlrmrTtY+zeXIhXZ Gogw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oZXgBiZ7YOkoGyisWeubyUkOPcMd11xlE2xTsIL1hcs=; b=FMZBuVcbk9vNfvlElknv7G2IS7j3nY2vn8POF3OzfD0eYrCjkiu7kKu0zPzOfffpOZ w+NhxJfuYzrnzLsj3tm8LA1JkhSJuCLL9IVgtcT/4di+IQpt4ZD6BPuVoWrYQxsNOOth 7fwpZlfpxDCf2H9YQDBHEh4H5Fz7Ay8AdJhwpbX25b1ajRkXOSeqpDjn1wH9wlZ7wiXy ZC0TRi3e3fnlvBeaVN66Fw8pdjecKYbyrGwJ+YcImHKQbVq/SnPJnx00+E8koJY/Thga 3wYj+GjarjCAHjfSujO0mVFEJXMsOYnEmV1qGHXqmHGc8PXyA9mvjMW68i3W1IRguNEZ pIrw== X-Gm-Message-State: APjAAAUG7JBb5iFivfGHa6ure1yjfI3pcODrUr0I7G3rt9czWnsU8fuB 8gC7AUy1C2i4MBUCyJUS9iA= X-Google-Smtp-Source: APXvYqxRsfVaocdlSi5pMhGFrip887n9pCvGiTBOokLkS0zGZq+wSp+5cS7302YNUSziBslKQS3jMA== X-Received: by 2002:a19:4314:: with SMTP id q20mr16210252lfa.146.1573505832319; Mon, 11 Nov 2019 12:57:12 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:11 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/10] clk: tegra30: Use custom CCLK implementation Date: Mon, 11 Nov 2019 23:54:14 +0300 Message-Id: <20191111205419.16768-6-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index c8bc18e4d7e5..0fe03d69fe1a 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params __ro_after_init = { @@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void) clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); /* CCLKG */ - clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, + clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, - 0, 4, 0, 0, NULL); + 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; /* From patchwork Mon Nov 11 20:54:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2E2F417E6 for ; Mon, 11 Nov 2019 20:57:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 020E4206BB for ; Mon, 11 Nov 2019 20:57:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y16K0lf1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727226AbfKKU5R (ORCPT ); Mon, 11 Nov 2019 15:57:17 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:36234 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727151AbfKKU5P (ORCPT ); Mon, 11 Nov 2019 15:57:15 -0500 Received: by mail-lj1-f194.google.com with SMTP id k15so15326887lja.3; Mon, 11 Nov 2019 12:57:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UXRoHcvapztDcfGo7L2UwrKkYpLR6LIFA1LRvGGCLHM=; b=Y16K0lf1r0c5r7b0QZvjXDo856Bo2h0g3Vx8rA5ctOptD5GgpVn8RFRS7zHiQ8OQTW uLflg/MGAAckyQa6JdkhIr6QF/nbwGWVVVDY37UYqeDCgaWp4xbYTFbB/9+TQO8o7MRx o/y6DlTOmqv93+bt8jBGi4hm3X/UY8m+AGoQfJU/5v2u4/kA+d5X1WHqWnjQGiv07Y/p SFTmYN2AUM3MZqgtorAttIIpuSFGUvQ5oW7fzjkNlZMEA1F0qZcpsHVz7rVGY87aCHVx UUTsWi5NaiBQQ92aPO72QOm5q6xLuqFe/Y/TAjT2owFCAlqV2Uy6tzmT4OvNGdxWwBXz s7UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UXRoHcvapztDcfGo7L2UwrKkYpLR6LIFA1LRvGGCLHM=; b=nOBGOwhXSFsVBIsqFpzbl+zUKFY/nsfA1XkOH48NNEOzXxPMMFeZur4QqArekiUm0D gR3mIJ7M4EdczhTKeTojkVpTFkUyHuTVc3EhNUTmXhPvpLuUDlkYycmRBmfFOGXzgXPy 0II5TyzKzLydV6B0YeoEeTZuYho1D10MiUSSPsL6w3YbrukUuytSpeC2VwHJGLRwz8jm fJpIH34Py/vpIXQg9xoHxc0Rc4maWLZnk1vHkiEZIapEyqhjbVahbSMerKlvbvwW4bsU 6EQ8hVgRdCqIHUeA7xpp4au2DloXV9spZaphmrnOTvLpQxZfaoK+ed3j4ldMu+BTXAe6 UM/Q== X-Gm-Message-State: APjAAAU9pa3CKfnm1Poz+8oONRlZqOMpJPC1+MMspF1OKapZlVmqpfGC Ohld0wE69Evd7sjNtpeUtd0= X-Google-Smtp-Source: APXvYqyn0cx5YoyDXdIo5U0gzTbcs7JM4k2XHDa0/67O1r+p7CJ1LHcpUtT9Brf+sl4f6ssDZ8fRAQ== X-Received: by 2002:a2e:8855:: with SMTP id z21mr3588643ljj.212.1573505833382; Mon, 11 Nov 2019 12:57:13 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:12 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/10] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Mon, 11 Nov 2019 23:54:15 +0300 Message-Id: <20191111205419.16768-7-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs. Acked-by: Viresh Kumar Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..daeca6ae6b76 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + }; From patchwork Mon Nov 11 20:54:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BB0131864 for ; Mon, 11 Nov 2019 20:57:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 820D72196E for ; Mon, 11 Nov 2019 20:57:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="q5OVJZBW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727181AbfKKU5i (ORCPT ); Mon, 11 Nov 2019 15:57:38 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:44213 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727068AbfKKU5S (ORCPT ); Mon, 11 Nov 2019 15:57:18 -0500 Received: by mail-lj1-f196.google.com with SMTP id g3so15277412ljl.11; Mon, 11 Nov 2019 12:57:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w/eIjSCuG/Q7ryfJxSdCgpDMZ/8kVniI/DVsUoUGS7o=; b=q5OVJZBW5Ky23eT6pPh5xn1LGuDzI0YSDSg8TCPzq3DCgh9GK0vr1ZkaoqC8yVW3bA PwctTjhCngQP8xGW1u8JZBrtbU7z06WaOJRth86V7CPFPEzWnUsglWzNgdj2wC8L7R+O DJ2w4QsyttB15rN1KFEdIWe1tn51E9XQmR/E69x8TIb/f3LA7Yl4xp7rXqpk9NdSrOUz Pn8P228/d8CxmjDmA5FlTLH4UCcg5Knt/Tl8s0Mfy7tSJs5KJNe7o69jmrDrQyVqA0J9 qrtGDKj8wYE9pYYYZ+ZMIFTXOwFJ1sznfS7YREPDskuTy1wjvHRolj4FA4HN9R2Crj+f T45A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w/eIjSCuG/Q7ryfJxSdCgpDMZ/8kVniI/DVsUoUGS7o=; b=hAcOI1xGInJviuxdUPSB6BYBpGy74CVfYVSLH5MPYWy+Wk2kGw/h9m4qf67GhA9E1a GxU6OZly3EHy98DxJf0naPppSjLQqRtJ43klKD1Mo1ARO583/CK0eZOqp7rx7x6fLnVO 3yT2ZH6IwAs3RjLPolxXJrc7+rnoeypts68EoMczqBrfU53Wrs9Ug15XHERYHM8AEMAl 4OXzRX73KdjsLu2U0GMJxxkjMbQMUX0Hvuuk6mJlruzvlQsNgmsGm4vSHWVLTu3rMqIv tCrRz0Cms0Jl/nW4FDoYcqQnWYVashvU5SgM1FBQRqrJAo7WuaEsc6ZjUhLBMWUr/PAS tTsw== X-Gm-Message-State: APjAAAVNxSvKJE0EH/sEM186/KsyifWPZYvqkQ/Z/gWiBhIU7oLC5tgC crdPgG3V80Cz4YqWVfnR92M= X-Google-Smtp-Source: APXvYqxCt1O88q3sCehYUCdkH+hqxY32LugQ8KWN1bdmohpJVsUAjJmLcQh6kCTNDuj1+edG7h7IeQ== X-Received: by 2002:a2e:9bc3:: with SMTP id w3mr18350431ljj.94.1573505834530; Mon, 11 Nov 2019 12:57:14 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:14 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/10] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Date: Mon, 11 Nov 2019 23:54:16 +0300 Message-Id: <20191111205419.16768-8-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/tegra20-cpufreq.c | 217 +++++++-------------------- 3 files changed, 61 insertions(+), 164 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 3858d86cf409..92a6a5089979 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ default y config ARM_TEGRA20_CPUFREQ - tristate "Tegra20 CPUFreq support" - depends on ARCH_TEGRA + tristate "Tegra20/30 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help - This adds the CPUFreq driver support for Tegra20 SOCs. + This adds the CPUFreq driver support for Tegra20/30 SOCs. config ARM_TEGRA124_CPUFREQ bool "Tegra124 CPUFreq support" diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index f1d170dcf4d3..aba591d57c67 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -121,6 +121,8 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt8176", }, { .compatible = "mediatek,mt8183", }, + { .compatible = "nvidia,tegra20", }, + { .compatible = "nvidia,tegra30", }, { .compatible = "nvidia,tegra124", }, { .compatible = "nvidia,tegra210", }, diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index f84ecd22f488..8c893043953e 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -7,201 +7,96 @@ * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation */ -#include -#include +#include +#include #include #include #include +#include #include +#include #include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; - -struct tegra20_cpufreq { - struct device *dev; - struct cpufreq_driver driver; - struct clk *cpu_clk; - struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; -}; +#include +#include -static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, - unsigned int index) +static bool cpu0_node_has_opp_v2_prop(void) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - - /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq - */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) - return 0; - - return ifreq; -} + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; -static int tegra_target_intermediate(struct cpufreq_policy *policy, - unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; - - /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. - */ - clk_prepare_enable(cpufreq->pll_x_clk); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) - clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + if (of_get_property(np, "operating-points-v2", NULL)) + ret = true; + of_node_put(np); return ret; } -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - int ret; - - /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. - */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ - if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); - - /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. - */ - if (cpufreq->pll_x_prepared) { - clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; - } - - return ret; -} - -static int tegra_cpu_init(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_prepare_enable(cpufreq->cpu_clk); - - /* FIXME: what's the actual transition time? */ - cpufreq_generic_init(policy, freq_table, 300 * 1000); - policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; - return 0; -} - -static int tegra_cpu_exit(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_disable_unprepare(cpufreq->cpu_clk); - return 0; -} - static int tegra20_cpufreq_probe(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq; + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; + struct device *cpu_dev; + u32 versions[2]; int err; - cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); - if (!cpufreq) - return -ENOMEM; + if (!cpu0_node_has_opp_v2_prop()) { + dev_err(&pdev->dev, "operating points not found\n"); + dev_err(&pdev->dev, "please update your device tree\n"); + return -ENODEV; + } + + if (of_machine_is_compatible("nvidia,tegra20")) { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.soc_speedo_id); + } else { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.cpu_speedo_id); + } + + dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n", + versions[0], versions[1]); - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + cpu_dev = get_cpu_device(0); + if (WARN_ON(!cpu_dev)) + return -ENODEV; - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(cpufreq->pll_x_clk)) { - err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(&pdev->dev, "failed to set supported hw: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + err = PTR_ERR_OR_ZERO(cpufreq_dt); + if (err) { + dev_err(&pdev->dev, + "failed to create cpufreq-dt device: %d\n", err); + goto err_put_supported_hw; } - cpufreq->dev = &pdev->dev; - cpufreq->driver.get = cpufreq_generic_get; - cpufreq->driver.attr = cpufreq_generic_attr; - cpufreq->driver.init = tegra_cpu_init; - cpufreq->driver.exit = tegra_cpu_exit; - cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; - cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; - cpufreq->driver.suspend = cpufreq_generic_suspend; - cpufreq->driver.driver_data = cpufreq; - cpufreq->driver.target_index = tegra_target; - cpufreq->driver.get_intermediate = tegra_get_intermediate; - cpufreq->driver.target_intermediate = tegra_target_intermediate; - snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra"); - - err = cpufreq_register_driver(&cpufreq->driver); - if (err) - goto put_pll_p; - - platform_set_drvdata(pdev, cpufreq); + platform_set_drvdata(pdev, cpufreq_dt); return 0; -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); +err_put_supported_hw: + dev_pm_opp_put_supported_hw(opp_table); return err; } static int tegra20_cpufreq_remove(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev); + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; - cpufreq_unregister_driver(&cpufreq->driver); + cpufreq_dt = platform_get_drvdata(pdev); + platform_device_unregister(cpufreq_dt); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); + opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0)); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_opp_table(opp_table); return 0; } From patchwork Mon Nov 11 20:54:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67EB217E6 for ; Mon, 11 Nov 2019 20:57:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 452CF206BA for ; Mon, 11 Nov 2019 20:57:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pedissdr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727281AbfKKU5T (ORCPT ); Mon, 11 Nov 2019 15:57:19 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:39745 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727069AbfKKU5S (ORCPT ); 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[94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:15 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/10] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Date: Mon, 11 Nov 2019 23:54:17 +0300 Message-Id: <20191111205419.16768-9-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..1e3b85923ca3 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -95,6 +95,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Mon Nov 11 20:54:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237735 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BD95E17E6 for ; Mon, 11 Nov 2019 20:57:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9B993206BA for ; Mon, 11 Nov 2019 20:57:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UvEClIcN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727433AbfKKU52 (ORCPT ); Mon, 11 Nov 2019 15:57:28 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:45192 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727279AbfKKU5U (ORCPT ); Mon, 11 Nov 2019 15:57:20 -0500 Received: by mail-lj1-f195.google.com with SMTP id n21so15301203ljg.12; Mon, 11 Nov 2019 12:57:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7wI6f4nvMYsmBCMp+G12GdGK/taTCqKZ+wxQzPpgr3A=; b=UvEClIcN8WZ8RnOeSljmPiqtYRldJCcTvniINhrz4IZH9F5gKt1n3zylNvgNoqYjbm WUXvGEbe1YxJvnJm+dtM38/3CLrL/HrI6b04AeDMtgnfY8X5aAYtyNmllm7C1jcZpuhn NXwLaizPHXXg0W9Ro+fVA76dQcGkRcGLULdK/rbmvbVpA1Qy0jYC0X1hvL8SbiAYxVuC uMkujfWuemoMzd6QBbZB5jSGLlQ6idyUGf/BXpE7XLe692vApPgyco+baKWVTEIVL3ud eDnfBcYMl3DzU7CHrhr+sSCg5Bm4D3fc/VR7k2AXcLrdyPnuO/NIKQ+U9ywvS03oFl9l Qw1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7wI6f4nvMYsmBCMp+G12GdGK/taTCqKZ+wxQzPpgr3A=; b=mq4lh0uWqv79Daj/0fn13d612kBteLAZawJc+PIFfqS5pIh5G+mxA0mgfqewKQJ1ph 9YIsFCh6F1FSs0xXd4Uzuhq+SQcwCrcHSuu3LbUqaDd5zDt9BHscx7LKk7KEx9MS+dpo aOWxG3C2cHx3U+45Kkj+yLAaRDRlU+5ppzXETBd+W5xk7V7mutiKdwIKLDRM5PWPPKe7 jRMACGL5KxwVv2pxyLwH4553ZIrT3hMGYhbntTfDMzaiVVs1yzQ8PBd5cWY2iZP7Ql3q Trgv8yHMZtARK1WabHiXkPZRQMTXXhWn5T8gZNeavKr0RUrHqs5DLiNakojQJRruzsYI Wh7Q== X-Gm-Message-State: APjAAAVWzXmkJhd/G1hX5bM3PJIEn4zAZFDWsFyohnPs/1Jyciq7DG8B cmX+cvrbrcnC3QWS6aIdViM= X-Google-Smtp-Source: APXvYqx0AE7hJku7PB19jg39VXRzfIicaXFKyo3DiPAN1a5bI5RuU2L4MoDgdh2eE83w1Gq86Gcbfg== X-Received: by 2002:a2e:b5b8:: with SMTP id f24mr17180281ljn.188.1573505836788; Mon, 11 Nov 2019 12:57:16 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:16 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/10] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Date: Mon, 11 Nov 2019 23:54:18 +0300 Message-Id: <20191111205419.16768-10-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Set min/max voltage and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a3b0f3555cd2..6ebb3105af9e 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,9 +1806,14 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1873,22 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; From patchwork Mon Nov 11 20:54:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11237729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4451417E6 for ; Mon, 11 Nov 2019 20:57:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 20A3D217F9 for ; Mon, 11 Nov 2019 20:57:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qOXt9iKF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727453AbfKKU52 (ORCPT ); Mon, 11 Nov 2019 15:57:28 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:40153 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727148AbfKKU5U (ORCPT ); Mon, 11 Nov 2019 15:57:20 -0500 Received: by mail-lj1-f196.google.com with SMTP id q2so15324889ljg.7; Mon, 11 Nov 2019 12:57:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEJ200kbZVTsss1iDk6Wt5qRmYYgbTDuf+N828TJE+4=; b=qOXt9iKFr6xDFBoRl5SK08VLRff6TgxB2rYOoxCnGnD9ts6+XwNII6M3acbMna2hdm rtmkqVd7RqhlKm74cDnJ33qNeeB4Lt0lZ2LjKmOfYqoV6VLIO/sdSC2Q98+4SMLuYYdw I4CsKrhL2tFpd533/RmENck9GGLadx3xITeW9TUtnFNM3CdVcrAVhRfQ6+ykzRRhG0ix 5g+dphPPoJVHJXb8pYHuRuyvvRKDeip0NFFjrz5oQhztZpQHjEpvL76UkQm0AS8OLE/9 NhT21CVpE1HY/46aqLg9AqaxoT+HawSuOpPm2RB49eLgU6SdgQNzhJuZFPZ8m9PHb6yu HEUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEJ200kbZVTsss1iDk6Wt5qRmYYgbTDuf+N828TJE+4=; b=aDu+ghao32Tn1uGuj+u0+tlbuSX/JfgZ3KebArLJCaBPUOxUcMqRVkquL8Pkp7e78Y JmVQwx4WSvhsIpmbXC4I8FD5X5jjVosUQuGl/q6VvKJ+0duzQaF5p0boHksEDatYryLR MqTQvorjHELwfW6ckGF01XC1+ploWtR61zp4H6jprbyLML+8mn4Vs89o6qLu/C3vQFEi QoqoX5b9+YEmmvuKdRGq3whhB+dXV4EYRuqgyuaruy0rJW4SVtvbMjBGJaXzvGIk0unX 2kb+W1za2HLRmb9ri2Y8whcSDfWWDe0iDpmgYu8ScWkHEuNIaHVEb1laVIaemM++2pXS ni6A== X-Gm-Message-State: APjAAAXQdcE1HmXO+uiCClrFEEfsk4rXHEKb6qG969gLAeqEOjgGWN44 zidd/vd01i+0A4YKjnr4fDc= X-Google-Smtp-Source: APXvYqw7eSx5xIx3Pz7djTsqEWoIjJUneZL+QJcwMA6cb31frF+zzEu5E30djLMcC9WQg50DT+3ngw== X-Received: by 2002:a2e:b5d0:: with SMTP id g16mr17898135ljn.88.1573505837820; Mon, 11 Nov 2019 12:57:17 -0800 (PST) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id q124sm7423784ljq.93.2019.11.11.12.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2019 12:57:17 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/10] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Date: Mon, 11 Nov 2019 23:54:19 +0300 Message-Id: <20191111205419.16768-11-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191111205419.16768-1-digetx@gmail.com> References: <20191111205419.16768-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6ebb3105af9e..86556622be25 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -2124,4 +2126,26 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };