From patchwork Tue Nov 12 21:22:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240237 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50D4D13BD for ; Tue, 12 Nov 2019 21:24:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BC1121A49 for ; Tue, 12 Nov 2019 21:24:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="FUejoVzJ"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="BDe91L9n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727349AbfKLVXJ (ORCPT ); Tue, 12 Nov 2019 16:23:09 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:38614 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726936AbfKLVXI (ORCPT ); Tue, 12 Nov 2019 16:23:08 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2D65E60A1D; Tue, 12 Nov 2019 21:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593786; bh=L2q2tmLEBoegKjRUZwnmR0udPzMRG0BJ8jdF13VfroI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FUejoVzJCEU2ryL0KqPeX6SBiMSDT8GOwT+O2dmQKJMHoBUDn0xcapyBd0jNjv8Lf AS1qVdBAPb6vZc+dv3hVCYpde92G/Bxg0/EodNMze1AY/oV7bdzEqsjIq6ylcEvy9G xOcBlvaMkRQgIdKDMRTq+lo5mbE7DS16sAVQ4H18= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F25BC60595; Tue, 12 Nov 2019 21:23:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593783; bh=L2q2tmLEBoegKjRUZwnmR0udPzMRG0BJ8jdF13VfroI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BDe91L9nPwIktTmn/0glOVAkBkfKo5JFEfcTcbUYd13orv9I05Dsh85WLpP5o4u+5 gPaaqcrPzMKyhpmSeJjcA1Zz0Pc8+7hvZRDD/okZBshsgOR+UC6WYawNe90loIFj6M 1WqSDJqiIEjqktrWmOEqFdoIZDjzV2zxyspnw++o= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F25BC60595 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/18] firmware: qcom_scm: Rename macros and structures Date: Tue, 12 Nov 2019 13:22:37 -0800 Message-Id: <1573593774-12539-2-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename legacy-specific structures and macros with legacy prefix; rename smccc-specific structures and macros with smccc prefix. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-32.c | 70 ++++++++++++++++++++++-------------------- drivers/firmware/qcom_scm-64.c | 53 ++++++++++++++++---------------- 2 files changed, 64 insertions(+), 59 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index bee8729..5d52641 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2010,2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. */ @@ -39,22 +39,22 @@ static struct qcom_scm_entry qcom_scm_wb[] = { static DEFINE_MUTEX(qcom_scm_lock); /** - * struct qcom_scm_command - one SCM command buffer + * struct qcom_scm_legacy_command - one SCM command buffer * @len: total available memory for command and response * @buf_offset: start of command buffer * @resp_hdr_offset: start of response buffer * @id: command to be executed - * @buf: buffer returned from qcom_scm_get_command_buffer() + * @buf: buffer returned from legacy_get_command_buffer() * * An SCM command is laid out in memory as follows: * - * ------------------- <--- struct qcom_scm_command + * ------------------- <--- struct qcom_scm_legacy_command * | command header | - * ------------------- <--- qcom_scm_get_command_buffer() + * ------------------- <--- legacy_get_command_buffer() * | command buffer | - * ------------------- <--- struct qcom_scm_response and - * | response header | qcom_scm_command_to_response() - * ------------------- <--- qcom_scm_get_response_buffer() + * ------------------- <--- struct qcom_scm_legacy_response and + * | response header | legacy_command_to_response() + * ------------------- <--- legacy_get_response_buffer() * | response buffer | * ------------------- * @@ -62,7 +62,7 @@ static DEFINE_MUTEX(qcom_scm_lock); * you should always use the appropriate qcom_scm_get_*_buffer() routines * to access the buffers in a safe manner. */ -struct qcom_scm_command { +struct qcom_scm_legacy_command { __le32 len; __le32 buf_offset; __le32 resp_hdr_offset; @@ -71,52 +71,55 @@ struct qcom_scm_command { }; /** - * struct qcom_scm_response - one SCM response buffer + * struct qcom_scm_legacy_response - one SCM response buffer * @len: total available memory for response - * @buf_offset: start of response data relative to start of qcom_scm_response + * @buf_offset: start of response data relative to start of + * qcom_scm_legacy_response * @is_complete: indicates if the command has finished processing */ -struct qcom_scm_response { +struct qcom_scm_legacy_response { __le32 len; __le32 buf_offset; __le32 is_complete; }; /** - * qcom_scm_command_to_response() - Get a pointer to a qcom_scm_response + * legacy_command_to_response() - Get a pointer to a qcom_scm_legacy_response * @cmd: command * * Returns a pointer to a response for a command. */ -static inline struct qcom_scm_response *qcom_scm_command_to_response( - const struct qcom_scm_command *cmd) +static inline struct qcom_scm_legacy_response *legacy_command_to_response( + const struct qcom_scm_legacy_command *cmd) { return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset); } /** - * qcom_scm_get_command_buffer() - Get a pointer to a command buffer + * legacy_get_command_buffer() - Get a pointer to a command buffer * @cmd: command * * Returns a pointer to the command buffer of a command. */ -static inline void *qcom_scm_get_command_buffer(const struct qcom_scm_command *cmd) +static inline void *legacy_get_command_buffer( + const struct qcom_scm_legacy_command *cmd) { return (void *)cmd->buf; } /** - * qcom_scm_get_response_buffer() - Get a pointer to a response buffer + * legacy_get_response_buffer() - Get a pointer to a response buffer * @rsp: response * * Returns a pointer to a response buffer of a response. */ -static inline void *qcom_scm_get_response_buffer(const struct qcom_scm_response *rsp) +static inline void *legacy_get_response_buffer( + const struct qcom_scm_legacy_response *rsp) { return (void *)rsp + le32_to_cpu(rsp->buf_offset); } -static u32 smc(u32 cmd_addr) +static u32 __qcom_scm_call_do(u32 cmd_addr) { int context_id; register u32 r0 asm("r0") = 1; @@ -164,8 +167,8 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, size_t resp_len) { int ret; - struct qcom_scm_command *cmd; - struct qcom_scm_response *rsp; + struct qcom_scm_legacy_command *cmd; + struct qcom_scm_legacy_response *rsp; size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len; dma_addr_t cmd_phys; @@ -179,9 +182,9 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, cmd->id = cpu_to_le32((svc_id << 10) | cmd_id); if (cmd_buf) - memcpy(qcom_scm_get_command_buffer(cmd), cmd_buf, cmd_len); + memcpy(legacy_get_command_buffer(cmd), cmd_buf, cmd_len); - rsp = qcom_scm_command_to_response(cmd); + rsp = legacy_command_to_response(cmd); cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE); if (dma_mapping_error(dev, cmd_phys)) { @@ -190,7 +193,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, } mutex_lock(&qcom_scm_lock); - ret = smc(cmd_phys); + ret = __qcom_scm_call_do(cmd_phys); if (ret < 0) ret = qcom_scm_remap_error(ret); mutex_unlock(&qcom_scm_lock); @@ -206,7 +209,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + le32_to_cpu(rsp->buf_offset), resp_len, DMA_FROM_DEVICE); - memcpy(resp_buf, qcom_scm_get_response_buffer(rsp), + memcpy(resp_buf, legacy_get_response_buffer(rsp), resp_len); } out: @@ -215,11 +218,12 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, return ret; } -#define SCM_CLASS_REGISTER (0x2 << 8) -#define SCM_MASK_IRQS BIT(5) -#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \ - SCM_CLASS_REGISTER | \ - SCM_MASK_IRQS | \ +#define LEGACY_CLASS_REGISTER (0x2 << 8) +#define LEGACY_MASK_IRQS BIT(5) +#define LEGACY_ATOMIC_ID(svc, cmd, n) \ + (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \ + LEGACY_CLASS_REGISTER | \ + LEGACY_MASK_IRQS | \ (n & 0xf)) /** @@ -235,7 +239,7 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) { int context_id; - register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1); + register u32 r0 asm("r0") = LEGACY_ATOMIC_ID(svc, cmd, 1); register u32 r1 asm("r1") = (u32)&context_id; register u32 r2 asm("r2") = arg1; @@ -268,7 +272,7 @@ static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) { int context_id; - register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2); + register u32 r0 asm("r0") = LEGACY_ATOMIC_ID(svc, cmd, 2); register u32 r1 asm("r1") = (u32)&context_id; register u32 r2 asm("r2") = arg1; register u32 r3 asm("r3") = arg2; diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 7686786..8226b94 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved. */ #include @@ -14,7 +14,7 @@ #include "qcom_scm.h" -#define QCOM_SCM_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) +#define SMCCC_FUNCNUM(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) #define MAX_QCOM_SCM_ARGS 10 #define MAX_QCOM_SCM_RETS 3 @@ -58,11 +58,11 @@ static DEFINE_MUTEX(qcom_scm_lock); #define QCOM_SCM_EBUSY_WAIT_MS 30 #define QCOM_SCM_EBUSY_MAX_RETRY 20 -#define N_EXT_QCOM_SCM_ARGS 7 -#define FIRST_EXT_ARG_IDX 3 -#define N_REGISTER_ARGS (MAX_QCOM_SCM_ARGS - N_EXT_QCOM_SCM_ARGS + 1) +#define SMCCC_N_EXT_ARGS 7 +#define SMCCC_FIRST_EXT_IDX 3 +#define SMCCC_N_REG_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_EXT_ARGS + 1) -static void __qcom_scm_call_do(const struct qcom_scm_desc *desc, +static void __qcom_scm_call_do_quirk(const struct qcom_scm_desc *desc, struct arm_smccc_res *res, u32 fn_id, u64 x5, u32 type) { @@ -85,22 +85,23 @@ static void __qcom_scm_call_do(const struct qcom_scm_desc *desc, } while (res->a0 == QCOM_SCM_INTERRUPTED); } -static void qcom_scm_call_do(const struct qcom_scm_desc *desc, +static void qcom_scm_call_do_smccc(const struct qcom_scm_desc *desc, struct arm_smccc_res *res, u32 fn_id, u64 x5, bool atomic) { int retry_count = 0; if (atomic) { - __qcom_scm_call_do(desc, res, fn_id, x5, ARM_SMCCC_FAST_CALL); + __qcom_scm_call_do_quirk(desc, res, fn_id, x5, + ARM_SMCCC_FAST_CALL); return; } do { mutex_lock(&qcom_scm_lock); - __qcom_scm_call_do(desc, res, fn_id, x5, - ARM_SMCCC_STD_CALL); + __qcom_scm_call_do_quirk(desc, res, fn_id, x5, + ARM_SMCCC_STD_CALL); mutex_unlock(&qcom_scm_lock); @@ -112,21 +113,21 @@ static void qcom_scm_call_do(const struct qcom_scm_desc *desc, } while (res->a0 == QCOM_SCM_V2_EBUSY); } -static int ___qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, - const struct qcom_scm_desc *desc, - struct arm_smccc_res *res, bool atomic) +static int ___qcom_scm_call_smccc(struct device *dev, u32 svc_id, u32 cmd_id, + const struct qcom_scm_desc *desc, + struct arm_smccc_res *res, bool atomic) { int arglen = desc->arginfo & 0xf; int i; - u32 fn_id = QCOM_SCM_FNID(svc_id, cmd_id); - u64 x5 = desc->args[FIRST_EXT_ARG_IDX]; + u32 fn_id = SMCCC_FUNCNUM(svc_id, cmd_id); + u64 x5 = desc->args[SMCCC_FIRST_EXT_IDX]; dma_addr_t args_phys = 0; void *args_virt = NULL; size_t alloc_len; gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL; - if (unlikely(arglen > N_REGISTER_ARGS)) { - alloc_len = N_EXT_QCOM_SCM_ARGS * sizeof(u64); + if (unlikely(arglen > SMCCC_N_REG_ARGS)) { + alloc_len = SMCCC_N_EXT_ARGS * sizeof(u64); args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag); if (!args_virt) @@ -135,15 +136,15 @@ static int ___qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, if (qcom_smccc_convention == ARM_SMCCC_SMC_32) { __le32 *args = args_virt; - for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++) + for (i = 0; i < SMCCC_N_EXT_ARGS; i++) args[i] = cpu_to_le32(desc->args[i + - FIRST_EXT_ARG_IDX]); + SMCCC_FIRST_EXT_IDX]); } else { __le64 *args = args_virt; - for (i = 0; i < N_EXT_QCOM_SCM_ARGS; i++) + for (i = 0; i < SMCCC_N_EXT_ARGS; i++) args[i] = cpu_to_le64(desc->args[i + - FIRST_EXT_ARG_IDX]); + SMCCC_FIRST_EXT_IDX]); } args_phys = dma_map_single(dev, args_virt, alloc_len, @@ -157,7 +158,7 @@ static int ___qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, x5 = args_phys; } - qcom_scm_call_do(desc, res, fn_id, x5, atomic); + qcom_scm_call_do_smccc(desc, res, fn_id, x5, atomic); if (args_virt) { dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); @@ -185,7 +186,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, struct arm_smccc_res *res) { might_sleep(); - return ___qcom_scm_call(dev, svc_id, cmd_id, desc, res, false); + return ___qcom_scm_call_smccc(dev, svc_id, cmd_id, desc, res, false); } /** @@ -203,7 +204,7 @@ static int qcom_scm_call_atomic(struct device *dev, u32 svc_id, u32 cmd_id, const struct qcom_scm_desc *desc, struct arm_smccc_res *res) { - return ___qcom_scm_call(dev, svc_id, cmd_id, desc, res, true); + return ___qcom_scm_call_smccc(dev, svc_id, cmd_id, desc, res, true); } /** @@ -253,7 +254,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) struct arm_smccc_res res; desc.arginfo = QCOM_SCM_ARGS(1); - desc.args[0] = QCOM_SCM_FNID(svc_id, cmd_id) | + desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, @@ -295,7 +296,7 @@ void __qcom_scm_init(void) { u64 cmd; struct arm_smccc_res res; - u32 function = QCOM_SCM_FNID(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD); + u32 function = SMCCC_FUNCNUM(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD); /* First try a SMC64 call */ cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, From patchwork Tue Nov 12 21:22:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240239 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9974C1850 for ; Tue, 12 Nov 2019 21:24:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6EF3E21A49 for ; Tue, 12 Nov 2019 21:24:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="OuEO4G52"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="YdsgkKmh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727343AbfKLVXI (ORCPT ); Tue, 12 Nov 2019 16:23:08 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:38632 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727338AbfKLVXI (ORCPT ); Tue, 12 Nov 2019 16:23:08 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C7B3D607EF; Tue, 12 Nov 2019 21:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593787; bh=90NMdFg1vjtq9lQibDoLmx94A8PirCAI6VLa++0Jjlw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OuEO4G52pjaf/0gw37cjWclfbd5/UBU5aCQLIQ5l5HJxABcgmMfnNOxpoMASNomxU CfI8mmMv9qE7I73p0bbBeSqNnlVcRsWdB/b0nJLIWcRtVW+bzV97XCUoSzzX8HoLnB TkrrDoGAo5IXniGsbOH1SAaUmDHnIkzQGIWsqHWI= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 99D0B6087D; Tue, 12 Nov 2019 21:23:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593784; bh=90NMdFg1vjtq9lQibDoLmx94A8PirCAI6VLa++0Jjlw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YdsgkKmhGZ5msn4zf3LrHcWUsqnBPs9gZhVx2WPcxFVTY4aIst9sq1Tw7hvddOF2B ft/gJ+TuYPuK/Ot0ZE61qOP5TmXHqWqA/VygEBZYDf1Q5M8dLS1+/vmiij7b766X23 CLUvngyq2LhYrK0mFqs+NzhMCz7F9KDMiQloZkcw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 99D0B6087D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/18] firmware: qcom_scm: Add funcnum IDs Date: Tue, 12 Nov 2019 13:22:38 -0800 Message-Id: <1573593774-12539-3-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add LEGACY_FUNCNUM to qcom_scm-32.c and move SMCCC_FUNCNUM closer to other smccc-specific macros. Signed-off-by: Elliot Berman Reviewed-by: Stephen Boyd --- drivers/firmware/qcom_scm-32.c | 8 +++++--- drivers/firmware/qcom_scm-64.c | 3 +-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 5d52641..5077fcf 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -38,6 +38,8 @@ static struct qcom_scm_entry qcom_scm_wb[] = { static DEFINE_MUTEX(qcom_scm_lock); +#define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff)) + /** * struct qcom_scm_legacy_command - one SCM command buffer * @len: total available memory for command and response @@ -180,7 +182,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, cmd->buf_offset = cpu_to_le32(sizeof(*cmd)); cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len); - cmd->id = cpu_to_le32((svc_id << 10) | cmd_id); + cmd->id = cpu_to_le32(LEGACY_FUNCNUM(svc_id, cmd_id)); if (cmd_buf) memcpy(legacy_get_command_buffer(cmd), cmd_buf, cmd_len); @@ -221,7 +223,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, #define LEGACY_CLASS_REGISTER (0x2 << 8) #define LEGACY_MASK_IRQS BIT(5) #define LEGACY_ATOMIC_ID(svc, cmd, n) \ - (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \ + ((LEGACY_FUNCNUM(svc, cmd) << 12) | \ LEGACY_CLASS_REGISTER | \ LEGACY_MASK_IRQS | \ (n & 0xf)) @@ -424,7 +426,7 @@ void __qcom_scm_cpu_power_down(u32 flags) int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) { int ret; - __le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id); + __le32 svc_cmd = cpu_to_le32(LEGACY_FUNCNUM(svc_id, cmd_id)); __le32 ret_val = 0; ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 8226b94..de337b3 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -14,8 +14,6 @@ #include "qcom_scm.h" -#define SMCCC_FUNCNUM(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) - #define MAX_QCOM_SCM_ARGS 10 #define MAX_QCOM_SCM_RETS 3 @@ -58,6 +56,7 @@ static DEFINE_MUTEX(qcom_scm_lock); #define QCOM_SCM_EBUSY_WAIT_MS 30 #define QCOM_SCM_EBUSY_MAX_RETRY 20 +#define SMCCC_FUNCNUM(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) #define SMCCC_N_EXT_ARGS 7 #define SMCCC_FIRST_EXT_IDX 3 #define SMCCC_N_REG_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_EXT_ARGS + 1) From patchwork Tue Nov 12 21:22:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB01F1850 for ; Tue, 12 Nov 2019 21:24:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B96920659 for ; Tue, 12 Nov 2019 21:24:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="klrzqtdl"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Gq5VyvLQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727414AbfKLVXO (ORCPT ); Tue, 12 Nov 2019 16:23:14 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:38692 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727365AbfKLVXJ (ORCPT ); Tue, 12 Nov 2019 16:23:09 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8352A60A61; Tue, 12 Nov 2019 21:23:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593788; bh=Bb0bcKAxGO7VWwcNchC7uaDqK22feiPjektT7AJPf8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=klrzqtdlO7jODd4kcGYluOy4J4Mun11IyduDyEjZrodl98oDosKaA+KzuBcKFY/dB D2jQeiuwb5Jn2YS6zC6VXbDRISs5PBYJHJZNpR/bSLnul39gAD/0b2bxgLUEuc4ub2 XdKPJXzpXHBFNA6NGYhpRi/NWagwB6JJNmielm/A= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7C75D607EF; Tue, 12 Nov 2019 21:23:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593785; bh=Bb0bcKAxGO7VWwcNchC7uaDqK22feiPjektT7AJPf8U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gq5VyvLQgBBCQ56IdFCy+sV5yMTn5GNc9GwyouN820JYDmuvN8pGVFCwSfCjGUo/P /KwesPE2Wen4Cl6jaWYgHRfKEvRy9/tUiMg8Eth/+/VSMNcLBkBWAa1n+UhoaLZeBs okd3bg/6aDWHXt9hsUQgWg+xAH51HLA9nvYzeKzw= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7C75D607EF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/18] firmware: qcom_scm-64: Make SMCCC macros less magical Date: Tue, 12 Nov 2019 13:22:39 -0800 Message-Id: <1573593774-12539-4-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Improve understandability of SMCCC macros as they are all functions of how many arguments can be shoved in registers and how many SCM arguments are supported. Signed-off-by: Elliot Berman Reviewed-by: Stephen Boyd --- drivers/firmware/qcom_scm-64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index de337b3..badc245 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -57,9 +57,9 @@ static DEFINE_MUTEX(qcom_scm_lock); #define QCOM_SCM_EBUSY_MAX_RETRY 20 #define SMCCC_FUNCNUM(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) -#define SMCCC_N_EXT_ARGS 7 -#define SMCCC_FIRST_EXT_IDX 3 -#define SMCCC_N_REG_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_EXT_ARGS + 1) +#define SMCCC_N_REG_ARGS 4 +#define SMCCC_FIRST_EXT_IDX (SMCCC_N_REG_ARGS - 1) +#define SMCCC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_REG_ARGS + 1) static void __qcom_scm_call_do_quirk(const struct qcom_scm_desc *desc, struct arm_smccc_res *res, u32 fn_id, From patchwork Tue Nov 12 21:22:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84E0C15AB for ; Tue, 12 Nov 2019 21:24:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A64820659 for ; Tue, 12 Nov 2019 21:24:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="g24Hw2cX"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="JAGvU8DG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727466AbfKLVYL (ORCPT ); Tue, 12 Nov 2019 16:24:11 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39174 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727032AbfKLVXV (ORCPT ); Tue, 12 Nov 2019 16:23:21 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9463460D7D; Tue, 12 Nov 2019 21:23:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593800; bh=tanBwZfnSRKSaEd0iSsROCptX/YCAWwJun+GOLZkApg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g24Hw2cXgwZiq+Q9aaSWM40N5I3sMSuXaGjXEuB/8RnkDRn0WArEOwsd0DmMJbDof WbfuvEElXCk+bxuTKP+vnLDeJLoghmolGge7s+nfs0usD/DsMQf1S9GjgjASGc/jXr /+Le64qxyXiIRuSdIw7gWcvB+AL/Sws94jw4aHug= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 96FF560B69; Tue, 12 Nov 2019 21:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593786; bh=tanBwZfnSRKSaEd0iSsROCptX/YCAWwJun+GOLZkApg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JAGvU8DGQsrrJnFN0JSuLZfJR/o+igc3FL/ERPRGBXibOgjCuFprmlVI+qj1sfJ3l VJ0FEt0vVWZ0XolPkHi7RP+dqJztoQtq1FR+g4GMF7YHay7J0/dD3d7kCwMGSmaI+G hKXGRtIlkGaYb2XPoxYQFL6VCZXmcDcRqrge+JsI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 96FF560B69 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/18] firmware: qcom_scm: Apply consistent naming scheme to command IDs Date: Tue, 12 Nov 2019 13:22:40 -0800 Message-Id: <1573593774-12539-5-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Create a consistent naming scheme for command IDs. The scheme is QCOM_SCM_##svc_##cmd. Remove unused macros QCOM_SCM_FLAG_HLOS, QCOM_SCM_FLAG_COLDBOOT_MC, QCOM_SCM_FLAG_WARMBOOT_MC, QCOM_SCM_CMD_CORE_HOTPLUGGED, and QCOM_SCM_BOOT_ADDR_MC. Reviewed-by: Bjorn Andersson Reviewed-by: Vinod Koul Signed-off-by: Elliot Berman Reviewed-by: Stephen Boyd --- drivers/firmware/qcom_scm-32.c | 28 +++++++++++++-------------- drivers/firmware/qcom_scm-64.c | 38 ++++++++++++++++++------------------- drivers/firmware/qcom_scm.c | 13 +++++-------- drivers/firmware/qcom_scm.h | 43 +++++++++++++++++++----------------------- 4 files changed, 57 insertions(+), 65 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 5077fcf..fca7279 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -360,7 +360,7 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR, flags, virt_to_phys(entry)); } @@ -399,7 +399,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, cmd.addr = cpu_to_le32(virt_to_phys(entry)); cmd.flags = cpu_to_le32(flags); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR, &cmd, sizeof(cmd), NULL, 0); if (!ret) { for_each_cpu(cpu, cpus) @@ -419,7 +419,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, */ void __qcom_scm_cpu_power_down(u32 flags) { - qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC, + qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_TERMINATE_PC, flags & QCOM_SCM_FLUSH_FLAG_MASK); } @@ -429,7 +429,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) __le32 svc_cmd = cpu_to_le32(LEGACY_FUNCNUM(svc_id, cmd_id)); __le32 ret_val = 0; - ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL, &svc_cmd, sizeof(svc_cmd), &ret_val, sizeof(ret_val)); if (ret) @@ -444,7 +444,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) return -ERANGE; - return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, + return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, req, req_cnt * sizeof(*req), resp, sizeof(*resp)); } @@ -460,7 +460,7 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) in = cpu_to_le32(peripheral); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_IS_SUPPORTED_CMD, + QCOM_SCM_PIL_PAS_IS_SUPPORTED, &in, sizeof(in), &out, sizeof(out)); @@ -481,7 +481,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, request.image_addr = cpu_to_le32(metadata_phys); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_INIT_IMAGE_CMD, + QCOM_SCM_PIL_PAS_INIT_IMAGE, &request, sizeof(request), &scm_ret, sizeof(scm_ret)); @@ -504,7 +504,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, request.len = cpu_to_le32(size); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_MEM_SETUP_CMD, + QCOM_SCM_PIL_PAS_MEM_SETUP, &request, sizeof(request), &scm_ret, sizeof(scm_ret)); @@ -519,7 +519,7 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) in = cpu_to_le32(peripheral); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_AUTH_AND_RESET_CMD, + QCOM_SCM_PIL_PAS_AUTH_AND_RESET, &in, sizeof(in), &out, sizeof(out)); @@ -534,7 +534,7 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) in = cpu_to_le32(peripheral); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_SHUTDOWN_CMD, + QCOM_SCM_PIL_PAS_SHUTDOWN, &in, sizeof(in), &out, sizeof(out)); @@ -547,7 +547,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) __le32 in = cpu_to_le32(reset); int ret; - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET, &in, sizeof(in), &out, sizeof(out)); @@ -556,8 +556,8 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { - return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE, - enable ? QCOM_SCM_SET_DLOAD_MODE : 0, 0); + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE, + enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0, 0); } int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) @@ -572,7 +572,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) req.state = cpu_to_le32(state); req.id = cpu_to_le32(id); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE, &req, sizeof(req), &scm_ret, sizeof(scm_ret)); return ret ? : le32_to_cpu(scm_ret); diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index badc245..7de6022 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -256,7 +256,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL, &desc, &res); return ret ? : res.a1; @@ -284,7 +284,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, desc.args[9] = req[4].val; desc.arginfo = QCOM_SCM_ARGS(10); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_CMD_HDCP, &desc, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, &desc, &res); *resp = res.a1; @@ -295,7 +295,7 @@ void __qcom_scm_init(void) { u64 cmd; struct arm_smccc_res res; - u32 function = SMCCC_FUNCNUM(QCOM_SCM_SVC_INFO, QCOM_IS_CALL_AVAIL_CMD); + u32 function = SMCCC_FUNCNUM(QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL); /* First try a SMC64 call */ cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, @@ -320,7 +320,7 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) desc.arginfo = QCOM_SCM_ARGS(1); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_IS_SUPPORTED_CMD, + QCOM_SCM_PIL_PAS_IS_SUPPORTED, &desc, &res); return ret ? false : !!res.a1; @@ -337,7 +337,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, desc.args[1] = metadata_phys; desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_INIT_IMAGE_CMD, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_INIT_IMAGE, &desc, &res); return ret ? : res.a1; @@ -355,7 +355,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, desc.args[2] = size; desc.arginfo = QCOM_SCM_ARGS(3); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MEM_SETUP_CMD, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MEM_SETUP, &desc, &res); return ret ? : res.a1; @@ -371,7 +371,7 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) desc.arginfo = QCOM_SCM_ARGS(1); ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_AUTH_AND_RESET_CMD, + QCOM_SCM_PIL_PAS_AUTH_AND_RESET, &desc, &res); return ret ? : res.a1; @@ -386,7 +386,7 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_SHUTDOWN_CMD, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_SHUTDOWN, &desc, &res); return ret ? : res.a1; @@ -402,7 +402,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) desc.args[1] = 0; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PAS_MSS_RESET, &desc, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET, &desc, &res); return ret ? : res.a1; @@ -418,7 +418,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) desc.args[1] = id; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE, &desc, &res); return ret ? : res.a1; @@ -445,7 +445,7 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, QCOM_SCM_VAL, QCOM_SCM_VAL); ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, - QCOM_MEM_PROT_ASSIGN_ID, + QCOM_SCM_MP_ASSIGN, &desc, &res); return ret ? : res.a1; @@ -461,7 +461,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) desc.args[1] = spare; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_RESTORE_SEC_CFG, + ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG, &desc, &res); return ret ? : res.a1; @@ -478,7 +478,7 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, desc.arginfo = QCOM_SCM_ARGS(1); ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, - QCOM_SCM_IOMMU_SECURE_PTBL_SIZE, &desc, &res); + QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, &desc, &res); if (size) *size = res.a1; @@ -500,7 +500,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, QCOM_SCM_VAL); ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, - QCOM_SCM_IOMMU_SECURE_PTBL_INIT, &desc, &res); + QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, &desc, &res); /* the pg table has been initialized already, ignore the error */ if (ret == -EPERM) @@ -514,11 +514,11 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable) struct qcom_scm_desc desc = {0}; struct arm_smccc_res res; - desc.args[0] = QCOM_SCM_SET_DLOAD_MODE; - desc.args[1] = enable ? QCOM_SCM_SET_DLOAD_MODE : 0; + desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; + desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_DLOAD_MODE, + return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE, &desc, &res); } @@ -558,10 +558,10 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en) struct qcom_scm_desc desc = {0}; struct arm_smccc_res res; - desc.args[0] = QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL; + desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; desc.args[1] = en; desc.arginfo = QCOM_SCM_ARGS(2); return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM, - QCOM_SCM_CONFIG_ERRATA1, &desc, &res); + QCOM_SCM_SMMU_CONFIG_ERRATA1, &desc, &res); } diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index a729e05..72757c5 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1,8 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* - * Qualcomm SCM driver - * - * Copyright (c) 2010,2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. */ #include @@ -142,7 +139,7 @@ bool qcom_scm_hdcp_available(void) return ret; ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, - QCOM_SCM_CMD_HDCP); + QCOM_SCM_HDCP_INVOKE); qcom_scm_clk_disable(); @@ -183,7 +180,7 @@ bool qcom_scm_pas_supported(u32 peripheral) int ret; ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PAS_IS_SUPPORTED_CMD); + QCOM_SCM_PIL_PAS_IS_SUPPORTED); if (ret <= 0) return false; @@ -370,12 +367,12 @@ static void qcom_scm_set_download_mode(bool enable) avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_BOOT, - QCOM_SCM_SET_DLOAD_MODE); + QCOM_SCM_BOOT_SET_DLOAD_MODE); if (avail) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else if (__scm->dload_mode_addr) { ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr, - enable ? QCOM_SCM_SET_DLOAD_MODE : 0); + enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n"); diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index baee744..dfb5db2 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -1,27 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved. */ #ifndef __QCOM_SCM_INT_H #define __QCOM_SCM_INT_H #define QCOM_SCM_SVC_BOOT 0x1 -#define QCOM_SCM_BOOT_ADDR 0x1 -#define QCOM_SCM_SET_DLOAD_MODE 0x10 -#define QCOM_SCM_BOOT_ADDR_MC 0x11 -#define QCOM_SCM_SET_REMOTE_STATE 0xa +#define QCOM_SCM_BOOT_SET_ADDR 0x1 +#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 +#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id); extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable); -#define QCOM_SCM_FLAG_HLOS 0x01 -#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02 -#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04 extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, const cpumask_t *cpus); extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); -#define QCOM_SCM_CMD_TERMINATE_PC 0x2 +#define QCOM_SCM_BOOT_TERMINATE_PC 0x2 #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 -#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10 extern void __qcom_scm_cpu_power_down(u32 flags); #define QCOM_SCM_SVC_IO 0x5 @@ -31,24 +26,24 @@ extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned in extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val); #define QCOM_SCM_SVC_INFO 0x6 -#define QCOM_IS_CALL_AVAIL_CMD 0x1 +#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1 extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id); #define QCOM_SCM_SVC_HDCP 0x11 -#define QCOM_SCM_CMD_HDCP 0x01 +#define QCOM_SCM_HDCP_INVOKE 0x01 extern int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); extern void __qcom_scm_init(void); #define QCOM_SCM_SVC_PIL 0x2 -#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 -#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 -#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5 -#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6 -#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7 -#define QCOM_SCM_PAS_MSS_RESET 0xa +#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1 +#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2 +#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x5 +#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6 +#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7 +#define QCOM_SCM_PIL_PAS_MSS_RESET 0xa extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral); extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, dma_addr_t metadata_phys); @@ -86,21 +81,21 @@ static inline int qcom_scm_remap_error(int err) } #define QCOM_SCM_SVC_MP 0xc -#define QCOM_SCM_RESTORE_SEC_CFG 2 +#define QCOM_SCM_MP_RESTORE_SEC_CFG 2 extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare); -#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3 -#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4 +#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3 +#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4 #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 -#define QCOM_SCM_CONFIG_ERRATA1 0x3 -#define QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL 0x2 +#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3 +#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2 extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, size_t *size); extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, u32 spare); extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable); -#define QCOM_MEM_PROT_ASSIGN_ID 0x16 +#define QCOM_SCM_MP_ASSIGN 0x16 extern int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, size_t mem_sz, phys_addr_t src, size_t src_sz, From patchwork Tue Nov 12 21:22:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240205 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9548315AB for ; Tue, 12 Nov 2019 21:23:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74FBA222BD for ; Tue, 12 Nov 2019 21:23:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="LmHQ9GBk"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Rd9Uo2AY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727438AbfKLVXQ (ORCPT ); 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Tue, 12 Nov 2019 21:23:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593787; bh=bXyBI5AuQffduxbyN6qjv/MoNnBO9v+k9/XvDo2RvcQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Rd9Uo2AYG/3/PoJoJsZHhPEECLMY4XKqVYQ63kdY5UsRszrkFpuS+XpRPZb+BAO// ZQsaso3hqwUfXXvLYryjGQwHfVBCTN+XjJRUD/JPqgiC4OQFnufmcaUR9KuMjXnxGN kwCNkG61itKxthBbYXQDmXVvnEUm9uo2eeljC2NE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DEABA60B7F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/18] firmware: qcom_scm: Remove unused qcom_scm_get_version Date: Tue, 12 Nov 2019 13:22:41 -0800 Message-Id: <1573593774-12539-6-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove unused qcom_scm_get_version. Reviewed-by: Bjorn Andersson Reviewed-by: Vinod Koul Signed-off-by: Elliot Berman Reviewed-by: Stephen Boyd --- drivers/firmware/qcom_scm-32.c | 36 ------------------------------------ include/linux/qcom_scm.h | 2 -- 2 files changed, 38 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index fca7279..e06d59b 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -295,42 +295,6 @@ static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) return r0; } -u32 qcom_scm_get_version(void) -{ - int context_id; - static u32 version = -1; - register u32 r0 asm("r0"); - register u32 r1 asm("r1"); - - if (version != -1) - return version; - - mutex_lock(&qcom_scm_lock); - - r0 = 0x1 << 8; - r1 = (u32)&context_id; - do { - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r1") - __asmeq("%2", "r0") - __asmeq("%3", "r1") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0), "=r" (r1) - : "r" (r0), "r" (r1) - : "r2", "r3", "r12"); - } while (r0 == QCOM_SCM_INTERRUPTED); - - version = r1; - mutex_unlock(&qcom_scm_lock); - - return version; -} -EXPORT_SYMBOL(qcom_scm_get_version); - /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index ffd72b3..c52c591 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -53,7 +53,6 @@ extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt); extern void qcom_scm_cpu_power_down(u32 flags); -extern u32 qcom_scm_get_version(void); extern int qcom_scm_set_remote_state(u32 state, u32 id); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); @@ -92,7 +91,6 @@ static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt) { return -ENODEV; } static inline void qcom_scm_cpu_power_down(u32 flags) {} -static inline u32 qcom_scm_get_version(void) { return 0; } static inline u32 qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; } From patchwork Tue Nov 12 21:22:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240231 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C025013BD for ; Tue, 12 Nov 2019 21:24:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8DDA221D7F for ; Tue, 12 Nov 2019 21:24:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="I+LN/YG0"; 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Tue, 12 Nov 2019 21:23:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593789; bh=TIf68m5LeHPB7X4KWkFF67zI67J/RPqLtDEj+g2WZRk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N3FcRRbFi7btPD09sv3XuLv17rfbgH/H7EqNNJtA491LR8WAFgKjmuaj+H+VJ44I6 DpExtsk0kdGUXNw6G6Y+7+web/tnkwsjU38E8LzXDr861+abbYsuY+fANoAWojkfmd e3WWHmQl70dbIC4LV4pBlBVb/TfMws1yl2EPw/hc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2B21660BFA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/18] firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc Date: Tue, 12 Nov 2019 13:22:42 -0800 Message-Id: <1573593774-12539-7-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Service, command, and owner IDs are all part of qcom_scm_desc struct and have no special reason to be a function argument (or hard-coded in the case of owner). Moving them to be part of qcom_scm_desc struct improves readability. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-64.c | 192 +++++++++++++++++++++++++---------------- 1 file changed, 120 insertions(+), 72 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 7de6022..e81fb6e 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -46,8 +46,11 @@ enum qcom_scm_arg_types { * @res: The values returned by the secure syscall */ struct qcom_scm_desc { + u32 svc; + u32 cmd; u32 arginfo; u64 args[MAX_QCOM_SCM_ARGS]; + u32 owner; }; static u64 qcom_smccc_convention = -1; @@ -62,14 +65,16 @@ static DEFINE_MUTEX(qcom_scm_lock); #define SMCCC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_REG_ARGS + 1) static void __qcom_scm_call_do_quirk(const struct qcom_scm_desc *desc, - struct arm_smccc_res *res, u32 fn_id, - u64 x5, u32 type) + struct arm_smccc_res *res, u64 x5, u32 type) { u64 cmd; struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 }; - cmd = ARM_SMCCC_CALL_VAL(type, qcom_smccc_convention, - ARM_SMCCC_OWNER_SIP, fn_id); + cmd = ARM_SMCCC_CALL_VAL( + type, + qcom_smccc_convention, + desc->owner, + SMCCC_FUNCNUM(desc->svc, desc->cmd)); quirk.state.a6 = 0; @@ -85,22 +90,19 @@ static void __qcom_scm_call_do_quirk(const struct qcom_scm_desc *desc, } static void qcom_scm_call_do_smccc(const struct qcom_scm_desc *desc, - struct arm_smccc_res *res, u32 fn_id, - u64 x5, bool atomic) + struct arm_smccc_res *res, u64 x5, bool atomic) { int retry_count = 0; if (atomic) { - __qcom_scm_call_do_quirk(desc, res, fn_id, x5, - ARM_SMCCC_FAST_CALL); + __qcom_scm_call_do_quirk(desc, res, x5, ARM_SMCCC_FAST_CALL); return; } do { mutex_lock(&qcom_scm_lock); - __qcom_scm_call_do_quirk(desc, res, fn_id, x5, - ARM_SMCCC_STD_CALL); + __qcom_scm_call_do_quirk(desc, res, x5, ARM_SMCCC_STD_CALL); mutex_unlock(&qcom_scm_lock); @@ -112,13 +114,12 @@ static void qcom_scm_call_do_smccc(const struct qcom_scm_desc *desc, } while (res->a0 == QCOM_SCM_V2_EBUSY); } -static int ___qcom_scm_call_smccc(struct device *dev, u32 svc_id, u32 cmd_id, +static int ___qcom_scm_call_smccc(struct device *dev, const struct qcom_scm_desc *desc, struct arm_smccc_res *res, bool atomic) { int arglen = desc->arginfo & 0xf; int i; - u32 fn_id = SMCCC_FUNCNUM(svc_id, cmd_id); u64 x5 = desc->args[SMCCC_FIRST_EXT_IDX]; dma_addr_t args_phys = 0; void *args_virt = NULL; @@ -157,7 +158,7 @@ static int ___qcom_scm_call_smccc(struct device *dev, u32 svc_id, u32 cmd_id, x5 = args_phys; } - qcom_scm_call_do_smccc(desc, res, fn_id, x5, atomic); + qcom_scm_call_do_smccc(desc, res, x5, atomic); if (args_virt) { dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); @@ -180,12 +181,11 @@ static int ___qcom_scm_call_smccc(struct device *dev, u32 svc_id, u32 cmd_id, * Sends a command to the SCM and waits for the command to finish processing. * This should *only* be called in pre-emptible context. */ -static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, - const struct qcom_scm_desc *desc, +static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, struct arm_smccc_res *res) { might_sleep(); - return ___qcom_scm_call_smccc(dev, svc_id, cmd_id, desc, res, false); + return ___qcom_scm_call_smccc(dev, desc, res, false); } /** @@ -199,11 +199,11 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, * Sends a command to the SCM and waits for the command to finish processing. * This can be called in atomic context. */ -static int qcom_scm_call_atomic(struct device *dev, u32 svc_id, u32 cmd_id, +static int qcom_scm_call_atomic(struct device *dev, const struct qcom_scm_desc *desc, struct arm_smccc_res *res) { - return ___qcom_scm_call_smccc(dev, svc_id, cmd_id, desc, res, true); + return ___qcom_scm_call_smccc(dev, desc, res, true); } /** @@ -249,15 +249,18 @@ void __qcom_scm_cpu_power_down(u32 flags) int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_INFO, + .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.arginfo = QCOM_SCM_ARGS(1); desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } @@ -266,7 +269,11 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_HDCP, + .cmd = QCOM_SCM_HDCP_INVOKE, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) @@ -284,8 +291,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, desc.args[9] = req[4].val; desc.arginfo = QCOM_SCM_ARGS(10); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, &desc, - &res); + ret = qcom_scm_call(dev, &desc, &res); *resp = res.a1; return ret; @@ -313,15 +319,17 @@ void __qcom_scm_init(void) bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_IS_SUPPORTED, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? false : !!res.a1; } @@ -330,15 +338,18 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, dma_addr_t metadata_phys) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = peripheral; desc.args[1] = metadata_phys; desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_INIT_IMAGE, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } @@ -347,7 +358,11 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, phys_addr_t addr, phys_addr_t size) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = peripheral; @@ -355,8 +370,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, desc.args[2] = size; desc.arginfo = QCOM_SCM_ARGS(3); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MEM_SETUP, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } @@ -364,15 +378,17 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_AUTH_AND_RESET, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } @@ -380,21 +396,28 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_SHUTDOWN, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; int ret; @@ -402,15 +425,18 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) desc.args[1] = 0; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET, &desc, - &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; int ret; @@ -418,8 +444,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) desc.args[1] = id; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } @@ -429,7 +454,11 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, phys_addr_t dest, size_t dest_sz) { int ret; - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_ASSIGN, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = mem_region; @@ -444,16 +473,18 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, - QCOM_SCM_MP_ASSIGN, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; int ret; @@ -461,8 +492,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) desc.args[1] = spare; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); return ret ? : res.a1; } @@ -470,15 +500,18 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, size_t *size) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; int ret; desc.args[0] = spare; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, - QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); if (size) *size = res.a1; @@ -489,7 +522,11 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, u32 spare) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; int ret; @@ -499,8 +536,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, QCOM_SCM_VAL); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, - QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); /* the pg table has been initialized already, ignore the error */ if (ret == -EPERM) @@ -511,29 +547,35 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE, - &desc, &res); + return qcom_scm_call(dev, &desc, &res); } int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_READ, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; int ret; desc.args[0] = addr; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, - &desc, &res); + ret = qcom_scm_call(dev, &desc, &res); if (ret >= 0) *val = res.a1; @@ -542,26 +584,32 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_WRITE, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = addr; desc.args[1] = val; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, - &desc, &res); + return qcom_scm_call(dev, &desc, &res); } int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en) { - struct qcom_scm_desc desc = {0}; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_SMMU_PROGRAM, + .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, + .owner = ARM_SMCCC_OWNER_SIP, + }; struct arm_smccc_res res; desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; desc.args[1] = en; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM, - QCOM_SCM_SMMU_CONFIG_ERRATA1, &desc, &res); + return qcom_scm_call_atomic(dev, &desc, &res); } From patchwork Tue Nov 12 21:22:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240227 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2739715AB for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bpR7Z4A9ex0SuMJJobfEOZJj78e+qdunru8RQkun5044DT4trUgoiD7I/Uj1nee59 ryQ/ovgLk33YP7kh/N0/G1I72EMRs3FqD5HlaPNHgIAgFRTwyEWIc3zbghBmDJkUbu ZF5CYFACenkn+KE8zn/KVHU8SyaisPpt7z5PhiBM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 631A960CA5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/18] firmware: qcom_scm-64: Add SCM results to descriptor Date: Tue, 12 Nov 2019 13:22:43 -0800 Message-Id: <1573593774-12539-8-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove knowledge of arm_smccc_res struct from client wrappers so that client wrappers only work QCOM SCM data structures. SCM calls may have up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling those 3 arguments accordingly. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-64.c | 105 ++++++++++++++++++----------------------- 1 file changed, 45 insertions(+), 60 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index e81fb6e..f0a5f24 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -50,6 +50,7 @@ struct qcom_scm_desc { u32 cmd; u32 arginfo; u64 args[MAX_QCOM_SCM_ARGS]; + u64 result[MAX_QCOM_SCM_RETS]; u32 owner; }; @@ -115,8 +116,7 @@ static void qcom_scm_call_do_smccc(const struct qcom_scm_desc *desc, } static int ___qcom_scm_call_smccc(struct device *dev, - const struct qcom_scm_desc *desc, - struct arm_smccc_res *res, bool atomic) + struct qcom_scm_desc *desc, bool atomic) { int arglen = desc->arginfo & 0xf; int i; @@ -125,6 +125,7 @@ static int ___qcom_scm_call_smccc(struct device *dev, void *args_virt = NULL; size_t alloc_len; gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL; + struct arm_smccc_res res; if (unlikely(arglen > SMCCC_N_REG_ARGS)) { alloc_len = SMCCC_N_EXT_ARGS * sizeof(u64); @@ -158,15 +159,19 @@ static int ___qcom_scm_call_smccc(struct device *dev, x5 = args_phys; } - qcom_scm_call_do_smccc(desc, res, x5, atomic); + qcom_scm_call_do_smccc(desc, &res, x5, atomic); if (args_virt) { dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); kfree(args_virt); } - if (res->a0 < 0) - return qcom_scm_remap_error(res->a0); + desc->result[0] = res.a1; + desc->result[1] = res.a2; + desc->result[2] = res.a3; + + if (res.a0 < 0) + return qcom_scm_remap_error(res.a0); return 0; } @@ -181,11 +186,10 @@ static int ___qcom_scm_call_smccc(struct device *dev, * Sends a command to the SCM and waits for the command to finish processing. * This should *only* be called in pre-emptible context. */ -static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, - struct arm_smccc_res *res) +static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) { might_sleep(); - return ___qcom_scm_call_smccc(dev, desc, res, false); + return ___qcom_scm_call_smccc(dev, desc, false); } /** @@ -199,11 +203,9 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, * Sends a command to the SCM and waits for the command to finish processing. * This can be called in atomic context. */ -static int qcom_scm_call_atomic(struct device *dev, - const struct qcom_scm_desc *desc, - struct arm_smccc_res *res) +static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) { - return ___qcom_scm_call_smccc(dev, desc, res, true); + return ___qcom_scm_call_smccc(dev, desc, true); } /** @@ -254,15 +256,14 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.arginfo = QCOM_SCM_ARGS(1); desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, @@ -274,7 +275,6 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, .cmd = QCOM_SCM_HDCP_INVOKE, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) return -ERANGE; @@ -291,8 +291,8 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, desc.args[9] = req[4].val; desc.arginfo = QCOM_SCM_ARGS(10); - ret = qcom_scm_call(dev, &desc, &res); - *resp = res.a1; + ret = qcom_scm_call(dev, &desc); + *resp = desc.result[0]; return ret; } @@ -324,14 +324,13 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? false : !!res.a1; + return ret ? false : !!desc.result[0]; } int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, @@ -343,15 +342,14 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = peripheral; desc.args[1] = metadata_phys; desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, @@ -363,16 +361,15 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = peripheral; desc.args[1] = addr; desc.args[2] = size; desc.arginfo = QCOM_SCM_ARGS(3); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) @@ -383,14 +380,13 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) @@ -401,14 +397,13 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = peripheral; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) @@ -418,16 +413,15 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; int ret; desc.args[0] = reset; desc.args[1] = 0; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) @@ -437,16 +431,15 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; int ret; desc.args[0] = state; desc.args[1] = id; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, @@ -459,7 +452,6 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, .cmd = QCOM_SCM_MP_ASSIGN, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = mem_region; desc.args[1] = mem_sz; @@ -473,9 +465,9 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) @@ -485,16 +477,15 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; int ret; desc.args[0] = device_id; desc.args[1] = spare; desc.arginfo = QCOM_SCM_ARGS(2); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); - return ret ? : res.a1; + return ret ? : desc.result[0]; } int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, @@ -505,18 +496,17 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; int ret; desc.args[0] = spare; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); if (size) - *size = res.a1; + *size = desc.result[0]; - return ret ? : res.a2; + return ret ? : desc.result[1]; } int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, @@ -527,7 +517,6 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; int ret; desc.args[0] = addr; @@ -536,7 +525,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, QCOM_SCM_VAL); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); /* the pg table has been initialized already, ignore the error */ if (ret == -EPERM) @@ -552,13 +541,12 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable) .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call(dev, &desc, &res); + return qcom_scm_call(dev, &desc); } int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, @@ -569,15 +557,14 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, .cmd = QCOM_SCM_IO_READ, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; int ret; desc.args[0] = addr; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call(dev, &desc, &res); + ret = qcom_scm_call(dev, &desc); if (ret >= 0) - *val = res.a1; + *val = desc.result[0]; return ret < 0 ? ret : 0; } @@ -589,13 +576,12 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) .cmd = QCOM_SCM_IO_WRITE, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = addr; desc.args[1] = val; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call(dev, &desc, &res); + return qcom_scm_call(dev, &desc); } int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en) @@ -605,11 +591,10 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en) .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, .owner = ARM_SMCCC_OWNER_SIP, }; - struct arm_smccc_res res; desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; desc.args[1] = en; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call_atomic(dev, &desc, &res); + return qcom_scm_call_atomic(dev, &desc); } From patchwork Tue Nov 12 21:22:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240223 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73C5113BD for ; Tue, 12 Nov 2019 21:24:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 538D721A49 for ; Tue, 12 Nov 2019 21:24:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="XFAHHdQA"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="l8pRSzJL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727058AbfKLVXZ (ORCPT ); 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Tue, 12 Nov 2019 21:23:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593791; bh=7eiREBf1RGRjSS3nNlTVOIFdtWUN/TEDxOjP5hvI3eo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l8pRSzJLKGw/IQ9zdCcVchrDo6pNPgvfX/aNyzy8hIuKKyq7pfOXhAXbPUuHeNvAf gK3ub+3e8rpXnMmvlEKEpewfRgMa0o8vgsYqRt9J0gkc8yFhpKXCp6jY2cUZrSclsi p59Dt+pdtqTr1xDuG9WvBvE70nsUZ9l8Sb01r960= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 99B8860D39 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/18] firmware: qcom_scm-64: Remove qcom_scm_call_do_smccc Date: Tue, 12 Nov 2019 13:22:44 -0800 Message-Id: <1573593774-12539-9-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove thin wrapper to qcom_scm_call_do_smccc because it doesn't do enough of anything interesting to dedicate its own function. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-64.c | 46 ++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 26 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index f0a5f24..4131093 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -90,31 +90,6 @@ static void __qcom_scm_call_do_quirk(const struct qcom_scm_desc *desc, } while (res->a0 == QCOM_SCM_INTERRUPTED); } -static void qcom_scm_call_do_smccc(const struct qcom_scm_desc *desc, - struct arm_smccc_res *res, u64 x5, bool atomic) -{ - int retry_count = 0; - - if (atomic) { - __qcom_scm_call_do_quirk(desc, res, x5, ARM_SMCCC_FAST_CALL); - return; - } - - do { - mutex_lock(&qcom_scm_lock); - - __qcom_scm_call_do_quirk(desc, res, x5, ARM_SMCCC_STD_CALL); - - mutex_unlock(&qcom_scm_lock); - - if (res->a0 == QCOM_SCM_V2_EBUSY) { - if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) - break; - msleep(QCOM_SCM_EBUSY_WAIT_MS); - } - } while (res->a0 == QCOM_SCM_V2_EBUSY); -} - static int ___qcom_scm_call_smccc(struct device *dev, struct qcom_scm_desc *desc, bool atomic) { @@ -159,7 +134,26 @@ static int ___qcom_scm_call_smccc(struct device *dev, x5 = args_phys; } - qcom_scm_call_do_smccc(desc, &res, x5, atomic); + if (atomic) { + __qcom_scm_call_do_quirk(desc, &res, x5, ARM_SMCCC_FAST_CALL); + } else { + int retry_count = 0; + + do { + mutex_lock(&qcom_scm_lock); + + __qcom_scm_call_do_quirk(desc, &res, x5, + ARM_SMCCC_STD_CALL); + + mutex_unlock(&qcom_scm_lock); + + if (res.a0 == QCOM_SCM_V2_EBUSY) { + if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY) + break; + msleep(QCOM_SCM_EBUSY_WAIT_MS); + } + } while (res.a0 == QCOM_SCM_V2_EBUSY); + } if (args_virt) { dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE); From patchwork Tue Nov 12 21:22:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68DC315AB for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CNtXo/lCZkD+x/FEKPvJF7lKaSFAEW/yedbwzsbbPOIw5d3JfwITUQnHxakx6hspU UmZTdm18i4+ju0hogIREu7RBHhOniDAPoLNakBI4FgYb7bNG3aOiP6NLcV2wAmllmk D6yBhhCljdT6vQcfMTxwaMap0gWlvytYRmMCQ9UM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A832A60BE6 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/18] firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc Date: Tue, 12 Nov 2019 13:22:45 -0800 Message-Id: <1573593774-12539-10-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcom_scm_call_smccc should be responsible for converting qcom_scm_desc into arguments for smc call. Consolidate the dispersed logic to convert qcom_scm_desc into smc arguments inside qcom_scm_call_smccc. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-64.c | 45 +++++++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 4131093..977654bb 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -54,6 +54,10 @@ struct qcom_scm_desc { u32 owner; }; +struct arm_smccc_args { + unsigned long a[8]; +}; + static u64 qcom_smccc_convention = -1; static DEFINE_MUTEX(qcom_scm_lock); @@ -64,28 +68,24 @@ static DEFINE_MUTEX(qcom_scm_lock); #define SMCCC_N_REG_ARGS 4 #define SMCCC_FIRST_EXT_IDX (SMCCC_N_REG_ARGS - 1) #define SMCCC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_REG_ARGS + 1) +#define SMCCC_FIRST_REG_IDX 2 +#define SMCCC_LAST_REG_IDX (SMCCC_FIRST_REG_IDX + SMCCC_N_REG_ARGS - 1) -static void __qcom_scm_call_do_quirk(const struct qcom_scm_desc *desc, - struct arm_smccc_res *res, u64 x5, u32 type) +static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc, + struct arm_smccc_res *res) { - u64 cmd; + unsigned long a0 = smc->a[0]; struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 }; - cmd = ARM_SMCCC_CALL_VAL( - type, - qcom_smccc_convention, - desc->owner, - SMCCC_FUNCNUM(desc->svc, desc->cmd)); - quirk.state.a6 = 0; do { - arm_smccc_smc_quirk(cmd, desc->arginfo, desc->args[0], - desc->args[1], desc->args[2], x5, - quirk.state.a6, 0, res, &quirk); + arm_smccc_smc_quirk(a0, smc->a[1], smc->a[2], smc->a[3], + smc->a[4], smc->a[5], quirk.state.a6, + smc->a[7], res, &quirk); if (res->a0 == QCOM_SCM_INTERRUPTED) - cmd = res->a0; + a0 = res->a0; } while (res->a0 == QCOM_SCM_INTERRUPTED); } @@ -95,12 +95,22 @@ static int ___qcom_scm_call_smccc(struct device *dev, { int arglen = desc->arginfo & 0xf; int i; - u64 x5 = desc->args[SMCCC_FIRST_EXT_IDX]; dma_addr_t args_phys = 0; void *args_virt = NULL; size_t alloc_len; gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL; + u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL; struct arm_smccc_res res; + struct arm_smccc_args smc = {0}; + + smc.a[0] = ARM_SMCCC_CALL_VAL( + smccc_call_type, + qcom_smccc_convention, + desc->owner, + SMCCC_FUNCNUM(desc->svc, desc->cmd)); + smc.a[1] = desc->arginfo; + for (i = 0; i < SMCCC_N_REG_ARGS; i++) + smc.a[i + SMCCC_FIRST_REG_IDX] = desc->args[i]; if (unlikely(arglen > SMCCC_N_REG_ARGS)) { alloc_len = SMCCC_N_EXT_ARGS * sizeof(u64); @@ -131,19 +141,18 @@ static int ___qcom_scm_call_smccc(struct device *dev, return -ENOMEM; } - x5 = args_phys; + smc.a[SMCCC_LAST_REG_IDX] = args_phys; } if (atomic) { - __qcom_scm_call_do_quirk(desc, &res, x5, ARM_SMCCC_FAST_CALL); + __qcom_scm_call_do_quirk(&smc, &res); } else { int retry_count = 0; do { mutex_lock(&qcom_scm_lock); - __qcom_scm_call_do_quirk(desc, &res, x5, - ARM_SMCCC_STD_CALL); + __qcom_scm_call_do_quirk(&smc, &res); mutex_unlock(&qcom_scm_lock); From patchwork Tue Nov 12 21:22:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240229 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A668A13BD for ; Tue, 12 Nov 2019 21:24:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8271E222C2 for ; Tue, 12 Nov 2019 21:24:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="ZoME8pav"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="N43tycCs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727598AbfKLVYG (ORCPT ); Tue, 12 Nov 2019 16:24:06 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39224 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727466AbfKLVXW (ORCPT ); Tue, 12 Nov 2019 16:23:22 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A7B0B60D83; Tue, 12 Nov 2019 21:23:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593801; bh=0UWW0rRiXr5uzuNzBnxmiwinxhzqv4//UV0PjBT639s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZoME8pavg9+yDmDbQ3QMOB/x8RjHrvAX5f1kWZwuPcUP8LEmPbQzmEd3pTqcey97+ 2R0b03AMrfbT4btF0iScB6sKDqPVWRUcDBDQK6jw/cyC3PoOmEbeG6y6i1OnAdd7Gi aozMlb5jOp6e0iPj9J8tTSqQijqSBo6DJfCdQETM= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A54EC60D7E; Tue, 12 Nov 2019 21:23:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593793; bh=0UWW0rRiXr5uzuNzBnxmiwinxhzqv4//UV0PjBT639s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N43tycCs6JSMLXH5/sZ9F+vuMZPYzmmDQwfdu5DETTu83gPzUSYI3UOWRzLN0oCsY XxCwedq8JJHeVeNkffzbp2QS0sNrWwCc85twyvRxami9awDJpgvw4rHTgkglMQphgU o+gF0Nv/c0ixq5i/BMdvCcq2Czh9CCKhHFF5HHNo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A54EC60D7E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/18] firmware: qcom_scm-64: Improve SMC convention detection Date: Tue, 12 Nov 2019 13:22:46 -0800 Message-Id: <1573593774-12539-11-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Improve the calling convention detection to use __qcom_scm_is_call_available() and not blindly assume 32-bit mode if the checks fails. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-64.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 977654bb..b82b450 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -302,21 +302,20 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, void __qcom_scm_init(void) { - u64 cmd; - struct arm_smccc_res res; - u32 function = SMCCC_FUNCNUM(QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL); - - /* First try a SMC64 call */ - cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, - ARM_SMCCC_OWNER_SIP, function); - - arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)), - 0, 0, 0, 0, 0, &res); - - if (!res.a0 && res.a1) - qcom_smccc_convention = ARM_SMCCC_SMC_64; - else - qcom_smccc_convention = ARM_SMCCC_SMC_32; + qcom_smccc_convention = ARM_SMCCC_SMC_64; + if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, + QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) + goto out; + + qcom_smccc_convention = ARM_SMCCC_SMC_32; + if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, + QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) + goto out; + + qcom_smccc_convention = -1; + BUG(); +out: + pr_debug("QCOM SCM SMC Convention: %llu\n", qcom_smccc_convention); } bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) From patchwork Tue Nov 12 21:22:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240207 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55FF415AB for ; Tue, 12 Nov 2019 21:23:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E204222C2 for ; Tue, 12 Nov 2019 21:23:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="iCeiQUG8"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="UX6t9+SV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727497AbfKLVX3 (ORCPT ); Tue, 12 Nov 2019 16:23:29 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39336 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727413AbfKLVX0 (ORCPT ); Tue, 12 Nov 2019 16:23:26 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A1D8A60D97; Tue, 12 Nov 2019 21:23:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593804; bh=qE8ieS9/hBmGsP2uuG3y5Q8i34qp8phWRAEYYau4cuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iCeiQUG85DDUPPSRBsI1sjOGUebaoKFhPjTDYl8+QTmNkXzjetuixTMEPtlGmm/Aj qdczStPo+VRMqvTEG/UFL4N4yRN58bsvTQ2J/YFgprOduQInagVll0s61HqXSepSui /XeKIagsUtSLnw1VauZi/5KCBfepzUFUPI4BXxnI= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AEAF860D8D; Tue, 12 Nov 2019 21:23:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593794; bh=qE8ieS9/hBmGsP2uuG3y5Q8i34qp8phWRAEYYau4cuA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UX6t9+SVrpes6E8NvP8gzkEJmAJHoYqFQy9+6XqKv/jTKkVkm/DX+iKX37ypDfGD/ rzhEPIpF8yiO8lM1+6y2BC4tn9e0Nc84gCkXpj1YUX+QYuILKq5gmd4kQ58xNaW9Ik F+nffNL22LZNMsAEpXh4d8ipc2z6cUzG5vB5gX5s= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AEAF860D8D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/18] firmware: qcom_scm-32: Use SMC arch wrappers Date: Tue, 12 Nov 2019 13:22:47 -0800 Message-Id: <1573593774-12539-12-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use SMC arch wrappers instead of inline assembly. Signed-off-by: Elliot Berman Reviewed-by: Stephen Boyd --- drivers/firmware/Makefile | 1 - drivers/firmware/qcom_scm-32.c | 71 ++++++++++-------------------------------- 2 files changed, 17 insertions(+), 55 deletions(-) diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 3fcb919..747fb73 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -20,7 +20,6 @@ obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o obj-$(CONFIG_QCOM_SCM) += qcom_scm.o obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o -CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index e06d59b..c3aeccf 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "qcom_scm.h" @@ -124,25 +125,13 @@ static inline void *legacy_get_response_buffer( static u32 __qcom_scm_call_do(u32 cmd_addr) { int context_id; - register u32 r0 asm("r0") = 1; - register u32 r1 asm("r1") = (u32)&context_id; - register u32 r2 asm("r2") = cmd_addr; + struct arm_smccc_res res; do { - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3", "r12"); - } while (r0 == QCOM_SCM_INTERRUPTED); - - return r0; + arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr, + 0, 0, 0, 0, 0, &res); + } while (res.a0 == QCOM_SCM_INTERRUPTED); + + return res.a0; } /** @@ -240,24 +229,12 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) { int context_id; + struct arm_smccc_res res; + + arm_smccc_smc(LEGACY_ATOMIC_ID(svc, cmd, 1), (unsigned long)&context_id, + arg1, 0, 0, 0, 0, 0, &res); - register u32 r0 asm("r0") = LEGACY_ATOMIC_ID(svc, cmd, 1); - register u32 r1 asm("r1") = (u32)&context_id; - register u32 r2 asm("r2") = arg1; - - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2) - : "r3", "r12"); - return r0; + return res.a0; } /** @@ -273,26 +250,12 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) { int context_id; + struct arm_smccc_res res; + + arm_smccc_smc(LEGACY_ATOMIC_ID(svc, cmd, 2), (unsigned long)&context_id, + arg1, arg2, 0, 0, 0, 0, &res); - register u32 r0 asm("r0") = LEGACY_ATOMIC_ID(svc, cmd, 2); - register u32 r1 asm("r1") = (u32)&context_id; - register u32 r2 asm("r2") = arg1; - register u32 r3 asm("r3") = arg2; - - asm volatile( - __asmeq("%0", "r0") - __asmeq("%1", "r0") - __asmeq("%2", "r1") - __asmeq("%3", "r2") - __asmeq("%4", "r3") -#ifdef REQUIRES_SEC - ".arch_extension sec\n" -#endif - "smc #0 @ switch to secure world\n" - : "=r" (r0) - : "r" (r0), "r" (r1), "r" (r2), "r" (r3) - : "r12"); - return r0; + return res.a0; } /** From patchwork Tue Nov 12 21:22:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240219 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89EED15AB for ; Tue, 12 Nov 2019 21:23:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 567F5214E0 for ; Tue, 12 Nov 2019 21:23:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="NDYUP6Zh"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="kP+J0+w4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727536AbfKLVX3 (ORCPT ); Tue, 12 Nov 2019 16:23:29 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39404 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727528AbfKLVX2 (ORCPT ); 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Tue, 12 Nov 2019 21:23:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593795; bh=OweLmDKIb+NOEidQTgGNOokTWlrBfkD4d0RRcT5W/Q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kP+J0+w4GYFh+l7/oqZ/61qrjxqUKL7ptc+qkZSXRu/0rYIPGpKzvwK72qxhsb2H/ IzvAUkhqKHuRfGQ25cJwada0uc9VQ4W7RFYxS0niUJprpDNrQN8yl0vRPDCR/uYnZf er63bS/12C0FQANa/MKPVvLuMm0diAYgME4LdGc4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C47F560DA7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 12/18] firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls Date: Tue, 12 Nov 2019 13:22:48 -0800 Message-Id: <1573593774-12539-13-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use qcom_scm_desc in non-atomic calls to remove legacy convention details from every SCM wrapper function. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-32.c | 283 +++++++++++++++++++++++++---------------- 1 file changed, 172 insertions(+), 111 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c3aeccf..4c287f6 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -39,6 +39,46 @@ static struct qcom_scm_entry qcom_scm_wb[] = { static DEFINE_MUTEX(qcom_scm_lock); +#define MAX_QCOM_SCM_ARGS 10 +#define MAX_QCOM_SCM_RETS 3 + +enum qcom_scm_arg_types { + QCOM_SCM_VAL, + QCOM_SCM_RO, + QCOM_SCM_RW, + QCOM_SCM_BUFVAL, +}; + +#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\ + (((a) & 0x3) << 4) | \ + (((b) & 0x3) << 6) | \ + (((c) & 0x3) << 8) | \ + (((d) & 0x3) << 10) | \ + (((e) & 0x3) << 12) | \ + (((f) & 0x3) << 14) | \ + (((g) & 0x3) << 16) | \ + (((h) & 0x3) << 18) | \ + (((i) & 0x3) << 20) | \ + (((j) & 0x3) << 22) | \ + ((num) & 0xf)) + +#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + +/** + * struct qcom_scm_desc + * @arginfo: Metadata describing the arguments in args[] + * @args: The array of arguments for the secure syscall + * @res: The values returned by the secure syscall + */ +struct qcom_scm_desc { + u32 svc; + u32 cmd; + u32 arginfo; + u64 args[MAX_QCOM_SCM_ARGS]; + u64 result[MAX_QCOM_SCM_RETS]; + u32 owner; +}; + #define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff)) /** @@ -135,16 +175,8 @@ static u32 __qcom_scm_call_do(u32 cmd_addr) } /** - * qcom_scm_call() - Send an SCM command - * @dev: struct device - * @svc_id: service identifier - * @cmd_id: command identifier - * @cmd_buf: command buffer - * @cmd_len: length of the command buffer - * @resp_buf: response buffer - * @resp_len: length of the response buffer - * - * Sends a command to the SCM and waits for the command to finish processing. + * qcom_scm_call() - Sends a command to the SCM and waits for the command to + * finish processing. * * A note on cache maintenance: * Note that any buffers that are expected to be accessed by the secure world @@ -153,15 +185,19 @@ static u32 __qcom_scm_call_do(u32 cmd_addr) * and response buffers is taken care of by qcom_scm_call; however, callers are * responsible for any other cached buffers passed over to the secure world. */ -static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, - const void *cmd_buf, size_t cmd_len, void *resp_buf, - size_t resp_len) +static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) { + int arglen = desc->arginfo & 0xf; int ret; + size_t i; struct qcom_scm_legacy_command *cmd; struct qcom_scm_legacy_response *rsp; + const size_t cmd_len = arglen * sizeof(__le32); + const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32); size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len; dma_addr_t cmd_phys; + __le32 *arg_buf; + __le32 *res_buf; cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL); if (!cmd) @@ -170,10 +206,11 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, cmd->len = cpu_to_le32(alloc_len); cmd->buf_offset = cpu_to_le32(sizeof(*cmd)); cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len); + cmd->id = cpu_to_le32(LEGACY_FUNCNUM(desc->svc, desc->cmd)); - cmd->id = cpu_to_le32(LEGACY_FUNCNUM(svc_id, cmd_id)); - if (cmd_buf) - memcpy(legacy_get_command_buffer(cmd), cmd_buf, cmd_len); + arg_buf = legacy_get_command_buffer(cmd); + for (i = 0; i < arglen; i++) + arg_buf[i] = cpu_to_le32(desc->args[i]); rsp = legacy_command_to_response(cmd); @@ -196,13 +233,13 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id, sizeof(*rsp), DMA_FROM_DEVICE); } while (!rsp->is_complete); - if (resp_buf) { - dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + - le32_to_cpu(rsp->buf_offset), - resp_len, DMA_FROM_DEVICE); - memcpy(resp_buf, legacy_get_response_buffer(rsp), - resp_len); - } + dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + + le32_to_cpu(rsp->buf_offset), + resp_len, DMA_FROM_DEVICE); + + res_buf = legacy_get_response_buffer(rsp); + for (i = 0; i < MAX_QCOM_SCM_RETS; i++) + desc->result[i] = le32_to_cpu(res_buf[i]); out: dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE); kfree(cmd); @@ -305,10 +342,10 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, int ret; int flags = 0; int cpu; - struct { - __le32 flags; - __le32 addr; - } cmd; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR, + }; /* * Reassign only if we are switching from hotplug entry point @@ -324,10 +361,11 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, if (!flags) return 0; - cmd.addr = cpu_to_le32(virt_to_phys(entry)); - cmd.flags = cpu_to_le32(flags); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR, - &cmd, sizeof(cmd), NULL, 0); + desc.args[0] = flags; + desc.args[1] = virt_to_phys(entry); + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(dev, &desc); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry; @@ -353,26 +391,47 @@ void __qcom_scm_cpu_power_down(u32 flags) int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) { int ret; - __le32 svc_cmd = cpu_to_le32(LEGACY_FUNCNUM(svc_id, cmd_id)); - __le32 ret_val = 0; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_INFO, + .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, + .args[0] = LEGACY_FUNCNUM(svc_id, cmd_id), + .arginfo = QCOM_SCM_ARGS(1), + }; - ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL, - &svc_cmd, sizeof(svc_cmd), &ret_val, - sizeof(ret_val)); - if (ret) - return ret; + ret = qcom_scm_call(dev, &desc); - return le32_to_cpu(ret_val); + return ret ? : desc.result[0]; } int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) { + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_HDCP, + .cmd = QCOM_SCM_HDCP_INVOKE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) return -ERANGE; - return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, - req, req_cnt * sizeof(*req), resp, sizeof(*resp)); + desc.args[0] = req[0].addr; + desc.args[1] = req[0].val; + desc.args[2] = req[1].addr; + desc.args[3] = req[1].val; + desc.args[4] = req[2].addr; + desc.args[5] = req[2].val; + desc.args[6] = req[3].addr; + desc.args[7] = req[3].val; + desc.args[8] = req[4].addr; + desc.args[9] = req[4].val; + desc.arginfo = QCOM_SCM_ARGS(10); + + ret = qcom_scm_call(dev, &desc); + *resp = desc.result[0]; + + return ret; } void __qcom_scm_init(void) @@ -381,104 +440,107 @@ void __qcom_scm_init(void) bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) { - __le32 out; - __le32 in; int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, + .owner = ARM_SMCCC_OWNER_SIP, + }; - in = cpu_to_le32(peripheral); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_IS_SUPPORTED, - &in, sizeof(in), - &out, sizeof(out)); + desc.args[0] = peripheral; + desc.arginfo = QCOM_SCM_ARGS(1); - return ret ? false : !!out; + ret = qcom_scm_call(dev, &desc); + + return ret ? false : !!desc.result[0]; } int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, dma_addr_t metadata_phys) { - __le32 scm_ret; int ret; - struct { - __le32 proc; - __le32 image_addr; - } request; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, + .owner = ARM_SMCCC_OWNER_SIP, + }; - request.proc = cpu_to_le32(peripheral); - request.image_addr = cpu_to_le32(metadata_phys); + desc.args[0] = peripheral; + desc.args[1] = metadata_phys; + desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_INIT_IMAGE, - &request, sizeof(request), - &scm_ret, sizeof(scm_ret)); + ret = qcom_scm_call(dev, &desc); - return ret ? : le32_to_cpu(scm_ret); + return ret ? : desc.result[0]; } int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, - phys_addr_t addr, phys_addr_t size) + phys_addr_t addr, phys_addr_t size) { - __le32 scm_ret; int ret; - struct { - __le32 proc; - __le32 addr; - __le32 len; - } request; - - request.proc = cpu_to_le32(peripheral); - request.addr = cpu_to_le32(addr); - request.len = cpu_to_le32(size); - - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_MEM_SETUP, - &request, sizeof(request), - &scm_ret, sizeof(scm_ret)); - - return ret ? : le32_to_cpu(scm_ret); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = peripheral; + desc.args[1] = addr; + desc.args[2] = size; + desc.arginfo = QCOM_SCM_ARGS(3); + + ret = qcom_scm_call(dev, &desc); + + return ret ? : desc.result[0]; } int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) { - __le32 out; - __le32 in; int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, + .owner = ARM_SMCCC_OWNER_SIP, + }; - in = cpu_to_le32(peripheral); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_AUTH_AND_RESET, - &in, sizeof(in), - &out, sizeof(out)); + ret = qcom_scm_call(dev, &desc); - return ret ? : le32_to_cpu(out); + return ret ? : desc.result[0]; } int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) { - __le32 out; - __le32 in; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, + .owner = ARM_SMCCC_OWNER_SIP, + }; int ret; - in = cpu_to_le32(peripheral); - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_SHUTDOWN, - &in, sizeof(in), - &out, sizeof(out)); + desc.args[0] = peripheral; + desc.arginfo = QCOM_SCM_ARGS(1); - return ret ? : le32_to_cpu(out); + ret = qcom_scm_call(dev, &desc); + + return ret ? : desc.result[0]; } int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { - __le32 out; - __le32 in = cpu_to_le32(reset); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, + .owner = ARM_SMCCC_OWNER_SIP, + }; int ret; - ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET, - &in, sizeof(in), - &out, sizeof(out)); + desc.args[0] = reset; + desc.args[1] = 0; + desc.arginfo = QCOM_SCM_ARGS(2); - return ret ? : le32_to_cpu(out); + ret = qcom_scm_call(dev, &desc); + + return ret ? : desc.result[0]; } int __qcom_scm_set_dload_mode(struct device *dev, bool enable) @@ -489,20 +551,19 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable) int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) { - struct { - __le32 state; - __le32 id; - } req; - __le32 scm_ret = 0; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, + .owner = ARM_SMCCC_OWNER_SIP, + }; int ret; - req.state = cpu_to_le32(state); - req.id = cpu_to_le32(id); + desc.args[0] = state; + desc.args[1] = id; - ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE, - &req, sizeof(req), &scm_ret, sizeof(scm_ret)); + ret = qcom_scm_call(dev, &desc); - return ret ? : le32_to_cpu(scm_ret); + return ret ? : desc.result[0]; } int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, From patchwork Tue Nov 12 21:22:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240211 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 308BB13BD for ; Tue, 12 Nov 2019 21:23:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 07EB6214E0 for ; Tue, 12 Nov 2019 21:23:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="I6JjTCZD"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="IT45tcuJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727610AbfKLVXi (ORCPT ); Tue, 12 Nov 2019 16:23:38 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39530 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727558AbfKLVXd (ORCPT ); Tue, 12 Nov 2019 16:23:33 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A92B760E1C; Tue, 12 Nov 2019 21:23:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593811; bh=69sjY0Bsd+QEFmg+FpleUKMSHBQWLRsduYB+GG7/ZHs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I6JjTCZDJ5CeNhwj4x3sUbTl/5KyVlIxH63VT5JkWcAXmbwlYsY4pnJGNpsBI06qL 9/z4RBX+ZnMc4RpYUUixH+q3Dvj/H2oOWDhQl98KKMIawZ9aPk3MprYPCuQ8x2OjUJ Ud0u/IUDZ+MFmmydhQJdGsg3UejFaO5nt/oOWh8o= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id ED9DD60DB6; Tue, 12 Nov 2019 21:23:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593796; bh=69sjY0Bsd+QEFmg+FpleUKMSHBQWLRsduYB+GG7/ZHs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IT45tcuJ/BStN9C0RZyT1vbfHnURnHXrKYvI275tnb7WiXnvqHJz2WHW6n4cQBXGU XmBRktoGK0bxfwYdnMixgqb4R9XVX5dE+Pl1+2Jb+CGWaJ/h2zf9jWK2XPZhRXNLlW G0c1LOmbL1Z6vW6MMJTaWqyS0I3YTwnlvLJiUDpY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org ED9DD60DB6 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 13/18] firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call Date: Tue, 12 Nov 2019 13:22:49 -0800 Message-Id: <1573593774-12539-14-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org - Move SMCCC register filling to qcom_scm_call so that qcom_scm_call_do only needs to concern itself with retry mechanism. - Use arm_smccc_args struct in atomic variants as well. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-32.c | 47 ++++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 4c287f6..913a77c 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -78,6 +78,9 @@ struct qcom_scm_desc { u64 result[MAX_QCOM_SCM_RETS]; u32 owner; }; +struct arm_smccc_args { + unsigned long a[8]; +}; #define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff)) @@ -162,16 +165,13 @@ static inline void *legacy_get_response_buffer( return (void *)rsp + le32_to_cpu(rsp->buf_offset); } -static u32 __qcom_scm_call_do(u32 cmd_addr) +static void __qcom_scm_call_do(const struct arm_smccc_args *smc, + struct arm_smccc_res *res) { - int context_id; - struct arm_smccc_res res; do { - arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr, - 0, 0, 0, 0, 0, &res); - } while (res.a0 == QCOM_SCM_INTERRUPTED); - - return res.a0; + arm_smccc_smc(smc->a[0], smc->a[1], smc->a[2], smc->a[3], + smc->a[4], smc->a[5], smc->a[6], smc->a[7], res); + } while (res->a0 == QCOM_SCM_INTERRUPTED); } /** @@ -188,10 +188,12 @@ static u32 __qcom_scm_call_do(u32 cmd_addr) static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) { int arglen = desc->arginfo & 0xf; - int ret; + int ret = 0, context_id; size_t i; struct qcom_scm_legacy_command *cmd; struct qcom_scm_legacy_response *rsp; + struct arm_smccc_args smc = {0}; + struct arm_smccc_res res; const size_t cmd_len = arglen * sizeof(__le32); const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32); size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len; @@ -220,10 +222,14 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) return -ENOMEM; } + smc.a[0] = 1; + smc.a[1] = (unsigned long)&context_id; + smc.a[2] = cmd_phys; + mutex_lock(&qcom_scm_lock); - ret = __qcom_scm_call_do(cmd_phys); - if (ret < 0) - ret = qcom_scm_remap_error(ret); + __qcom_scm_call_do(&smc, &res); + if (res.a0 < 0) + ret = qcom_scm_remap_error(res.a0); mutex_unlock(&qcom_scm_lock); if (ret) goto out; @@ -266,10 +272,14 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) { int context_id; + struct arm_smccc_args smc = {0}; struct arm_smccc_res res; - arm_smccc_smc(LEGACY_ATOMIC_ID(svc, cmd, 1), (unsigned long)&context_id, - arg1, 0, 0, 0, 0, 0, &res); + smc.a[0] = LEGACY_ATOMIC_ID(svc, cmd, 1); + smc.a[1] = (unsigned long)&context_id; + smc.a[2] = arg1; + arm_smccc_smc(smc.a[0], smc.a[1], smc.a[2], smc.a[3], + smc.a[4], smc.a[5], smc.a[6], smc.a[7], &res); return res.a0; } @@ -287,10 +297,15 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) { int context_id; + struct arm_smccc_args smc = {0}; struct arm_smccc_res res; - arm_smccc_smc(LEGACY_ATOMIC_ID(svc, cmd, 2), (unsigned long)&context_id, - arg1, arg2, 0, 0, 0, 0, &res); + smc.a[0] = LEGACY_ATOMIC_ID(svc, cmd, 2); + smc.a[1] = (unsigned long)&context_id; + smc.a[2] = arg1; + smc.a[3] = arg2; + arm_smccc_smc(smc.a[0], smc.a[1], smc.a[2], smc.a[3], + smc.a[4], smc.a[5], smc.a[6], smc.a[7], &res); return res.a0; } From patchwork Tue Nov 12 21:22:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240209 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C983D13BD for ; Tue, 12 Nov 2019 21:23:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0FF2222BD for ; Tue, 12 Nov 2019 21:23:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="IAlcEVjD"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="CJL+t1AQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727544AbfKLVXa (ORCPT ); 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Tue, 12 Nov 2019 21:23:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593797; bh=4M99796mPoiByWOUZ9CnX7Wb00T7c7NC9OQ8KHDM7dg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CJL+t1AQ8XO9ErPQDnmOANE7Fba4V76w9c+MWjwHE0+EruuKSrmPGwL4WFkBWHOph K23GQF7e7lQGLmnqSkx4LZ+mIwcEsWicDmJD1QedhnhV5rnm1rs1cVvzMkYidMvzSF orwaMtX9R2p6A+m6mmOlM7N4A4+JmSWJw/5cs9PE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 166C260DBA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 14/18] firmware: qcom_scm-32: Create common legacy atomic call Date: Tue, 12 Nov 2019 13:22:50 -0800 Message-Id: <1573593774-12539-15-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Per [1], legacy calling convention supports up to 5 arguments and 3 return values. Create one function to support this combination. [1]: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/scm.c?h=kernel.lnx.4.9.r28-rel#n1024 Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-32.c | 107 +++++++++++++++++++++++++---------------- 1 file changed, 66 insertions(+), 41 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 913a77c..eca18e1 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -252,6 +252,8 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) return ret; } +#define LEGACY_ATOMIC_N_REG_ARGS 5 +#define LEGACY_ATOMIC_FIRST_REG_IDX 2 #define LEGACY_CLASS_REGISTER (0x2 << 8) #define LEGACY_MASK_IRQS BIT(5) #define LEGACY_ATOMIC_ID(svc, cmd, n) \ @@ -261,52 +263,34 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) (n & 0xf)) /** - * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument - * @svc_id: service identifier - * @cmd_id: command identifier - * @arg1: first argument + * qcom_scm_call_atomic() - Send an atomic SCM command with up to 5 arguments + * and 3 return values * * This shall only be used with commands that are guaranteed to be * uninterruptable, atomic and SMP safe. */ -static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) +static int qcom_scm_call_atomic(struct qcom_scm_desc *desc) { int context_id; struct arm_smccc_args smc = {0}; struct arm_smccc_res res; + size_t i, arglen = desc->arginfo & 0xf; - smc.a[0] = LEGACY_ATOMIC_ID(svc, cmd, 1); - smc.a[1] = (unsigned long)&context_id; - smc.a[2] = arg1; - arm_smccc_smc(smc.a[0], smc.a[1], smc.a[2], smc.a[3], - smc.a[4], smc.a[5], smc.a[6], smc.a[7], &res); + BUG_ON(arglen > LEGACY_ATOMIC_N_REG_ARGS); - return res.a0; -} + smc.a[0] = LEGACY_ATOMIC_ID(desc->svc, desc->cmd, arglen); + smc.a[1] = (unsigned long)&context_id; -/** - * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments - * @svc_id: service identifier - * @cmd_id: command identifier - * @arg1: first argument - * @arg2: second argument - * - * This shall only be used with commands that are guaranteed to be - * uninterruptable, atomic and SMP safe. - */ -static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) -{ - int context_id; - struct arm_smccc_args smc = {0}; - struct arm_smccc_res res; + for (i = 0; i < arglen; i++) + smc.a[i + LEGACY_ATOMIC_FIRST_REG_IDX] = desc->args[i]; - smc.a[0] = LEGACY_ATOMIC_ID(svc, cmd, 2); - smc.a[1] = (unsigned long)&context_id; - smc.a[2] = arg1; - smc.a[3] = arg2; arm_smccc_smc(smc.a[0], smc.a[1], smc.a[2], smc.a[3], smc.a[4], smc.a[5], smc.a[6], smc.a[7], &res); + desc->result[0] = res.a1; + desc->result[1] = res.a2; + desc->result[2] = res.a3; + return res.a0; } @@ -328,6 +312,11 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) QCOM_SCM_FLAG_COLDBOOT_CPU2, QCOM_SCM_FLAG_COLDBOOT_CPU3, }; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR, + .owner = ARM_SMCCC_OWNER_SIP, + }; if (!cpus || (cpus && cpumask_empty(cpus))) return -EINVAL; @@ -339,8 +328,11 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR, - flags, virt_to_phys(entry)); + desc.args[0] = flags; + desc.args[1] = virt_to_phys(entry); + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(&desc); } /** @@ -399,8 +391,15 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, */ void __qcom_scm_cpu_power_down(u32 flags) { - qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_TERMINATE_PC, - flags & QCOM_SCM_FLUSH_FLAG_MASK); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_TERMINATE_PC, + .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, + .arginfo = QCOM_SCM_ARGS(1), + .owner = ARM_SMCCC_OWNER_SIP, + }; + + qcom_scm_call_atomic(&desc); } int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) @@ -560,8 +559,17 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { - return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0, 0); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; + desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(&desc); } int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) @@ -610,18 +618,35 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val) { int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_READ, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = addr; + desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr); + ret = qcom_scm_call_atomic(&desc); if (ret >= 0) - *val = ret; + *val = desc.result[0]; return ret < 0 ? ret : 0; } int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) { - return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE, - addr, val); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_WRITE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = addr; + desc.args[1] = val; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(&desc); } int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable) From patchwork Tue Nov 12 21:22:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240221 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48F8315AB for ; Tue, 12 Nov 2019 21:24:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 200FF21D7F for ; Tue, 12 Nov 2019 21:24:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="cEPffaIS"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="SOMAv161" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727514AbfKLVXz (ORCPT ); Tue, 12 Nov 2019 16:23:55 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39456 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727537AbfKLVXa (ORCPT ); Tue, 12 Nov 2019 16:23:30 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4A8AE60E74; Tue, 12 Nov 2019 21:23:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593809; bh=wYDOZB/YAonq1CatbFTG+Ux5sV3vBmtfWfxuRkP1OYc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cEPffaISI1brHz+vp/a5R7SuxlHC1o+FFJZD2CyG+L9ow2mT3GZu0/QoCz9sTx8kb 6hvfpVvfVMtxdF2BnpuB1/kuJ8FTPp1fHYtVS3LSxvpn7tKqa3puouGbRrkgq1/Lsc bQpQxVRSL5j1vtrtYAhqmww7///o9YXvaphFkk8E= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 328EA60DEA; Tue, 12 Nov 2019 21:23:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593799; bh=wYDOZB/YAonq1CatbFTG+Ux5sV3vBmtfWfxuRkP1OYc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SOMAv161py6eYFrXt2MxTysDoh+uWErBJIQOPUH5aRmQl6OJmlZnY5eOcP0cK1oio UeG6mAHOd0IIaTEKarBz43KD1B5+c/vcV2ULVuP1VcJYxFNHEk5x8na0znqlcIqrBB SsK8O9EhzBmeqVEgst75bTEUH2aAoQYQgcvSNMzA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 328EA60DEA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 15/18] firmware: qcom_scm-32: Add device argument to atomic calls Date: Tue, 12 Nov 2019 13:22:51 -0800 Message-Id: <1573593774-12539-16-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add this unused parameter to reduce merge friction between SMCCC and legacy based conventions. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-32.c | 17 +++++++++-------- drivers/firmware/qcom_scm-64.c | 5 +++-- drivers/firmware/qcom_scm.c | 5 +++-- drivers/firmware/qcom_scm.h | 5 +++-- 4 files changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index eca18e1..c1c0831 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -269,7 +269,7 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) * This shall only be used with commands that are guaranteed to be * uninterruptable, atomic and SMP safe. */ -static int qcom_scm_call_atomic(struct qcom_scm_desc *desc) +static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) { int context_id; struct arm_smccc_args smc = {0}; @@ -302,7 +302,8 @@ static int qcom_scm_call_atomic(struct qcom_scm_desc *desc) * Set the cold boot address of the cpus. Any cpu outside the supported * range would be removed from the cpu present mask. */ -int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) +int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry, + const cpumask_t *cpus) { int flags = 0; int cpu; @@ -332,7 +333,7 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) desc.args[1] = virt_to_phys(entry); desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call_atomic(&desc); + return qcom_scm_call_atomic(dev, &desc); } /** @@ -389,7 +390,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, * the control would return from this function, otherwise, the cpu jumps to the * warm boot entry point set for this cpu upon reset. */ -void __qcom_scm_cpu_power_down(u32 flags) +void __qcom_scm_cpu_power_down(struct device *dev, u32 flags) { struct qcom_scm_desc desc = { .svc = QCOM_SCM_SVC_BOOT, @@ -399,7 +400,7 @@ void __qcom_scm_cpu_power_down(u32 flags) .owner = ARM_SMCCC_OWNER_SIP, }; - qcom_scm_call_atomic(&desc); + qcom_scm_call_atomic(dev, &desc); } int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) @@ -569,7 +570,7 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable) desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call_atomic(&desc); + return qcom_scm_call_atomic(dev, &desc); } int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) @@ -627,7 +628,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, desc.args[0] = addr; desc.arginfo = QCOM_SCM_ARGS(1); - ret = qcom_scm_call_atomic(&desc); + ret = qcom_scm_call_atomic(dev, &desc); if (ret >= 0) *val = desc.result[0]; @@ -646,7 +647,7 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) desc.args[1] = val; desc.arginfo = QCOM_SCM_ARGS(2); - return qcom_scm_call_atomic(&desc); + return qcom_scm_call_atomic(dev, &desc); } int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable) diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index b82b450..5088c0c 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -219,7 +219,8 @@ static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) * Set the cold boot address of the cpus. Any cpu outside the supported * range would be removed from the cpu present mask. */ -int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) +int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry, + const cpumask_t *cpus) { return -ENOTSUPP; } @@ -247,7 +248,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, * the control would return from this function, otherwise, the cpu jumps to the * warm boot entry point set for this cpu upon reset. */ -void __qcom_scm_cpu_power_down(u32 flags) +void __qcom_scm_cpu_power_down(struct device *dev, u32 flags) { } diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 72757c5..1875e48 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -94,7 +94,8 @@ static void qcom_scm_clk_disable(void) */ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) { - return __qcom_scm_set_cold_boot_addr(entry, cpus); + return __qcom_scm_set_cold_boot_addr(__scm ? __scm->dev : NULL, entry, + cpus); } EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); @@ -122,7 +123,7 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); */ void qcom_scm_cpu_power_down(u32 flags) { - __qcom_scm_cpu_power_down(flags); + __qcom_scm_cpu_power_down(__scm ? __scm->dev : NULL, flags); } EXPORT_SYMBOL(qcom_scm_cpu_power_down); diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index dfb5db2..35cdacf 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -13,11 +13,12 @@ extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable); extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, const cpumask_t *cpus); -extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); +extern int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry, + const cpumask_t *cpus); #define QCOM_SCM_BOOT_TERMINATE_PC 0x2 #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 -extern void __qcom_scm_cpu_power_down(u32 flags); +extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags); #define QCOM_SCM_SVC_IO 0x5 #define QCOM_SCM_IO_READ 0x1 From patchwork Tue Nov 12 21:22:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240215 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9AC515AB for ; Tue, 12 Nov 2019 21:23:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8370621A49 for ; Tue, 12 Nov 2019 21:23:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Q4cUK9xw"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="fO2dU4pw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727620AbfKLVXp (ORCPT ); Tue, 12 Nov 2019 16:23:45 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39738 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727631AbfKLVXo (ORCPT ); Tue, 12 Nov 2019 16:23:44 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CE5F46055C; Tue, 12 Nov 2019 21:23:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593821; bh=Wv+nhrxa3ebd0WbZ6Pk3Dsk+zKXagMdXxAXFvISgL2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q4cUK9xwiUyRdnG4wwK+AzHJqd9237a+KDfT7DlZ4rik+LNLpCRBk1GT0aKpobR19 ss2lYm25LZcqxRfYgYvchsrT9u9VCBPxDtpuDEAGYmHMGPq9jSGGr/YqZJ+7D4ekGf VC0p1vyp2Zibd30Fi1kNomMSaZwZc3u3MRSb6vHU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 74F9360E0D; Tue, 12 Nov 2019 21:23:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593800; bh=Wv+nhrxa3ebd0WbZ6Pk3Dsk+zKXagMdXxAXFvISgL2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fO2dU4pwuNj/UW165Q3cy5Yo5CBYJ4fNcrvhdy72TjOa505vgEAo+MKEK7ob71kLF 4ly3TnBKr4Jv+2xnygW0NcCtpyyCDmgIEt8eZmTWiS2TCGu145Jem6UuqKb8L0gdcM VbYeAmgQ3HnhGzcSRF9AGqd6Z2XhiBFTUgc+PBto= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 74F9360E0D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 16/18] firmware: qcom_scm: Remove thin wrappers Date: Tue, 12 Nov 2019 13:22:52 -0800 Message-Id: <1573593774-12539-17-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcom_scm-32 and qcom_scm-64 implementations are nearly identical, so make qcom_scm_call and qcom_scm_call_atomic unique to each. There are the following catches: - __qcom_scm_is_call_available is still in each -32,-64 implementation as the argument is unique to each convention - For some functions, only one implementation was provided in -32 or -64. The actual implementation was moved into qcom_scm.c - io_writel and io_readl in -64 were not atomic and -32 they were. Atomic is the better option, so use it. Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm-32.c | 407 +---------------------------------------- drivers/firmware/qcom_scm-64.c | 399 +--------------------------------------- drivers/firmware/qcom_scm.c | 359 +++++++++++++++++++++++++++++++++--- drivers/firmware/qcom_scm.h | 75 ++++---- 4 files changed, 382 insertions(+), 858 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c1c0831..9e3789d 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -15,69 +15,8 @@ #include "qcom_scm.h" -#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 -#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 -#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 -#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20 - -#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04 -#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02 -#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10 -#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40 - -struct qcom_scm_entry { - int flag; - void *entry; -}; - -static struct qcom_scm_entry qcom_scm_wb[] = { - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 }, - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 }, - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 }, - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 }, -}; - static DEFINE_MUTEX(qcom_scm_lock); -#define MAX_QCOM_SCM_ARGS 10 -#define MAX_QCOM_SCM_RETS 3 - -enum qcom_scm_arg_types { - QCOM_SCM_VAL, - QCOM_SCM_RO, - QCOM_SCM_RW, - QCOM_SCM_BUFVAL, -}; - -#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\ - (((a) & 0x3) << 4) | \ - (((b) & 0x3) << 6) | \ - (((c) & 0x3) << 8) | \ - (((d) & 0x3) << 10) | \ - (((e) & 0x3) << 12) | \ - (((f) & 0x3) << 14) | \ - (((g) & 0x3) << 16) | \ - (((h) & 0x3) << 18) | \ - (((i) & 0x3) << 20) | \ - (((j) & 0x3) << 22) | \ - ((num) & 0xf)) - -#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - -/** - * struct qcom_scm_desc - * @arginfo: Metadata describing the arguments in args[] - * @args: The array of arguments for the secure syscall - * @res: The values returned by the secure syscall - */ -struct qcom_scm_desc { - u32 svc; - u32 cmd; - u32 arginfo; - u64 args[MAX_QCOM_SCM_ARGS]; - u64 result[MAX_QCOM_SCM_RETS]; - u32 owner; -}; struct arm_smccc_args { unsigned long a[8]; }; @@ -185,7 +124,7 @@ static void __qcom_scm_call_do(const struct arm_smccc_args *smc, * and response buffers is taken care of by qcom_scm_call; however, callers are * responsible for any other cached buffers passed over to the secure world. */ -static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) +int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) { int arglen = desc->arginfo & 0xf; int ret = 0, context_id; @@ -269,7 +208,7 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) * This shall only be used with commands that are guaranteed to be * uninterruptable, atomic and SMP safe. */ -static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) +int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) { int context_id; struct arm_smccc_args smc = {0}; @@ -294,115 +233,6 @@ static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) return res.a0; } -/** - * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the cold boot address of the cpus. Any cpu outside the supported - * range would be removed from the cpu present mask. - */ -int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry, - const cpumask_t *cpus) -{ - int flags = 0; - int cpu; - int scm_cb_flags[] = { - QCOM_SCM_FLAG_COLDBOOT_CPU0, - QCOM_SCM_FLAG_COLDBOOT_CPU1, - QCOM_SCM_FLAG_COLDBOOT_CPU2, - QCOM_SCM_FLAG_COLDBOOT_CPU3, - }; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_ADDR, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - if (!cpus || (cpus && cpumask_empty(cpus))) - return -EINVAL; - - for_each_cpu(cpu, cpus) { - if (cpu < ARRAY_SIZE(scm_cb_flags)) - flags |= scm_cb_flags[cpu]; - else - set_cpu_present(cpu, false); - } - - desc.args[0] = flags; - desc.args[1] = virt_to_phys(entry); - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call_atomic(dev, &desc); -} - -/** - * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the Linux entry point for the SCM to transfer control to when coming - * out of a power down. CPU power down may be executed on cpuidle or hotplug. - */ -int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, - const cpumask_t *cpus) -{ - int ret; - int flags = 0; - int cpu; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_ADDR, - }; - - /* - * Reassign only if we are switching from hotplug entry point - * to cpuidle entry point or vice versa. - */ - for_each_cpu(cpu, cpus) { - if (entry == qcom_scm_wb[cpu].entry) - continue; - flags |= qcom_scm_wb[cpu].flag; - } - - /* No change in entry function */ - if (!flags) - return 0; - - desc.args[0] = flags; - desc.args[1] = virt_to_phys(entry); - desc.arginfo = QCOM_SCM_ARGS(2); - - ret = qcom_scm_call(dev, &desc); - if (!ret) { - for_each_cpu(cpu, cpus) - qcom_scm_wb[cpu].entry = entry; - } - - return ret; -} - -/** - * qcom_scm_cpu_power_down() - Power down the cpu - * @flags - Flags to flush cache - * - * This is an end point to power down cpu. If there was a pending interrupt, - * the control would return from this function, otherwise, the cpu jumps to the - * warm boot entry point set for this cpu upon reset. - */ -void __qcom_scm_cpu_power_down(struct device *dev, u32 flags) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_TERMINATE_PC, - .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, - .arginfo = QCOM_SCM_ARGS(1), - .owner = ARM_SMCCC_OWNER_SIP, - }; - - qcom_scm_call_atomic(dev, &desc); -} - int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) { int ret; @@ -418,239 +248,6 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) return ret ? : desc.result[0]; } -int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, - u32 req_cnt, u32 *resp) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_HDCP, - .cmd = QCOM_SCM_HDCP_INVOKE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) - return -ERANGE; - - desc.args[0] = req[0].addr; - desc.args[1] = req[0].val; - desc.args[2] = req[1].addr; - desc.args[3] = req[1].val; - desc.args[4] = req[2].addr; - desc.args[5] = req[2].val; - desc.args[6] = req[3].addr; - desc.args[7] = req[3].val; - desc.args[8] = req[4].addr; - desc.args[9] = req[4].val; - desc.arginfo = QCOM_SCM_ARGS(10); - - ret = qcom_scm_call(dev, &desc); - *resp = desc.result[0]; - - return ret; -} - void __qcom_scm_init(void) { } - -bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - - return ret ? false : !!desc.result[0]; -} - -int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, - dma_addr_t metadata_phys) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.args[1] = metadata_phys; - desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, - phys_addr_t addr, phys_addr_t size) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.args[1] = addr; - desc.args[2] = size; - desc.arginfo = QCOM_SCM_ARGS(3); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = peripheral; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = reset; - desc.args[1] = 0; - desc.arginfo = QCOM_SCM_ARGS(2); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_set_dload_mode(struct device *dev, bool enable) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call_atomic(dev, &desc); -} - -int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = state; - desc.args[1] = id; - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, - size_t mem_sz, phys_addr_t src, size_t src_sz, - phys_addr_t dest, size_t dest_sz) -{ - return -ENODEV; -} - -int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, - u32 spare) -{ - return -ENODEV; -} - -int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, - size_t *size) -{ - return -ENODEV; -} - -int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, - u32 spare) -{ - return -ENODEV; -} - -int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, - unsigned int *val) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_IO, - .cmd = QCOM_SCM_IO_READ, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = addr; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call_atomic(dev, &desc); - if (ret >= 0) - *val = desc.result[0]; - - return ret < 0 ? ret : 0; -} - -int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_IO, - .cmd = QCOM_SCM_IO_WRITE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = addr; - desc.args[1] = val; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call_atomic(dev, &desc); -} - -int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable) -{ - return -ENODEV; -} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 5088c0c..1e81b89 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -14,46 +14,6 @@ #include "qcom_scm.h" -#define MAX_QCOM_SCM_ARGS 10 -#define MAX_QCOM_SCM_RETS 3 - -enum qcom_scm_arg_types { - QCOM_SCM_VAL, - QCOM_SCM_RO, - QCOM_SCM_RW, - QCOM_SCM_BUFVAL, -}; - -#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\ - (((a) & 0x3) << 4) | \ - (((b) & 0x3) << 6) | \ - (((c) & 0x3) << 8) | \ - (((d) & 0x3) << 10) | \ - (((e) & 0x3) << 12) | \ - (((f) & 0x3) << 14) | \ - (((g) & 0x3) << 16) | \ - (((h) & 0x3) << 18) | \ - (((i) & 0x3) << 20) | \ - (((j) & 0x3) << 22) | \ - ((num) & 0xf)) - -#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) - -/** - * struct qcom_scm_desc - * @arginfo: Metadata describing the arguments in args[] - * @args: The array of arguments for the secure syscall - * @res: The values returned by the secure syscall - */ -struct qcom_scm_desc { - u32 svc; - u32 cmd; - u32 arginfo; - u64 args[MAX_QCOM_SCM_ARGS]; - u64 result[MAX_QCOM_SCM_RETS]; - u32 owner; -}; - struct arm_smccc_args { unsigned long a[8]; }; @@ -189,7 +149,7 @@ static int ___qcom_scm_call_smccc(struct device *dev, * Sends a command to the SCM and waits for the command to finish processing. * This should *only* be called in pre-emptible context. */ -static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) +int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) { might_sleep(); return ___qcom_scm_call_smccc(dev, desc, false); @@ -206,52 +166,11 @@ static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) * Sends a command to the SCM and waits for the command to finish processing. * This can be called in atomic context. */ -static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) +int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) { return ___qcom_scm_call_smccc(dev, desc, true); } -/** - * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the cold boot address of the cpus. Any cpu outside the supported - * range would be removed from the cpu present mask. - */ -int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry, - const cpumask_t *cpus) -{ - return -ENOTSUPP; -} - -/** - * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus - * @dev: Device pointer - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the Linux entry point for the SCM to transfer control to when coming - * out of a power down. CPU power down may be executed on cpuidle or hotplug. - */ -int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, - const cpumask_t *cpus) -{ - return -ENOTSUPP; -} - -/** - * qcom_scm_cpu_power_down() - Power down the cpu - * @flags - Flags to flush cache - * - * This is an end point to power down cpu. If there was a pending interrupt, - * the control would return from this function, otherwise, the cpu jumps to the - * warm boot entry point set for this cpu upon reset. - */ -void __qcom_scm_cpu_power_down(struct device *dev, u32 flags) -{ -} - int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) { int ret; @@ -270,37 +189,6 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) return ret ? : desc.result[0]; } -int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, - u32 req_cnt, u32 *resp) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_HDCP, - .cmd = QCOM_SCM_HDCP_INVOKE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) - return -ERANGE; - - desc.args[0] = req[0].addr; - desc.args[1] = req[0].val; - desc.args[2] = req[1].addr; - desc.args[3] = req[1].val; - desc.args[4] = req[2].addr; - desc.args[5] = req[2].val; - desc.args[6] = req[3].addr; - desc.args[7] = req[3].val; - desc.args[8] = req[4].addr; - desc.args[9] = req[4].val; - desc.arginfo = QCOM_SCM_ARGS(10); - - ret = qcom_scm_call(dev, &desc); - *resp = desc.result[0]; - - return ret; -} - void __qcom_scm_init(void) { qcom_smccc_convention = ARM_SMCCC_SMC_64; @@ -318,286 +206,3 @@ void __qcom_scm_init(void) out: pr_debug("QCOM SCM SMC Convention: %llu\n", qcom_smccc_convention); } - -bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - - return ret ? false : !!desc.result[0]; -} - -int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, - dma_addr_t metadata_phys) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.args[1] = metadata_phys; - desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, - phys_addr_t addr, phys_addr_t size) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.args[1] = addr; - desc.args[2] = size; - desc.arginfo = QCOM_SCM_ARGS(3); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = peripheral; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = reset; - desc.args[1] = 0; - desc.arginfo = QCOM_SCM_ARGS(2); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = state; - desc.args[1] = id; - desc.arginfo = QCOM_SCM_ARGS(2); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, - size_t mem_sz, phys_addr_t src, size_t src_sz, - phys_addr_t dest, size_t dest_sz) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_MP, - .cmd = QCOM_SCM_MP_ASSIGN, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = mem_region; - desc.args[1] = mem_sz; - desc.args[2] = src; - desc.args[3] = src_sz; - desc.args[4] = dest; - desc.args[5] = dest_sz; - desc.args[6] = 0; - - desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL, - QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, - QCOM_SCM_VAL, QCOM_SCM_VAL); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_MP, - .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = device_id; - desc.args[1] = spare; - desc.arginfo = QCOM_SCM_ARGS(2); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, - size_t *size) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_MP, - .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = spare; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - - if (size) - *size = desc.result[0]; - - return ret ? : desc.result[1]; -} - -int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, - u32 spare) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_MP, - .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = addr; - desc.args[1] = size; - desc.args[2] = spare; - desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, - QCOM_SCM_VAL); - - ret = qcom_scm_call(dev, &desc); - - /* the pg table has been initialized already, ignore the error */ - if (ret == -EPERM) - ret = 0; - - return ret; -} - -int __qcom_scm_set_dload_mode(struct device *dev, bool enable) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call(dev, &desc); -} - -int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, - unsigned int *val) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_IO, - .cmd = QCOM_SCM_IO_READ, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = addr; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(dev, &desc); - if (ret >= 0) - *val = desc.result[0]; - - return ret < 0 ? ret : 0; -} - -int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_IO, - .cmd = QCOM_SCM_IO_WRITE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = addr; - desc.args[1] = val; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call(dev, &desc); -} - -int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_SMMU_PROGRAM, - .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; - desc.args[1] = en; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call_atomic(dev, &desc); -} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 1875e48..2dc9ca6 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "qcom_scm.h" @@ -84,6 +85,11 @@ static void qcom_scm_clk_disable(void) clk_disable_unprepare(__scm->bus_clk); } +#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 +#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 +#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 +#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20 + /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus @@ -94,11 +100,55 @@ static void qcom_scm_clk_disable(void) */ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) { - return __qcom_scm_set_cold_boot_addr(__scm ? __scm->dev : NULL, entry, - cpus); + int flags = 0; + int cpu; + int scm_cb_flags[] = { + QCOM_SCM_FLAG_COLDBOOT_CPU0, + QCOM_SCM_FLAG_COLDBOOT_CPU1, + QCOM_SCM_FLAG_COLDBOOT_CPU2, + QCOM_SCM_FLAG_COLDBOOT_CPU3, + }; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + if (!cpus || (cpus && cpumask_empty(cpus))) + return -EINVAL; + + for_each_cpu(cpu, cpus) { + if (cpu < ARRAY_SIZE(scm_cb_flags)) + flags |= scm_cb_flags[cpu]; + else + set_cpu_present(cpu, false); + } + + desc.args[0] = flags; + desc.args[1] = virt_to_phys(entry); + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc); } EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); +#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04 +#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02 +#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10 +#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40 + +struct qcom_scm_wb_entry { + int flag; + void *entry; +}; + +static struct qcom_scm_wb_entry qcom_scm_wb[] = { + { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 }, + { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 }, + { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 }, + { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 }, +}; + /** * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus * @entry: Entry point function for the cpus @@ -109,7 +159,39 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); */ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) { - return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus); + int ret; + int flags = 0; + int cpu; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR, + }; + + /* + * Reassign only if we are switching from hotplug entry point + * to cpuidle entry point or vice versa. + */ + for_each_cpu(cpu, cpus) { + if (entry == qcom_scm_wb[cpu].entry) + continue; + flags |= qcom_scm_wb[cpu].flag; + } + + /* No change in entry function */ + if (!flags) + return 0; + + desc.args[0] = flags; + desc.args[1] = virt_to_phys(entry); + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(__scm->dev, &desc); + if (!ret) { + for_each_cpu(cpu, cpus) + qcom_scm_wb[cpu].entry = entry; + } + + return ret; } EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); @@ -123,7 +205,15 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); */ void qcom_scm_cpu_power_down(u32 flags) { - __qcom_scm_cpu_power_down(__scm ? __scm->dev : NULL, flags); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_TERMINATE_PC, + .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, + .arginfo = QCOM_SCM_ARGS(1), + .owner = ARM_SMCCC_OWNER_SIP, + }; + + qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc); } EXPORT_SYMBOL(qcom_scm_cpu_power_down); @@ -158,13 +248,37 @@ EXPORT_SYMBOL(qcom_scm_hdcp_available); */ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) { - int ret = qcom_scm_clk_enable(); + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_HDCP, + .cmd = QCOM_SCM_HDCP_INVOKE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) + return -ERANGE; + ret = qcom_scm_clk_enable(); if (ret) return ret; - ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp); + desc.args[0] = req[0].addr; + desc.args[1] = req[0].val; + desc.args[2] = req[1].addr; + desc.args[3] = req[1].val; + desc.args[4] = req[2].addr; + desc.args[5] = req[2].val; + desc.args[6] = req[3].addr; + desc.args[7] = req[3].val; + desc.args[8] = req[4].addr; + desc.args[9] = req[4].val; + desc.arginfo = QCOM_SCM_ARGS(10); + + ret = qcom_scm_call(__scm->dev, &desc); + *resp = desc.result[0]; + qcom_scm_clk_disable(); + return ret; } EXPORT_SYMBOL(qcom_scm_hdcp_req); @@ -179,13 +293,23 @@ EXPORT_SYMBOL(qcom_scm_hdcp_req); bool qcom_scm_pas_supported(u32 peripheral) { int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, + .owner = ARM_SMCCC_OWNER_SIP, + }; ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_IS_SUPPORTED); if (ret <= 0) return false; - return __qcom_scm_pas_supported(__scm->dev, peripheral); + desc.args[0] = peripheral; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(__scm->dev, &desc); + + return ret ? false : !!desc.result[0]; } EXPORT_SYMBOL(qcom_scm_pas_supported); @@ -206,6 +330,11 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) dma_addr_t mdata_phys; void *mdata_buf; int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, + .owner = ARM_SMCCC_OWNER_SIP, + }; /* * During the scm call memory protection will be enabled for the meta @@ -224,14 +353,18 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) if (ret) goto free_metadata; - ret = __qcom_scm_pas_init_image(__scm->dev, peripheral, mdata_phys); + desc.args[0] = peripheral; + desc.args[1] = mdata_phys; + desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW); + + ret = qcom_scm_call(__scm->dev, &desc); qcom_scm_clk_disable(); free_metadata: dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); - return ret; + return ret ? : desc.result[0]; } EXPORT_SYMBOL(qcom_scm_pas_init_image); @@ -247,15 +380,25 @@ EXPORT_SYMBOL(qcom_scm_pas_init_image); int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) { int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, + .owner = ARM_SMCCC_OWNER_SIP, + }; ret = qcom_scm_clk_enable(); if (ret) return ret; - ret = __qcom_scm_pas_mem_setup(__scm->dev, peripheral, addr, size); + desc.args[0] = peripheral; + desc.args[1] = addr; + desc.args[2] = size; + desc.arginfo = QCOM_SCM_ARGS(3); + + ret = qcom_scm_call(__scm->dev, &desc); qcom_scm_clk_disable(); - return ret; + return ret ? : desc.result[0]; } EXPORT_SYMBOL(qcom_scm_pas_mem_setup); @@ -269,15 +412,20 @@ EXPORT_SYMBOL(qcom_scm_pas_mem_setup); int qcom_scm_pas_auth_and_reset(u32 peripheral) { int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, + .owner = ARM_SMCCC_OWNER_SIP, + }; ret = qcom_scm_clk_enable(); if (ret) return ret; - ret = __qcom_scm_pas_auth_and_reset(__scm->dev, peripheral); + ret = qcom_scm_call(__scm->dev, &desc); qcom_scm_clk_disable(); - return ret; + return ret ? : desc.result[0]; } EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset); @@ -290,18 +438,44 @@ EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset); int qcom_scm_pas_shutdown(u32 peripheral) { int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, + .owner = ARM_SMCCC_OWNER_SIP, + }; ret = qcom_scm_clk_enable(); if (ret) return ret; - ret = __qcom_scm_pas_shutdown(__scm->dev, peripheral); + desc.args[0] = peripheral; + desc.arginfo = QCOM_SCM_ARGS(1); + ret = qcom_scm_call(__scm->dev, &desc); + qcom_scm_clk_disable(); - return ret; + return ret ? : desc.result[0]; } EXPORT_SYMBOL(qcom_scm_pas_shutdown); +static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = reset; + desc.args[1] = 0; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(__scm->dev, &desc); + + return ret ? : desc.result[0]; +} + static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev, unsigned long idx) { @@ -327,40 +501,136 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = { int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { - return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = device_id; + desc.args[1] = spare; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(__scm->dev, &desc); + + return ret ? : desc.result[0]; } EXPORT_SYMBOL(qcom_scm_restore_sec_cfg); int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { - return __qcom_scm_iommu_secure_ptbl_size(__scm->dev, spare, size); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = spare; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(__scm->dev, &desc); + + if (size) + *size = desc.result[0]; + + return ret ? : desc.result[1]; } EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size); int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { - return __qcom_scm_iommu_secure_ptbl_init(__scm->dev, addr, size, spare); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = addr; + desc.args[1] = size; + desc.args[2] = spare; + desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, + QCOM_SCM_VAL); + + ret = qcom_scm_call(__scm->dev, &desc); + + /* the pg table has been initialized already, ignore the error */ + if (ret == -EPERM) + ret = 0; + + return ret; } EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { - return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_SMMU_PROGRAM, + .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; + desc.args[1] = en; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(__scm->dev, &desc); } EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { - return __qcom_scm_io_readl(__scm->dev, addr, val); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_READ, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = addr; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(__scm->dev, &desc); + if (ret >= 0) + *val = desc.result[0]; + + return ret < 0 ? ret : 0; } EXPORT_SYMBOL(qcom_scm_io_readl); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { - return __qcom_scm_io_writel(__scm->dev, addr, val); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_WRITE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = addr; + desc.args[1] = val; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call(__scm->dev, &desc); } EXPORT_SYMBOL(qcom_scm_io_writel); +static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; + desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call(__scm->dev, &desc); +} + static void qcom_scm_set_download_mode(bool enable) { bool avail; @@ -372,8 +642,8 @@ static void qcom_scm_set_download_mode(bool enable) if (avail) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else if (__scm->dload_mode_addr) { - ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + ret = qcom_scm_io_writel(__scm->dload_mode_addr, + enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n"); @@ -420,10 +690,51 @@ EXPORT_SYMBOL(qcom_scm_is_available); int qcom_scm_set_remote_state(u32 state, u32 id) { - return __qcom_scm_set_remote_state(__scm->dev, state, id); + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = state; + desc.args[1] = id; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(__scm->dev, &desc); + + return ret ? : desc.result[0]; } EXPORT_SYMBOL(qcom_scm_set_remote_state); +static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, + size_t mem_sz, phys_addr_t src, size_t src_sz, + phys_addr_t dest, size_t dest_sz) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_ASSIGN, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = mem_region; + desc.args[1] = mem_sz; + desc.args[2] = src; + desc.args[3] = src_sz; + desc.args[4] = dest; + desc.args[5] = dest_sz; + desc.args[6] = 0; + + desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL, + QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, + QCOM_SCM_VAL, QCOM_SCM_VAL); + + ret = qcom_scm_call(dev, &desc); + + return ret ? : desc.result[0]; +} + /** * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership * @mem_addr: mem region whose ownership need to be reassigned diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 35cdacf..efbd31b 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -4,27 +4,60 @@ #ifndef __QCOM_SCM_INT_H #define __QCOM_SCM_INT_H +#define MAX_QCOM_SCM_ARGS 10 +#define MAX_QCOM_SCM_RETS 3 + +enum qcom_scm_arg_types { + QCOM_SCM_VAL, + QCOM_SCM_RO, + QCOM_SCM_RW, + QCOM_SCM_BUFVAL, +}; + +#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\ + (((a) & 0x3) << 4) | \ + (((b) & 0x3) << 6) | \ + (((c) & 0x3) << 8) | \ + (((d) & 0x3) << 10) | \ + (((e) & 0x3) << 12) | \ + (((f) & 0x3) << 14) | \ + (((g) & 0x3) << 16) | \ + (((h) & 0x3) << 18) | \ + (((i) & 0x3) << 20) | \ + (((j) & 0x3) << 22) | \ + ((num) & 0xf)) + +#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + +/** + * struct qcom_scm_desc + * @arginfo: Metadata describing the arguments in args[] + * @args: The array of arguments for the secure syscall + * @res: The values returned by the secure syscall + */ +struct qcom_scm_desc { + u32 svc; + u32 cmd; + u32 arginfo; + u64 args[MAX_QCOM_SCM_ARGS]; + u64 result[MAX_QCOM_SCM_RETS]; + u32 owner; +}; + +extern int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc); +extern int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc); + #define QCOM_SCM_SVC_BOOT 0x1 #define QCOM_SCM_BOOT_SET_ADDR 0x1 #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa -extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id); -extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable); - -extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, - const cpumask_t *cpus); -extern int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry, - const cpumask_t *cpus); #define QCOM_SCM_BOOT_TERMINATE_PC 0x2 #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 -extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags); #define QCOM_SCM_SVC_IO 0x5 #define QCOM_SCM_IO_READ 0x1 #define QCOM_SCM_IO_WRITE 0x2 -extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val); -extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val); #define QCOM_SCM_SVC_INFO 0x6 #define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1 @@ -33,8 +66,6 @@ extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, #define QCOM_SCM_SVC_HDCP 0x11 #define QCOM_SCM_HDCP_INVOKE 0x01 -extern int __qcom_scm_hdcp_req(struct device *dev, - struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); extern void __qcom_scm_init(void); @@ -45,14 +76,6 @@ extern void __qcom_scm_init(void); #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7 #define QCOM_SCM_PIL_PAS_MSS_RESET 0xa -extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral); -extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, - dma_addr_t metadata_phys); -extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, - phys_addr_t addr, phys_addr_t size); -extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral); -extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral); -extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset); /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 @@ -83,23 +106,11 @@ static inline int qcom_scm_remap_error(int err) #define QCOM_SCM_SVC_MP 0xc #define QCOM_SCM_MP_RESTORE_SEC_CFG 2 -extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, - u32 spare); #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4 #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2 -extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, - size_t *size); -extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, - u32 size, u32 spare); -extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, - bool enable); #define QCOM_SCM_MP_ASSIGN 0x16 -extern int __qcom_scm_assign_mem(struct device *dev, - phys_addr_t mem_region, size_t mem_sz, - phys_addr_t src, size_t src_sz, - phys_addr_t dest, size_t dest_sz); #endif From patchwork Tue Nov 12 21:22:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240217 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED65013BD for ; Tue, 12 Nov 2019 21:23:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BADDF2196E for ; Tue, 12 Nov 2019 21:23:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="QYaAFodG"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="mcAwudpx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727529AbfKLVXt (ORCPT ); Tue, 12 Nov 2019 16:23:49 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39724 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727558AbfKLVXl (ORCPT ); Tue, 12 Nov 2019 16:23:41 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 68F5360E41; Tue, 12 Nov 2019 21:23:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593820; bh=3ShVWlPxHy6AL9JZ69PAjwpmkYBqKlOzEw16PWYc5DE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QYaAFodGMISQJj21yscIt4Ue65RwZfPIh936ZDI50o0tJG6x3071GWOO7J82dsjtM PoV0XmCY7T6a8yfxyFxMtgtxH9yDmbseOt7goGsYlWdNuuD/CMGDwgFUxI1Xt54vCK t9jjrRYEd/x3qT7DjJ9Lq4XplWfgTXN01Ntog0zw= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from eberman-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: eberman@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C18E460E3C; Tue, 12 Nov 2019 21:23:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593801; bh=3ShVWlPxHy6AL9JZ69PAjwpmkYBqKlOzEw16PWYc5DE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mcAwudpxp91VL+AdljWcxg1OrRqbVTwbzCWYJpNVMll0IABcq7K7xylN9KKwuPnqo MD67Smt+20l5tvL63C/28sBYL1+P0MHTHB/DaTjlg9KPNxu9mNSVupLyxUERmzHwjP nTbGXSXc/zGCKRErKXxzsnlZd4s4I8tY2HUUHP8k= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C18E460E3C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 17/18] firmware: qcom_scm: Dynamically support SMCCC and legacy conventions Date: Tue, 12 Nov 2019 13:22:53 -0800 Message-Id: <1573593774-12539-18-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Dynamically support SMCCCC and legacy conventions by detecting which convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can then be moved in qcom_scm.c and use underlying convention backend as appropriate. Thus, rename qcom_scm-64,-32 to reflect that they are backends for -smccc and -legacy, respectively. Signed-off-by: Elliot Berman --- drivers/firmware/Kconfig | 8 -- drivers/firmware/Makefile | 4 +- .../firmware/{qcom_scm-32.c => qcom_scm-legacy.c} | 24 +---- .../firmware/{qcom_scm-64.c => qcom_scm-smccc.c} | 77 +------------- drivers/firmware/qcom_scm.c | 113 ++++++++++++++++++++- drivers/firmware/qcom_scm.h | 23 +++-- 6 files changed, 137 insertions(+), 112 deletions(-) rename drivers/firmware/{qcom_scm-32.c => qcom_scm-legacy.c} (92%) rename drivers/firmware/{qcom_scm-64.c => qcom_scm-smccc.c} (60%) diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index e40a77b..ea869ad 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -239,14 +239,6 @@ config QCOM_SCM depends on ARM || ARM64 select RESET_CONTROLLER -config QCOM_SCM_32 - def_bool y - depends on QCOM_SCM && ARM - -config QCOM_SCM_64 - def_bool y - depends on QCOM_SCM && ARM64 - config QCOM_SCM_DOWNLOAD_MODE_DEFAULT bool "Qualcomm download mode enabled by default" depends on QCOM_SCM diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index 747fb73..4ae2f55 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -17,9 +17,7 @@ obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o -obj-$(CONFIG_QCOM_SCM) += qcom_scm.o -obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o -obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o +obj-$(CONFIG_QCOM_SCM) += qcom_scm.o qcom_scm-smccc.o qcom_scm-legacy.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-legacy.c similarity index 92% rename from drivers/firmware/qcom_scm-32.c rename to drivers/firmware/qcom_scm-legacy.c index 9e3789d..8d7ce69 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-legacy.c @@ -21,7 +21,6 @@ struct arm_smccc_args { unsigned long a[8]; }; -#define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff)) /** * struct qcom_scm_legacy_command - one SCM command buffer @@ -124,7 +123,7 @@ static void __qcom_scm_call_do(const struct arm_smccc_args *smc, * and response buffers is taken care of by qcom_scm_call; however, callers are * responsible for any other cached buffers passed over to the secure world. */ -int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) +int qcom_scm_call_legacy(struct device *dev, struct qcom_scm_desc *desc) { int arglen = desc->arginfo & 0xf; int ret = 0, context_id; @@ -208,7 +207,7 @@ int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) * This shall only be used with commands that are guaranteed to be * uninterruptable, atomic and SMP safe. */ -int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) +int qcom_scm_call_legacy_atomic(struct device *dev, struct qcom_scm_desc *desc) { int context_id; struct arm_smccc_args smc = {0}; @@ -232,22 +231,3 @@ int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) return res.a0; } - -int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_INFO, - .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, - .args[0] = LEGACY_FUNCNUM(svc_id, cmd_id), - .arginfo = QCOM_SCM_ARGS(1), - }; - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -void __qcom_scm_init(void) -{ -} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-smccc.c similarity index 60% rename from drivers/firmware/qcom_scm-64.c rename to drivers/firmware/qcom_scm-smccc.c index 1e81b89..f398f09 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-smccc.c @@ -18,13 +18,11 @@ struct arm_smccc_args { unsigned long a[8]; }; -static u64 qcom_smccc_convention = -1; static DEFINE_MUTEX(qcom_scm_lock); #define QCOM_SCM_EBUSY_WAIT_MS 30 #define QCOM_SCM_EBUSY_MAX_RETRY 20 -#define SMCCC_FUNCNUM(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) #define SMCCC_N_REG_ARGS 4 #define SMCCC_FIRST_EXT_IDX (SMCCC_N_REG_ARGS - 1) #define SMCCC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SMCCC_N_REG_ARGS + 1) @@ -50,8 +48,8 @@ static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc, } while (res->a0 == QCOM_SCM_INTERRUPTED); } -static int ___qcom_scm_call_smccc(struct device *dev, - struct qcom_scm_desc *desc, bool atomic) +int qcom_scm_call_smccc(struct device *dev, struct qcom_scm_desc *desc, + bool atomic) { int arglen = desc->arginfo & 0xf; int i; @@ -60,6 +58,9 @@ static int ___qcom_scm_call_smccc(struct device *dev, size_t alloc_len; gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL; u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL; + u32 qcom_smccc_convention = + (qcom_scm_convention == SMC_CONVENTION_ARM_32) ? + ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64; struct arm_smccc_res res; struct arm_smccc_args smc = {0}; @@ -138,71 +139,3 @@ static int ___qcom_scm_call_smccc(struct device *dev, return 0; } - -/** - * qcom_scm_call() - Invoke a syscall in the secure world - * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier - * @desc: Descriptor structure containing arguments and return values - * - * Sends a command to the SCM and waits for the command to finish processing. - * This should *only* be called in pre-emptible context. - */ -int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) -{ - might_sleep(); - return ___qcom_scm_call_smccc(dev, desc, false); -} - -/** - * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() - * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier - * @desc: Descriptor structure containing arguments and return values - * @res: Structure containing results from SMC/HVC call - * - * Sends a command to the SCM and waits for the command to finish processing. - * This can be called in atomic context. - */ -int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) -{ - return ___qcom_scm_call_smccc(dev, desc, true); -} - -int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_INFO, - .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.arginfo = QCOM_SCM_ARGS(1); - desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | - (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - -void __qcom_scm_init(void) -{ - qcom_smccc_convention = ARM_SMCCC_SMC_64; - if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, - QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) - goto out; - - qcom_smccc_convention = ARM_SMCCC_SMC_32; - if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, - QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) - goto out; - - qcom_smccc_convention = -1; - BUG(); -out: - pr_debug("QCOM SCM SMC Convention: %llu\n", qcom_smccc_convention); -} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 2dc9ca6..b122fa7 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -85,6 +85,117 @@ static void qcom_scm_clk_disable(void) clk_disable_unprepare(__scm->bus_clk); } +static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, + u32 cmd_id); + +enum qcom_scm_convention qcom_scm_convention; +static enum qcom_scm_convention __get_convention(void) +{ + if (likely(qcom_scm_convention != SMC_CONVENTION_UNKNOWN)) + return qcom_scm_convention; + + qcom_scm_convention = SMC_CONVENTION_LEGACY; + if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, + QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) + goto out; + + qcom_scm_convention = SMC_CONVENTION_ARM_64; + if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, + QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) + goto out; + + qcom_scm_convention = SMC_CONVENTION_ARM_32; + if (__qcom_scm_is_call_available(NULL, QCOM_SCM_SVC_INFO, + QCOM_SCM_INFO_IS_CALL_AVAIL) == 1) + goto out; + + qcom_scm_convention = SMC_CONVENTION_UNKNOWN; + BUG(); +out: + pr_debug("QCOM SCM SMC Convention: %d\n", qcom_scm_convention); + return qcom_scm_convention; +} + +/** + * qcom_scm_call() - Invoke a syscall in the secure world + * @dev: device + * @svc_id: service identifier + * @cmd_id: command identifier + * @desc: Descriptor structure containing arguments and return values + * + * Sends a command to the SCM and waits for the command to finish processing. + * This should *only* be called in pre-emptible context. + */ +static int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc) +{ + might_sleep(); + switch (__get_convention()) { + case SMC_CONVENTION_ARM_32: + case SMC_CONVENTION_ARM_64: + return qcom_scm_call_smccc(dev, desc, false); + case SMC_CONVENTION_LEGACY: + return qcom_scm_call_legacy(dev, desc); + default: + pr_err("Unknown current SCM calling convention.\n"); + return -EINVAL; + } +} + +/** + * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() + * @dev: device + * @svc_id: service identifier + * @cmd_id: command identifier + * @desc: Descriptor structure containing arguments and return values + * @res: Structure containing results from SMC/HVC call + * + * Sends a command to the SCM and waits for the command to finish processing. + * This can be called in atomic context. + */ +static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) +{ + switch (__get_convention()) { + case SMC_CONVENTION_ARM_32: + case SMC_CONVENTION_ARM_64: + return qcom_scm_call_smccc(dev, desc, true); + case SMC_CONVENTION_LEGACY: + return qcom_scm_call_legacy_atomic(dev, desc); + default: + pr_err("Unknown current SCM calling convention.\n"); + return -EINVAL; + } +} + +static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, + u32 cmd_id) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_INFO, + .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.arginfo = QCOM_SCM_ARGS(1); + switch (__get_convention()) { + case SMC_CONVENTION_ARM_32: + case SMC_CONVENTION_ARM_64: + desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | + (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); + break; + case SMC_CONVENTION_LEGACY: + desc.args[0] = LEGACY_FUNCNUM(svc_id, cmd_id); + break; + default: + pr_err("Unknown SMC convention being used\n"); + return -EINVAL; + } + + ret = qcom_scm_call(dev, &desc); + + return ret ? : desc.result[0]; +} + #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 @@ -887,7 +998,7 @@ static int qcom_scm_probe(struct platform_device *pdev) __scm = scm; __scm->dev = &pdev->dev; - __qcom_scm_init(); + __get_convention(); /* * If requested enable "download mode", from this point on warmboot diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index efbd31b..9252498 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -4,6 +4,15 @@ #ifndef __QCOM_SCM_INT_H #define __QCOM_SCM_INT_H +enum qcom_scm_convention { + SMC_CONVENTION_UNKNOWN, + SMC_CONVENTION_LEGACY, + SMC_CONVENTION_ARM_32, + SMC_CONVENTION_ARM_64, +}; + +extern enum qcom_scm_convention qcom_scm_convention; + #define MAX_QCOM_SCM_ARGS 10 #define MAX_QCOM_SCM_RETS 3 @@ -44,8 +53,14 @@ struct qcom_scm_desc { u32 owner; }; -extern int qcom_scm_call(struct device *dev, struct qcom_scm_desc *desc); -extern int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc); +#define SMCCC_FUNCNUM(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF)) +extern int qcom_scm_call_smccc(struct device *dev, struct qcom_scm_desc *desc, + bool atomic); + +#define LEGACY_FUNCNUM(s, c) (((s) << 10) | ((c) & 0x3ff)) +extern int qcom_scm_call_legacy_atomic(struct device *dev, + struct qcom_scm_desc *desc); +extern int qcom_scm_call_legacy(struct device *dev, struct qcom_scm_desc *desc); #define QCOM_SCM_SVC_BOOT 0x1 #define QCOM_SCM_BOOT_SET_ADDR 0x1 @@ -61,14 +76,10 @@ extern int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc); #define QCOM_SCM_SVC_INFO 0x6 #define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1 -extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, - u32 cmd_id); #define QCOM_SCM_SVC_HDCP 0x11 #define QCOM_SCM_HDCP_INVOKE 0x01 -extern void __qcom_scm_init(void); - #define QCOM_SCM_SVC_PIL 0x2 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1 #define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2 From patchwork Tue Nov 12 21:22:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 11240213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 715F915AB for ; Tue, 12 Nov 2019 21:23:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2EF8221E6F for ; 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Tue, 12 Nov 2019 21:23:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1573593802; bh=UNt2o5b21usfutEFdS4JXMNpEaVTvTzueKnWUHOi/rk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T8mOurHCGQpGUWmHNfytBHJzfpCLReSS9G1Jk7iqALeebfR9ETMRyb77RB0OnKudw 0rikoJ5yJ+z46SN0ltAAbutSWQYIaikAji1y+eHY8BIT+wHvHlhT1P9BsvQzm6bpL2 qZP5tGlM5Qk/ng09R7Cd2uiJ9DHmG90lYdnJSu2Y= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E66A860E75 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=eberman@codeaurora.org From: Elliot Berman To: bjorn.andersson@linaro.org, saiprakash.ranjan@codeaurora.org, agross@kernel.org, swboyd@chromium.org Cc: Elliot Berman , tsoni@codeaurora.org, sidgup@codeaurora.org, psodagud@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 18/18] firmware: qcom_scm: Order functions, definitions by service/command Date: Tue, 12 Nov 2019 13:22:54 -0800 Message-Id: <1573593774-12539-19-git-send-email-eberman@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> References: <1573593774-12539-1-git-send-email-eberman@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Definitions throughout qcom_scm are loosely grouped and loosely ordered. Sort all the functions/definitions by service ID/command ID to improve sanity when needing to add new functionality to this driver. Acked-by: Bjorn Andersson Signed-off-by: Elliot Berman --- drivers/firmware/qcom_scm.c | 524 ++++++++++++++++++++++---------------------- drivers/firmware/qcom_scm.h | 54 +++-- include/linux/qcom_scm.h | 97 ++++---- 3 files changed, 344 insertions(+), 331 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index b122fa7..f953f3c 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -37,19 +37,6 @@ struct qcom_scm { u64 dload_mode_addr; }; -struct qcom_scm_current_perm_info { - __le32 vmid; - __le32 perm; - __le64 ctx; - __le32 ctx_size; - __le32 unused; -}; - -struct qcom_scm_mem_map_info { - __le64 mem_addr; - __le64 mem_size; -}; - static struct qcom_scm *__scm; static int qcom_scm_clk_enable(void) @@ -166,36 +153,6 @@ static int qcom_scm_call_atomic(struct device *dev, struct qcom_scm_desc *desc) } } -static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, - u32 cmd_id) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_INFO, - .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.arginfo = QCOM_SCM_ARGS(1); - switch (__get_convention()) { - case SMC_CONVENTION_ARM_32: - case SMC_CONVENTION_ARM_64: - desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | - (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); - break; - case SMC_CONVENTION_LEGACY: - desc.args[0] = LEGACY_FUNCNUM(svc_id, cmd_id); - break; - default: - pr_err("Unknown SMC convention being used\n"); - return -EINVAL; - } - - ret = qcom_scm_call(dev, &desc); - - return ret ? : desc.result[0]; -} - #define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 #define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 #define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 @@ -306,6 +263,8 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) } EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); +#define QCOM_SCM_FLUSH_FLAG_MASK 0x03 + /** * qcom_scm_cpu_power_down() - Power down the cpu * @flags - Flags to flush cache @@ -328,101 +287,61 @@ void qcom_scm_cpu_power_down(u32 flags) } EXPORT_SYMBOL(qcom_scm_cpu_power_down); -/** - * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. - * - * Return true if HDCP is supported, false if not. - */ -bool qcom_scm_hdcp_available(void) -{ - int ret = qcom_scm_clk_enable(); - - if (ret) - return ret; - - ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, - QCOM_SCM_HDCP_INVOKE); - - qcom_scm_clk_disable(); - - return ret > 0 ? true : false; -} -EXPORT_SYMBOL(qcom_scm_hdcp_available); - -/** - * qcom_scm_hdcp_req() - Send HDCP request. - * @req: HDCP request array - * @req_cnt: HDCP request array count - * @resp: response buffer passed to SCM - * - * Write HDCP register(s) through SCM. - */ -int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) +int qcom_scm_set_remote_state(u32 state, u32 id) { - int ret; struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_HDCP, - .cmd = QCOM_SCM_HDCP_INVOKE, + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, .owner = ARM_SMCCC_OWNER_SIP, }; + int ret; - if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) - return -ERANGE; - - ret = qcom_scm_clk_enable(); - if (ret) - return ret; - - desc.args[0] = req[0].addr; - desc.args[1] = req[0].val; - desc.args[2] = req[1].addr; - desc.args[3] = req[1].val; - desc.args[4] = req[2].addr; - desc.args[5] = req[2].val; - desc.args[6] = req[3].addr; - desc.args[7] = req[3].val; - desc.args[8] = req[4].addr; - desc.args[9] = req[4].val; - desc.arginfo = QCOM_SCM_ARGS(10); + desc.args[0] = state; + desc.args[1] = id; + desc.arginfo = QCOM_SCM_ARGS(2); ret = qcom_scm_call(__scm->dev, &desc); - *resp = desc.result[0]; - - qcom_scm_clk_disable(); - return ret; + return ret ? : desc.result[0]; } -EXPORT_SYMBOL(qcom_scm_hdcp_req); +EXPORT_SYMBOL(qcom_scm_set_remote_state); -/** - * qcom_scm_pas_supported() - Check if the peripheral authentication service is - * available for the given peripherial - * @peripheral: peripheral id - * - * Returns true if PAS is supported for this peripheral, otherwise false. - */ -bool qcom_scm_pas_supported(u32 peripheral) +static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { - int ret; struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_PIL, - .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, .owner = ARM_SMCCC_OWNER_SIP, }; - ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, - QCOM_SCM_PIL_PAS_IS_SUPPORTED); - if (ret <= 0) - return false; + desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; + desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; + desc.arginfo = QCOM_SCM_ARGS(2); - desc.args[0] = peripheral; - desc.arginfo = QCOM_SCM_ARGS(1); + return qcom_scm_call(__scm->dev, &desc); +} - ret = qcom_scm_call(__scm->dev, &desc); +static void qcom_scm_set_download_mode(bool enable) +{ + bool avail; + int ret = 0; - return ret ? false : !!desc.result[0]; + avail = __qcom_scm_is_call_available(__scm->dev, + QCOM_SCM_SVC_BOOT, + QCOM_SCM_BOOT_SET_DLOAD_MODE); + if (avail) { + ret = __qcom_scm_set_dload_mode(__scm->dev, enable); + } else if (__scm->dload_mode_addr) { + ret = qcom_scm_io_writel(__scm->dload_mode_addr, + enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + } else { + dev_err(__scm->dev, + "No available mechanism for setting download mode\n"); + } + + if (ret) + dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } -EXPORT_SYMBOL(qcom_scm_pas_supported); /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service @@ -569,6 +488,36 @@ int qcom_scm_pas_shutdown(u32 peripheral) } EXPORT_SYMBOL(qcom_scm_pas_shutdown); +/** + * qcom_scm_pas_supported() - Check if the peripheral authentication service is + * available for the given peripherial + * @peripheral: peripheral id + * + * Returns true if PAS is supported for this peripheral, otherwise false. + */ +bool qcom_scm_pas_supported(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_PIL_PAS_IS_SUPPORTED); + if (ret <= 0) + return false; + + desc.args[0] = peripheral; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(__scm->dev, &desc); + + return ret ? false : !!desc.result[0]; +} +EXPORT_SYMBOL(qcom_scm_pas_supported); + static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { struct qcom_scm_desc desc = { @@ -610,6 +559,72 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = { .deassert = qcom_scm_pas_reset_deassert, }; +int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_READ, + .owner = ARM_SMCCC_OWNER_SIP, + }; + int ret; + + desc.args[0] = addr; + desc.arginfo = QCOM_SCM_ARGS(1); + + ret = qcom_scm_call(__scm->dev, &desc); + if (ret >= 0) + *val = desc.result[0]; + + return ret < 0 ? ret : 0; +} +EXPORT_SYMBOL(qcom_scm_io_readl); + +int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_IO, + .cmd = QCOM_SCM_IO_WRITE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = addr; + desc.args[1] = val; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call(__scm->dev, &desc); +} +EXPORT_SYMBOL(qcom_scm_io_writel); + +static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, + u32 cmd_id) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_INFO, + .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.arginfo = QCOM_SCM_ARGS(1); + switch (__get_convention()) { + case SMC_CONVENTION_ARM_32: + case SMC_CONVENTION_ARM_64: + desc.args[0] = SMCCC_FUNCNUM(svc_id, cmd_id) | + (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); + break; + case SMC_CONVENTION_LEGACY: + desc.args[0] = LEGACY_FUNCNUM(svc_id, cmd_id); + break; + default: + pr_err("Unknown SMC convention being used\n"); + return -EINVAL; + } + + ret = qcom_scm_call(dev, &desc); + + return ret ? : desc.result[0]; +} + int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { struct qcom_scm_desc desc = { @@ -675,148 +690,18 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) } EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); -int qcom_scm_qsmmu500_wait_safe_toggle(bool en) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_SMMU_PROGRAM, - .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; - desc.args[1] = en; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call_atomic(__scm->dev, &desc); -} -EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); - -int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_IO, - .cmd = QCOM_SCM_IO_READ, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = addr; - desc.arginfo = QCOM_SCM_ARGS(1); - - ret = qcom_scm_call(__scm->dev, &desc); - if (ret >= 0) - *val = desc.result[0]; - - return ret < 0 ? ret : 0; -} -EXPORT_SYMBOL(qcom_scm_io_readl); - -int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_IO, - .cmd = QCOM_SCM_IO_WRITE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = addr; - desc.args[1] = val; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call(__scm->dev, &desc); -} -EXPORT_SYMBOL(qcom_scm_io_writel); - -static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - - desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE; - desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; - desc.arginfo = QCOM_SCM_ARGS(2); - - return qcom_scm_call(__scm->dev, &desc); -} - -static void qcom_scm_set_download_mode(bool enable) -{ - bool avail; - int ret = 0; - - avail = __qcom_scm_is_call_available(__scm->dev, - QCOM_SCM_SVC_BOOT, - QCOM_SCM_BOOT_SET_DLOAD_MODE); - if (avail) { - ret = __qcom_scm_set_dload_mode(__scm->dev, enable); - } else if (__scm->dload_mode_addr) { - ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); - } else { - dev_err(__scm->dev, - "No available mechanism for setting download mode\n"); - } - - if (ret) - dev_err(__scm->dev, "failed to set download mode: %d\n", ret); -} - -static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) -{ - struct device_node *tcsr; - struct device_node *np = dev->of_node; - struct resource res; - u32 offset; - int ret; - - tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); - if (!tcsr) - return 0; - - ret = of_address_to_resource(tcsr, 0, &res); - of_node_put(tcsr); - if (ret) - return ret; - - ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); - if (ret < 0) - return ret; - - *addr = res.start + offset; - - return 0; -} - -/** - * qcom_scm_is_available() - Checks if SCM is available - */ -bool qcom_scm_is_available(void) -{ - return !!__scm; -} -EXPORT_SYMBOL(qcom_scm_is_available); - -int qcom_scm_set_remote_state(u32 state, u32 id) -{ - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, - .owner = ARM_SMCCC_OWNER_SIP, - }; - int ret; - - desc.args[0] = state; - desc.args[1] = id; - desc.arginfo = QCOM_SCM_ARGS(2); - - ret = qcom_scm_call(__scm->dev, &desc); +struct qcom_scm_current_perm_info { + __le32 vmid; + __le32 perm; + __le64 ctx; + __le32 ctx_size; + __le32 unused; +}; - return ret ? : desc.result[0]; -} -EXPORT_SYMBOL(qcom_scm_set_remote_state); +struct qcom_scm_mem_map_info { + __le64 mem_addr; + __le64 mem_size; +}; static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, size_t mem_sz, phys_addr_t src, size_t src_sz, @@ -928,6 +813,125 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, } EXPORT_SYMBOL(qcom_scm_assign_mem); +/** + * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. + * + * Return true if HDCP is supported, false if not. + */ +bool qcom_scm_hdcp_available(void) +{ + int ret = qcom_scm_clk_enable(); + + if (ret) + return ret; + + ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, + QCOM_SCM_HDCP_INVOKE); + + qcom_scm_clk_disable(); + + return ret > 0 ? true : false; +} +EXPORT_SYMBOL(qcom_scm_hdcp_available); + +/** + * qcom_scm_hdcp_req() - Send HDCP request. + * @req: HDCP request array + * @req_cnt: HDCP request array count + * @resp: response buffer passed to SCM + * + * Write HDCP register(s) through SCM. + */ +int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_HDCP, + .cmd = QCOM_SCM_HDCP_INVOKE, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) + return -ERANGE; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + desc.args[0] = req[0].addr; + desc.args[1] = req[0].val; + desc.args[2] = req[1].addr; + desc.args[3] = req[1].val; + desc.args[4] = req[2].addr; + desc.args[5] = req[2].val; + desc.args[6] = req[3].addr; + desc.args[7] = req[3].val; + desc.args[8] = req[4].addr; + desc.args[9] = req[4].val; + desc.arginfo = QCOM_SCM_ARGS(10); + + ret = qcom_scm_call(__scm->dev, &desc); + *resp = desc.result[0]; + + + qcom_scm_clk_disable(); + + return ret; +} +EXPORT_SYMBOL(qcom_scm_hdcp_req); + +#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 +int qcom_scm_qsmmu500_wait_safe_toggle(bool en) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_SMMU_PROGRAM, + .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL; + desc.args[1] = en; + desc.arginfo = QCOM_SCM_ARGS(2); + + return qcom_scm_call_atomic(__scm->dev, &desc); +} +EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); + +static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) +{ + struct device_node *tcsr; + struct device_node *np = dev->of_node; + struct resource res; + u32 offset; + int ret; + + tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); + if (!tcsr) + return 0; + + ret = of_address_to_resource(tcsr, 0, &res); + of_node_put(tcsr); + if (ret) + return ret; + + ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); + if (ret < 0) + return ret; + + *addr = res.start + offset; + + return 0; +} + +/** + * qcom_scm_is_available() - Checks if SCM is available + */ +bool qcom_scm_is_available(void) +{ + return !!__scm; +} +EXPORT_SYMBOL(qcom_scm_is_available); + static int qcom_scm_probe(struct platform_device *pdev) { struct qcom_scm *scm; diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 9252498..dda7354 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -62,31 +62,38 @@ extern int qcom_scm_call_legacy_atomic(struct device *dev, struct qcom_scm_desc *desc); extern int qcom_scm_call_legacy(struct device *dev, struct qcom_scm_desc *desc); -#define QCOM_SCM_SVC_BOOT 0x1 -#define QCOM_SCM_BOOT_SET_ADDR 0x1 +#define QCOM_SCM_SVC_BOOT 0x01 +#define QCOM_SCM_BOOT_SET_ADDR 0x01 +#define QCOM_SCM_BOOT_TERMINATE_PC 0x02 +#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 -#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa -#define QCOM_SCM_BOOT_TERMINATE_PC 0x2 -#define QCOM_SCM_FLUSH_FLAG_MASK 0x3 +#define QCOM_SCM_SVC_PIL 0x02 +#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 +#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02 +#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05 +#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 +#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 +#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a -#define QCOM_SCM_SVC_IO 0x5 -#define QCOM_SCM_IO_READ 0x1 -#define QCOM_SCM_IO_WRITE 0x2 +#define QCOM_SCM_SVC_IO 0x05 +#define QCOM_SCM_IO_READ 0x01 +#define QCOM_SCM_IO_WRITE 0x02 -#define QCOM_SCM_SVC_INFO 0x6 -#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1 +#define QCOM_SCM_SVC_INFO 0x06 +#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01 -#define QCOM_SCM_SVC_HDCP 0x11 -#define QCOM_SCM_HDCP_INVOKE 0x01 +#define QCOM_SCM_SVC_MP 0x0c +#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02 +#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03 +#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04 +#define QCOM_SCM_MP_ASSIGN 0x16 -#define QCOM_SCM_SVC_PIL 0x2 -#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1 -#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2 -#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x5 -#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6 -#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7 -#define QCOM_SCM_PIL_PAS_MSS_RESET 0xa +#define QCOM_SCM_SVC_HDCP 0x11 +#define QCOM_SCM_HDCP_INVOKE 0x01 + +#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 +#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 @@ -115,13 +122,4 @@ static inline int qcom_scm_remap_error(int err) return -EINVAL; } -#define QCOM_SCM_SVC_MP 0xc -#define QCOM_SCM_MP_RESTORE_SEC_CFG 2 -#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3 -#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4 -#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 -#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3 -#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2 -#define QCOM_SCM_MP_ASSIGN 0x16 - #endif diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index c52c591..a699759 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. */ #ifndef __QCOM_SCM_H @@ -35,69 +35,80 @@ struct qcom_scm_vmperm { #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC) #if IS_ENABLED(CONFIG_QCOM_SCM) +extern bool qcom_scm_is_available(void); + extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus); -extern bool qcom_scm_is_available(void); -extern bool qcom_scm_hdcp_available(void); -extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, - u32 *resp); -extern bool qcom_scm_pas_supported(u32 peripheral); +extern void qcom_scm_cpu_power_down(u32 flags); +extern int qcom_scm_set_remote_state(u32 state, u32 id); + extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size); extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); +extern bool qcom_scm_pas_supported(u32 peripheral); + +extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); +extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); + +extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); +extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); +extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, unsigned int *src, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt); -extern void qcom_scm_cpu_power_down(u32 flags); -extern int qcom_scm_set_remote_state(u32 state, u32 id); -extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); -extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); -extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); + +extern bool qcom_scm_hdcp_available(void); +extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, + u32 *resp); + extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); -extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); -extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); #else #include -static inline -int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) -{ - return -ENODEV; -} -static inline -int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) -{ - return -ENODEV; -} static inline bool qcom_scm_is_available(void) { return false; } -static inline bool qcom_scm_hdcp_available(void) { return false; } -static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, - u32 *resp) { return -ENODEV; } -static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; } + +static inline int qcom_scm_set_cold_boot_addr(void *entry, + const cpumask_t *cpus) { return -ENODEV; } +static inline int qcom_scm_set_warm_boot_addr(void *entry, + const cpumask_t *cpus) { return -ENODEV; } +static inline void qcom_scm_cpu_power_down(u32 flags) {} +static inline u32 qcom_scm_set_remote_state(u32 state,u32 id) + { return -ENODEV; } + static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, - size_t size) { return -ENODEV; } + size_t size) { return -ENODEV; } static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, - phys_addr_t size) { return -ENODEV; } -static inline int -qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; } + phys_addr_t size) { return -ENODEV; } +static inline int qcom_scm_pas_auth_and_reset(u32 peripheral) + { return -ENODEV; } static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; } +static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; } + +static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) + { return -ENODEV; } +static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) + { return -ENODEV; } + +static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) + { return -ENODEV; } +static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) + { return -ENODEV; } +static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) + { return -ENODEV; } static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - unsigned int *src, - const struct qcom_scm_vmperm *newvm, - unsigned int dest_cnt) { return -ENODEV; } -static inline void qcom_scm_cpu_power_down(u32 flags) {} -static inline u32 -qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; } -static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; } -static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; } -static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; } -static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; } -static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; } -static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; } + unsigned int *src, const struct qcom_scm_vmperm *newvm, + unsigned int dest_cnt) { return -ENODEV; } + +static inline bool qcom_scm_hdcp_available(void) { return false; } +static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, + u32 *resp) { return -ENODEV; } + +static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) + { return -ENODEV; } #endif #endif