From patchwork Tue Sep 18 13:47:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10604389 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59FB615A6 for ; Tue, 18 Sep 2018 13:48:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49A3F2A139 for ; Tue, 18 Sep 2018 13:48:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B9FD2A132; Tue, 18 Sep 2018 13:48:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D14702A132 for ; Tue, 18 Sep 2018 13:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729701AbeIRTVG (ORCPT ); Tue, 18 Sep 2018 15:21:06 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:10213 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729197AbeIRTVG (ORCPT ); Tue, 18 Sep 2018 15:21:06 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:24 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 43BB279573; Tue, 18 Sep 2018 22:48:24 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.53,389,1531753200"; d="scan'208";a="291253448" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.250]) by relmlii1.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:21 +0900 From: Fabrizio Castro To: Laurent Pinchart , Geert Uytterhoeven , Linus Walleij Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Simon Horman , Chris Paterson , Biju Das Subject: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups Date: Tue, 18 Sep 2018 14:47:54 +0100 Message-Id: <1537278478-1744-2-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add I2C4 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 995c959..d4de404 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1197,6 +1197,42 @@ static const unsigned int avb_avtp_capture_b_pins[] = { static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), +}; +static const unsigned int i2c4_a_mux[] = { + SCL4_A_MARK, SDA4_A_MARK, +}; +static const unsigned int i2c4_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31), +}; +static const unsigned int i2c4_b_mux[] = { + SCL4_B_MARK, SDA4_B_MARK, +}; +static const unsigned int i2c4_c_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), +}; +static const unsigned int i2c4_c_mux[] = { + SCL4_C_MARK, SDA4_C_MARK, +}; +static const unsigned int i2c4_d_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), +}; +static const unsigned int i2c4_d_mux[] = { + SCL4_D_MARK, SDA4_D_MARK, +}; +static const unsigned int i2c4_e_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6), +}; +static const unsigned int i2c4_e_mux[] = { + SCL4_E_MARK, SDA4_E_MARK, +}; /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data1_pins[] = { /* D0 */ @@ -1487,6 +1523,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(i2c4_a), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c4_d), + SH_PFC_PIN_GROUP(i2c4_e), SH_PFC_PIN_GROUP(mmc_data1), SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), @@ -1541,6 +1582,15 @@ static const char * const avb_groups[] = { "avb_avtp_match_b", "avb_avtp_capture_b", }; + +static const char * const i2c4_groups[] = { + "i2c4_a", + "i2c4_b", + "i2c4_c", + "i2c4_d", + "i2c4_e", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -1604,6 +1654,7 @@ static const char * const scif_clk_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), From patchwork Tue Sep 18 13:47:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10604391 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E5E413AD for ; Tue, 18 Sep 2018 13:48:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D05B2ABE9 for ; Tue, 18 Sep 2018 13:48:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6130E2ABF4; Tue, 18 Sep 2018 13:48:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD3522A74F for ; Tue, 18 Sep 2018 13:48:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729739AbeIRTVJ (ORCPT ); Tue, 18 Sep 2018 15:21:09 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:10213 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729197AbeIRTVJ (ORCPT ); Tue, 18 Sep 2018 15:21:09 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:26 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id CF5FC7957C; Tue, 18 Sep 2018 22:48:26 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.53,389,1531753200"; d="scan'208";a="291253450" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.250]) by relmlii1.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:24 +0900 From: Fabrizio Castro To: Laurent Pinchart , Geert Uytterhoeven , Linus Walleij Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Simon Horman , Chris Paterson , Biju Das Subject: [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups Date: Tue, 18 Sep 2018 14:47:55 +0100 Message-Id: <1537278478-1744-3-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DU0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 109 ++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index d4de404..a16a010 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1197,6 +1197,93 @@ static const unsigned int avb_avtp_capture_b_pins[] = { static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du0_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), +}; +static const unsigned int du0_rgb666_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, +}; +static const unsigned int du0_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16), +}; +static const unsigned int du0_rgb888_mux[] = { + DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK, + DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK, + DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK, + DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK, + DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, + DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, +}; +static const unsigned int du0_clk0_out_pins[] = { + /* DOTCLKOUT0 */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int du0_clk0_out_mux[] = { + DU0_DOTCLKOUT0_MARK +}; +static const unsigned int du0_clk1_out_pins[] = { + /* DOTCLKOUT1 */ + RCAR_GP_PIN(2, 26), +}; +static const unsigned int du0_clk1_out_mux[] = { + DU0_DOTCLKOUT1_MARK +}; +static const unsigned int du0_clk_in_pins[] = { + /* CLKIN */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int du0_clk_in_mux[] = { + DU0_DOTCLKIN_MARK +}; +static const unsigned int du0_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27), +}; +static const unsigned int du0_sync_mux[] = { + DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK +}; +static const unsigned int du0_oddf_pins[] = { + /* EXODDF/ODDF/DISP/CDE */ + RCAR_GP_PIN(2, 29), +}; +static const unsigned int du0_oddf_mux[] = { + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du0_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(2, 31), +}; +static const unsigned int du0_cde_mux[] = { + DU0_CDE_MARK, +}; +static const unsigned int du0_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int du0_disp_mux[] = { + DU0_DISP_MARK +}; /* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_a_pins[] = { /* SCL, SDA */ @@ -1523,6 +1610,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(du0_rgb666), + SH_PFC_PIN_GROUP(du0_rgb888), + SH_PFC_PIN_GROUP(du0_clk0_out), + SH_PFC_PIN_GROUP(du0_clk1_out), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du0_sync), + SH_PFC_PIN_GROUP(du0_oddf), + SH_PFC_PIN_GROUP(du0_cde), + SH_PFC_PIN_GROUP(du0_disp), SH_PFC_PIN_GROUP(i2c4_a), SH_PFC_PIN_GROUP(i2c4_b), SH_PFC_PIN_GROUP(i2c4_c), @@ -1583,6 +1679,18 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const du0_groups[] = { + "du0_rgb666", + "du0_rgb888", + "du0_clk0_out", + "du0_clk1_out", + "du0_clk_in", + "du0_sync", + "du0_oddf", + "du0_cde", + "du0_disp", +}; + static const char * const i2c4_groups[] = { "i2c4_a", "i2c4_b", @@ -1654,6 +1762,7 @@ static const char * const scif_clk_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(scif0), From patchwork Tue Sep 18 13:47:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10604393 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05F3313AD for ; Tue, 18 Sep 2018 13:48:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA6982ABE9 for ; Tue, 18 Sep 2018 13:48:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DEEA92ABF3; Tue, 18 Sep 2018 13:48:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88BC02ABE9 for ; Tue, 18 Sep 2018 13:48:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729893AbeIRTVN (ORCPT ); Tue, 18 Sep 2018 15:21:13 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:32303 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729877AbeIRTVM (ORCPT ); Tue, 18 Sep 2018 15:21:12 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie3.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:29 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 69EA379584; Tue, 18 Sep 2018 22:48:29 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.53,389,1531753200"; d="scan'208";a="291253453" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.250]) by relmlii1.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:27 +0900 From: Fabrizio Castro To: Laurent Pinchart , Geert Uytterhoeven , Linus Walleij Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Simon Horman , Chris Paterson , Biju Das Subject: [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups Date: Tue, 18 Sep 2018 14:47:56 +0100 Message-Id: <1537278478-1744-4-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add QSPI0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index a16a010..33661f8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1357,6 +1357,30 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), + RCAR_GP_PIN(1, 20), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -1628,6 +1652,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -1706,6 +1733,12 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_data_b", @@ -1765,6 +1798,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), From patchwork Tue Sep 18 13:47:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10604395 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F00915A6 for ; Tue, 18 Sep 2018 13:48:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F06E2ABE9 for ; Tue, 18 Sep 2018 13:48:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 632552ABF3; Tue, 18 Sep 2018 13:48:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B5862ABE9 for ; Tue, 18 Sep 2018 13:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729877AbeIRTVP (ORCPT ); Tue, 18 Sep 2018 15:21:15 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:32303 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729879AbeIRTVO (ORCPT ); Tue, 18 Sep 2018 15:21:14 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie3.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:31 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id F3E9C79586; Tue, 18 Sep 2018 22:48:31 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.53,389,1531753200"; d="scan'208";a="291253454" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.250]) by relmlii1.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:29 +0900 From: Fabrizio Castro To: Laurent Pinchart , Geert Uytterhoeven , Linus Walleij Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Simon Horman , Chris Paterson , Biju Das Subject: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups Date: Tue, 18 Sep 2018 14:47:57 +0100 Message-Id: <1537278478-1744-5-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add SDHI2 pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 33661f8..43ad702 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1619,6 +1619,43 @@ static const unsigned int scif_clk_b_pins[] = { static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), + RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 20), +}; +static const unsigned int sdhi2_cd_mux[] = { + SD2_CD_MARK, +}; +static const unsigned int sdhi2_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 21), +}; +static const unsigned int sdhi2_wp_mux[] = { + SD2_WP_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_col), @@ -1688,6 +1725,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_f), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), }; static const char * const avb_groups[] = { @@ -1793,6 +1835,14 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_ctrl", + "sdhi2_cd", + "sdhi2_wp", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), @@ -1806,6 +1856,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi2), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { From patchwork Tue Sep 18 13:47:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10604397 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C559A15A6 for ; Tue, 18 Sep 2018 13:48:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B42D12ABE9 for ; Tue, 18 Sep 2018 13:48:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A828D2ABF5; Tue, 18 Sep 2018 13:48:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5314D2ABE9 for ; Tue, 18 Sep 2018 13:48:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729903AbeIRTVQ (ORCPT ); Tue, 18 Sep 2018 15:21:16 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:32303 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729879AbeIRTVP (ORCPT ); Tue, 18 Sep 2018 15:21:15 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie3.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:34 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 87D3D7959E; Tue, 18 Sep 2018 22:48:34 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.53,389,1531753200"; d="scan'208";a="291253456" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.250]) by relmlii1.idc.renesas.com with ESMTP; 18 Sep 2018 22:48:32 +0900 From: Fabrizio Castro To: Laurent Pinchart , Geert Uytterhoeven , Linus Walleij Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Simon Horman , Chris Paterson , Biju Das Subject: [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB pin groups Date: Tue, 18 Sep 2018 14:47:58 +0100 Message-Id: <1537278478-1744-6-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1537278478-1744-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add USB[01] pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 43ad702..3d36e5f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -1656,6 +1656,24 @@ static const unsigned int sdhi2_wp_pins[] = { static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + RCAR_GP_PIN(0, 0), /* PWEN */ + RCAR_GP_PIN(0, 1), /* OVC */ +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, + USB0_OVC_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + RCAR_GP_PIN(0, 2), /* PWEN */ + RCAR_GP_PIN(0, 3), /* OVC */ +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, + USB1_OVC_MARK, +}; static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_col), @@ -1730,6 +1748,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), }; static const char * const avb_groups[] = { @@ -1843,6 +1863,14 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp", }; +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du0), @@ -1857,6 +1885,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = {