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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id a12sm9419246pfk.188.2019.11.14.20.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 20:41:26 -0800 (PST) Subject: [PULL 1/4] remove unnecessary ifdef TARGET_RISCV64 Date: Thu, 14 Nov 2019 20:41:01 -0800 Message-Id: <20191115044104.4197-2-palmer@dabbelt.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com> References: <20191115044104.4197-1-palmer@dabbelt.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, "hiroyuki.obinata" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: "hiroyuki.obinata" Signed-off-by: Hiroyuki Obinata Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b26533d4fd78..ab6a891dc381 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,12 +64,10 @@ static const int tcg_memop_lookup[8] = { [0] = MO_SB, [1] = MO_TESW, [2] = MO_TESL, + [3] = MO_TEQ, [4] = MO_UB, [5] = MO_TEUW, -#ifdef TARGET_RISCV64 - [3] = MO_TEQ, [6] = MO_TEUL, -#endif }; #endif From patchwork Fri Nov 15 04:41:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11244787 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4D54E930 for ; Fri, 15 Nov 2019 04:44:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23245206E6 for ; Fri, 15 Nov 2019 04:44:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=dabbelt-com.20150623.gappssmtp.com header.i=@dabbelt-com.20150623.gappssmtp.com header.b="XDFFDNZ2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23245206E6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=dabbelt.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iVTT3-0001Dx-16 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 14 Nov 2019 23:44:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49662) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iVTQJ-00060I-J7 for qemu-devel@nongnu.org; Thu, 14 Nov 2019 23:41:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iVTQI-00085S-5j for qemu-devel@nongnu.org; Thu, 14 Nov 2019 23:41:31 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:45205) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iVTQH-000859-Vv for qemu-devel@nongnu.org; Thu, 14 Nov 2019 23:41:30 -0500 Received: by mail-pg1-x541.google.com with SMTP id k1so3882661pgg.12 for ; Thu, 14 Nov 2019 20:41:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dabbelt-com.20150623.gappssmtp.com; s=20150623; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=BDRz7F8WZuWovA+zwb21EWtUEg2HMx8lqlNygTR580E=; b=XDFFDNZ20uGcvoeCSAFqRCYg+iMD7suGQ9t4gEXwrQdJ8RxgoTlDz/0mJJ8Z3/QjX9 xNpfZ0P+SOsd0fEOdcLJAZ5jGysTD970lW2beMHtvTBQcJbWRn225YsEvHL/zzfWqeKo 6iULEEDUBqEgAT/qhEEA/XdvUnynNZxyAazGlBflkZSA/VMF8dv6SQievEFelCCGwkAq o8nBSB0NLpCGjvvbHlJpfS87bzloypBgxmRItNFZG+FQk7Mo71EaiosmtyJhzU5XuzSe TJvkKrUXwafhTS9hHfYTne52QKkuPZ+VqzlNUDzjoYSIOh0LHwgU3K2ri9gUjM3chHr0 RfHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=BDRz7F8WZuWovA+zwb21EWtUEg2HMx8lqlNygTR580E=; b=raxZhOOOKw6+lxfqN0YKi0Nfdruxhg4gseCC/je8feqR8Lt9b/p10fqsrCQOmnzkMh AbRkt+4pAQ7uI9eYAUXVjgLNfYv3Tv6hpCKDH/Kcvu3xhUFGYD/BeIZqm5Tgyc3jKAsw Z8/vSwDAGJHDvdy1XOBxYwyynASiwWc6asCHdeXbvYEcksxXI/0fzFIhmg8xS0oDe2+B R/LSmNZsCNBPLN11LXVoT1ZGx5l7IipeVPsVZPKVWBDvaXiYlKO/lmNDnAqgWVu3jyZ0 n9EfayL/8kST7vr+rozKiBIWbvN37TfDkar0MbWIH10ccedE24YM0plHm0Dsbw7k2n2k N/8w== X-Gm-Message-State: APjAAAXYIBk84SlfeYdIDFq/ODzGXdpG86AX+6ZYq+IVRPbOPyDHE52w J2DPmee+GkcTFJxK6AzT9cyv+Q== X-Google-Smtp-Source: APXvYqwS6BlPymmpZsOvMaGNc5Nh6d6tU1tqyb9rIdi4gqOgLrr0sZEK36fxzsQm3X6s/H1i5VVy2w== X-Received: by 2002:a63:ec4b:: with SMTP id r11mr13922642pgj.147.1573792888617; Thu, 14 Nov 2019 20:41:28 -0800 (PST) Received: from localhost (c-67-161-15-180.hsd1.ca.comcast.net. [67.161.15.180]) by smtp.gmail.com with ESMTPSA id a145sm9138943pfa.7.2019.11.14.20.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 20:41:28 -0800 (PST) Subject: [PULL 2/4] target/riscv: Remove atomic accesses to MIP CSR Date: Thu, 14 Nov 2019 20:41:02 -0800 Message-Id: <20191115044104.4197-3-palmer@dabbelt.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com> References: <20191115044104.4197-1-palmer@dabbelt.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Instead of relying on atomics to access the MIP register let's update our helper function to instead just lock the IO mutex thread before writing. This follows the same concept as used in PPC for handling interrupts Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 5 ++-- target/riscv/cpu.h | 9 -------- target/riscv/cpu_helper.c | 48 +++++++++++++++------------------------ target/riscv/csr.c | 2 +- 4 files changed, 21 insertions(+), 43 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3939963b71ab..d37861a4305b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -224,8 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", - (target_ulong)atomic_read(&env->mip)); + qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); @@ -275,7 +274,7 @@ static bool riscv_cpu_has_work(CPUState *cs) * Definition of the WFI instruction requires it to ignore the privilege * mode and delegation registers, but respect individual enables */ - return (atomic_read(&env->mip) & env->mie) != 0; + return (env->mip & env->mie) != 0; #else return true; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c64c68538d8..e59343e13c02 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,15 +121,6 @@ struct CPURISCVState { target_ulong mhartid; target_ulong mstatus; - /* - * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously - * by I/O threads. It should be read with atomic_read. It should be updated - * using riscv_cpu_update_mip with the iothread mutex held. The iothread - * mutex must be held because mip must be consistent with the CPU inturrept - * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt - * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. - * mip is 32-bits to allow atomic_read on 32-bit hosts. - */ uint32_t mip; uint32_t miclaim; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f13131a51bde..767c8762ac42 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" @@ -38,7 +39,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) { target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); - target_ulong pending = atomic_read(&env->mip) & env->mie; + target_ulong pending = env->mip & env->mie; target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); target_ulong irqs = (pending & ~env->mideleg & -mie) | @@ -92,42 +93,29 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) } } -struct CpuAsyncInfo { - uint32_t new_mip; -}; - -static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, - run_on_cpu_data data) -{ - struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr; - - if (info->new_mip) { - cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); - } - - g_free(info); -} - uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) { CPURISCVState *env = &cpu->env; CPUState *cs = CPU(cpu); - struct CpuAsyncInfo *info; - uint32_t old, new, cmp = atomic_read(&env->mip); + uint32_t old = env->mip; + bool locked = false; + + if (!qemu_mutex_iothread_locked()) { + locked = true; + qemu_mutex_lock_iothread(); + } - do { - old = cmp; - new = (old & ~mask) | (value & mask); - cmp = atomic_cmpxchg(&env->mip, old, new); - } while (old != cmp); + env->mip = (env->mip & ~mask) | (value & mask); - info = g_new(struct CpuAsyncInfo, 1); - info->new_mip = new; + if (env->mip) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } - async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async, - RUN_ON_CPU_HOST_PTR(info)); + if (locked) { + qemu_mutex_unlock_iothread(); + } return old; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 974c9c20b5f4..da02f9f0b177 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -579,7 +579,7 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, if (mask) { old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); } else { - old_mip = atomic_read(&env->mip); + old_mip = env->mip; } if (ret_value) { From patchwork Fri Nov 15 04:41:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11244783 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43E721393 for ; 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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id r16sm6287784pgl.77.2019.11.14.20.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 20:41:29 -0800 (PST) Subject: [PULL 3/4] opensbi: Upgrade from v0.4 to v0.5 Date: Thu, 14 Nov 2019 20:41:03 -0800 Message-Id: <20191115044104.4197-4-palmer@dabbelt.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com> References: <20191115044104.4197-1-palmer@dabbelt.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis This release has: Lot of critical fixes Hypervisor extension support SBI v0.2 base extension support Debug prints support Handle traps when doing unpriv load/store Allow compiling without FP support Use git describe to generate boot-time banner Andes AE350 platform support ShortLog: Anup Patel (14): platform: sifive/fu540: Move FDT further up lib: Allow compiling without FP support lib: Introduce sbi_dprintf() API lib: Use sbi_dprintf() for invalid CSRs lib: Handle traps when doing unpriv load/store in get_insn() lib: Delegate supervisor ecall to HS-mode when H extension available lib: Extend sbi_hart_switch_mode() to support hypervisor extension lib: Extend sbi_trap_redirect() for hypervisor extension lib: Redirect WFI trapped from VS/VU mode to HS-mode include: Extend get_insn() to read instruction from VS/VU mode lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSR Makefile: Minor fix in OPENSBI_VERSION_GIT lib: Fix coldboot race condition observed on emulators/simulators include: Bump-up version to 0.5 Atish Patra (16): lib: Provide an atomic exchange function unsigned long lib: Fix race conditions in tlb fifo access. platform: Remove the ipi_sync method from all platforms. lib: Fix timer for 32 bit lib: Support atomic swap instructions lib: Upgrade to full flush if size is at least threshold docs: Update the fu540 platform guide as per U-Boot documents. lib: Change tlb range flush threshold to 4k page instead of 1G lib: provide a platform specific tlb range flush threshold lib: Fix tlb flush range limit value Test: Move test payload related code out of interface header lib: Align error codes as per SBI specification. lib: Rename existing SBI implementation as 0.1. lib: Remove redundant variable assignment lib: Implement SBI v0.2 lib: Provide a platform hook to implement vendor specific SBI extensions. Bin Meng (6): platform: sifive: fu540: Use standard value string for cpu node status README: Document 32-bit / 64-bit images build treewide: Use conventional names for 32-bit and 64-bit platform: sifive: fu540: Expand FDT size before any patching firmware: Use macro instead of magic number for boot status docs: platform: Update descriptions for qemu/sifive_u support Damien Le Moal (4): kendryte/k210: Use sifive UART driver kendryte/k210: remove sysctl code README: Update license information kendryte/k210: remove unused file Georg Kotheimer (1): utils: Use cpu_to_fdt32() when writing to fdt Jacob Garber (4): lib: Use bitwise & instead of boolean && lib: Use correct type for return value lib: Prevent unintended sign extensions lib: Correct null pointer check Lukas Auer (1): firmware: do not use relocated _boot_status before it is valid Nylon Chen (3): firmware: Fix the loop condition of _wait_relocate_copy_done section platform: Add Andes AE350 initial support scripts: Add AE350 to platform list in the binary archive script Palmer Dabbelt (1): Include `git describe` in OpenSBI Zong Li (1): Write MSIP by using memory-mapped control register Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin 36888 -> 40984 bytes pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 45064 -> 49160 bytes pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin 40968 -> 45064 bytes roms/opensbi | 2 +- 4 files changed, 1 insertion(+), 1 deletion(-) diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin index f5bcaa56954c860d09acc0cb337c1666d88b6efb..6c5b7b89f676392b687d9835ac9fbdc34f3052cd 100644 GIT binary patch delta 14873 zcmcJ030M@@w(hQ~uBvWCX>DY1N=ri{#9%89(L`lxTF~GS(O?`Y5k1LOBQc35Cuy*# zZW{;GEjA=3;snY$F~p7%eaC=EgP25#5z*YJL_{<>2~LP8$X&auQDe@1-@EU755M*8 zu08zw-)j%G*4kxmKAl@eo6`nG+!CTtPdkkeUR@sH%OIp-m`+`OGIHmQ7kAP~&W|3? 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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id 67sm9182645pjz.27.2019.11.14.20.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 20:41:32 -0800 (PST) Subject: [PULL 4/4] riscv/virt: Increase flash size Date: Thu, 14 Nov 2019 20:41:04 -0800 Message-Id: <20191115044104.4197-5-palmer@dabbelt.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com> References: <20191115044104.4197-1-palmer@dabbelt.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Coreboot developers have requested that they have at least 32MB of flash to load binaries. We currently have 32MB of flash, but it is split in two to allow loading two flash binaries. Let's increase the flash size from 32MB to 64MB to ensure we have a single region that is 32MB. No QEMU release has include flash in the RISC-V virt machine, so this isn't a breaking change. Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cc8f311e6bbb..23f340df193e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -62,7 +62,7 @@ static const struct MemmapEntry { [VIRT_PLIC] = { 0xc000000, 0x4000000 }, [VIRT_UART0] = { 0x10000000, 0x100 }, [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, - [VIRT_FLASH] = { 0x20000000, 0x2000000 }, + [VIRT_FLASH] = { 0x20000000, 0x4000000 }, [VIRT_DRAM] = { 0x80000000, 0x0 }, [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },