From patchwork Fri Nov 15 08:58:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 11245881 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BEB8B138C for ; Fri, 15 Nov 2019 10:04:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A92122073B for ; Fri, 15 Nov 2019 10:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727241AbfKOKEG (ORCPT ); Fri, 15 Nov 2019 05:04:06 -0500 Received: from twhmllg3.macronix.com ([122.147.135.201]:20688 "EHLO TWHMLLG3.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbfKOKEG (ORCPT ); Fri, 15 Nov 2019 05:04:06 -0500 Received: from TWHMLLG3.macronix.com (localhost [127.0.0.2] (may be forged)) by TWHMLLG3.macronix.com with ESMTP id xAF9005D047026 for ; Fri, 15 Nov 2019 17:00:00 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG3.macronix.com with ESMTP id xAF8wWGu046218; Fri, 15 Nov 2019 16:58:33 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, marek.vasut@gmail.com, dwmw2@infradead.org, computersforpeace@gmail.com, vigneshr@ti.com, bbrezillon@kernel.org, tudor.ambarus@microchip.com Cc: juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang , Boris Brezillon Subject: [PATCH 1/4] spi: spi-mem: Add support for Octal 8D-8D-8D mode Date: Fri, 15 Nov 2019 16:58:05 +0800 Message-Id: <1573808288-19365-2-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> References: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG3.macronix.com xAF8wWGu046218 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org According to JESD216C SPI NORs are using 2 bytes opcodes when operated in OPI (Octal Peripheral Interface). To add extension command, command bytes number and Double Transfer Rate(DTR) fields to the spi_mem_op struct. Signed-off-by: Boris Brezillon Signed-off-by: Mason Yang --- drivers/spi/spi-mem.c | 8 +++++++- include/linux/spi/spi-mem.h | 13 +++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 9f0fa9f..eb33dd85 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -154,6 +154,12 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, op->data.dir == SPI_MEM_DATA_OUT)) return false; + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) + return false; + + if (op->cmd.nbytes != 1) + return false; + return true; } EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); @@ -168,7 +174,7 @@ static bool spi_mem_buswidth_is_valid(u8 buswidth) static int spi_mem_check_op(const struct spi_mem_op *op) { - if (!op->cmd.buswidth) + if (!op->cmd.buswidth || op->cmd.nbytes < 1 || op->cmd.nbytes > 2) return -EINVAL; if ((op->addr.nbytes && !op->addr.buswidth) || diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index af9ff2f..bf54079 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -17,6 +17,7 @@ { \ .buswidth = __buswidth, \ .opcode = __opcode, \ + .nbytes = 1, \ } #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ @@ -69,11 +70,15 @@ enum spi_mem_data_dir { /** * struct spi_mem_op - describes a SPI memory operation + * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid) * @cmd.buswidth: number of IO lines used to transmit the command + * @cmd.dtr: set true to transfer opcode in double transfer rate mode * @cmd.opcode: operation opcode + * @cmd.ext_opcode: extension operation opcode * @addr.nbytes: number of address bytes to send. Can be zero if the operation * does not need to send an address * @addr.buswidth: number of IO lines used to transmit the address cycles + * @addr.dtr: set true to transfer address bytes in double transfer rate mode * @addr.val: address value. This value is always sent MSB first on the bus. * Note that only @addr.nbytes are taken into account in this * address value, so users should make sure the value fits in the @@ -81,34 +86,42 @@ enum spi_mem_data_dir { * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can * be zero if the operation does not require dummy bytes * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes + * @dummy.dtr: set true to transfer dummy bytes in double transfer rate mode * @data.buswidth: number of IO lanes used to send/receive the data * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data + * @data.dtr: set true to transfer data bytes in double transfer rate mode * @data.buf.in: input buffer (must be DMA-able) * @data.buf.out: output buffer (must be DMA-able) */ struct spi_mem_op { struct { + u8 nbytes; u8 buswidth; + bool dtr; u8 opcode; + u8 ext_opcode; } cmd; struct { u8 nbytes; u8 buswidth; + bool dtr; u64 val; } addr; struct { u8 nbytes; u8 buswidth; + bool dtr; } dummy; struct { u8 buswidth; enum spi_mem_data_dir dir; unsigned int nbytes; + bool dtr; union { void *in; const void *out; From patchwork Fri Nov 15 08:58:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 11245877 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2179C138C for ; Fri, 15 Nov 2019 10:04:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EE1912073B for ; Fri, 15 Nov 2019 10:04:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727202AbfKOKEC (ORCPT ); Fri, 15 Nov 2019 05:04:02 -0500 Received: from twhmllg3.macronix.com ([122.147.135.201]:20683 "EHLO TWHMLLG3.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbfKOKEC (ORCPT ); Fri, 15 Nov 2019 05:04:02 -0500 Received: from TWHMLLG3.macronix.com (localhost [127.0.0.2] (may be forged)) by TWHMLLG3.macronix.com with ESMTP id xAF8xw8U046952 for ; Fri, 15 Nov 2019 16:59:58 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG3.macronix.com with ESMTP id xAF8wWGv046218; Fri, 15 Nov 2019 16:58:34 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, marek.vasut@gmail.com, dwmw2@infradead.org, computersforpeace@gmail.com, vigneshr@ti.com, bbrezillon@kernel.org, tudor.ambarus@microchip.com Cc: juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang , Boris Brezillon Subject: [PATCH 2/4] mtd: spi-nor: Add support for Octal 8D-8D-8D mode Date: Fri, 15 Nov 2019 16:58:06 +0800 Message-Id: <1573808288-19365-3-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> References: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG3.macronix.com xAF8wWGv046218 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org According to JESD216C (JEDEC Basic Flash Parameter Table 18th DWORD) Octal DTR(8D-8D-8D) command and command extension (00b: same, 01b: inverse) to add extension command mode in spi_nor struct and to add write_cr2 (Write CFG Reg 2) for 8-8-8/8D-8D-8D mode sequences enable. Define the relevant macrons and enum to add such modes and make sure op->xxx.dtr fields, command nbytes and extension command are properly filled and unmask DTR and X-X-X modes in spi_nor_spimem_adjust_hwcaps() so that DTR and X-X-X support detection is done through spi_mem_supports_op(). Signed-off-by: Boris Brezillon Signed-off-by: Mason Yang --- drivers/mtd/spi-nor/spi-nor.c | 159 ++++++++++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 58 +++++++++++++-- 2 files changed, 206 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 7acf4a9..4cdf52d 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -320,6 +320,23 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + if (spi_nor_protocol_is_8_8_8(nor->read_proto)) { + op.cmd.nbytes = 2; + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~nor->read_opcode; + else + op.cmd.ext_opcode = nor->read_opcode; + + if (spi_nor_protocol_is_8D_8D_8D(nor->read_proto)) { + op.dummy.nbytes *= 2; + op.cmd.dtr = true; + op.addr.dtr = true; + op.dummy.dtr = true; + op.data.dtr = true; + } + } + return spi_nor_spimem_xfer_data(nor, &op); } @@ -367,6 +384,21 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) op.addr.nbytes = 0; + if (spi_nor_protocol_is_8_8_8(nor->write_proto)) { + op.cmd.nbytes = 2; + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~nor->program_opcode; + else + op.cmd.ext_opcode = nor->program_opcode; + + if (spi_nor_protocol_is_8D_8D_8D(nor->write_proto)) { + op.cmd.dtr = true; + op.addr.dtr = true; + op.data.dtr = true; + } + } + return spi_nor_spimem_xfer_data(nor, &op); } @@ -404,6 +436,30 @@ static int read_sr(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + if (spi_nor_protocol_is_8_8_8(nor->read_proto)) { + op.cmd.buswidth = 8; + op.addr.buswidth = 8; + op.dummy.buswidth = 8; + op.data.buswidth = 8; + op.cmd.nbytes = 2; + op.addr.nbytes = 4; + op.dummy.nbytes = 4; + op.addr.val = 0; + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~SPINOR_OP_RDSR; + else + op.cmd.ext_opcode = SPINOR_OP_RDSR; + + if (spi_nor_protocol_is_8D_8D_8D(nor->read_proto)) { + op.dummy.nbytes *= 2; + op.cmd.dtr = true; + op.addr.dtr = true; + op.dummy.dtr = true; + op.data.dtr = true; + } + } + ret = spi_mem_exec_op(nor->spimem, &op); } else { ret = nor->read_reg(nor, SPINOR_OP_RDSR, nor->bouncebuf, 1); @@ -508,6 +564,19 @@ static int write_enable(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + if (spi_nor_protocol_is_8_8_8(nor->write_proto)) { + op.cmd.buswidth = 8; + op.cmd.nbytes = 2; + + if (spi_nor_protocol_is_8D_8D_8D(nor->write_proto)) + op.cmd.dtr = true; + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~SPINOR_OP_WREN; + else + op.cmd.ext_opcode = SPINOR_OP_WREN; + } + return spi_mem_exec_op(nor->spimem, &op); } @@ -526,12 +595,65 @@ static int write_disable(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + if (spi_nor_protocol_is_8_8_8(nor->write_proto)) { + op.cmd.buswidth = 8; + op.cmd.nbytes = 2; + + if (spi_nor_protocol_is_8D_8D_8D(nor->write_proto)) + op.cmd.dtr = true; + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~SPINOR_OP_WRDI; + else + op.cmd.ext_opcode = SPINOR_OP_WRDI; + } + return spi_mem_exec_op(nor->spimem, &op); } return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); } +/* + * Write configuration register 2 one byte + * Returns negative if error occurred. + */ +static int write_cr2(struct spi_nor *nor, u32 addr, u8 val) +{ + write_enable(nor); + + nor->bouncebuf[0] = val; + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRCR2, 1), + SPI_MEM_OP_ADDR(4, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); + + if (spi_nor_protocol_is_8_8_8(nor->write_proto)) { + op.cmd.buswidth = 8; + op.addr.buswidth = 8; + op.data.buswidth = 8; + op.cmd.nbytes = 2; + + if (spi_nor_protocol_is_8D_8D_8D(nor->write_proto)) { + op.cmd.dtr = true; + op.addr.dtr = true; + op.data.dtr = true; + } + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~SPINOR_OP_WRCR2; + else + op.cmd.ext_opcode = SPINOR_OP_WRCR2; + } + + return spi_mem_exec_op(nor->spimem, &op); + } + + return -ENOTSUPP; +} + static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -868,6 +990,19 @@ static int erase_chip(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + if (spi_nor_protocol_is_8_8_8(nor->write_proto)) { + op.cmd.buswidth = 8; + op.cmd.nbytes = 2; + + if (spi_nor_protocol_is_8D_8D_8D(nor->write_proto)) + op.cmd.dtr = true; + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~SPINOR_OP_CHIP_ERASE; + else + op.cmd.ext_opcode = SPINOR_OP_CHIP_ERASE; + } + return spi_mem_exec_op(nor->spimem, &op); } @@ -945,6 +1080,22 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_DATA); + if (spi_nor_protocol_is_8_8_8(nor->write_proto)) { + op.cmd.buswidth = 8; + op.addr.buswidth = 8; + op.cmd.nbytes = 2; + + if (spi_nor_protocol_is_8D_8D_8D(nor->write_proto)) { + op.cmd.dtr = true; + op.addr.dtr = true; + } + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~nor->erase_opcode; + else + op.cmd.ext_opcode = nor->erase_opcode; + } + return spi_mem_exec_op(nor->spimem, &op); } @@ -2825,6 +2976,7 @@ static int spi_nor_hwcaps_read2cmd(u32 hwcaps) { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, + { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8D_8D_8D }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, @@ -2841,6 +2993,7 @@ static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, + { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8D_8D_8D }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, @@ -3010,12 +3163,6 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor, struct spi_nor_flash_parameter *params = &nor->params; unsigned int cap; - /* DTR modes are not supported yet, mask them all. */ - *hwcaps &= ~SNOR_HWCAPS_DTR; - - /* X-X-X modes are not supported yet, mask them all. */ - *hwcaps &= ~SNOR_HWCAPS_X_X_X; - for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { int rdidx, ppidx; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index fc0b4b1..2e720ca 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -84,6 +84,9 @@ #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_READ_8_8_8 SPINOR_OP_READ_1_4_4_4B +#define SPINOR_OP_PP_8_8_8 SPINOR_OP_PP_4B +#define SPINOR_OP_PP_8D_8D_8D SPINOR_OP_PP_4B /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ #define SPINOR_OP_READ_1_1_1_DTR 0x0d @@ -93,6 +96,7 @@ #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee +#define SPINOR_OP_READ_8D_8D_8D SPINOR_OP_READ_1_4_4_DTR_4B /* Used for SST flashes only. */ #define SPINOR_OP_BP 0x02 /* Byte program */ @@ -107,6 +111,8 @@ #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ #define XSR_RDY BIT(7) /* Ready */ +/* Write CFG Reg 2 - defined in JEDEC JESD216C. */ +#define SPINOR_OP_WRCR2 0x72 /* Write configuration register 2 */ /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ @@ -150,6 +156,13 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* Configuration register 2, offset 0 */ +#define CR2_REG0 0x0 +#define CR2_REG0_MODE_MASK GENMASK(1, 0) +#define CR2_REG0_MODE_SPI 0 +#define CR2_REG0_MODE_OPI_STR 1 +#define CR2_REG0_MODE_OPI_DTR 2 + /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK GENMASK(23, 16) #define SNOR_PROTO_INST_SHIFT 16 @@ -170,6 +183,7 @@ SNOR_PROTO_DATA_MASK) #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ +#define SNOR_PROTO_IS_8D_8D_8D BIT(25) /* Full Octal DTR */ #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ (SNOR_PROTO_INST(_inst_nbits) | \ @@ -179,6 +193,10 @@ (SNOR_PROTO_IS_DTR | \ SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) +#define SNOR_PROTO_8D_8D_8D(_nbits) \ + (SNOR_PROTO_IS_8D_8D_8D | \ + SNOR_PROTO_STR(_nbits, _nbits, _nbits)) + enum spi_nor_protocol { SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), @@ -195,6 +213,7 @@ enum spi_nor_protocol { SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), + SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_8D_8D_8D(8), }; static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) @@ -202,6 +221,16 @@ static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) return !!(proto & SNOR_PROTO_IS_DTR); } +static inline bool spi_nor_protocol_is_8_8_8(enum spi_nor_protocol proto) +{ + return !!(proto & SNOR_PROTO_8_8_8); +} + +static inline bool spi_nor_protocol_is_8D_8D_8D(enum spi_nor_protocol proto) +{ + return !!(proto & SNOR_PROTO_IS_8D_8D_8D); +} + static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) { return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >> @@ -349,7 +378,7 @@ struct spi_nor_hwcaps { * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly * (Slow) Read. */ -#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0) +#define SNOR_HWCAPS_READ_MASK GENMASK(15, 0) #define SNOR_HWCAPS_READ BIT(0) #define SNOR_HWCAPS_READ_FAST BIT(1) #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) @@ -366,11 +395,12 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_READ_4_4_4 BIT(9) #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10) -#define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11) +#define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11) #define SNOR_HWCAPS_READ_1_1_8 BIT(11) #define SNOR_HWCAPS_READ_1_8_8 BIT(12) #define SNOR_HWCAPS_READ_8_8_8 BIT(13) #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14) +#define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15) /* * Page Program capabilities. @@ -381,7 +411,7 @@ struct spi_nor_hwcaps { * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory * implements such commands. */ -#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16) +#define SNOR_HWCAPS_PP_MASK GENMASK(23, 16) #define SNOR_HWCAPS_PP BIT(16) #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17) @@ -389,10 +419,17 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_PP_1_4_4 BIT(18) #define SNOR_HWCAPS_PP_4_4_4 BIT(19) -#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20) +#define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20) #define SNOR_HWCAPS_PP_1_1_8 BIT(20) #define SNOR_HWCAPS_PP_1_8_8 BIT(21) #define SNOR_HWCAPS_PP_8_8_8 BIT(22) +#define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23) + +#define SNOR_HWCAPS_OPI_FULL_STR (SNOR_HWCAPS_READ_8_8_8 | \ + SNOR_HWCAPS_PP_8_8_8) + +#define SNOR_HWCAPS_OPI_FULL_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \ + SNOR_HWCAPS_PP_8_8_8_DTR) #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \ SNOR_HWCAPS_READ_4_4_4 | \ @@ -403,7 +440,9 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \ SNOR_HWCAPS_READ_1_2_2_DTR | \ SNOR_HWCAPS_READ_1_4_4_DTR | \ - SNOR_HWCAPS_READ_1_8_8_DTR) + SNOR_HWCAPS_READ_1_8_8_DTR | \ + SNOR_HWCAPS_READ_8_8_8_DTR | \ + SNOR_HWCAPS_PP_8_8_8_DTR) #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \ SNOR_HWCAPS_PP_MASK) @@ -442,6 +481,7 @@ enum spi_nor_read_command_index { SNOR_CMD_READ_1_8_8, SNOR_CMD_READ_8_8_8, SNOR_CMD_READ_1_8_8_DTR, + SNOR_CMD_READ_8D_8D_8D, SNOR_CMD_READ_MAX }; @@ -458,6 +498,7 @@ enum spi_nor_pp_command_index { SNOR_CMD_PP_1_1_8, SNOR_CMD_PP_1_8_8, SNOR_CMD_PP_8_8_8, + SNOR_CMD_PP_8D_8D_8D, SNOR_CMD_PP_MAX }; @@ -528,6 +569,11 @@ struct spi_nor_flash_parameter { */ struct flash_info; +enum extension_cmd_mode { + EXT_CMD_IS_CMD, + EXT_CMD_IS_INVERSE, +}; + /** * struct spi_nor - Structure for defining a the SPI NOR layer * @mtd: point to a mtd_info structure @@ -537,6 +583,7 @@ struct spi_nor_flash_parameter { * @bouncebuf: bounce buffer used when the buffer passed by the MTD * layer is not DMA-able * @bouncebuf_size: size of the bounce buffer + * @ext_cmd_mode: extension command mode, 0: same, 1: inverse * @info: spi-nor part JDEC MFR id and other info * @page_size: the page size of the SPI NOR * @addr_width: number of address bytes @@ -575,6 +622,7 @@ struct spi_nor { struct spi_mem *spimem; u8 *bouncebuf; size_t bouncebuf_size; + enum extension_cmd_mode ext_cmd_mode; const struct flash_info *info; u32 page_size; u8 addr_width; From patchwork Fri Nov 15 08:58:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 11245873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B2096C1 for ; Fri, 15 Nov 2019 10:04:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2B9022073B for ; Fri, 15 Nov 2019 10:04:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726930AbfKOKD7 (ORCPT ); Fri, 15 Nov 2019 05:03:59 -0500 Received: from twhmllg3.macronix.com ([122.147.135.201]:20679 "EHLO TWHMLLG3.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbfKOKD7 (ORCPT ); Fri, 15 Nov 2019 05:03:59 -0500 X-Greylist: delayed 3848 seconds by postgrey-1.27 at vger.kernel.org; Fri, 15 Nov 2019 05:03:59 EST Received: from TWHMLLG3.macronix.com (localhost [127.0.0.2] (may be forged)) by TWHMLLG3.macronix.com with ESMTP id xAF8xoZr046888 for ; Fri, 15 Nov 2019 16:59:50 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG3.macronix.com with ESMTP id xAF8wWGw046218; Fri, 15 Nov 2019 16:58:35 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, marek.vasut@gmail.com, dwmw2@infradead.org, computersforpeace@gmail.com, vigneshr@ti.com, bbrezillon@kernel.org, tudor.ambarus@microchip.com Cc: juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang , Boris Brezillon Subject: [PATCH 3/4] mtd: spi-nor: Add Octal 8D-8D-8D mode support for Macronix mx25uw51245g Date: Fri, 15 Nov 2019 16:58:07 +0800 Message-Id: <1573808288-19365-4-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> References: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG3.macronix.com xAF8wWGw046218 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org mx25uw51245g is a SPI NOR that supports 1-1-1/8-8-8 mode and the SFDPRD command but returns an empty SFDP page. This forces us to add a new entry in the flash_info table and patch spi_nor_fixups hooks to tweak flash parameters for spi_nor_read/pp_setting() and then to enter Octal 8D-8D-8D modes. Signed-off-by: Boris Brezillon Signed-off-by: Mason Yang --- drivers/mtd/spi-nor/spi-nor.c | 114 ++++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 3 ++ 2 files changed, 117 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 4cdf52d..9013590 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -615,6 +615,56 @@ static int write_disable(struct spi_nor *nor) } /* + * Read configuration register 2, returning its value in the + * location. Return the configuration register 2 value. + * Returns negative if error occurred. + */ +static int read_cr2(struct spi_nor *nor, u32 addr) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR2, 1), + SPI_MEM_OP_ADDR(4, addr, 1), + SPI_MEM_OP_DUMMY(4, 1), + SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + + if (spi_nor_protocol_is_8_8_8(nor->read_proto)) { + op.cmd.buswidth = 8; + op.addr.buswidth = 8; + op.dummy.buswidth = 8; + op.data.buswidth = 8; + op.cmd.nbytes = 2; + + if (spi_nor_protocol_is_8D_8D_8D(nor->read_proto)) { + op.dummy.nbytes *= 2; + op.cmd.dtr = true; + op.addr.dtr = true; + op.dummy.dtr = true; + op.data.dtr = true; + } + + if (nor->ext_cmd_mode == EXT_CMD_IS_INVERSE) + op.cmd.ext_opcode = ~SPINOR_OP_RDCR2; + else + op.cmd.ext_opcode = SPINOR_OP_RDCR2; + } + + ret = spi_mem_exec_op(nor->spimem, &op); + } else { + ret = -ENOTSUPP; + } + + if (ret < 0) { + dev_err(nor->dev, "error %d reading CR\n", ret); + return ret; + } + + return nor->bouncebuf[0]; +} + +/* * Write configuration register 2 one byte * Returns negative if error occurred. */ @@ -2275,10 +2325,72 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor) return 0; } +static void +spi_nor_set_read_settings(struct spi_nor_read_command *read, + u8 num_mode_clocks, + u8 num_wait_states, + u8 opcode, + enum spi_nor_protocol proto); + +static void +spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, + u8 opcode, + enum spi_nor_protocol proto); + +static void +mx25uw51245g_default_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = &nor->params; + + if (!(nor->spimem->spi->mode & (SPI_RX_OCTAL | SPI_TX_OCTAL))) + return; + + /* Octal 8S-8S-8S mode */ + params->hwcaps.mask |= SNOR_HWCAPS_OPI_FULL_STR; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8], + 0, 20, SPINOR_OP_READ_8_8_8, + SNOR_PROTO_8_8_8); + + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8], + SPINOR_OP_PP_8_8_8, SNOR_PROTO_8_8_8); + + /* Octal 8D-8D-8D mode */ + params->hwcaps.mask |= SNOR_HWCAPS_OPI_FULL_DTR; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8D_8D_8D], + 0, 20, SPINOR_OP_READ_8D_8D_8D, + SNOR_PROTO_8_8_8_DTR); + + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8D_8D_8D], + SPINOR_OP_PP_8D_8D_8D, SNOR_PROTO_8_8_8_DTR); + + nor->ext_cmd_mode = EXT_CMD_IS_INVERSE; +} + +static void +mx25uw51245g_post_sfdp_fixups(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = &nor->params; + u8 cr2; + + cr2 = read_cr2(nor, CR2_REG0) & CR2_REG0_MODE_MASK; + + if (params->hwcaps.mask & SNOR_HWCAPS_OPI_FULL_DTR) + cr2 |= CR2_REG0_MODE_OPI_DTR; + else if (params->hwcaps.mask & SNOR_HWCAPS_OPI_FULL_STR) + cr2 |= CR2_REG0_MODE_OPI_STR; + + write_cr2(nor, CR2_REG0, cr2); +} + static struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, }; +static struct spi_nor_fixups mx25uw51245g_fixups = { + .default_init = mx25uw51245g_default_init, + .post_sfdp = mx25uw51245g_post_sfdp_fixups, +}; + static void gd25q256_default_init(struct spi_nor *nor) { /* @@ -2442,6 +2554,8 @@ static void gd25q256_default_init(struct spi_nor *nor) SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) .fixups = &mx25l25635_fixups }, { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, + { "mx25uw51245g", INFO(0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_4B_OPCODES) + .fixups = &mx25uw51245g_fixups}, { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2e720ca..3aa54dd 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -114,6 +114,9 @@ /* Write CFG Reg 2 - defined in JEDEC JESD216C. */ #define SPINOR_OP_WRCR2 0x72 /* Write configuration register 2 */ +/* Used for Macronix flashes only */ +#define SPINOR_OP_RDCR2 0x71 /* Read configuration register 2 */ + /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ From patchwork Fri Nov 15 08:58:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 11245875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 87B50138C for ; Fri, 15 Nov 2019 10:04:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 71DF12073B for ; Fri, 15 Nov 2019 10:04:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727137AbfKOKEB (ORCPT ); Fri, 15 Nov 2019 05:04:01 -0500 Received: from twhmllg3.macronix.com ([122.147.135.201]:20680 "EHLO TWHMLLG3.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726920AbfKOKEB (ORCPT ); Fri, 15 Nov 2019 05:04:01 -0500 Received: from TWHMLLG3.macronix.com (localhost [127.0.0.2] (may be forged)) by TWHMLLG3.macronix.com with ESMTP id xAF8xp4i046911 for ; Fri, 15 Nov 2019 16:59:51 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG3.macronix.com with ESMTP id xAF8wWGx046218; Fri, 15 Nov 2019 16:58:36 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: Mason Yang To: broonie@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, marek.vasut@gmail.com, dwmw2@infradead.org, computersforpeace@gmail.com, vigneshr@ti.com, bbrezillon@kernel.org, tudor.ambarus@microchip.com Cc: juliensu@mxic.com.tw, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, Mason Yang Subject: [PATCH 4/4] spi: mxic: Add support for Octal 8D-8D-8D mode Date: Fri, 15 Nov 2019 16:58:08 +0800 Message-Id: <1573808288-19365-5-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> References: <1573808288-19365-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG3.macronix.com xAF8wWGx046218 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org patch driver for 8-8-8 and 8D-8D-8D mode support. Signed-off-by: Mason Yang --- drivers/spi/spi-mxic.c | 98 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 31 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index f48563c..50e2055 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -280,10 +280,58 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } +static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op) +{ + u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) | + OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) | + (op->cmd.dtr ? OP_CMD_DDR : 0); + + if (op->addr.nbytes) + cfg |= OP_ADDR_BYTES(op->addr.nbytes) | + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) | + (op->addr.dtr ? OP_ADDR_DDR : 0); + + if (op->dummy.nbytes) + cfg |= OP_DUMMY_CYC(op->dummy.nbytes); + + if (op->data.nbytes) { + cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | + (op->data.dtr ? OP_DATA_DDR : 0); + if (op->data.dir == SPI_MEM_DATA_IN) { + cfg |= OP_READ; + if (op->data.dtr == OP_DATA_DDR) + cfg |= OP_DQS_EN; + } + } + + return cfg; +} + +static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags) +{ + struct mxic_spi *mxic = spi_master_get_devdata(spi->master); + int nio = 1; + + if (spi->mode & (SPI_RX_OCTAL | SPI_TX_OCTAL)) + nio = 8; + else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) + nio = 4; + else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) + nio = 2; + + writel(flags | HC_CFG_NIO(nio) | + HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) | + HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1), + mxic->regs + HC_CFG); +} + static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, void *rxbuf, unsigned int len) { unsigned int pos = 0; + bool dtr_enabled; + + dtr_enabled = (readl(mxic->regs + SS_CTRL(0)) & OP_DATA_DDR); while (pos < len) { unsigned int nbytes = len - pos; @@ -302,6 +350,9 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, if (ret) return ret; + if (dtr_enabled && len & 0x1) + nbytes++; + writel(data, mxic->regs + TXD(nbytes % 4)); if (rxbuf) { @@ -319,6 +370,8 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, data = readl(mxic->regs + RXD); data >>= (8 * (4 - nbytes)); + if (dtr_enabled && len & 0x1) + nbytes++; memcpy(rxbuf + pos, &data, nbytes); WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); } else { @@ -335,8 +388,8 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, static bool mxic_spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { - if (op->data.buswidth > 4 || op->addr.buswidth > 4 || - op->dummy.buswidth > 4 || op->cmd.buswidth > 4) + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) return false; if (op->data.nbytes && op->dummy.nbytes && @@ -353,47 +406,29 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); - int nio = 1, i, ret; - u32 ss_ctrl; + int i, ret; u8 addr[8]; + u8 cmd[2]; ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); if (ret) return ret; - if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) - nio = 4; - else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) - nio = 2; + mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN); - writel(HC_CFG_NIO(nio) | - HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) | - HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) | - HC_CFG_MAN_CS_EN, - mxic->regs + HC_CFG); writel(HC_EN_BIT, mxic->regs + HC_EN); - ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1); - - if (op->addr.nbytes) - ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) | - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1); - - if (op->dummy.nbytes) - ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes); - - if (op->data.nbytes) { - ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1); - if (op->data.dir == SPI_MEM_DATA_IN) - ss_ctrl |= OP_READ; - } - - writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select)); + writel(mxic_spi_mem_prep_op_cfg(op), + mxic->regs + SS_CTRL(mem->spi->chip_select)); writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, mxic->regs + HC_CFG); - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1); + cmd[0] = op->cmd.opcode; + if (op->cmd.nbytes == 2) + cmd[1] = op->cmd.ext_opcode; + + ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); if (ret) goto out; @@ -566,7 +601,8 @@ static int mxic_spi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_MASK(8); master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_TX_DUAL | - SPI_RX_QUAD | SPI_TX_QUAD; + SPI_RX_QUAD | SPI_TX_QUAD | + SPI_RX_OCTAL | SPI_TX_OCTAL; mxic_spi_hw_init(mxic);