From patchwork Fri Nov 15 14:54:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 11246509 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E9394138C for ; Fri, 15 Nov 2019 14:56:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D229320732 for ; Fri, 15 Nov 2019 14:56:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D229320732 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C40806E634; Fri, 15 Nov 2019 14:56:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id B09F96E634 for ; Fri, 15 Nov 2019 14:56:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Nov 2019 06:56:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,308,1569308400"; d="scan'208";a="203408572" Received: from slisovsk-lenovo-ideapad-720s-13ikb.fi.intel.com ([10.237.72.89]) by fmsmga008.fm.intel.com with ESMTP; 15 Nov 2019 06:56:38 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Fri, 15 Nov 2019 16:54:00 +0200 Message-Id: <20191115145401.20709-2-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191115145401.20709-1-stanislav.lisovskiy@intel.com> References: <20191115145401.20709-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently intel_can_enable_sagv function contains a mix of workarounds for different platforms some of them are not valid for gens >= 11 already, so lets split it into separate functions. v2: - Rework watermark calculation algorithm to attempt to calculate Level 0 watermark with added sagv block time latency and check if it fits in DBuf in order to determine if SAGV can be enabled already at this stage, just as BSpec 49325 states. if that fails rollback to usual Level 0 latency and disable SAGV. - Remove unneeded tabs(James Ausmus) v3: Rebased the patch v4: - Added back interlaced check for Gen12 and added separate function for TGL SAGV check (thanks to James Ausmus for spotting) - Removed unneeded gen check - Extracted Gen12 SAGV decision making code to a separate function from skl_compute_wm v5: - Added SAGV global state to dev_priv, because we need to track all pipes, not only those in atomic state. Each pipe has now correspondent bit mask reflecting, whether it can tolerate SAGV or not(thanks to Ville Syrjala for suggestions). - Now using active flag instead of enable in crc usage check. v6: - Fixed rebase conflicts v7: - kms_cursor_legacy seems to get broken because of multiple memcpy calls when copying level 0 water marks for enabled SAGV, to fix this now simply using that field right away, without copying, for that introduced a new wm_level accessor which decides which wm_level to return based on SAGV state. v8: - Protect crtc_sagv_mask same way as we do for other global state changes: i.e check if changes are needed, then grab all crtc locks to serialize the changes. Signed-off-by: Stanislav Lisovskiy Cc: Ville Syrjälä Cc: James Ausmus --- drivers/gpu/drm/i915/display/intel_display.c | 12 +- .../drm/i915/display/intel_display_types.h | 15 + drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/intel_pm.c | 418 ++++++++++++++++-- drivers/gpu/drm/i915/intel_pm.h | 1 + 5 files changed, 409 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index adf50c4b38ad..7f31e33d0b16 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13401,7 +13401,10 @@ static void verify_wm_state(struct intel_crtc *crtc, /* Watermarks */ for (level = 0; level <= max_level; level++) { if (skl_wm_level_equals(&hw_plane_wm->wm[level], - &sw_plane_wm->wm[level])) + &sw_plane_wm->wm[level]) || + (skl_wm_level_equals(&hw_plane_wm->wm[level], + &sw_plane_wm->sagv_wm0) && + (level == 0))) continue; DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", @@ -13453,7 +13456,10 @@ static void verify_wm_state(struct intel_crtc *crtc, /* Watermarks */ for (level = 0; level <= max_level; level++) { if (skl_wm_level_equals(&hw_plane_wm->wm[level], - &sw_plane_wm->wm[level])) + &sw_plane_wm->wm[level]) || + (skl_wm_level_equals(&hw_plane_wm->wm[level], + &sw_plane_wm->sagv_wm0) && + (level == 0))) continue; DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", @@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) new_crtc_state); } + dev_priv->crtc_sagv_mask = state->crtc_sagv_mask; + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { intel_post_plane_update(old_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 83ea04149b77..6a300cac883f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -490,6 +490,20 @@ struct intel_atomic_state { */ u8 active_pipe_changes; + /* + * Contains a mask which reflects whether correspondent pipe + * can tolerate SAGV or not, so that we can make a decision + * at atomic_commit_tail stage, whether we enable it or not + * based on global state in dev_priv. + */ + u32 crtc_sagv_mask; + + /* + * Used to determine if the mask has been already calculated + * for this state, to avoid unnecessary calculations. + */ + bool crtc_sagv_mask_set; + u8 active_pipes; /* minimum acceptable cdclk for each pipe */ int min_cdclk[I915_MAX_PIPES]; @@ -670,6 +684,7 @@ struct skl_plane_wm { struct skl_wm_level wm[8]; struct skl_wm_level uv_wm[8]; struct skl_wm_level trans_wm; + struct skl_wm_level sagv_wm0; bool is_planar; }; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1779f600fcfb..0ac9d7b006ca 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1171,6 +1171,12 @@ struct drm_i915_private { u32 sagv_block_time_us; + /* + * Contains a bit mask, whether correspondent + * pipe allows SAGV or not. + */ + u32 crtc_sagv_mask; + struct { /* * Raw watermark latency values: diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 05ba9e1bd247..c914bd1862ba 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv) return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv); } -static bool +bool intel_has_sagv(struct drm_i915_private *dev_priv) { - /* HACK! */ - if (IS_GEN(dev_priv, 12)) - return false; - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; } @@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) return 0; } -bool intel_can_enable_sagv(struct intel_atomic_state *state) +static void skl_set_sagv_mask(struct intel_atomic_state *state) { struct drm_device *dev = state->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) enum pipe pipe; int level, latency; + if (state->crtc_sagv_mask_set) + return; + if (!intel_has_sagv(dev_priv)) - return false; + return; /* * If there are no active CRTCs, no additional checks need be performed */ if (hweight8(state->active_pipes) == 0) - return true; + return; /* * SKL+ workaround: bspec recommends we disable SAGV when we have * more then one pipe enabled */ if (hweight8(state->active_pipes) > 1) - return false; + return; /* Since we're now guaranteed to only have one active CRTC... */ pipe = ffs(state->active_pipes) - 1; crtc = intel_get_crtc_for_pipe(dev_priv, pipe); crtc_state = to_intel_crtc_state(crtc->base.state); + state->crtc_sagv_mask &= ~BIT(crtc->pipe); - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) - return false; + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { + state->crtc_sagv_mask_set = true; + return; + } for_each_intel_plane_on_crtc(dev, crtc, plane) { struct skl_plane_wm *wm = @@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state) * incur memory latencies higher than sagv_block_time_us we * can't enable SAGV. */ - if (latency < dev_priv->sagv_block_time_us) + if (latency < dev_priv->sagv_block_time_us) { + state->crtc_sagv_mask_set = true; + return; + } + } + + state->crtc_sagv_mask |= BIT(crtc->pipe); + state->crtc_sagv_mask_set = true; +} + +static void tgl_set_sagv_mask(struct intel_atomic_state *state); + +static void icl_set_sagv_mask(struct intel_atomic_state *state) +{ + struct drm_device *dev = state->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc; + struct intel_crtc_state *new_crtc_state; + int level, latency; + int i; + int plane_id; + + if (state->crtc_sagv_mask_set) + return; + + if (!intel_has_sagv(dev_priv)) + return; + + /* + * If there are no active CRTCs, no additional checks need be performed + */ + if (hweight8(state->active_pipes) == 0) + return; + + for_each_new_intel_crtc_in_state(state, crtc, + new_crtc_state, i) { + unsigned int flags = crtc->base.state->adjusted_mode.flags; + bool can_sagv; + + if (flags & DRM_MODE_FLAG_INTERLACE) + continue; + + if (!new_crtc_state->hw.active) + continue; + + can_sagv = true; + for_each_plane_id_on_crtc(crtc, plane_id) { + struct skl_plane_wm *wm = + &new_crtc_state->wm.skl.optimal.planes[plane_id]; + + /* Skip this plane if it's not enabled */ + if (!wm->wm[0].plane_en) + continue; + + /* Find the highest enabled wm level for this plane */ + for (level = ilk_wm_max_level(dev_priv); + !wm->wm[level].plane_en; --level) { + } + + latency = dev_priv->wm.skl_latency[level]; + + /* + * If any of the planes on this pipe don't enable + * wm levels that incur memory latencies higher than + * sagv_block_time_us we can't enable SAGV. + */ + if (latency < dev_priv->sagv_block_time_us) { + can_sagv = false; + break; + } + } + if (can_sagv) + state->crtc_sagv_mask |= BIT(crtc->pipe); + else + state->crtc_sagv_mask &= ~BIT(crtc->pipe); + } + state->crtc_sagv_mask_set = true; +} + +bool intel_can_enable_sagv(struct intel_atomic_state *state) +{ + struct drm_device *dev = state->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + int ret, i; + struct intel_crtc *crtc; + struct intel_crtc_state *new_crtc_state; + + /* + * Make sure we always pick global state first, + * there shouldn't be any issue as we hold only locks + * to correspondent crtcs in state, however once + * we detect that we need to change SAGV mask + * in global state, we will grab all the crtc locks + * in order to get this serialized, thus other + * racing commits having other crtc locks, will have + * to start over again, as stated by Wound-Wait + * algorithm. + */ + state->crtc_sagv_mask = dev_priv->crtc_sagv_mask; + + if (INTEL_GEN(dev_priv) >= 12) + tgl_set_sagv_mask(state); + else if (INTEL_GEN(dev_priv) == 11) + icl_set_sagv_mask(state); + else + skl_set_sagv_mask(state); + + /* + * For SAGV we need to account all the pipes, + * not only the ones which are in state currently. + * Grab all locks if we detect that we are actually + * going to do something. + */ + if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) { + ret = intel_atomic_serialize_global_state(state); + if (ret) { + DRM_DEBUG_KMS("Could not serialize global state\n"); + return false; + } + } + + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + u32 mask = BIT(crtc->pipe); + bool state_sagv_masked = (mask & state->crtc_sagv_mask) == 0; + + if (!new_crtc_state->hw.active) + continue; + + if (state_sagv_masked) return false; } @@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, int color_plane); static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, int level, + u32 latency, const struct skl_wm_params *wp, const struct skl_wm_level *result_prev, struct skl_wm_level *result /* out */); @@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, WARN_ON(ret); for (level = 0; level <= max_level; level++) { - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm); + u32 latency = dev_priv->wm.skl_latency[level]; + + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm); + if (wm.min_ddb_alloc == U16_MAX) break; @@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state, return total_data_rate; } +static int +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state, + struct skl_ddb_allocation *ddb /* out */) +{ + struct drm_crtc *crtc = crtc_state->uapi.crtc; + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; + u16 alloc_size; + u16 total[I915_MAX_PLANES] = {}; + u64 total_data_rate; + enum plane_id plane_id; + int num_active; + u64 plane_data_rate[I915_MAX_PLANES] = {}; + u32 blocks; + + /* + * No need to check gen here, we call this only for gen12 + */ + total_data_rate = + icl_get_total_relative_data_rate(crtc_state, + plane_data_rate); + + skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, + total_data_rate, + ddb, alloc, &num_active); + alloc_size = skl_ddb_entry_size(alloc); + if (alloc_size == 0) + return -ENOSPC; + + /* Allocate fixed number of blocks for cursor. */ + total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active); + alloc_size -= total[PLANE_CURSOR]; + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start = + alloc->end - total[PLANE_CURSOR]; + crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end; + + /* + * Do check if we can fit L0 + sagv_block_time and + * disable SAGV if we can't. + */ + blocks = 0; + for_each_plane_id_on_crtc(intel_crtc, plane_id) { + const struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane_id]; + + if (plane_id == PLANE_CURSOR) { + if (WARN_ON(wm->sagv_wm0.min_ddb_alloc > + total[PLANE_CURSOR])) { + blocks = U32_MAX; + break; + } + continue; + } + + blocks += wm->sagv_wm0.min_ddb_alloc; + if (blocks > alloc_size) + return -ENOSPC; + } + return 0; +} + +const struct skl_wm_level * +skl_plane_wm_level(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + int level, + bool yuv) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + enum plane_id plane_id = plane->id; + const struct skl_plane_wm *wm = + &crtc_state->wm.skl.optimal.planes[plane_id]; + + /* + * Looks ridicilous but need to check if state is not + * NULL here as it might be as some cursor plane manipulations + * seem to happen when no atomic state is actually present, + * despite crtc_state is allocated. Removing state check + * from here will result in kernel panic on boot. + * However we now need to check whether should be use SAGV + * wm levels here. + */ + if (state) { + struct intel_atomic_state *intel_state = + to_intel_atomic_state(state); + if (intel_can_enable_sagv(intel_state) && !level) + return &wm->sagv_wm0; + } + + return yuv ? &wm->uv_wm[level] : &wm->wm[level]; +} + static int skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, struct skl_ddb_allocation *ddb /* out */) @@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, u16 uv_total[I915_MAX_PLANES] = {}; u64 total_data_rate; enum plane_id plane_id; + struct intel_plane *plane; + const struct skl_wm_level *wm_level; + const struct skl_wm_level *wm_uv_level; int num_active; u64 plane_data_rate[I915_MAX_PLANES] = {}; u64 uv_plane_data_rate[I915_MAX_PLANES] = {}; @@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, */ for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) { blocks = 0; - for_each_plane_id_on_crtc(intel_crtc, plane_id) { - const struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane_id]; + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { + plane_id = plane->id; + wm_level = skl_plane_wm_level(plane, crtc_state, + level, false); + wm_uv_level = skl_plane_wm_level(plane, crtc_state, + level, true); if (plane_id == PLANE_CURSOR) { - if (WARN_ON(wm->wm[level].min_ddb_alloc > + if (WARN_ON(wm_level->min_ddb_alloc > total[PLANE_CURSOR])) { blocks = U32_MAX; break; @@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, continue; } - blocks += wm->wm[level].min_ddb_alloc; - blocks += wm->uv_wm[level].min_ddb_alloc; + blocks += wm_level->min_ddb_alloc; + blocks += wm_uv_level->min_ddb_alloc; } if (blocks <= alloc_size) { @@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, * watermark level, plus an extra share of the leftover blocks * proportional to its relative data rate. */ - for_each_plane_id_on_crtc(intel_crtc, plane_id) { - const struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane_id]; + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { u64 rate; u16 extra; + plane_id = plane->id; + wm_level = skl_plane_wm_level(plane, crtc_state, + level, false); + wm_uv_level = skl_plane_wm_level(plane, crtc_state, + level, true); + if (plane_id == PLANE_CURSOR) continue; @@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, extra = min_t(u16, alloc_size, DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate)); - total[plane_id] = wm->wm[level].min_ddb_alloc + extra; + total[plane_id] = wm_level->min_ddb_alloc + extra; alloc_size -= extra; total_data_rate -= rate; @@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, extra = min_t(u16, alloc_size, DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate)); - uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra; + uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra; alloc_size -= extra; total_data_rate -= rate; } @@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, * that aren't actually possible. */ for (level++; level <= ilk_wm_max_level(dev_priv); level++) { - for_each_plane_id_on_crtc(intel_crtc, plane_id) { + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { struct skl_plane_wm *wm = - &crtc_state->wm.skl.optimal.planes[plane_id]; + &crtc_state->wm.skl.optimal.planes[plane->id]; + + wm_level = skl_plane_wm_level(plane, crtc_state, + level, false); + wm_uv_level = skl_plane_wm_level(plane, crtc_state, + level, true); /* * We only disable the watermarks for each plane if @@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, * planes must be enabled before the level will be used." * So this is actually safe to do. */ - if (wm->wm[level].min_ddb_alloc > total[plane_id] || - wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id]) - memset(&wm->wm[level], 0, sizeof(wm->wm[level])); + if (wm_level->min_ddb_alloc > total[plane->id] || + wm_uv_level->min_ddb_alloc > uv_total[plane->id]) + memset(&wm->wm[level], 0, + sizeof(struct skl_wm_level)); /* * Wa_1408961008:icl, ehl @@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, */ if (IS_GEN(dev_priv, 11) && level == 1 && wm->wm[0].plane_en) { - wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; - wm->wm[level].plane_res_l = wm->wm[0].plane_res_l; - wm->wm[level].ignore_lines = wm->wm[0].ignore_lines; + wm_level = skl_plane_wm_level(plane, crtc_state, + 0, false); + wm->wm[level].plane_res_b = + wm_level->plane_res_b; + wm->wm[level].plane_res_l = + wm_level->plane_res_l; + wm->wm[level].ignore_lines = + wm_level->ignore_lines; } } } @@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, int level, + u32 latency, const struct skl_wm_params *wp, const struct skl_wm_level *result_prev, struct skl_wm_level *result /* out */) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - u32 latency = dev_priv->wm.skl_latency[level]; uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t selected_result; u32 res_blocks, res_lines, min_ddb_alloc = 0; @@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, static void skl_compute_wm_levels(const struct intel_crtc_state *crtc_state, const struct skl_wm_params *wm_params, - struct skl_wm_level *levels) + struct skl_plane_wm *plane_wm, + bool yuv) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); int level, max_level = ilk_wm_max_level(dev_priv); + /* + * Check which kind of plane is it and based on that calculate + * correspondent WM levels. + */ + struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm; struct skl_wm_level *result_prev = &levels[0]; for (level = 0; level <= max_level; level++) { struct skl_wm_level *result = &levels[level]; + u32 latency = dev_priv->wm.skl_latency[level]; - skl_compute_plane_wm(crtc_state, level, wm_params, - result_prev, result); + skl_compute_plane_wm(crtc_state, level, latency, + wm_params, result_prev, result); result_prev = result; } + /* + * For Gen12 if it is an L0 we need to also + * consider sagv_block_time when calculating + * L0 watermark - we will need that when making + * a decision whether enable SAGV or not. + * For older gens we agreed to copy L0 value for + * compatibility. + */ + if ((INTEL_GEN(dev_priv) >= 12)) { + u32 latency = dev_priv->wm.skl_latency[0]; + + latency += dev_priv->sagv_block_time_us; + skl_compute_plane_wm(crtc_state, 0, latency, + wm_params, &levels[0], + &plane_wm->sagv_wm0); + } else + memcpy(&plane_wm->sagv_wm0, &levels[0], + sizeof(struct skl_wm_level)); } static u32 @@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state, if (ret) return ret; - skl_compute_wm_levels(crtc_state, &wm_params, wm->wm); + skl_compute_wm_levels(crtc_state, &wm_params, wm, false); skl_compute_transition_wm(crtc_state, &wm_params, wm); return 0; @@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state, if (ret) return ret; - skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm); + skl_compute_wm_levels(crtc_state, &wm_params, wm, true); return 0; } @@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane *plane, &crtc_state->wm.skl.plane_ddb_y[plane_id]; const struct skl_ddb_entry *ddb_uv = &crtc_state->wm.skl.plane_ddb_uv[plane_id]; + const struct skl_wm_level *wm_level; for (level = 0; level <= max_level; level++) { + wm_level = skl_plane_wm_level(plane, crtc_state, level, false); + skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), &wm->trans_wm); @@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane *plane, &crtc_state->wm.skl.optimal.planes[plane_id]; const struct skl_ddb_entry *ddb = &crtc_state->wm.skl.plane_ddb_y[plane_id]; + const struct skl_wm_level *wm_level; for (level = 0; level <= max_level; level++) { + wm_level = skl_plane_wm_level(plane, crtc_state, level, false); + skl_write_wm_level(dev_priv, CUR_WM(pipe, level), - &wm->wm[level]); + wm_level); } skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); @@ -5451,18 +5729,73 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, return 0; } +static void tgl_set_sagv_mask(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + struct intel_crtc_state *new_crtc_state; + struct intel_crtc_state *old_crtc_state; + struct skl_ddb_allocation *ddb = &state->wm_results.ddb; + int ret; + int i; + struct intel_plane *plane; + + if (state->crtc_sagv_mask_set) + return; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + int pipe_bit = BIT(crtc->pipe); + bool skip = true; + + /* + * If we had set this mast already once for this state, + * no need to waste CPU cycles for doing this again. + */ + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { + enum plane_id plane_id = plane->id; + + if (!skl_plane_wm_equals(dev_priv, + &old_crtc_state->wm.skl.optimal.planes[plane_id], + &new_crtc_state->wm.skl.optimal.planes[plane_id])) { + skip = false; + break; + } + } + + /* + * Check if wm levels are actually the same as for previous + * state, which means we can just skip doing this long check + * and just copy correspondent bit from previous state. + */ + if (skip) + continue; + + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb); + if (!ret) + state->crtc_sagv_mask |= pipe_bit; + else + state->crtc_sagv_mask &= ~pipe_bit; + } + state->crtc_sagv_mask_set = true; +} + static int skl_compute_wm(struct intel_atomic_state *state) { struct intel_crtc *crtc; struct intel_crtc_state *new_crtc_state; struct intel_crtc_state *old_crtc_state; - struct skl_ddb_values *results = &state->wm_results; int ret, i; + struct skl_ddb_values *results = &state->wm_results; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); /* Clear all dirty flags */ results->dirty_pipes = 0; + /* If we exit before check is done */ + state->crtc_sagv_mask = dev_priv->crtc_sagv_mask; + ret = skl_ddb_add_affected_pipes(state); if (ret) return ret; @@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, val = I915_READ(CUR_WM(pipe, level)); skl_wm_level_from_reg_val(val, &wm->wm[level]); + if (level == 0) + memcpy(&wm->sagv_wm0, &wm->wm[level], + sizeof(struct skl_wm_level)); } if (plane_id != PLANE_CURSOR) diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index b579c724b915..53275860731a 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, void g4x_wm_sanitize(struct drm_i915_private *dev_priv); void vlv_wm_sanitize(struct drm_i915_private *dev_priv); bool intel_can_enable_sagv(struct intel_atomic_state *state); +bool intel_has_sagv(struct drm_i915_private *dev_priv); int intel_enable_sagv(struct drm_i915_private *dev_priv); int intel_disable_sagv(struct drm_i915_private *dev_priv); bool skl_wm_level_equals(const struct skl_wm_level *l1, From patchwork Fri Nov 15 14:54:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 11246511 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC98B930 for ; Fri, 15 Nov 2019 14:56:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5AF120674 for ; Fri, 15 Nov 2019 14:56:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5AF120674 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3162A6E785; Fri, 15 Nov 2019 14:56:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7341B6E634 for ; Fri, 15 Nov 2019 14:56:43 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Nov 2019 06:56:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,308,1569308400"; d="scan'208";a="203408580" Received: from slisovsk-lenovo-ideapad-720s-13ikb.fi.intel.com ([10.237.72.89]) by fmsmga008.fm.intel.com with ESMTP; 15 Nov 2019 06:56:40 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Fri, 15 Nov 2019 16:54:01 +0200 Message-Id: <20191115145401.20709-3-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191115145401.20709-1-stanislav.lisovskiy@intel.com> References: <20191115145401.20709-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to BSpec 53998, we should try to restrict qgv points, which can't provide enough bandwidth for desired display configuration. Currently we are just comparing against all of those and take minimum(worst case). v2: Fixed wrong PCode reply mask, removed hardcoded values. v3: Forbid simultaneous legacy SAGV PCode requests and restricting qgv points. Put the actual restriction to commit function, added serialization(thanks to Ville) to prevent commit being applied out of order in case of nonblocking and/or nomodeset commits. v4: - Minor code refactoring, fixed few typos(thanks to James Ausmus) - Change the naming of qgv point masking/unmasking functions(James Ausmus). - Simplify the masking/unmasking operation itself, as we don't need to mask only single point per request(James Ausmus) - Reject and stick to highest bandwidth point if SAGV can't be enabled(BSpec) v5: - Add new mailbox reply codes, which seems to happen during boot time for TGL and indicate that QGV setting is not yet available. v6: - Increase number of supported QGV points to be in sync with BSpec. v7: - Rebased and resolved conflict to fix build failure. - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) v8: - Don't report an error if we can't restrict qgv points, as SAGV can be disabled by BIOS, which is completely legal. So don't make CI panic. Instead if we detect that there is only 1 QGV point accessible just analyze if we can fit the required bandwidth requirements, but no need in restricting. v9: - Fix wrong QGV transition if we have 0 planes and no SAGV simultaneously. v10: - Fix CDCLK corruption, because of global state getting serialized without modeset, which caused copying of non-calculated cdclk to be copied to dev_priv(thanks to Ville for the hint). v11: - Remove unneeded headers and spaces(Matthew Roper) - Remove unneeded intel_qgv_info qi struct from bw check and zero out the needed one(Matthew Roper) - Changed QGV error message to have more clear meaning(Matthew Roper) - Use state->modeset_set instead of any_ms(Matthew Roper) - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) - Moved unrelated changes to other patch(using latency as parameter for plane wm calculation, moved to SAGV refactoring patch) Reviewed-by: James Ausmus Signed-off-by: Stanislav Lisovskiy Cc: Ville Syrjälä Cc: James Ausmus --- drivers/gpu/drm/i915/display/intel_atomic.h | 2 + drivers/gpu/drm/i915/display/intel_bw.c | 134 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_bw.h | 2 + drivers/gpu/drm/i915/display/intel_display.c | 91 +++++++++++- .../drm/i915/display/intel_display_types.h | 3 + drivers/gpu/drm/i915/i915_drv.h | 7 +- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_sideband.c | 27 +++- 8 files changed, 241 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h index 7b49623419ba..41a2a89c9bdb 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.h +++ b/drivers/gpu/drm/i915/display/intel_atomic.h @@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state); struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); void intel_atomic_state_clear(struct drm_atomic_state *state); +int intel_atomic_serialize_global_state(struct intel_atomic_state *state); + struct intel_crtc_state * intel_atomic_get_crtc_state(struct drm_atomic_state *state, struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 3f6e29f61323..809fc1bf99c5 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -8,6 +8,9 @@ #include "intel_bw.h" #include "intel_display_types.h" #include "intel_sideband.h" +#include "intel_atomic.h" +#include "intel_pm.h" + /* Parameters for Qclk Geyserville (QGV) */ struct intel_qgv_point { @@ -15,7 +18,7 @@ struct intel_qgv_point { }; struct intel_qgv_info { - struct intel_qgv_point points[3]; + struct intel_qgv_point points[NUM_SAGV_POINTS]; u8 num_points; u8 num_channels; u8 t_bl; @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, return 0; } +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, + u32 points_mask) +{ + int ret; + + /* bspec says to keep retrying for at least 1 ms */ + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, + points_mask, + GEN11_PCODE_POINTS_RESTRICTED_MASK, + GEN11_PCODE_POINTS_RESTRICTED, + 1); + + if (ret < 0) { + DRM_ERROR("Failed to disable qgv points (%d)\n", ret); + return ret; + } + + return 0; +} + static int icl_get_qgv_points(struct drm_i915_private *dev_priv, struct intel_qgv_info *qi) { @@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) icl_get_bw_info(dev_priv, &icl_sa_info); } -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, - int num_planes) -{ - if (INTEL_GEN(dev_priv) >= 11) - /* - * FIXME with SAGV disabled maybe we can assume - * point 1 will always be used? Seems to match - * the behaviour observed in the wild. - */ - return min3(icl_max_bw(dev_priv, num_planes, 0), - icl_max_bw(dev_priv, num_planes, 1), - icl_max_bw(dev_priv, num_planes, 2)); - else - return UINT_MAX; -} - static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) { /* @@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) unsigned int data_rate, max_data_rate; unsigned int num_active_planes; struct intel_crtc *crtc; - int i; + int i, ret; + u32 allowed_points = 0; + unsigned int max_bw_point = 0, max_bw = 0; + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points; + u32 mask = (1 << num_qgv_points) - 1; /* FIXME earlier gens need some checks too */ if (INTEL_GEN(dev_priv) < 11) @@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) data_rate = intel_bw_data_rate(dev_priv, bw_state); num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); - data_rate = DIV_ROUND_UP(data_rate, 1000); - if (data_rate > max_data_rate) { - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", - data_rate, max_data_rate, num_active_planes); + for (i = 0; i < num_qgv_points; i++) { + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i); + /* + * We need to know which qgv point gives us + * maximum bandwidth in order to disable SAGV + * if we find that we exceed SAGV block time + * with watermarks. By that moment we already + * have those, as it is calculated earlier in + * intel_atomic_check, + */ + if (max_data_rate > max_bw) { + max_bw_point = i; + max_bw = max_data_rate; + } + if (max_data_rate >= data_rate) + allowed_points |= BIT(i); + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n", + i, max_data_rate, data_rate); + } + + /* + * BSpec states that we always should have at least one allowed point + * left, so if we couldn't - simply reject the configuration for obvious + * reasons. + */ + if (allowed_points == 0) { + DRM_DEBUG_KMS("No QGV points provide sufficient memory" + " bandwidth for display configuration.\n"); return -EINVAL; } + /* + * In case if SAGV is disabled in BIOS, we always get 1 + * SAGV point, but we can't send PCode commands to restrict it + * as it will fail and pointless anyway. + */ + if (num_qgv_points == 1) + dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + else + dev_priv->sagv_status = I915_SAGV_ENABLED; + + /* + * Leave only single point with highest bandwidth, if + * we can't enable SAGV according to BSpec. + */ + if (!intel_can_enable_sagv(state)) { + + /* + * This is a border line condition when we have 0 planes + * and SAGV not enabled means that we should keep QGV with + * highest bandwidth, however algorithm returns wrong result + * for 0 planes and 0 data rate, so just stick to last config + * then. Otherwise use the QGV point with highest BW according + * to BSpec. + */ + if (!data_rate && !num_active_planes) { + DRM_DEBUG_KMS("No SAGV, using old QGV mask\n"); + allowed_points = (~dev_priv->qgv_points_mask) & mask; + } else { + allowed_points = 1 << max_bw_point; + DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n", + max_bw_point); + } + } + /* + * We store the ones which need to be masked as that is what PCode + * actually accepts as a parameter. + */ + state->qgv_points_mask = (~allowed_points) & mask; + + DRM_DEBUG_KMS("New state %p qgv mask %x\n", + state, state->qgv_points_mask); + + /* + * If the actual mask had changed we need to make sure that + * the commits are serialized(in case this is a nomodeset, nonblocking) + */ + if (state->qgv_points_mask != dev_priv->qgv_points_mask) { + ret = intel_atomic_serialize_global_state(state); + if (ret) { + DRM_DEBUG_KMS("Could not serialize global state\n"); + return ret; + } + } + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 9db10af012f4..66bf9bc10b73 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state *state); void intel_bw_crtc_update(struct intel_bw_state *bw_state, const struct intel_crtc_state *crtc_state); +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, + u32 points_mask); #endif /* __INTEL_BW_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7f31e33d0b16..fd35d0b0699c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14755,6 +14755,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work) intel_atomic_helper_free_state(i915); } +static void intel_qgv_points_mask(struct intel_atomic_state *state) +{ + struct drm_device *dev = state->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + int ret; + u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask; + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points; + unsigned int mask = (1 << num_qgv_points) - 1; + + /* + * As we don't know initial hardware state during initial commit + * we should not do anything, until we actually figure out, + * what are the qgv points to mask. + */ + if (!new_mask) + return; + + WARN_ON(new_mask == mask); + + /* + * Just return if we can't control SAGV or don't have it. + */ + if (!intel_has_sagv(dev_priv)) + return; + + /* + * Restrict required qgv points before updating the configuration. + * According to BSpec we can't mask and unmask qgv points at the same + * time. Also masking should be done before updating the configuration + * and unmasking afterwards. + */ + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask); + if (ret < 0) + DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n", + ret); + else + dev_priv->qgv_points_mask = new_mask; +} + +static void intel_qgv_points_unmask(struct intel_atomic_state *state) +{ + struct drm_device *dev = state->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + int ret; + u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask; + + /* + * As we don't know initial hardware state during initial commit + * we should not do anything, until we actually figure out, + * what are the qgv points to mask. + */ + if (!new_mask) + return; + + /* + * Just return if we can't control SAGV or don't have it. + */ + if (!intel_has_sagv(dev_priv)) + return; + + /* + * Allow required qgv points after updating the configuration. + * According to BSpec we can't mask and unmask qgv points at the same + * time. Also masking should be done before updating the configuration + * and unmasking afterwards. + */ + ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask); + if (ret < 0) + DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n", + ret); + else + dev_priv->qgv_points_mask = new_mask; +} + static void intel_atomic_commit_tail(struct intel_atomic_state *state) { struct drm_device *dev = state->base.dev; @@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } } + if ((INTEL_GEN(dev_priv) >= 11)) + intel_qgv_points_mask(state); + intel_commit_modeset_disables(state); /* FIXME: Eventually get rid of our crtc->config pointer */ @@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * SKL workaround: bspec recommends we disable the SAGV when we * have more then one pipe enabled */ - if (!intel_can_enable_sagv(state)) - intel_disable_sagv(dev_priv); + if (INTEL_GEN(dev_priv) < 11) + if (!intel_can_enable_sagv(state)) + intel_disable_sagv(dev_priv); intel_modeset_verify_disabled(dev_priv, state); } @@ -14883,8 +14961,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) intel_verify_planes(state); - if (state->modeset && intel_can_enable_sagv(state)) - intel_enable_sagv(dev_priv); + if (INTEL_GEN(dev_priv) < 11) { + if (state->modeset && intel_can_enable_sagv(state)) + intel_enable_sagv(dev_priv); + } else + intel_qgv_points_unmask(state); drm_atomic_helper_commit_hw_done(&state->base); @@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct drm_device *dev, intel_shared_dpll_swap_state(state); intel_atomic_track_fbs(state); - if (state->global_state_changed) { + if (state->global_state_changed && state->modeset) { assert_global_state_locked(dev_priv); memcpy(dev_priv->min_cdclk, state->min_cdclk, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6a300cac883f..3535857dfed2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -534,6 +534,9 @@ struct intel_atomic_state { struct i915_sw_fence commit_ready; struct llist_node freed; + + /* Gen11+ only */ + u32 qgv_points_mask; }; struct intel_plane_state { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0ac9d7b006ca..54657b68010a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -850,6 +850,9 @@ enum intel_pipe_crc_source { INTEL_PIPE_CRC_SOURCE_MAX, }; +/* BSpec precisely defines this */ +#define NUM_SAGV_POINTS 8 + #define INTEL_PIPE_CRC_ENTRIES_NR 128 struct intel_pipe_crc { spinlock_t lock; @@ -1238,11 +1241,13 @@ struct drm_i915_private { } dram_info; struct intel_bw_info { - unsigned int deratedbw[3]; /* for each QGV point */ + unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */ u8 num_qgv_points; u8 num_planes; } max_bw[6]; + u32 qgv_points_mask; + struct drm_private_obj bw_obj; struct intel_runtime_pm runtime_pm; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a4e5a4ae3885..2ea83ff681b9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8981,6 +8981,8 @@ enum { #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF #define GEN7_PCODE_TIMEOUT 0x2 #define GEN7_PCODE_ILLEGAL_DATA 0x3 +#define GEN11_PCODE_MAIL_BOX_LOCKED 0x6 +#define GEN11_PCODE_REJECTED 0x11 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 #define GEN6_PCODE_READ_RC6VIDS 0x5 @@ -9002,6 +9004,7 @@ enum { #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 @@ -9014,6 +9017,8 @@ enum { #define GEN9_SAGV_IS_DISABLED 0x1 #define GEN9_SAGV_ENABLE 0x3 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 +#define GEN11_PCODE_POINTS_RESTRICTED 0x0 +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1 #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index e06b35b844a0..ff9dbed094d8 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox) } } +static inline int gen11_check_mailbox_status(u32 mbox) +{ + switch (mbox & GEN6_PCODE_ERROR_MASK) { + case GEN6_PCODE_SUCCESS: + return 0; + case GEN6_PCODE_ILLEGAL_CMD: + return -ENXIO; + case GEN7_PCODE_TIMEOUT: + return -ETIMEDOUT; + case GEN7_PCODE_ILLEGAL_DATA: + return -EINVAL; + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: + return -EOVERFLOW; + case GEN11_PCODE_MAIL_BOX_LOCKED: + return -EAGAIN; + case GEN11_PCODE_REJECTED: + return -EACCES; + default: + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK); + return 0; + } +} + static int __sandybridge_pcode_rw(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1, int fast_timeout_us, @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915, if (is_read && val1) *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1); - if (INTEL_GEN(i915) > 6) + if (INTEL_GEN(i915) >= 11) + return gen11_check_mailbox_status(mbox); + else if (INTEL_GEN(i915) > 6) return gen7_check_mailbox_status(mbox); else return gen6_check_mailbox_status(mbox);