From patchwork Sat Nov 16 00:52:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 11247403 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 241C41393 for ; Sat, 16 Nov 2019 00:52:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF4D920740 for ; Sat, 16 Nov 2019 00:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573865577; bh=ONcyJ//SGD1mZoiN15ibjsK1Ny7X1eS1qAreB943Snw=; h=From:To:Cc:Subject:Date:List-ID:From; b=xvVd/8YrZlqYRhZb5OIb9vA37waWFPFeMQo2CC3g0E6A2bsM8UfCEdAiqqTTjxKYn zzm9eCDoxpr035m/7THUynQshKG6a8gTilzrkzeT5c3eHQ7XXzpazkZwpk+4VIVlG8 uKojPjJtCsoWuiBGJchvsIcfYY6WoWeLgPNd2CnQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727275AbfKPAwn (ORCPT ); Fri, 15 Nov 2019 19:52:43 -0500 Received: from mail-oi1-f196.google.com ([209.85.167.196]:45062 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727112AbfKPAwn (ORCPT ); Fri, 15 Nov 2019 19:52:43 -0500 Received: by mail-oi1-f196.google.com with SMTP id 14so10233900oir.12; Fri, 15 Nov 2019 16:52:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=nWoMQ0paWOmaUsqalpGTNE9kf3zkQUzvDJAB/ODhtQI=; b=pWcYfcHehFfatfjpzjUhwdXkxX1SkDub3jrhghsQXkvRkodcXyv5A1ysH2nC3Di/09 PhI36FAfOFWmIYnSXmiyPfo/8vZsVseFOZdMChvAQccvlTSzA+H1gM6SU8YMm1fZaJee H9cbPEb9f7s0+BoANrB5syW3wPkLmziUs5ZWoheS3F8BCdQSfV09spGvnPDhuQyGkLlK 0b/orE0Ng51P/d13aeZxktQGrTBS8/FsZjdpoDJbVKxhkO5gr98FDmO4YkFzUUQdnWhq wmeI8mSSqFW6OIc5+etMa0hqO91VQj0G5f3GoddPCj9dgSSRghH7ybTl2oqgVCKTysli H9eQ== X-Gm-Message-State: APjAAAUyUivQiCEoRV1Lx/DlDZgjPs6TankHicUfTe5arPxcV7iSZiuD p943rUFs6W9LAtY6mB05pq7JRFc= X-Google-Smtp-Source: APXvYqxDPJ1BWP4pTS1D7z522kFc2WMxm7LqVnyyAdUsHtniQgmyyWk+hP4cf0Wf7J1GjpqUXNM68g== X-Received: by 2002:a05:6808:b1c:: with SMTP id s28mr9147959oij.12.1573865561362; Fri, 15 Nov 2019 16:52:41 -0800 (PST) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id g18sm3525680otg.50.2019.11.15.16.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 16:52:40 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Linus Walleij , Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray Subject: [PATCH 1/3] dt-bindings: PCI: Convert Arm Versatile binding to DT schema Date: Fri, 15 Nov 2019 18:52:38 -0600 Message-Id: <20191116005240.15722-1-robh@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the Arm Versatile PCI host binding to a DT schema. Cc: Linus Walleij Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Cc: Andrew Murray Signed-off-by: Rob Herring Acked-by: Linus Walleij --- .../devicetree/bindings/pci/versatile.txt | 59 ------------ .../devicetree/bindings/pci/versatile.yaml | 92 +++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 93 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/versatile.txt create mode 100644 Documentation/devicetree/bindings/pci/versatile.yaml diff --git a/Documentation/devicetree/bindings/pci/versatile.txt b/Documentation/devicetree/bindings/pci/versatile.txt deleted file mode 100644 index 0a702b13d2ac..000000000000 --- a/Documentation/devicetree/bindings/pci/versatile.txt +++ /dev/null @@ -1,59 +0,0 @@ -* ARM Versatile Platform Baseboard PCI interface - -PCI host controller found on the ARM Versatile PB board's FPGA. - -Required properties: -- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI - controller. -- reg: base addresses and lengths of the PCI controller. There must be 3 - entries: - - Versatile-specific registers - - Self Config space - - Config space -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- bus-range: set to <0 0xff> -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties to define - the mapping of the PCI interface to interrupt numbers. - -Example: - -pci-controller@10001000 { - compatible = "arm,versatile-pci"; - device_type = "pci"; - reg = <0x10001000 0x1000 - 0x41000000 0x10000 - 0x42000000 0x100000>; - bus-range = <0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */ - 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */ - 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ - - interrupt-map-mask = <0x1800 0 0 7>; - interrupt-map = <0x1800 0 0 1 &sic 28 - 0x1800 0 0 2 &sic 29 - 0x1800 0 0 3 &sic 30 - 0x1800 0 0 4 &sic 27 - - 0x1000 0 0 1 &sic 27 - 0x1000 0 0 2 &sic 28 - 0x1000 0 0 3 &sic 29 - 0x1000 0 0 4 &sic 30 - - 0x0800 0 0 1 &sic 30 - 0x0800 0 0 2 &sic 27 - 0x0800 0 0 3 &sic 28 - 0x0800 0 0 4 &sic 29 - - 0x0000 0 0 1 &sic 29 - 0x0000 0 0 2 &sic 30 - 0x0000 0 0 3 &sic 27 - 0x0000 0 0 4 &sic 28>; -}; diff --git a/Documentation/devicetree/bindings/pci/versatile.yaml b/Documentation/devicetree/bindings/pci/versatile.yaml new file mode 100644 index 000000000000..07a48c27db1f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/versatile.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/versatile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile Platform Baseboard PCI interface + +maintainers: + - Rob Herring + +description: |+ + PCI host controller found on the ARM Versatile PB board's FPGA. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: arm,versatile-pci + + reg: + items: + - description: Versatile-specific registers + - description: Self Config space + - description: Config space + + ranges: + maxItems: 3 + + "#interrupt-cells": true + + interrupt-map: + maxItems: 16 + + interrupt-map-mask: + items: + - const: 0x1800 + - const: 0 + - const: 0 + - const: 7 + +required: + - compatible + - reg + - ranges + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + +examples: + - | + pci@10001000 { + compatible = "arm,versatile-pci"; + device_type = "pci"; + reg = <0x10001000 0x1000>, + <0x41000000 0x10000>, + <0x42000000 0x100000>; + bus-range = <0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + ranges = + <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */ + <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */ + <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */ + + interrupt-map-mask = <0x1800 0 0 7>; + interrupt-map = <0x1800 0 0 1 &sic 28>, + <0x1800 0 0 2 &sic 29>, + <0x1800 0 0 3 &sic 30>, + <0x1800 0 0 4 &sic 27>, + + <0x1000 0 0 1 &sic 27>, + <0x1000 0 0 2 &sic 28>, + <0x1000 0 0 3 &sic 29>, + <0x1000 0 0 4 &sic 30>, + + <0x0800 0 0 1 &sic 30>, + <0x0800 0 0 2 &sic 27>, + <0x0800 0 0 3 &sic 28>, + <0x0800 0 0 4 &sic 29>, + + <0x0000 0 0 1 &sic 29>, + <0x0000 0 0 2 &sic 30>, + <0x0000 0 0 3 &sic 27>, + <0x0000 0 0 4 &sic 28>; + }; + + +... diff --git a/MAINTAINERS b/MAINTAINERS index c6c34d04ce95..48a90f0833b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12401,7 +12401,7 @@ M: Rob Herring L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org S: Maintained -F: Documentation/devicetree/bindings/pci/versatile.txt +F: Documentation/devicetree/bindings/pci/versatile.yaml F: drivers/pci/controller/pci-versatile.c PCI DRIVER FOR ARMADA 8K From patchwork Sat Nov 16 00:52:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 11247399 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 71BE413BD for ; Sat, 16 Nov 2019 00:52:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F07F20733 for ; Sat, 16 Nov 2019 00:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573865576; bh=w11hF+8S7RN0l7WYVfSo8S/6fdKgsmt2Asf8mJYJKzw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=A8oNBV2pbGqly2lBaZp4VrxqQIOSjVcha7oswVC7XDVYtOeDbz0Qr6YRsvkyzS8Zs 6gNaAAo1xbs8nqX4ucq/588LCVoEdoufo9rOsZG/LTX3Nw3+OT8XU4EwsIngye/Rfj ZsRiv0zdoI+BpA6jVdGAXFS5T02MBgBlnkSEcXL8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727325AbfKPAwo (ORCPT ); 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[24.155.109.49]) by smtp.googlemail.com with ESMTPSA id g18sm3525680otg.50.2019.11.15.16.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 16:52:41 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Alan Douglas , Scott Telford , Tom Joseph , Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray Subject: [PATCH 2/3] dt-bindings: PCI: Convert Cadence host to DT schema Date: Fri, 15 Nov 2019 18:52:39 -0600 Message-Id: <20191116005240.15722-2-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191116005240.15722-1-robh@kernel.org> References: <20191116005240.15722-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the Cadence PCIe host binding to DT schema. The 'phy-names' definition is incomplete. 'vendor-id' and 'device-id' aren't listed as those are standard PCI properties. They were incorrectly defined as 16-bit when they should be 32-bits (even though only 16-bits are used). 'cdns,max-outbound-regions' should really be removed. It serves no purpose other than bounds checking 'ranges'. If 'ranges' is wrong for the h/w, what's going to ensure 'cdns,max-outbound-regions' is correct. 'cdns,no-bar-match-nbits' is also suspect. This probably could be determined from 'dma-ranges' using the sizes. Cc: Alan Douglas Cc: Scott Telford Cc: Tom Joseph Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Cc: Andrew Murray Signed-off-by: Rob Herring --- .../bindings/pci/cdns,cdns-pcie-host.txt | 66 ----------- .../bindings/pci/cdns,cdns-pcie-host.yaml | 106 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 107 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt create mode 100644 Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt deleted file mode 100644 index 91de69c713a9..000000000000 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ /dev/null @@ -1,66 +0,0 @@ -* Cadence PCIe host controller - -This PCIe controller inherits the base properties defined in -host-generic-pci.txt. - -Required properties: -- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. -- reg: Should contain the controller register base address, PCIe configuration - window base address, and AXI interface region base address respectively. -- reg-names: Must be "reg", "cfg" and "mem" respectively. -- #address-cells: Set to <3> -- #size-cells: Set to <2> -- device_type: Set to "pci" -- ranges: Ranges for the PCI memory and I/O regions -- #interrupt-cells: Set to <1> -- interrupt-map-mask and interrupt-map: Standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers. - -Optional properties: -- cdns,max-outbound-regions: Set to maximum number of outbound regions - (default 32) -- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the - number of least significant bits kept during inbound (PCIe -> AXI) address - translations (default 32) -- vendor-id: The PCI vendor ID (16 bits, default is design dependent) -- device-id: The PCI device ID (16 bits, default is design dependent) -- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more - than one in the list. If only one PHY listed it must manage all lanes. -- phy-names: List of names to identify the PHY. - -Example: - -pcie@fb000000 { - compatible = "cdns,cdns-pcie-host"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; - vendor-id = /bits/ 16 <0x17cd>; - device-id = /bits/ 16 <0x0200>; - - reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; - - ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, - <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; - - #interrupt-cells = <0x1>; - - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; - - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - - msi-parent = <&its_pci>; - - phys = <&pcie_phy0>; - phy-names = "pcie-phy"; -}; diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml new file mode 100644 index 000000000000..ada77e267b68 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence PCIe host controller + +maintainers: + - Alan Douglas + - Scott Telford + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: cdns,cdns-pcie-host + + reg: + maxItems: 3 + + reg-names: + items: + - const: reg + - const: cfg + - const: mem + + cdns,max-outbound-regions: + description: maximum number of outbound regions + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + + cdns,no-bar-match-nbits: + description: + Set into the no BAR match register to configure the number of least + significant bits kept during inbound (PCIe -> AXI) address translations + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + default: 32 + + msi-parent: true + + phys: + description: + One per lane if more than one in the list. If only one PHY listed it must + manage all lanes. + minItems: 1 + maxItems: 16 + + phy-names: + items: + - const: pcie-phy + # FIXME: names when more than 1 + +required: + - reg + - reg-names + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@fb000000 { + compatible = "cdns,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = /bits/ 16 <0x17cd>; + device-id = /bits/ 16 <0x0200>; + + reg = <0x0 0xfb000000 0x0 0x01000000>, + <0x0 0x41000000 0x0 0x00001000>, + <0x0 0x40000000 0x0 0x04000000>; + reg-names = "reg", "cfg", "mem"; + + ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, + <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + + #interrupt-cells = <0x1>; + + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + + msi-parent = <&its_pci>; + + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 48a90f0833b8..21f3393c36e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12416,7 +12416,7 @@ PCI DRIVER FOR CADENCE PCIE IP M: Tom Joseph L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/cdns,*.txt +F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/pcie-cadence* PCI DRIVER FOR FREESCALE LAYERSCAPE From patchwork Sat Nov 16 00:52:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 11247401 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98B6414ED for ; Sat, 16 Nov 2019 00:52:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7060D2073C for ; Sat, 16 Nov 2019 00:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573865576; bh=WStutCMUfiDRt9iRoF80eNCumZHsKvjOsRHUNt+AitY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=tN5uPvzFMluRqJOjquL7EL13iAby7loobYnccVsQ0LB5kKdb/P77132asHmChljnD xGdofWyqgnAX9sV0dA/ErGS4WsNtAtgzWhhHnP0ya2amCJljgpzHa0PQgz1O3+JrBy Gidi8PfzyYbZI5mj36TZYn9/vyZgxN2VAHtIIyLw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727365AbfKPAwp (ORCPT ); Fri, 15 Nov 2019 19:52:45 -0500 Received: from mail-ot1-f65.google.com ([209.85.210.65]:38395 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727361AbfKPAwp (ORCPT ); Fri, 15 Nov 2019 19:52:45 -0500 Received: by mail-ot1-f65.google.com with SMTP id z25so9601200oti.5; Fri, 15 Nov 2019 16:52:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QiZWV9+TKcIvaa+QbP2SeO8UjexKrCZpIntBA+lfA0E=; b=sDLhbsa55udlhY656H66v1ZJy07DkbwIk/PgIWi490+IRiUfR0PC4qcUT5TO+TQy4F 5S0RjPV/O0WKwFwllkEpwbzfJ3akvt49YIlnE4JNyxSMRiRjkqLogSo+nCq8DmxiGgmy kPmcI3nwZAbnf/MJnJq481yMHqOdHb2B6DQ/1F/oZxENmDqM7jkaX4tiJSNhE6A4pEmt YCdGHPVIFQfK/dEVaRY8pK6REg2zxvDrhd27EWrfbCnJKhbYO8orgo0NCkEfQKm30JH5 /ocVvXuwgCH/pLhex7uL8uQpVUTKKh/kVBm7OllCJmDTTR8OI0PfOgOhxLb497s8h7Og A75w== X-Gm-Message-State: APjAAAX5WVjPR9CL4dKXPIFibTs+Iz8ji9hWrcx07O/a+1Y97hZpQYsI Rvc4/OChxo7kLNGCH2URAVm2h48= X-Google-Smtp-Source: APXvYqxw5BsBMu3h7fAuw5plahHWVntkiS+sPpbeUOhyxemqnl9wrXQmNx7BNWol13upwftpoBICvw== X-Received: by 2002:a9d:1b01:: with SMTP id l1mr2862145otl.141.1573865563474; Fri, 15 Nov 2019 16:52:43 -0800 (PST) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id g18sm3525680otg.50.2019.11.15.16.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 16:52:42 -0800 (PST) From: Rob Herring To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray , Zhou Wang , Will Deacon , David Daney Subject: [PATCH 3/3] dt-bindings: PCI: Convert generic host binding to DT schema Date: Fri, 15 Nov 2019 18:52:40 -0600 Message-Id: <20191116005240.15722-3-robh@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191116005240.15722-1-robh@kernel.org> References: <20191116005240.15722-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema. Cc: Bjorn Helgaas Cc: Lorenzo Pieralisi Cc: Andrew Murray Cc: Zhou Wang Cc: Will Deacon Cc: David Daney Signed-off-by: Rob Herring --- .../bindings/pci/arm,juno-r1-pcie.txt | 10 -- .../bindings/pci/designware-pcie-ecam.txt | 42 ----- .../bindings/pci/hisilicon-pcie.txt | 4 +- .../bindings/pci/host-generic-pci.txt | 101 ------------ .../bindings/pci/host-generic-pci.yaml | 150 ++++++++++++++++++ .../bindings/pci/pci-thunder-ecam.txt | 30 ---- .../bindings/pci/pci-thunder-pem.txt | 7 +- .../bindings/pci/plda,xpressrich3-axi.txt | 12 -- MAINTAINERS | 2 +- 9 files changed, 155 insertions(+), 203 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt diff --git a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt b/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt deleted file mode 100644 index f7514c170a32..000000000000 --- a/Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt +++ /dev/null @@ -1,10 +0,0 @@ -* ARM Juno R1 PCIe interface - -This PCIe host controller is based on PLDA XpressRICH3-AXI IP -and thus inherits all the common properties defined in plda,xpressrich3-axi.txt -as well as the base properties defined in host-generic-pci.txt. - -Required properties: - - compatible: "arm,juno-r1-pcie" - - dma-coherent: The host controller bridges the AXI transactions into PCIe bus - in a manner that makes the DMA operations to appear coherent to the CPUs. diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted file mode 100644 index 515b2f9542e5..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Synopsys DesignWare PCIe root complex in ECAM shift mode - -In some cases, firmware may already have configured the Synopsys DesignWare -PCIe controller in RC mode with static ATU window mappings that cover all -config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. -In this case, there is no need for the OS to perform any low level setup -of clocks, PHYs or device registers, nor is there any reason for the driver -to reconfigure ATU windows for config and/or IO space accesses at runtime. - -In cases where the IP was synthesized with a minimum ATU window size of -64 KB, it cannot be supported by the generic ECAM driver, because it -requires special config space accessors that filter accesses to device #1 -and beyond on the first bus. - -Required properties: -- compatible: "marvell,armada8k-pcie-ecam" or - "socionext,synquacer-pcie-ecam" or - "snps,dw-pcie-ecam" (must be preceded by a more specific match) - -Please refer to the binding document of "pci-host-ecam-generic" in the -file host-generic-pci.txt for a description of the remaining required -and optional properties. - -Example: - - pcie1: pcie@7f000000 { - compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; - device_type = "pci"; - reg = <0x0 0x7f000000 0x0 0xf00000>; - bus-range = <0x0 0xe>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, - <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, - <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; - - #interrupt-cells = <0x1>; - interrupt-map-mask = <0x0 0x0 0x0 0x0>; - interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; - msi-map = <0x0 &its 0x0 0x10000>; - dma-coherent; - }; diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index 0dcb87d6554f..adf66a26b70b 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -49,10 +49,10 @@ compliant for all devices other than the root complex. In such cases, the host controller should be described as below. The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. +host-generic-pci.yaml except as listed below. Properties of the host controller node that differ from -host-generic-pci.txt: +host-generic-pci.yaml: - compatible : Must be "hisilicon,hip06-pcie-ecam", or "hisilicon,hip07-pcie-ecam" diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt deleted file mode 100644 index 614b594f4e72..000000000000 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ /dev/null @@ -1,101 +0,0 @@ -* Generic PCI host controller - -Firmware-initialised PCI host controllers and PCI emulations, such as the -virtio-pci implementations found in kvmtool and other para-virtualised -systems, do not require driver support for complexities such as regulator -and clock management. In fact, the controller may not even require the -configuration of a control interface by the operating system, instead -presenting a set of fixed windows describing a subset of IO, Memory and -Configuration Spaces. - -Such a controller can be described purely in terms of the standardized device -tree bindings communicated in pci.txt: - - -Properties of the host controller node: - -- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic" - depending on the layout of configuration space (CAM vs - ECAM respectively). - -- device_type : Must be "pci". - -- ranges : As described in IEEE Std 1275-1994, but must provide - at least a definition of non-prefetchable memory. One - or both of prefetchable Memory and IO Space may also - be provided. - -- bus-range : Optional property (also described in IEEE Std 1275-1994) - to indicate the range of bus numbers for this controller. - If absent, defaults to <0 255> (i.e. all buses). - -- #address-cells : Must be 3. - -- #size-cells : Must be 2. - -- reg : The Configuration Space base address and size, as accessed - from the parent bus. The base address corresponds to - the first bus in the "bus-range" property. If no - "bus-range" is specified, this will be bus 0 (the default). - -Properties of the /chosen node: - -- linux,pci-probe-only - : Optional property which takes a single-cell argument. - If '0', then Linux will assign devices in its usual manner, - otherwise it will not try to assign devices and instead use - them as they are configured already. - -Configuration Space is assumed to be memory-mapped (as opposed to being -accessed via an ioport) and laid out with a direct correspondence to the -geography of a PCI bus address by concatenating the various components to -form an offset. - -For CAM, this 24-bit offset is: - - cfg_offset(bus, device, function, register) = - bus << 16 | device << 11 | function << 8 | register - -While ECAM extends this by 4 bits to accommodate 4k of function space: - - cfg_offset(bus, device, function, register) = - bus << 20 | device << 15 | function << 12 | register - -Interrupt mapping is exactly as described in `Open Firmware Recommended -Practice: Interrupt Mapping' and requires the following properties: - -- #interrupt-cells : Must be 1 - -- interrupt-map : - -- interrupt-map-mask : - - -Example: - -pci { - compatible = "pci-host-cam-generic" - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0x1>; - - // CPU_PHYSICAL(2) SIZE(2) - reg = <0x0 0x40000000 0x0 0x1000000>; - - // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) - ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, - <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; - - - #interrupt-cells = <0x1>; - - // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) - interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1 - 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1 - 0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1 - 0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; - - // PCI_DEVICE(3) INT#(1) - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; -} diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file mode 100644 index 000000000000..7c3f3b2bdd57 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic PCI host controller + +maintainers: + - Will Deacon + +description: | + Firmware-initialised PCI host controllers and PCI emulations, such as the + virtio-pci implementations found in kvmtool and other para-virtualised + systems, do not require driver support for complexities such as regulator + and clock management. In fact, the controller may not even require the + configuration of a control interface by the operating system, instead + presenting a set of fixed windows describing a subset of IO, Memory and + Configuration Spaces. + + Configuration Space is assumed to be memory-mapped (as opposed to being + accessed via an ioport) and laid out with a direct correspondence to the + geography of a PCI bus address by concatenating the various components to + form an offset. + + For CAM, this 24-bit offset is: + + cfg_offset(bus, device, function, register) = + bus << 16 | device << 11 | function << 8 | register + + While ECAM extends this by 4 bits to accommodate 4k of function space: + + cfg_offset(bus, device, function, register) = + bus << 20 | device << 15 | function << 12 | register + + Interrupt mapping is exactly as described in `Open Firmware Recommended + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + description: Depends on the layout of configuration space (CAM vs ECAM + respectively). May also have more specific compatibles. + anyOf: + - description: + PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP + items: + - const: arm,juno-r1-pcie + - const: plda,xpressrich3-axi + - const: pci-host-ecam-generic + - description: | + ThunderX PCI host controller for pass-1.x silicon + + Firmware-initialized PCI host controller to on-chip devices found on + some Cavium ThunderX processors. These devices have ECAM-based config + access, but the BARs are all at fixed addresses. We handle the fixed + addresses by synthesizing Enhanced Allocation (EA) capabilities for + these devices. + const: cavium,pci-host-thunder-ecam + - description: | + In some cases, firmware may already have configured the Synopsys + DesignWare PCIe controller in RC mode with static ATU window mappings + that cover all config, MMIO and I/O spaces in a [mostly] ECAM + compatible fashion. In this case, there is no need for the OS to + perform any low level setup of clocks, PHYs or device registers, nor + is there any reason for the driver to reconfigure ATU windows for + config and/or IO space accesses at runtime. + + In cases where the IP was synthesized with a minimum ATU window size + of 64 KB, it cannot be supported by the generic ECAM driver, because + it requires special config space accessors that filter accesses to + device #1 and beyond on the first bus. + items: + - enum: + - marvell,armada8k-pcie-ecam + - socionext,synquacer-pcie-ecam + - const: snps,dw-pcie-ecam + - contains: + enum: + - pci-host-cam-generic + - pci-host-ecam-generic + + reg: + description: + The Configuration Space base address and size, as accessed from the parent + bus. The base address corresponds to the first bus in the "bus-range" + property. If no "bus-range" is specified, this will be bus 0 (the + default). + maxItems: 1 + + ranges: + description: + As described in IEEE Std 1275-1994, but must provide at least a + definition of non-prefetchable memory. One or both of prefetchable Memory + and IO Space may also be provided. + minItems: 1 + maxItems: 3 + + dma-coherent: + description: The host controller bridges the AXI transactions into PCIe bus + in a manner that makes the DMA operations to appear coherent to the CPUs. + +required: + - compatible + - reg + - ranges + +if: + properties: + compatible: + contains: + const: arm,juno-r1-pcie +then: + required: + - dma-coherent + +examples: + - | + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie@40000000 { + compatible = "pci-host-cam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x0 0x40000000 0x0 0x1000000>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>, + <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>; + + #interrupt-cells = <0x1>; + + // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3) + interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>, + < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>, + <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>, + <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>; + + // PCI_DEVICE(3) INT#(1) + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt b/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt deleted file mode 100644 index f478874b79ce..000000000000 --- a/Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt +++ /dev/null @@ -1,30 +0,0 @@ -* ThunderX PCI host controller for pass-1.x silicon - -Firmware-initialized PCI host controller to on-chip devices found on -some Cavium ThunderX processors. These devices have ECAM-based config -access, but the BARs are all at fixed addresses. We handle the fixed -addresses by synthesizing Enhanced Allocation (EA) capabilities for -these devices. - -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: - -- compatible : Must be "cavium,pci-host-thunder-ecam" - -Example: - - pcie@84b000000000 { - compatible = "cavium,pci-host-thunder-ecam"; - device_type = "pci"; - msi-parent = <&its>; - msi-map = <0 &its 0x30000 0x10000>; - bus-range = <0 31>; - #size-cells = <2>; - #address-cells = <3>; - #stream-id-cells = <1>; - reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */ - ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */ - }; diff --git a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt index f131faea3b7c..f3c87d55753b 100644 --- a/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt +++ b/Documentation/devicetree/bindings/pci/pci-thunder-pem.txt @@ -3,11 +3,8 @@ Firmware-initialized PCI host controller found on some Cavium ThunderX processors. -The properties and their meanings are identical to those described in -host-generic-pci.txt except as listed below. - -Properties of the host controller node that differ from -host-generic-pci.txt: +In addition to standard PCI host bridge properties, the following properties +are required: - compatible : Must be "cavium,pci-host-thunder-pem" diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt deleted file mode 100644 index f3f75bfb42bc..000000000000 --- a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt +++ /dev/null @@ -1,12 +0,0 @@ -* PLDA XpressRICH3-AXI host controller - -The PLDA XpressRICH3-AXI host controller can be configured in a manner that -makes it compliant with the SBSA[1] standard published by ARM Ltd. For those -scenarios, the host-generic-pci.txt bindings apply with the following additions -to the compatible property: - -Required properties: - - compatible: should contain "plda,xpressrich3-axi" to identify the IP used. - - -[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/ diff --git a/MAINTAINERS b/MAINTAINERS index 21f3393c36e3..3a5ddc0d530c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12434,7 +12434,7 @@ M: Will Deacon L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/pci/host-generic-pci.txt +F: Documentation/devicetree/bindings/pci/host-generic-pci.yaml F: drivers/pci/controller/pci-host-common.c F: drivers/pci/controller/pci-host-generic.c