From patchwork Sun Nov 17 13:59:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248393 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C82914ED for ; Sun, 17 Nov 2019 14:00:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4CDC620850 for ; Sun, 17 Nov 2019 14:00:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="DjU0C/ID" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726102AbfKQN77 (ORCPT ); Sun, 17 Nov 2019 08:59:59 -0500 Received: from mail-wr1-f53.google.com ([209.85.221.53]:44952 "EHLO mail-wr1-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726037AbfKQN77 (ORCPT ); Sun, 17 Nov 2019 08:59:59 -0500 Received: by mail-wr1-f53.google.com with SMTP id f2so16350600wrs.11; Sun, 17 Nov 2019 05:59:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AI7oneBVr9Sh8KI/EU2QuzQzAJVjV4haI51WvzEvAjc=; b=DjU0C/ID1NfUiIWc88ECCm8hYmVDymKmODomd9NlTEsQA8kBmsbs9Yaj+kV6+S3A5Y cVEOSM45iyG8La96kCE9baDwHRe7utZmIwOLfBjEvaTeUIvE5zqLB02xRFbOfu2VCHU8 dSreasOblG5NC6BNBkl60rb8ag1Et8+4ALPBseCMh438x6pL4cnq9B/li7a9Ss5gfygZ SgnQxzr7dY1oFI26nE4jTwDuvXdIyYdjNLcMhNr4pTdUXSMwE7IfUzkVgkjtKrLpscEL xeru+GS5Jn/GLwnLZdcdvCOH4y70Yvft70eW4Y1ZXWfkp5kmSZrEWNiLBHGLU6CyZMrG 6OLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AI7oneBVr9Sh8KI/EU2QuzQzAJVjV4haI51WvzEvAjc=; b=bZMPBcxaHd2eAENk6IlqugwNl2okQXR7CU0kiIKZxantIJArxFyABQ5nloAX6hDtyi scFS1BYZEWUY90lYZeecepgpMUCPj+dGWuzDDiqyxSZh2DFXEfQUhM00ABnDzNBSGC5l 1MeLnipzDnL46Xmq4XCwXGmZT7EfwwO9A2K/UmGAO2fBSmrCj3gUcCff7JVLVLQH68Xk M6D4EQ918ezqGeAE4s0XWRe4i3SjBtwv6eu+tKlb3Ete78x3Rawz8sG/zg8GNNmBjhjK QQO/5onyzGW0BGJ/YdKYpYA6SJIdPs4NzfGPpNOWWd6ab3IWQBZ00BdKvCLd1JARoYdl afDQ== X-Gm-Message-State: APjAAAVMjwGNF3MXgozyNc2uLTxNNOdWFIA6taxBhejk8bZN2N22RYYV dkZaa/dwKCHWh7yI3ZhXFaI= X-Google-Smtp-Source: APXvYqxuh9+V3F0zaSkPtijZBTMVQwPp1ojlde26tDjEtxtx16d/NlKmKiJeZpZDN+YTugtSvMi/+A== X-Received: by 2002:a5d:42c8:: with SMTP id t8mr20309817wrr.87.1573999196558; Sun, 17 Nov 2019 05:59:56 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n65sm18004803wmf.28.2019.11.17.05.59.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 05:59:56 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl , Rob Herring Subject: [PATCH v3 1/5] dt-bindings: clock: meson8b: add the clock inputs Date: Sun, 17 Nov 2019 14:59:23 +0100 Message-Id: <20191117135927.135428-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> References: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Reviewed-by: Rob Herring Signed-off-by: Martin Blumenstingl --- .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index 4d94091c1d2d..cc51e4746b3b 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -11,6 +11,11 @@ Required Properties: - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs - #clock-cells: should be 1. - #reset-cells: should be 1. +- clocks: list of clock phandles, one for each entry in clock-names +- clock-names: should contain the following: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) Parent node should have the following properties : - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" From patchwork Sun Nov 17 13:59:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248387 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CE481393 for ; Sun, 17 Nov 2019 14:00:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0D39620740 for ; Sun, 17 Nov 2019 14:00:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="Ci1s6DmF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726234AbfKQOAA (ORCPT ); Sun, 17 Nov 2019 09:00:00 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:32796 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726069AbfKQN77 (ORCPT ); Sun, 17 Nov 2019 08:59:59 -0500 Received: by mail-wr1-f68.google.com with SMTP id w9so16397827wrr.0; Sun, 17 Nov 2019 05:59:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wYheJOg1NZzECr658le7NqXjuqImUz/Kw+GoeDiCAg0=; b=Ci1s6DmFUtw7M7Vs9pzJsGsOCzUinirsXZj6J48Hg0YKhROz57Hk+s2q26eJHg/1wV Lxr97WsLsrpsjq4IftTRlxBdkWZFGdlywbdBYglWo7hZUsHJQtv3K0+dONSpIDEiZ8dR xXIhJc+PuHWryoprmGQbzxZuys59fqmsUhvHIPjImnGbMw6LSPUNGeci0fY/V8wbVkJu LsRdB2CI547U+UWOPQhbVuLQ0enwHFK3UfxmVWA2DNyBmTRVQigHVdBFzOJX1mUHd0kI 4dx1U0yy8uq1NXaQxMAYJbyRlhXkk7ilZtwuJ021OnjnM5Mc2zVNwofMuS53WMtSzfAb ZsPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wYheJOg1NZzECr658le7NqXjuqImUz/Kw+GoeDiCAg0=; b=m7mnupKcweuCLLqDfiBEefmaL7eykZJ2CR61+6RO8BVFYpjKZPMOhu4jnhuY0TRLx8 RDu5ImSQbJbmO3nTpYvQKbctNL3ifpfWIgUTJyl5zf6m1EZbCH41oWxjK/iLM6fqCoEj i0G5nDJCInWleFvV8gVMaoQ+iiXnRiSy3SZdgAQ43kxqNewvCJs8qrkrETz7FE0TvBI6 hhRxABVsI8NSKrjOuQOcZ1A7cgCU4ArMn1WB6DYVjW1nmQJhVJaPNNE8dnPf5W3abx+W r+2aBJb/gxLxT1nEhDndNNKAbnsBC/jCPAXsDWONiqIQcaDPtZhIH7QabIhmLYhuvPTp IUZg== X-Gm-Message-State: APjAAAWl+qYUWlFzAiqXskxk0UdG2dDHll2kbnnSyLbgyYJEmDIHiEIj VwGcRW/7LWbwGcGnypPkwMU= X-Google-Smtp-Source: APXvYqzuRu/LHBhYR7+sZR5cemFrtpnOuzCWp3HT/9ni5iw/xVQKsmBZEyrmCCUYY4F2wIxyjxefCQ== X-Received: by 2002:adf:c50a:: with SMTP id q10mr26940232wrf.374.1573999197651; Sun, 17 Nov 2019 05:59:57 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n65sm18004803wmf.28.2019.11.17.05.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 05:59:57 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v3 2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier Date: Sun, 17 Nov 2019 14:59:24 +0100 Message-Id: <20191117135927.135428-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> References: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Switch from clk_set_parent() to clk_hw_set_parent() now that we have a way to configure a mux clock based on clk_hw pointers. This simplifies the meson8b_cpu_clk_notifier_cb logic. No functional changes. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 67e6691e080c..d376f80e806d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3585,7 +3585,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = { struct meson8b_nb_data { struct notifier_block nb; - struct clk_hw_onecell_data *onecell_data; + struct clk_hw *cpu_clk; }; static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, @@ -3593,30 +3593,25 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb, { struct meson8b_nb_data *nb_data = container_of(nb, struct meson8b_nb_data, nb); - struct clk_hw **hws = nb_data->onecell_data->hws; - struct clk_hw *cpu_clk_hw, *parent_clk_hw; - struct clk *cpu_clk, *parent_clk; + struct clk_hw *parent_clk; int ret; switch (event) { case PRE_RATE_CHANGE: - parent_clk_hw = hws[CLKID_XTAL]; + /* xtal */ + parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); break; case POST_RATE_CHANGE: - parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL]; + /* cpu_scale_out_sel */ + parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); break; default: return NOTIFY_DONE; } - cpu_clk_hw = hws[CLKID_CPUCLK]; - cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw)); - - parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw)); - - ret = clk_set_parent(cpu_clk, parent_clk); + ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); if (ret) return notifier_from_errno(ret); @@ -3695,7 +3690,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } - meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data; + meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK]; /* * FIXME we shouldn't program the muxes in notifier handlers. The From patchwork Sun Nov 17 13:59:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248383 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E365159A for ; Sun, 17 Nov 2019 14:00:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4BE1E2088F for ; Sun, 17 Nov 2019 14:00:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="uX3kkks5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726273AbfKQOAD (ORCPT ); Sun, 17 Nov 2019 09:00:03 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:35272 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726069AbfKQOAC (ORCPT ); Sun, 17 Nov 2019 09:00:02 -0500 Received: by mail-wm1-f68.google.com with SMTP id 8so15870245wmo.0; Sun, 17 Nov 2019 05:59:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VK1JO8dp501rCEWUDhaKb+5p4cyh/6ctrMeXSGi6/vI=; b=uX3kkks5u09MSU6+9FB6NjV7WG1co9tZzINsNjFFrAuUPaeY/LpqjaxYBKw1rgs2ci AtRVoMgC/7mQXqQaxeNAjmEBgaq8AlfvbgG6GN17hSWOKG8XpuN9qVxgbaGXLMMjmWG9 T9UlDdy5XnqdavAM+l6CY+nHHTMpTnCfwXb9P0s0kSycGW3T8J9W3ppong8i+YvXPvio 9pu2FQpHTpOYG3YHJWhg37Pe5S9Ty03Z6WAz0fqMWszAFPYokzm1iqPTUWD9Jy1hBZx/ F++OWtatB0jXOEZMXmS3MlK2rkhcjPH4o/LTvaHQko2TRMyVwf8QZcOgydXrTP90crJK X2VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VK1JO8dp501rCEWUDhaKb+5p4cyh/6ctrMeXSGi6/vI=; b=VTqt8O9qFzx+EH+0E5EMJL/SE98F0+HtB8rgByIvDFkOEFHni5MSN0Q4Ee08/8WIBo LnTOX5T4jNltgYwyH88bo0SggpATU8mqxfy7MdN0oRKCfXJmJdVjSHp62BTpbWXKIFRP YiEEYqceY7HtxIoUHeqIs7ZhG1Q4jCX7wQOQmc2+uLcbQdDkQAI3mUn/bkfyP1P9eVSU AAE5VsuIjX3/Yj/MUfj7ifAOaMdFRiuCjiDBSGmAt1iZf9HWbwpmyoOVxNOTsd0E/vZH KJBRgOQeyy399P78v2L3DQuDRfsUL3fGZV+LjNV4GrLAke/P2w1ddQzxGpvr3gMUq+rk SjnQ== X-Gm-Message-State: APjAAAW+n4ailROEncf2lgCHvw0UZsCbfGyMHJG9OIj2Am0NrvyES+QW QgnSx/M+djhRI2U05xhAd4s= X-Google-Smtp-Source: APXvYqz2ho4QekV3NNoeQpC90s5YyGanfRKJwSw4FD4KLJzoleyj2nZK5zI9GOyuKLXdGsv2ZtMcOg== X-Received: by 2002:a05:600c:21d5:: with SMTP id x21mr19273737wmj.162.1573999198652; Sun, 17 Nov 2019 05:59:58 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n65sm18004803wmf.28.2019.11.17.05.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 05:59:58 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v3 3/5] clk: meson: meson8b: change references to the XTAL clock to use [fw_]name Date: Sun, 17 Nov 2019 14:59:25 +0100 Message-Id: <20191117135927.135428-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> References: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The XTAL clock is an actual crystal which is mounted on the PCB. Thus the meson8b clock controller driver should not provide the XTAL clock. The meson8b clock controller driver must not use references to the meson8b_xtal clock anymore before we can provide the XTAL clock via OF. Replace the references to the meson8b_xtal.hw by using clk_parent_data's .fw_name and .name = "xtal" (along with index = -1). This makes the common clock framework use the clock provided via OF and if that's not available it falls back to getting the clock by it's name (which is then the clk_fixed_rate which we register in our driver). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 78 +++++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 34 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d376f80e806d..f857a2c4d025 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -97,8 +97,10 @@ static struct clk_regmap meson8b_fixed_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "fixed_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -162,8 +164,10 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { /* sometimes also called "HPLL" or "HPLL PLL" */ .name = "hdmi_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -237,8 +241,10 @@ static struct clk_regmap meson8b_sys_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "sys_pll_dco", .ops = &meson_clk_pll_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .name = "xtal", + .index = -1, }, .num_parents = 1, }, @@ -631,9 +637,9 @@ static struct clk_regmap meson8b_cpu_in_sel = { .hw.init = &(struct clk_init_data){ .name = "cpu_in_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw, - &meson8b_sys_pll.hw, + .parent_data = (const struct clk_parent_data[]) { + { .fw_name = "xtal", .name = "xtal", .index = -1, }, + { .hw = &meson8b_sys_pll.hw, }, }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | @@ -736,9 +742,9 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name = "cpu_clk", .ops = &clk_regmap_mux_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw, - &meson8b_cpu_scale_out_sel.hw, + .parent_data = (const struct clk_parent_data[]) { + { .fw_name = "xtal", .name = "xtal", .index = -1, }, + { .hw = &meson8b_cpu_scale_out_sel.hw, }, }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | @@ -758,12 +764,12 @@ static struct clk_regmap meson8b_nand_clk_sel = { .name = "nand_clk_sel", .ops = &clk_regmap_mux_ops, /* FIXME all other parents are unknown: */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, - &meson8b_fclk_div7.hw, - &meson8b_xtal.hw, + .parent_data = (const struct clk_parent_data[]) { + { .hw = &meson8b_fclk_div4.hw, }, + { .hw = &meson8b_fclk_div3.hw, }, + { .hw = &meson8b_fclk_div5.hw, }, + { .hw = &meson8b_fclk_div7.hw, }, + { .fw_name = "xtal", .name = "xtal", .index = -1, }, }, .num_parents = 5, .flags = CLK_SET_RATE_PARENT, @@ -1721,8 +1727,10 @@ static struct clk_regmap meson8b_hdmi_sys_sel = { .name = "hdmi_sys_sel", .ops = &clk_regmap_mux_ro_ops, /* FIXME: all other parents are unknown */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .name = "xtal", + .index = -1, }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -1767,14 +1775,14 @@ static struct clk_regmap meson8b_hdmi_sys = { * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only * has mali_0 and no glitch-free mux. */ -static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = { - &meson8b_xtal.hw, - &meson8b_mpll2.hw, - &meson8b_mpll1.hw, - &meson8b_fclk_div7.hw, - &meson8b_fclk_div4.hw, - &meson8b_fclk_div3.hw, - &meson8b_fclk_div5.hw, +static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = { + { .fw_name = "xtal", .name = "xtal", .index = -1, }, + { .hw = &meson8b_mpll2.hw, }, + { .hw = &meson8b_mpll1.hw, }, + { .hw = &meson8b_fclk_div7.hw, }, + { .hw = &meson8b_fclk_div4.hw, }, + { .hw = &meson8b_fclk_div3.hw, }, + { .hw = &meson8b_fclk_div5.hw, }, }; static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; @@ -1789,8 +1797,8 @@ static struct clk_regmap meson8b_mali_0_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_mali_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws), + .parent_data = meson8b_mali_0_1_parent_data, + .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1844,8 +1852,8 @@ static struct clk_regmap meson8b_mali_1_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_mali_0_1_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws), + .parent_data = meson8b_mali_0_1_parent_data, + .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data), /* * Don't propagate rate changes up because the only changeable * parents are mpll1 and mpll2 but we need those for audio and @@ -1944,8 +1952,10 @@ static struct clk_regmap meson8m2_gp_pll_dco = { .hw.init = &(struct clk_init_data){ .name = "gp_pll_dco", .ops = &meson_clk_pll_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_xtal.hw + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .name = "xtal", + .index = -1, }, .num_parents = 1, }, From patchwork Sun Nov 17 13:59:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248381 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 414141393 for ; Sun, 17 Nov 2019 14:00:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2178C20850 for ; Sun, 17 Nov 2019 14:00:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="bOVqlywY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726290AbfKQOAD (ORCPT ); Sun, 17 Nov 2019 09:00:03 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:46890 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726266AbfKQOAC (ORCPT ); Sun, 17 Nov 2019 09:00:02 -0500 Received: by mail-wr1-f67.google.com with SMTP id b3so16355789wrs.13; Sun, 17 Nov 2019 06:00:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ALb0D3ZQCosHbu3XTz0Zl3zN169Kwv6XSNmMst3JsiU=; b=bOVqlywY/TN2WcGCQ6kihefkhnThvBvgSgqVpzw1sHaJcCOhgj31mlHerwO7cQ4tDE xEPorDMERAqXbU5AyaDE+rTC8v1wbzAmprTg99RL5u8dtY7wPnA2M+1ChWzbA/WTlR2T tdsgK1XJYDXFnfRcJiqjnjFq2lg9tlf3rReuufmQnWmjrxkYmr5pnFWi21Di7Rr9ShNK lHfiUgTZqGoxlh7P2o6vb9embjtkJzSwIaDd4hZ+g7fCnV4C87Q/N+S+zJBUa4OOXaUN kXJirZOOQzYLMuAUfbclBvw7S7Z5Xu34TSpiVa/+BbsRgosW9FWI3qu1+NDndwtvh6Qn z23g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ALb0D3ZQCosHbu3XTz0Zl3zN169Kwv6XSNmMst3JsiU=; b=kGn+6LBlTehK7BNw2Od/x1VNkyDdQb+K4tBbOc5psDPkbia3+YtMmmRNKnoQVsX1RE rbWssRsArYjoQywoSuIDNFX1A2Aeg/cT3+NSX7AVFdYxN6myd54wn7+xANARcHjvW4a2 RjFYNj2jTezBCWcwNMJ9ojfMFksYi2euP/FS3jrYSSz4KgnjPxYWZLU7IdwXxtbI/Om/ +zIJm0CV79hWis1DjbX65Up3zVoNcelYrAgAsydRTqhP42emBiORc+mCuknlpz78JFTK nsWP+oIenxMG/1Vg6R/pK9zp7Z/Hh4yGaowYLsNZp/mSA1KmRoN3lQXiKGeSnCFJM4Pr W53A== X-Gm-Message-State: APjAAAXq10VAliDKVMH8xLw80R8/1bY/0pfnJx82EpaqPdMu+6+kZTyZ QP6G5uwG+bmFjOZdjqqExeo= X-Google-Smtp-Source: APXvYqxodTdB4qW5P1m2ak/Tvv3QB8ZeIwlDZopM35wEeu5DhwcBl7avlGwHw4rIhIcjP9Ki91UvDg== X-Received: by 2002:adf:a119:: with SMTP id o25mr16461312wro.74.1573999200043; Sun, 17 Nov 2019 06:00:00 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n65sm18004803wmf.28.2019.11.17.05.59.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 05:59:59 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v3 4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF Date: Sun, 17 Nov 2019 14:59:26 +0100 Message-Id: <20191117135927.135428-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> References: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock driver should not register the XTAL clock - instead it should be provided via .dts and then passed to the clock controller. Skip the registration of the XTAL clock if a parent clock is provided via OF. Fall back to registering the XTAL clock if this is not the case to keep support for old .dtbs. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index f857a2c4d025..44e97bacd628 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3687,10 +3687,16 @@ static void __init meson8b_clkc_init_common(struct device_node *np, meson8b_clk_regmaps[i]->map = map; /* - * register all clks - * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 + * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the + * XTAL clock as input. */ - for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { + if (!IS_ERR(of_clk_get_by_name(np, "xtal"))) + i = CLKID_PLL_FIXED; + else + i = CLKID_XTAL; + + /* register all clks */ + for (; i < CLK_NR_CLKS; i++) { /* array might be sparse */ if (!clk_hw_onecell_data->hws[i]) continue; From patchwork Sun Nov 17 13:59:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11248385 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9690C184E for ; Sun, 17 Nov 2019 14:00:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 763CD2084D for ; Sun, 17 Nov 2019 14:00:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="dozuA7JK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726088AbfKQOAH (ORCPT ); Sun, 17 Nov 2019 09:00:07 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:43726 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726268AbfKQOAD (ORCPT ); Sun, 17 Nov 2019 09:00:03 -0500 Received: by mail-wr1-f67.google.com with SMTP id n1so16325627wra.10; Sun, 17 Nov 2019 06:00:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lfb97txnqBkpAAA0tczISRiqax5ID5KyvODmGSMgTQQ=; b=dozuA7JKPzxsob1ruenYebX+2uaraYQlCzRTEAu7EPK6gph0AbZCFHA+S/5MyNqBIG U3qymAOFS6vWauytLtQCtWkwbdVNdg483jY8NGjUbw9Vw6W2i0UE+ng5vK8J7uklbAfY WpJ2q846EfjkIszhGkbvdR6W2GJlSL2qj2t0iTHugUeSESi+20LOwQxSDq0OL22IYVNI RPhyRSmev++noqTcud3jT2qZPl2UfunG+/hqqpbUTh/ItsyFRKcqwqNU6cIiIbOBXNfU uyCoBtXaQa+BdwjDF9xqHWL14uJnCE/KjTqxl6Cd0kPq5bz40GGkrwvwxjgMUATksylH vVYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lfb97txnqBkpAAA0tczISRiqax5ID5KyvODmGSMgTQQ=; b=OIU+Bic3l3H8+sQnJnFdMjpaGiGT+ICqs6ycXuEVnaO+GaBXSTvTMhwnEY1lVQAACc U2Tnlb1o0dlOC+CKWv3e0nzUXLXz0QNDhtrDEPd7uEHEV1K0Cau01K2ZABTyP6ytawMd RIm+CqED8WaFiL7liPxqfBtmoiTgDMLmXT5ddEnmyZgpyC1f8HqTmyLdgR9y8+7sN2V7 0flFh6wXt+8GhsxRGcfYB8x3WABsQ7jxLC3LTXZIpgnmtm7EX1RAmDtflXyYXFbpmhQ7 1QhQdaZJ3GuOmDoxJS+WFYO2CluAhpNZz2uhW1RYLsvtvFwDFQMIo17TFaOSMQ5Z7q1W 2iaQ== X-Gm-Message-State: APjAAAVtyZxPJt04ilNmcW+jYqOUIQdnrFj4adJznvA05RhN+zgswCer 7+AoIxaJAZ9WsGa0G39Y5AQ6/bMW X-Google-Smtp-Source: APXvYqxH00nil5ICai5RDo5aD0yjFRhs/HB+0oOEKHsK3hLQUPvOZu3Ej+DTySsb5xf6DaKTR0H2Rg== X-Received: by 2002:a5d:5411:: with SMTP id g17mr24558469wrv.360.1573999201105; Sun, 17 Nov 2019 06:00:01 -0800 (PST) Received: from localhost.localdomain (p200300F1371CB100428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:371c:b100:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id n65sm18004803wmf.28.2019.11.17.06.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2019 06:00:00 -0800 (PST) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v3 5/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks Date: Sun, 17 Nov 2019 14:59:27 +0100 Message-Id: <20191117135927.135428-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> References: <20191117135927.135428-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Switch from clk_hw_register to of_clk_hw_register so we can use clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll" and possibly others from the .dtb. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 44e97bacd628..3408297bff65 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3701,7 +3701,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np, if (!clk_hw_onecell_data->hws[i]) continue; - ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]); + ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); if (ret) return; }