From patchwork Mon Nov 18 16:45:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11250013 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C2D014C0 for ; Mon, 18 Nov 2019 16:47:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 18C6721934 for ; Mon, 18 Nov 2019 16:47:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UntF5hGO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726962AbfKRQqv (ORCPT ); Mon, 18 Nov 2019 11:46:51 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:43325 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726435AbfKRQqv (ORCPT ); Mon, 18 Nov 2019 11:46:51 -0500 Received: by mail-lj1-f193.google.com with SMTP id y23so19714335ljh.10; Mon, 18 Nov 2019 08:46:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r/nohohxRUMshQs6j2Da0FE/YxPnOOD2XZg9k5AEvZQ=; b=UntF5hGOo1pq+9O5gMZYETsyG6z1nWvARzMhMWsqw/6gWOC8RxfzOSfI7fBl+zjVmO THNikHBYUw5sCUkmAHBOih+AtQaRD0Ho4GtDO55COy7lmMdjK5/ik3pTZUNAsLs6Znpd 6VDZf67vlDEO6Tk2SpRvyMgpdVhmN7oaJciDyFswkru/PrEKCFgBoR0dRLawQG+eCBdk o3thirYnKAChtb4t36CcRtL3aD5yTIOr6GFzMEd5lpEpJdxxwrXP327OExsPGgj8pOTJ CdhHWOfVLAZVS/2hf2Xrl7Td40QCbVcNh7E6cvPIne0mSgWre3vb/ocgm50kTgXZPCiy 4vWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r/nohohxRUMshQs6j2Da0FE/YxPnOOD2XZg9k5AEvZQ=; b=M8aNXGq7xFkOqZm0haT609GL/aTpnNUYW7sc67Ayhv/zBD52NTrdpN9zeOo7lo9z5x UC6vWtLBhJ3mkzDq3v/npuK7rgFOvtDqCSRGkH/33Z1XM+JOoyE+a36lQeoCYMsp/cmj feeabv0IXOlq74kM2v+jfAv2ArbWHiRu66Z7nz3oRVMSKuCRv1L/HDQWRw+sQUrEghsX MXVnRfhjgqZzS9p8ZaJ8bvEaYGZz+OKS1ggDn7AnipbUC0c4R3vnN6JFVN9R8CfVFFec 74XSQTaSsjvu7ux5zi7WQxkMkO/DtXj6RbJxrrVzvnuIfIVhItzvbebuj116DNqp9BVf tT/A== X-Gm-Message-State: APjAAAV/6aVRXfm2Fv1v2p5V8+Rl5SHeieQUI5GPxEjOPmFx9AQNK/fV SWu2WeOZPScZ3rWBCZSSYITRVLSD X-Google-Smtp-Source: APXvYqw500rK9XrD9rfViT293CtVxZiGBFRK0PCuQ2mRhSJe9pvmZiVbWKDsh734S04zzBNXfCLmvw== X-Received: by 2002:a2e:9842:: with SMTP id e2mr260463ljj.93.1574095606527; Mon, 18 Nov 2019 08:46:46 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:45 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 01/11] clk: tegra: Add custom CCLK implementation Date: Mon, 18 Nov 2019 19:45:02 +0300 Message-Id: <20191118164512.8676-2-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-super-cclk.c | 178 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 11 +- 3 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index df966ca06788..f04b490f5416 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -14,6 +14,7 @@ obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-super-cclk.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c new file mode 100644 index 000000000000..7bcb9e8d0860 --- /dev/null +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on clk-super.c + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Based on older tegra20-cpufreq driver by Colin Cross + * Copyright (C) 2010 Google, Inc. + * + * Author: Dmitry Osipenko + * Copyright (C) 2019 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLLP_INDEX 4 +#define PLLX_INDEX 8 + +#define SUPER_CDIV_ENB BIT(31) + +static u8 cclk_super_get_parent(struct clk_hw *hw) +{ + return tegra_clk_super_ops.get_parent(hw); +} + +static int cclk_super_set_parent(struct clk_hw *hw, u8 index) +{ + return tegra_clk_super_ops.set_parent(hw, index); +} + +static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); +} + +static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (cclk_super_get_parent(hw) == PLLX_INDEX) + return parent_rate; + + return tegra_clk_super_ops.recalc_rate(hw, parent_rate); +} + +static int cclk_super_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *pllp_hw = clk_hw_get_parent_by_index(hw, PLLP_INDEX); + struct clk_hw *pllx_hw = clk_hw_get_parent_by_index(hw, PLLX_INDEX); + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + unsigned long pllp_rate; + long rate = req->rate; + + if (WARN_ON_ONCE(!pllp_hw || !pllx_hw)) + return -EINVAL; + + /* + * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. + * PLLX will be disabled in this case, saving some power. + */ + pllp_rate = clk_hw_get_rate(pllp_hw); + + if (rate <= pllp_rate) { + if (super->flags & TEGRA20_SUPER_CLK) + rate = pllp_rate; + else + rate = tegra_clk_super_ops.round_rate(hw, rate, + &pllp_rate); + + req->best_parent_rate = pllp_rate; + req->best_parent_hw = pllp_hw; + req->rate = rate; + } else { + rate = clk_hw_round_rate(pllx_hw, rate); + req->best_parent_rate = rate; + req->best_parent_hw = pllx_hw; + req->rate = rate; + } + + if (WARN_ON_ONCE(rate <= 0)) + return -EINVAL; + + return 0; +} + +static const struct clk_ops tegra_cclk_super_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .set_rate = cclk_super_set_rate, + .recalc_rate = cclk_super_recalc_rate, + .determine_rate = cclk_super_determine_rate, +}; + +static const struct clk_ops tegra_cclk_super_mux_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .determine_rate = cclk_super_determine_rate, +}; + +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock) +{ + struct tegra_clk_super_mux *super; + struct clk *clk; + struct clk_init_data init; + u32 val; + + super = kzalloc(sizeof(*super), GFP_KERNEL); + if (!super) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + super->reg = reg; + super->lock = lock; + super->width = 4; + super->flags = clk_super_flags; + super->hw.init = &init; + + if (super->flags & TEGRA20_SUPER_CLK) { + init.ops = &tegra_cclk_super_mux_ops; + } else { + init.ops = &tegra_cclk_super_ops; + + super->frac_div.reg = reg + 4; + super->frac_div.shift = 16; + super->frac_div.width = 8; + super->frac_div.frac_width = 1; + super->frac_div.lock = lock; + super->div_ops = &tegra_clk_frac_div_ops; + } + + /* + * Tegra30+ has the following CPUG clock topology: + * + * +---+ +-------+ +-+ +-+ +-+ + * PLLP+->+ +->+DIVIDER+->+0| +-------->+0| ------------->+0| + * | | +-------+ | | | +---+ | | | | | + * PLLC+->+MUX| | +->+ | S | | +->+ | +->+CPU + * ... | | | | | | K | | | | +-------+ | | + * PLLX+->+-->+------------>+1| +->+ I +->+1| +->+ DIV2 +->+1| + * +---+ +++ | P | +++ |SKIPPER| +++ + * ^ | P | ^ +-------+ ^ + * | | E | | | + * PLLX_SEL+--+ | R | | OVERHEAT+--+ + * +---+ | + * | + * SUPER_CDIV_ENB+--+ + * + * Tegra20 is similar, but simpler. It doesn't have the divider and + * thermal DIV2 skipper. + * + * At least for now we're not going to use clock-skipper, hence let's + * ensure that it is disabled. + */ + val = readl_relaxed(reg + 4); + val &= ~SUPER_CDIV_ENB; + writel_relaxed(val, reg + 4); + + clk = clk_register(NULL, &super->hw); + if (IS_ERR(clk)) + kfree(super); + + return clk; +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 416a6b09f6a3..ee35a847df08 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -729,8 +729,10 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates * that this is LP cluster clock. * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5 - * super mux parent using PLLP branches. To use PLLP branches to CPU, need - * to configure additional bit PLLP_OUT_CPU in the clock registers. + * super mux parent using PLLP branches. To use PLLP branches to CPU, need + * to configure additional bit PLLP_OUT_CPU in the clock registers. + * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super + * clocks, it only has a clock-skipper. */ struct tegra_clk_super_mux { struct clk_hw hw; @@ -748,6 +750,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) #define TEGRA210_CPU_CLK BIT(1) +#define TEGRA20_SUPER_CLK BIT(2) extern const struct clk_ops tegra_clk_super_ops; struct clk *tegra_clk_register_super_mux(const char *name, @@ -758,6 +761,10 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Mon Nov 18 16:45:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11250023 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80D181390 for ; Mon, 18 Nov 2019 16:47:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 56B17218AE for ; Mon, 18 Nov 2019 16:47:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AMnRbLdQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726677AbfKRQqu (ORCPT ); Mon, 18 Nov 2019 11:46:50 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:40905 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfKRQqu (ORCPT ); Mon, 18 Nov 2019 11:46:50 -0500 Received: by mail-lj1-f193.google.com with SMTP id q2so19767485ljg.7; Mon, 18 Nov 2019 08:46:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y0gNszD0ptBgrgfqARNo4dCfpARXgUJI1xW2pH1mNqQ=; b=AMnRbLdQfenpLVnLwnoKmthFoia/qBJo4V8FZhRcpT1kRligp9K2XHi2QKxXKLRKsh dP6Zy1SGzXjQS+CrKneQNd6HheDriZha3AoH605RNMsdHwaNTmYP28x9ocb2DOcJdJcK qTU/5ykYzr6p0ww8E4Sdjoi2ffgH7apLuTRViE7YDnVmY91r89NTSPepv/K6I082VUiC uhF7KvP1P844SzHRR0VjqHY9nKXL0hUvN8ZZ58yp/jVFdIVebKNWjmnV0sm/FlILwUx7 Q4VLcGB76ab3WJBk9LZ/hMoRGXnGwjUw4kSvMZ9QeR58qjepubuQkjnMnGktfYgZuaLk XQbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y0gNszD0ptBgrgfqARNo4dCfpARXgUJI1xW2pH1mNqQ=; b=R/hztodzXVCSUF41/IIyIgV3iSWn6xFvG5jh7Wl7NTWcYS8dFej5CNRDNPzCnVQdAD hhl9uvh6uR3yXZe7oWKHjn28VtpDQprypKpPTg2RGAH0h7HywHWBYkYXlnte8Q3Ny/kp cWEb9t+UpMIpmmsuRcVYVyerid3IwfhjbkpLfK3MNcLhITtzIoocQ4JGOAGYMzC8Gg+B VhPg8feAGqQdVGztS3F7/5TJJgghm5xuW4VkmNjN6xQoO7nNcyGDa63HAiEaIOTwYafK SNPClcOMaGqBCXd3kNSQjcbiTgY0HdUCLPpVphiU3dquKrQiXva1J5a+m8CJcOfFyc6c Cdsw== X-Gm-Message-State: APjAAAVoZ2dXxd18BCbtTs7k+wL6IBOajYAXVhCVgCiollY6y1o2Zz+T Jnm71NsXaAL+tLO3Y/EU/Xk= X-Google-Smtp-Source: APXvYqz/ScRecKieVBX1sp9czjfXmCAdVkefP5wvCaTAy2Vo6vr9IFK29pNFdWsZc+VSNIF6TFRQvQ== X-Received: by 2002:a2e:2c1a:: with SMTP id s26mr243441ljs.239.1574095607750; Mon, 18 Nov 2019 08:46:47 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:47 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/11] clk: tegra: pll: Add pre/post rate-change hooks Date: Mon, 18 Nov 2019 19:45:03 +0300 Message-Id: <20191118164512.8676-3-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 12 +++++++++++- drivers/clk/tegra/clk.h | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 531c2b3d814e..0b212cf2e794 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, state = clk_pll_is_enabled(hw); + if (state && pll->params->pre_rate_change) { + ret = pll->params->pre_rate_change(); + if (WARN_ON(ret)) + return ret; + } + _get_pll_mnp(pll, &old_cfg); if (state && pll->params->defaults_set && pll->params->dyn_ramp && (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { ret = pll->params->dyn_ramp(pll, cfg); if (!ret) - return 0; + goto done; } if (state) { @@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, pll_clk_start_ss(pll); } +done: + if (state && pll->params->post_rate_change) + pll->params->post_rate_change(); + return ret; } diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ee35a847df08..fa18bef914af 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -266,6 +266,10 @@ struct tegra_clk_pll; * disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. + * @pre_rate_change: Callback which is invoked just before changing + * PLL's rate. + * @post_rate_change: Callback which is invoked right after changing + * PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -342,6 +346,8 @@ struct tegra_clk_pll_params { void (*set_defaults)(struct tegra_clk_pll *pll); int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg); + int (*pre_rate_change)(void); + void (*post_rate_change)(void); }; #define TEGRA_PLL_USE_LOCK BIT(0) From patchwork Mon Nov 18 16:45:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11250017 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FB9E1390 for ; Mon, 18 Nov 2019 16:47:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 20A1F218BA for ; Mon, 18 Nov 2019 16:47:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cn2Yy7WZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726635AbfKRQrb (ORCPT ); Mon, 18 Nov 2019 11:47:31 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:41577 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726472AbfKRQqv (ORCPT ); Mon, 18 Nov 2019 11:46:51 -0500 Received: by mail-lj1-f196.google.com with SMTP id m4so14794045ljj.8; Mon, 18 Nov 2019 08:46:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pG9lXccv0oOEUJTH/gOp3aikTwBYEJL3+x/Tztb4ZXo=; b=cn2Yy7WZjKpfPkxqhPZL3cm3uPcINgrwtJErnnQ1xIthJFcPBV6s5KOeuazEAwgTDd CX2h5pGsAFQI+DjdtlExJNnUb5TxjP7P6XU0nJKEZ+jqqSJDthBlIXskRE+qTBSyQzq1 Q5fF64vTRDzbRdRz1e/kTQiUHrcDnATe2Php1nCAX8qV4COzjRi2CqSSoGpc5W6vwLao HColuUwE5yi0DMA9iUBdfqud1sMI4a7pcuTkNY934C1ZG6PAQkx2weqmGv3chC50zKEP Ofd7vF4MZn7tmlLaIqx45vPFexpeA+804sc7fA1M0T9rurIC2aU+LyrGOzeDrkIhW6qX rDRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pG9lXccv0oOEUJTH/gOp3aikTwBYEJL3+x/Tztb4ZXo=; b=gEfNoK592Z6S579nAf/AXzjtk9dMSC4l7x4GaDcfqyVSpCsrz3LmUkO3cFaepmYZuk 83x3ZRHsEhbrYzgWe4FX+cBMNo3ozg9Rh/DS5VmoUrDhI3tzIwSpeJQdk+HJzL5oIc7e PkUpx/an1ttl9S6BzerFZHJc2pvL/ZaeCPs/k88Az6u01sFGRBOSyRm73W1SrkU7XC2c zN2zYBrapF/JsaLgdu0sScQnPhcvd/FCc7nyRIq6zKf9s7gL7EAdVlHP1G30CY3X+b9i Gvu4Wsvgcgq1dNI+axtvRKYgDWC7eYN1nkwOju6yjfw68K59wLvBgomah9tF8FKHOn+B +OnA== X-Gm-Message-State: APjAAAWzXgmL/Omlrs93tuEcmtPzsh4ntdcopH1MkZUe6rJhIngBg25G I2BQyP/BcFTGbhfjhGcb+2U= X-Google-Smtp-Source: APXvYqxHjz3Ecs55M2sI8pU6csg3HH+jE0WDtOLSgtZDCsx+6K+r5FpqYSBI0xapTQknmPmIQ8bCww== X-Received: by 2002:a2e:8ed6:: with SMTP id e22mr268631ljl.3.1574095608809; Mon, 18 Nov 2019 08:46:48 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:48 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 03/11] clk: tegra: cclk: Add helpers for handling PLLX rate changes Date: Mon, 18 Nov 2019 19:45:04 +0300 Message-Id: <20191118164512.8676-4-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 7bcb9e8d0860..a03119c30456 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,9 @@ #define SUPER_CDIV_ENB BIT(31) +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; + static u8 cclk_super_get_parent(struct clk_hw *hw) { return tegra_clk_super_ops.get_parent(hw); @@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, struct clk_init_data init; u32 val; + if (WARN_ON(cclk_super)) + return ERR_PTR(-EBUSY); + super = kzalloc(sizeof(*super), GFP_KERNEL); if (!super) return ERR_PTR(-ENOMEM); @@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk = clk_register(NULL, &super->hw); if (IS_ERR(clk)) kfree(super); + else + cclk_super = super; return clk; } + +int tegra_cclk_pre_pllx_rate_change(void) +{ + if (IS_ERR_OR_NULL(cclk_super)) + return -EINVAL; + + if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX) + cclk_on_pllx = true; + else + cclk_on_pllx = false; + + /* + * CPU needs to be temporarily re-parented away from PLLX if PLLX + * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. + */ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX); + + return 0; +} + +void tegra_cclk_post_pllx_rate_change(void) +{ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fa18bef914af..0afe28f4372b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change(void); +void tegra_cclk_post_pllx_rate_change(void); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Mon Nov 18 16:45:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11250009 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DA3C1390 for ; Mon, 18 Nov 2019 16:47:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1C2A8218BA for ; Mon, 18 Nov 2019 16:47:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Spe6Tzh6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727018AbfKRQqx (ORCPT ); Mon, 18 Nov 2019 11:46:53 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:42561 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726716AbfKRQqw (ORCPT ); Mon, 18 Nov 2019 11:46:52 -0500 Received: by mail-lj1-f195.google.com with SMTP id n5so19727525ljc.9; Mon, 18 Nov 2019 08:46:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CbLJtKoWfGlhZ2yYzvSNqEKgjc0Cow8QnHrPe+s4dKk=; b=Spe6Tzh60D3ZTg9s/zkyl7wl4CuoTu0oyslPSiyEOtyirEZQeaFbOey3pfBLyFETcC vSAzesQHoplqbIKVa4mA42Q13P9AOO+q3QCvMuxuAQOaHgBsVnD/rWZei158k2qX9dj2 FqjIy4eZSdcz43V6s/qW3wCERH/leZFhX5elCsc/kDREY8asUobqdAS12PAxDFUypcLc 7V3t5ABm336ZEc2TUIHxmH9ofZJT3fZDUicPe2ldnoWpef7eKz55pl+vKBSf+Z7cQyLA XFGZUPVYZ9muXzf85x0GR3Coc9b/dCdloxVUZxxFWXJS+yAEPhZK/x5ponNB3QEalP/B Lu5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CbLJtKoWfGlhZ2yYzvSNqEKgjc0Cow8QnHrPe+s4dKk=; b=iX//Qg5HA0FPkGpzvDjZbupVHuXtyP3wVvmJOX+ChzWfUSZrcOXUb0YMq2ROTqPw8P owMpA4Q+Oiz+Npx1bB4H7ZxEChMqh4z2na/hiFBvOQPL8XlVCWhmbOwE8+tyea9PTXs6 dhPHWW/A4Zxg+xH/slpiDxmjuEoWf4HJYTgFwq6aVuSu2kuVZB9cNIx+ho7VcSj5e0Cc HzM4GMbU3HVJhJyaKd3FTfn33Tc++dWZ2bf8gz6rQUrWPRUsGTDVdeBqL6RKV7TQSccz cGddGRb22VtkvSU6kjDPI9LXH70LoS+XuotWJ/dra0KQSZWg9JAVirHBAW1pascg9dHo PKSg== X-Gm-Message-State: APjAAAWSdhhNiDsBK5/0Ozhe+OjQrifWKfRX7oO3CeX1Y3WI7kD5DLbb O3r7W9udkA7UBsE+7l4vayw= X-Google-Smtp-Source: APXvYqzlStWq8xLfPnzIePvkf3wmed1fYUfNORwB5pIca2VkphXS5T1s/r1C+tDD8TaUy5o/TSi1/w== X-Received: by 2002:a2e:990b:: with SMTP id v11mr238497lji.151.1574095609837; Mon, 18 Nov 2019 08:46:49 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:49 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 04/11] clk: tegra20: Use custom CCLK implementation Date: Mon, 18 Nov 2019 19:45:05 +0300 Message-Id: <20191118164512.8676-5-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 4d8222f5c638..eb821666ca61 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params = { @@ -704,9 +706,10 @@ static void tegra20_super_clk_init(void) struct clk *clk; /* CCLK */ - clk = tegra_clk_register_super_mux("cclk", cclk_parents, + clk = tegra_clk_register_super_cclk("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, - clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, + NULL); clks[TEGRA20_CLK_CCLK] = clk; /* SCLK */ From patchwork Mon Nov 18 16:45:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11250003 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C28014C0 for ; Mon, 18 Nov 2019 16:47:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7C88F222A3 for ; Mon, 18 Nov 2019 16:47:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FEB2ycii" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727113AbfKRQq4 (ORCPT ); Mon, 18 Nov 2019 11:46:56 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:42563 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727007AbfKRQqz (ORCPT ); Mon, 18 Nov 2019 11:46:55 -0500 Received: by mail-lj1-f194.google.com with SMTP id n5so19727599ljc.9; Mon, 18 Nov 2019 08:46:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oZXgBiZ7YOkoGyisWeubyUkOPcMd11xlE2xTsIL1hcs=; b=FEB2yciicFM5rkAopit+Cycgfy+rgDcDNO1D1l2REgdESUrLizS2okO3oluoQa4u7A /P8Guj/HHQzLw67PKlgUREY1n4UHuPCC//wcBApH8T9AwTzLIf3qQrUY6ANbIfHOj2fb EFWVlr5tkdXzEZCVIj+EEAQwtiZ7eNrzjS4I0NMWhYrFpAe+wznS8A1ksAANt2t8+GRc zfBbtEgTHzr8Rorau+QJAxKR3em5Ry0u4Y0UtcxzsOb9NPj7hoFM808wlSU+ZnsgxLJ+ 8tZZy6G6lZ41edkaj27AE6DOcgP5ewZsXR0pjvqZ8+US2HKfRuBSE7aNN6wc+mB/kXAy g9Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oZXgBiZ7YOkoGyisWeubyUkOPcMd11xlE2xTsIL1hcs=; b=K+cQ0njA5ZeW6OtifGJLW/i1ce1yHRKJ28+ts1RxwMToC9nr641tEuWG2kh6Zo7pzO QV68LH9lCyHiqTe8viikIDmHipzM5HBLxYxKjGqqPAMRl5BTTK1XznnxYvVX+jhH66cg E+47ZUi+8DzJLkdjQMRfqZTXeNmDgYwklqGhQB4KqbNePCHcWyiq5UKvM5kwgSjXQRu5 Ntu5jU2jKOXFKjt54BVm5oSRB+43WpfZvSESN1o0WFMsNUDRpVPa8Soc982thksNswN2 3iT1jzJWw6y7C9qCEMwD20UnC/AQGVaPOOcGLd2sJX9Hux1BTfC+AdCzC55j1god1ALP DLsw== X-Gm-Message-State: APjAAAUExsbxmWFfAG5l1s/GtM7UDWCNyxrq2Py2h0h8lLxZkWUvZA8C Pd39gdMvXkjySgAwdeXyWF4= X-Google-Smtp-Source: APXvYqye2GKLQ1yaQqROyuS0/T2RW2xNdSuYo7BQZHAfJ7hhyt2zZOjPfv9V4XEn5pgdD9+yu/Dd8g== X-Received: by 2002:a2e:4703:: with SMTP id u3mr271809lja.126.1574095611004; Mon, 18 Nov 2019 08:46:51 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:50 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 05/11] clk: tegra30: Use custom CCLK implementation Date: Mon, 18 Nov 2019 19:45:06 +0300 Message-Id: <20191118164512.8676-6-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index c8bc18e4d7e5..0fe03d69fe1a 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params __ro_after_init = { @@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void) clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); /* CCLKG */ - clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, + clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, - 0, 4, 0, 0, NULL); + 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; /* From patchwork Mon Nov 18 16:45:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11250007 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 413F91390 for ; Mon, 18 Nov 2019 16:47:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21D7921934 for ; Mon, 18 Nov 2019 16:47:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ebx11epX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727059AbfKRQqy (ORCPT ); Mon, 18 Nov 2019 11:46:54 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:44526 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727001AbfKRQqy (ORCPT ); Mon, 18 Nov 2019 11:46:54 -0500 Received: by mail-lj1-f194.google.com with SMTP id g3so19709502ljl.11; Mon, 18 Nov 2019 08:46:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UXRoHcvapztDcfGo7L2UwrKkYpLR6LIFA1LRvGGCLHM=; b=ebx11epXp1Gz3ihhOwsxX6YPyaqQzXRfgHR4U50FAG7AxHVm3FrNhGEtwySbonpbiF gjRh7qAlkUjzhWJtdVfoWBLrzrh/vNVLaXbbnVoNjAwHPCQZTjaGcwC8W8JCfdm/qMix VibJFioGUCAZ2afPqJ+k8DU8yDDiZfWHK0jPxzLGDoc97fCXNPRmA++LNkX3YDd8XsnR ZOD7ZBkiVQZBC6wNJnxd5rMJre5IiEEeQXegl35yEbPGry3NGGLH12QQrrG+6naxvzxq MdoLOlfSkZsJviqqJwBEdCQXXGN9AWMXC+hEG5pu+G/6rKBVI/djsVhfLPx0QMZQM+kG MbxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UXRoHcvapztDcfGo7L2UwrKkYpLR6LIFA1LRvGGCLHM=; b=pMf+ZfiSYkTEk5aZadNGM1A6rwTzHC9Bj7XImCT1S8xNULP5tG2KJ7qkFtLstACuLS /xiBnkadtwYHkglC42ihdAfSqDAHJBfpzEpIsm69Qgfg7h4lWIuH1I422/loTq+C4avl ZAgWrFFt5cwB5HbC6tStZUW75Zv6E+NsySllQqqBwZx2+x0XFXUmP/0cFUelpS0Ye5tl DAKUz6ZoAebHYUT8CowOcC9Yr3gJRbsuKK79qLCNPHJ8dn2uF9c9BlmWQnRBUZiqYhkL K5QAhkB17o/m3nkocmF9zO+ei4kdnnljNZPYnGAi0XFaj3dmv05X5saddc441HNSYL7u OBzg== X-Gm-Message-State: APjAAAVo++W03pE4YkMlsLe68rEB+XlRFA6IOkUg+7TsRZ9uqboUiiw4 9PCxzjm9zXOgJmqEAyHTWqM= X-Google-Smtp-Source: APXvYqxUqsmjkdNpu1mD4oVQBY8s9NJw54ddMUiTEOvjA9Fh/1M+LplMfvnij1DnqfqrMr8H3NaWsA== X-Received: by 2002:a2e:9d84:: with SMTP id c4mr245952ljj.187.1574095612096; Mon, 18 Nov 2019 08:46:52 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:51 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 06/11] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Mon, 18 Nov 2019 19:45:07 +0300 Message-Id: <20191118164512.8676-7-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs. Acked-by: Viresh Kumar Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..daeca6ae6b76 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + }; From patchwork Mon Nov 18 16:45:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11249981 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1CAA1390 for ; Mon, 18 Nov 2019 16:46:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C1A3D2190F for ; Mon, 18 Nov 2019 16:46:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dSWGNAIs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727116AbfKRQq4 (ORCPT ); Mon, 18 Nov 2019 11:46:56 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:41584 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727031AbfKRQqz (ORCPT ); Mon, 18 Nov 2019 11:46:55 -0500 Received: by mail-lj1-f193.google.com with SMTP id m4so14794269ljj.8; Mon, 18 Nov 2019 08:46:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vSS5/MmskIAajZTBs7D6Zb0R76xGQBQ4vfEB2g+VhfI=; b=dSWGNAIscxuox8i/f4k9fxJCYXLkOYs8c4V9uuFlA9SegDARfNXm30V+fA26F1Vh9q qMZeV0Q1U5USzxnGztfqFCZtMakgozLP/mjXIEgy6jYUjpMH6LW6TzqXKOUHh5NhUXmv HgnG2O7OmmNmlwXyiBiSoyLCmrKVf1Iz8h+wG2anEr2cxpqitH4NwCVCIjVOheE3arkl BcYen5b28/Q268gKYw4B4Ll0Je8tZfsHTi704q3QVT4e1OfSpBtLzqRGGThP1ww50lIb e38JewaV4w3qTF4zTNxHYIJAWpes+C2QJH3TJwIuoFdaMkMPhoxJJOqFAaXVIWn7q2j5 qwhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vSS5/MmskIAajZTBs7D6Zb0R76xGQBQ4vfEB2g+VhfI=; b=h/EQjYk14X96cJk4i5xO7Z4DR0Fn/OMVdwtaRszIGhsFW5N+QAOvEIdayuWmrAbgTt pAeJDjV93RnvbptCzf0TnuhcOPx4tyRsMfDzVPiU9OjxXRbo4tKhXi37O+udZ192dYtC KY9F4z8JDVegEYMus+rmgQfWlcs5pnbU0+tEyhV+RYw43W/Zu94UbnMFFmNPBip6mR9q atXDUTUIbenSIMJZyihOnT/cujRwMiBXUz7ZEM4clG/70hPa9IE++hdrpO4hiT7lsCgV tXhfaHLi5slziGOO4S9tW4iMqCHhU29pud/gWldJH1M3l9D7r7zCEbr+ZNmm3QPapKYj RAtg== X-Gm-Message-State: APjAAAWe3cjoXUDGR8l1MkL3GlJVzcccKWaY7eXY9R0U9PL2daqHOmDO tJ47a1okXFI744gWVjzYn0U= X-Google-Smtp-Source: APXvYqxlqLM20mDO2M7+YU85rS6jMfO1OLrV46UKkfkkIY4+zlzsjCzi+zqjYWX3egQxQ401PtG5VQ== X-Received: by 2002:a2e:3313:: with SMTP id d19mr279650ljc.240.1574095613216; Mon, 18 Nov 2019 08:46:53 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:52 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 07/11] cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs Date: Mon, 18 Nov 2019 19:45:08 +0300 Message-Id: <20191118164512.8676-8-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Both NVIDIA Tegra20 and Tegra30 SoCs should be blacklisted because CPU OPPs use supported_hw and thus platdev isn't suitable for these SoCs. Currently cpufreq-dt driver produces a bit annoying warning splats during boot because valid OPPs are not found, this will be fixed once tegra20-cpufreq driver will be update to support cpufreq-dt. The warnings will also happen on older stable kernels using newer device-trees, thus this patch should be backported to stable kernels as well. Cc: Reported-by: Jon Hunter Fixes: 4053aa65c517 ("ARM: tegra: cardhu-a04: Add CPU Operating Performance Points") Signed-off-by: Dmitry Osipenko Acked-by: Viresh Kumar --- drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index f1d170dcf4d3..aba591d57c67 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -121,6 +121,8 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt8176", }, { .compatible = "mediatek,mt8183", }, + { .compatible = "nvidia,tegra20", }, + { .compatible = "nvidia,tegra30", }, { .compatible = "nvidia,tegra124", }, { .compatible = "nvidia,tegra210", }, From patchwork Mon Nov 18 16:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11249995 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 138A914DB for ; Mon, 18 Nov 2019 16:47:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DDE4A222A2 for ; Mon, 18 Nov 2019 16:47:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JHuArdoH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727135AbfKRQq6 (ORCPT ); Mon, 18 Nov 2019 11:46:58 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:46011 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727099AbfKRQq5 (ORCPT ); Mon, 18 Nov 2019 11:46:57 -0500 Received: by mail-lj1-f195.google.com with SMTP id n21so19690716ljg.12; Mon, 18 Nov 2019 08:46:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=se2anSzGz7QenPS18AqzH/OTmd+5146aZC1WTXOuiM4=; b=JHuArdoHqhlyZQxHh4yz6pJZkInGb346BBmsgUV+IVlKap1ONkaH5lDhcby69LG1oE xclam5SPHDNoq/AdIYgsO8oPbXt1e62vZrtitBkAoLTzVj2eTUdPHOpqB3x8agtExDDE KEMzNuMWWZDGQP+5eNy/q0cq7oMHVGapxZHTEgbGlA1AeEPvhHLkw0yCB9bNqxl+5Rro hV1lgqq35zGvRi/EV06Bjg6Fd1rln50BFqYEMv5iL1ebaqPWpxb33cEHJbL+Ww4l558i ZwD1Skd+XlWYco3nZ1Vlfu0beNofGOo4ISwBpVfO02erjqpPmB4V50AzetiQ06EfhFu9 J3UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=se2anSzGz7QenPS18AqzH/OTmd+5146aZC1WTXOuiM4=; b=tcOGkug214BbmhQHFFTWte+E3b0+ti3n8rvEqXJ+hjhRhzQlf3gV3R6JABoo/mccoj KRp9fClqViTslfaHv1JwAupHeTivUH9826OzrsFRsGMo02wP2Vpbz4JjExZFjG+ZpmIP D3Q0YB3SbfY36Irt6D6tQRGrY8DjISKmfDq0XR3+o6Hb+sncCtD/Ylrpfu+uzyGW3sqA ZxK++9pzoY2uu1dMzLEHldrAeI48E+p/pFU4ObJWjU69WsIyO3aRSHXpRx0+TjBVGu1B L4a/zvM3gyNy/eisZxlyK4SFPeaaRSILXzLtpC6dTbPaia6YvszTDQZgFnurQprBj9Os Ti+w== X-Gm-Message-State: APjAAAWgr2WoH4xkleliWkPzudKIIFHbP68QOz4zZ0xQOj/2+mTthy2W KgLvPWsMZHo+5S8MUVl0je8= X-Google-Smtp-Source: APXvYqye/+6FbDAbFFOsvp/8m/4aMbEhi/as+lMiVVskr1TXtlZoi0lV6D6RICGSoj0TRqOV5Ej8OA== X-Received: by 2002:a05:651c:1109:: with SMTP id d9mr276058ljo.192.1574095614276; Mon, 18 Nov 2019 08:46:54 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:53 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 08/11] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Date: Mon, 18 Nov 2019 19:45:09 +0300 Message-Id: <20191118164512.8676-9-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/tegra20-cpufreq.c | 217 ++++++++---------------------- 2 files changed, 59 insertions(+), 164 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 3858d86cf409..92a6a5089979 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ default y config ARM_TEGRA20_CPUFREQ - tristate "Tegra20 CPUFreq support" - depends on ARCH_TEGRA + tristate "Tegra20/30 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help - This adds the CPUFreq driver support for Tegra20 SOCs. + This adds the CPUFreq driver support for Tegra20/30 SOCs. config ARM_TEGRA124_CPUFREQ bool "Tegra124 CPUFreq support" diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index f84ecd22f488..8c893043953e 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -7,201 +7,96 @@ * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation */ -#include -#include +#include +#include #include #include #include +#include #include +#include #include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; - -struct tegra20_cpufreq { - struct device *dev; - struct cpufreq_driver driver; - struct clk *cpu_clk; - struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; -}; +#include +#include -static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, - unsigned int index) +static bool cpu0_node_has_opp_v2_prop(void) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - - /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq - */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) - return 0; - - return ifreq; -} + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; -static int tegra_target_intermediate(struct cpufreq_policy *policy, - unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; - - /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. - */ - clk_prepare_enable(cpufreq->pll_x_clk); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) - clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + if (of_get_property(np, "operating-points-v2", NULL)) + ret = true; + of_node_put(np); return ret; } -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - int ret; - - /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. - */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ - if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); - - /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. - */ - if (cpufreq->pll_x_prepared) { - clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; - } - - return ret; -} - -static int tegra_cpu_init(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_prepare_enable(cpufreq->cpu_clk); - - /* FIXME: what's the actual transition time? */ - cpufreq_generic_init(policy, freq_table, 300 * 1000); - policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; - return 0; -} - -static int tegra_cpu_exit(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_disable_unprepare(cpufreq->cpu_clk); - return 0; -} - static int tegra20_cpufreq_probe(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq; + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; + struct device *cpu_dev; + u32 versions[2]; int err; - cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); - if (!cpufreq) - return -ENOMEM; + if (!cpu0_node_has_opp_v2_prop()) { + dev_err(&pdev->dev, "operating points not found\n"); + dev_err(&pdev->dev, "please update your device tree\n"); + return -ENODEV; + } + + if (of_machine_is_compatible("nvidia,tegra20")) { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.soc_speedo_id); + } else { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.cpu_speedo_id); + } + + dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n", + versions[0], versions[1]); - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + cpu_dev = get_cpu_device(0); + if (WARN_ON(!cpu_dev)) + return -ENODEV; - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(cpufreq->pll_x_clk)) { - err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(&pdev->dev, "failed to set supported hw: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + err = PTR_ERR_OR_ZERO(cpufreq_dt); + if (err) { + dev_err(&pdev->dev, + "failed to create cpufreq-dt device: %d\n", err); + goto err_put_supported_hw; } - cpufreq->dev = &pdev->dev; - cpufreq->driver.get = cpufreq_generic_get; - cpufreq->driver.attr = cpufreq_generic_attr; - cpufreq->driver.init = tegra_cpu_init; - cpufreq->driver.exit = tegra_cpu_exit; - cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; - cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; - cpufreq->driver.suspend = cpufreq_generic_suspend; - cpufreq->driver.driver_data = cpufreq; - cpufreq->driver.target_index = tegra_target; - cpufreq->driver.get_intermediate = tegra_get_intermediate; - cpufreq->driver.target_intermediate = tegra_target_intermediate; - snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra"); - - err = cpufreq_register_driver(&cpufreq->driver); - if (err) - goto put_pll_p; - - platform_set_drvdata(pdev, cpufreq); + platform_set_drvdata(pdev, cpufreq_dt); return 0; -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); +err_put_supported_hw: + dev_pm_opp_put_supported_hw(opp_table); return err; } static int tegra20_cpufreq_remove(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev); + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; - cpufreq_unregister_driver(&cpufreq->driver); + cpufreq_dt = platform_get_drvdata(pdev); + platform_device_unregister(cpufreq_dt); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); + opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0)); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_opp_table(opp_table); return 0; } From patchwork Mon Nov 18 16:45:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11249993 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3CDC14C0 for ; Mon, 18 Nov 2019 16:47:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4471222A2 for ; Mon, 18 Nov 2019 16:47:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jTsDtw9o" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727143AbfKRQq6 (ORCPT ); Mon, 18 Nov 2019 11:46:58 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:46012 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727105AbfKRQq5 (ORCPT ); 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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:54 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/11] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Date: Mon, 18 Nov 2019 19:45:10 +0300 Message-Id: <20191118164512.8676-10-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..1e3b85923ca3 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -95,6 +95,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Mon Nov 18 16:45:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11249987 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6D5214DB for ; Mon, 18 Nov 2019 16:47:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C5067218BA for ; Mon, 18 Nov 2019 16:47:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IGenxVBB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727164AbfKRQq7 (ORCPT ); Mon, 18 Nov 2019 11:46:59 -0500 Received: from mail-lf1-f67.google.com ([209.85.167.67]:36322 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727121AbfKRQq7 (ORCPT ); Mon, 18 Nov 2019 11:46:59 -0500 Received: by mail-lf1-f67.google.com with SMTP id r14so7764193lff.3; Mon, 18 Nov 2019 08:46:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7wI6f4nvMYsmBCMp+G12GdGK/taTCqKZ+wxQzPpgr3A=; b=IGenxVBBU8LnP/bn6cALCeeOJCueMq4zduqrvldKlmvivlcwCa8smtTaZmyVVzNMRe ZgKhnTsISUj2T7LXIWJAlzDzIMz2s51/aqbzIrI724WhJLZZX9a3c3m/Ah2oNXD5523H ZWTVNzDDBG0Mkt344R5so24cirr9CBcKBht6I54YA2nbTEW2Qvf+4XdU0zY66okkIQYQ vqMMXJyjpFKQh2VqRpmtQ6+m5NTG2jEo8Wvpo1mf4d1HamChVku9OBDqtytrVbRo7cbw PFXT5pOdMlPjsQyZMbdnt+h0GLbXu80USktjq+BOQEe+WVQ5X8FSWM2R2CC3FNPE0+wY qUWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7wI6f4nvMYsmBCMp+G12GdGK/taTCqKZ+wxQzPpgr3A=; b=U4e3zR9UyjFsdC2YPi5DOIyz4ngn5m80IbpCb64dhPG2liD2/W6yOTjJFeLWmztNEh q0m8kj/QTbLSwZgRPA20kkEMP8CCizSP3zDFYK43HNOnQVqvY9OSJ5Ii1E32CZXTwA2q 5ELToFYWkb6kj0CsCrAfLkzzzKBW7pcL5Ua4IZXE3KYbFrSt78eMpF0nLcD2vUhepNHA b5S4odcFJV8jLjPj/KePpqUSno7Grr124ZZxClP0i4VaJJOYp0k+wzZIRmu5roWg9mOu 1Dw4w6Ib7XPqcKwiTn5iHkAAJu0zaCsX4XG/B1mtZaSZv7idREIwEpPorLgpDH+z5ZWR C5DQ== X-Gm-Message-State: APjAAAUd9SoM2RfiBKAAymaDFNK6Q97HhwXHXU99wDpGY4+8rKIGfqtK b/ORQ0Wkj8G7M2HFiMSZNAA= X-Google-Smtp-Source: APXvYqxIxc0KerZe9XzlTaSytbGDBdMdiNmvzPW92uEueNFjjRSMlpqIrfzdQofXyHu3hiVn+IuQ/A== X-Received: by 2002:a19:905:: with SMTP id 5mr235451lfj.123.1574095616462; Mon, 18 Nov 2019 08:46:56 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:56 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 10/11] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Date: Mon, 18 Nov 2019 19:45:11 +0300 Message-Id: <20191118164512.8676-11-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Set min/max voltage and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a3b0f3555cd2..6ebb3105af9e 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,9 +1806,14 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1873,22 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; From patchwork Mon Nov 18 16:45:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11249983 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B11801390 for ; Mon, 18 Nov 2019 16:47:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 90A962192B for ; Mon, 18 Nov 2019 16:47:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IGVCd2jc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727193AbfKRQrB (ORCPT ); Mon, 18 Nov 2019 11:47:01 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:34095 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727133AbfKRQrA (ORCPT ); Mon, 18 Nov 2019 11:47:00 -0500 Received: by mail-lf1-f65.google.com with SMTP id l28so4907136lfj.1; Mon, 18 Nov 2019 08:46:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BEJ200kbZVTsss1iDk6Wt5qRmYYgbTDuf+N828TJE+4=; b=IGVCd2jc4txLjHf/sfY4X+avJaXXVtxQiUXMfIumvdKaSAsNVzOtgcdtd+AHwpBqbO 7n/eTuOLD2NtFqmwiRinl5eTiqFcO2MsujzbRHbZG4KoBVqdb2FRgFpvtz8plrhU2rrK 0wItbJRA/PkavAFlXydHA8ROKZ1CfCqZVfbo5GkWzXMxYLWpvLGY2VHgwvX0ji8HKj1O cVmUMkz5AwoNLLUYqlsW9fuA7r9BFxvq0dkxEVRxJcVNLQe5qRfEtHYEc9VRv8t1+GVV HYT/BWiNOY5zamQOKShxM6d50RQ8FQayJ8RKvSIfoXfwRcP2qh7QNcIi5UPGgONFpW9m 5oNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BEJ200kbZVTsss1iDk6Wt5qRmYYgbTDuf+N828TJE+4=; b=eb4u8p9y2boFvjHGb1+CObnkDiiw/dIDVwXpVW+CgFcxHcF5rL5YkXUbRdt1blVsXT ZE8GevYqG2EEhi5TubeROpiihh3vjVpI6iZzPDbEkMPHzIOo1LX8y2mBv4W/HXtydktW 2KXUIHWSvQbTM2OTrFdEsgB0aveR7zkEDMeU7M04kn8CmT3pK5XN8vx6wrTM9e6Ow7Ox NRtCI0jn30IWeVR3u1RAzYFbRwgwgJuo/YCTpM6xBi49hPt1gK7AyqNIloSezTItj32K YWnVm3H7BuulJl7tgroNwk+EKGVy2s1kdn6W99xaK6EQJ+Zetiwo8Fi8MHAtjdFdhNrb q8pg== X-Gm-Message-State: APjAAAWMfcKVuKx3HuOnCAwUSG35xeFC4L8jws6PzazKKAe6U2vZlgnO yEiTUPhMoU+B5A5nkBxw/Wc= X-Google-Smtp-Source: APXvYqz478Bvh3VIehym/uGsiaTo42wDcevqvFNsiDJQj3upXVODL5mRJOxBSLNYfHEXEbPKE7y8Jg== X-Received: by 2002:ac2:5deb:: with SMTP id z11mr261378lfq.35.1574095617798; Mon, 18 Nov 2019 08:46:57 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id d4sm8880307lfi.32.2019.11.18.08.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 08:46:57 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 11/11] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Date: Mon, 18 Nov 2019 19:45:12 +0300 Message-Id: <20191118164512.8676-12-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118164512.8676-1-digetx@gmail.com> References: <20191118164512.8676-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6ebb3105af9e..86556622be25 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -2124,4 +2126,26 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };