From patchwork Wed Nov 20 13:59:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11253977 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 831076C1 for ; Wed, 20 Nov 2019 14:00:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46333224C0 for ; Wed, 20 Nov 2019 14:00:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="mXvSi061" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731521AbfKTN76 (ORCPT ); Wed, 20 Nov 2019 08:59:58 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25846 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727988AbfKTN75 (ORCPT ); Wed, 20 Nov 2019 08:59:57 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1574258378; cv=none; d=zohomail.com; s=zohoarc; b=IAtSU0eTiPp7P/dDrPhB1gsKHJoaPzDSjIwGOczUKdMBihU0SSYP7z66SikrBHraenQNPvAdOhdtZVyYm748rbG+qz3kQXWwf1P31IYFNceudqcXgKcNWq12mB5+aajeRtrlInEJI+GyO4sY/XfiA0wYdXbLOJO6dgVPq+kwxNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574258378; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To; bh=frgRYqjLMQtHBWb6dkHQosNEXbkljqK2JMMCleHhs4A=; b=kN/Umi7TAKviyPWMYlPJlzXtqWQqIk1rdl4Vza9ZgJ+3IKDg57CwOioKUCugw0nRwfC5b/ojTj/GMdFxKY/b+kuJyoLyeo+pQj2sS6ITE7orH/MNPg3bXv/6wNutQXwR0+sSOyIYyCsXTMQiBSbWJvJHktE7MtXwAqFbleHjf8Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=QEAB7jAFaH6OPCGncBaBdt4qW3hTgr1TOOEslZ7RylgBpoq0cWNdkduBdwvr5eB58zoAvfI34Twz Nd6z7zYp4aOYdYLprNUH5onPyrLKMDgp0+m3y9PmhLN2jIXw94C/ DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574258378; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=12469; bh=frgRYqjLMQtHBWb6dkHQosNEXbkljqK2JMMCleHhs4A=; b=mXvSi061O8Vf0zDWWbV6ynkoH48umPh8hrA9WEPTMQ3P9KPJl0xMop5V8kFW4C5C 05fnE5+DPqBvrVA+lBjSadzdl/2/CiZx/iWT2EY31wKMk70+DLWPZc2TUe/IW9RTND2 O/ZOEEkGES6IujL935ftbr2YmLJ6EDAq/nJDvUdo= Received: from zhouyanjie-virtual-machine.localdomain (171.221.112.99 [171.221.112.99]) by mx.zohomail.com with SMTPS id 1574258376299723.3961885721733; Wed, 20 Nov 2019 05:59:36 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paulburton@kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, paul@crapouillou.net, robh+dt@kernel.org, mark.rutland@arm.com, syq@debian.org Subject: [PATCH v2 1/4] pinctrl: Ingenic: Fix bugs in X1000 and X1500. Date: Wed, 20 Nov 2019 21:59:00 +0800 Message-Id: <1574258343-122458-2-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> References: <1573804011-2176-1-git-send-email-zhouyanjie@zoho.com> <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org 1.Fix the pullup parameter of X1000. 2.X1000 and X1500 have only one set of uart1 hwflow pin mapping, so modify "uart1_hwflow_d" to "uart1_hwflow". 3.X1000 has only one set of mmc1 pin mapping, so modify "mmc1-1bit-e/mmc1-4bit-e" to "mmc1-1bit/mmc1-4bit". 4.X1000 has only one regular externel memory controller that does not support nand flash, so change "nemc_" to "emc_". 5.X1500 has only one set of mmc, so modify "mmc0_" to "mmc_". Signed-off-by: Zhou Yanjie --- Notes: v1->v2: Modify "nemc_" to "emc_" because X1000 has only one regular externel memory controller that does not support nand flash. drivers/pinctrl/pinctrl-ingenic.c | 94 +++++++++++++++++++-------------------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 6e26830..059e39a 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1017,7 +1017,7 @@ static const struct ingenic_chip_info jz4780_chip_info = { }; static const u32 x1000_pull_ups[4] = { - 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff, + 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, }; static const u32 x1000_pull_downs[4] = { @@ -1028,7 +1028,7 @@ static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; -static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; @@ -1036,20 +1036,20 @@ static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; -static int x1000_nemc_8bit_data_pins[] = { +static int x1000_emc_8bit_data_pins[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, }; -static int x1000_nemc_16bit_data_pins[] = { +static int x1000_emc_16bit_data_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, }; -static int x1000_nemc_addr_pins[] = { +static int x1000_emc_addr_pins[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, }; -static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, }; -static int x1000_nemc_wait_pins[] = { 0x34, }; -static int x1000_nemc_cs1_pins[] = { 0x32, }; -static int x1000_nemc_cs2_pins[] = { 0x33, }; +static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; +static int x1000_emc_wait_pins[] = { 0x34, }; +static int x1000_emc_cs1_pins[] = { 0x32, }; +static int x1000_emc_cs2_pins[] = { 0x33, }; static int x1000_i2c0_pins[] = { 0x38, 0x37, }; static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; @@ -1078,7 +1078,7 @@ static int x1000_uart0_data_funcs[] = { 0, 0, }; static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; static int x1000_uart1_data_a_funcs[] = { 2, 2, }; static int x1000_uart1_data_d_funcs[] = { 1, 1, }; -static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; static int x1000_uart2_data_a_funcs[] = { 2, 2, }; static int x1000_uart2_data_d_funcs[] = { 0, 0, }; static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; @@ -1086,15 +1086,15 @@ static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; -static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_nemc_addr_funcs[] = { +static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_emc_addr_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; -static int x1000_nemc_rd_we_funcs[] = { 0, 0, }; -static int x1000_nemc_wait_funcs[] = { 0, }; -static int x1000_nemc_cs1_funcs[] = { 0, }; -static int x1000_nemc_cs2_funcs[] = { 0, }; +static int x1000_emc_rd_we_funcs[] = { 0, 0, }; +static int x1000_emc_wait_funcs[] = { 0, }; +static int x1000_emc_cs1_funcs[] = { 0, }; +static int x1000_emc_cs2_funcs[] = { 0, }; static int x1000_i2c0_funcs[] = { 0, 0, }; static int x1000_i2c1_a_funcs[] = { 2, 2, }; static int x1000_i2c1_c_funcs[] = { 0, 0, }; @@ -1116,7 +1116,7 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), - INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), @@ -1124,13 +1124,13 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), - INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data), - INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data), - INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr), - INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we), - INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait), - INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1), - INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2), + INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), + INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), + INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), + INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), + INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), + INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), + INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), @@ -1149,21 +1149,21 @@ static const struct group_desc x1000_groups[] = { static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *x1000_uart1_groups[] = { - "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", + "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; static const char *x1000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; static const char *x1000_mmc1_groups[] = { - "mmc1-1bit-e", "mmc1-4bit-e", + "mmc1-1bit", "mmc1-4bit", }; -static const char *x1000_nemc_groups[] = { - "nemc-8bit-data", "nemc-16bit-data", - "nemc-addr", "nemc-rd-we", "nemc-wait", +static const char *x1000_emc_groups[] = { + "emc-8bit-data", "emc-16bit-data", + "emc-addr", "emc-rd-we", "emc-wait", }; -static const char *x1000_cs1_groups[] = { "nemc-cs1", }; -static const char *x1000_cs2_groups[] = { "nemc-cs2", }; +static const char *x1000_cs1_groups[] = { "emc-cs1", }; +static const char *x1000_cs2_groups[] = { "emc-cs2", }; static const char *x1000_i2c0_groups[] = { "i2c0-data", }; static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; static const char *x1000_i2c2_groups[] = { "i2c2-data", }; @@ -1184,9 +1184,9 @@ static const struct function_desc x1000_functions[] = { { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, - { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), }, - { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, - { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, + { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, + { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, + { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, @@ -1224,11 +1224,11 @@ static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; -static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; -static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; -static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; +static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; +static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; static int x1500_i2c0_pins[] = { 0x38, 0x37, }; static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; @@ -1247,11 +1247,11 @@ static int x1500_uart0_data_funcs[] = { 0, 0, }; static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; static int x1500_uart1_data_a_funcs[] = { 2, 2, }; static int x1500_uart1_data_d_funcs[] = { 1, 1, }; -static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; static int x1500_uart2_data_a_funcs[] = { 2, 2, }; static int x1500_uart2_data_d_funcs[] = { 0, 0, }; -static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, }; -static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, }; +static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; +static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; static int x1500_i2c0_funcs[] = { 0, 0, }; static int x1500_i2c1_a_funcs[] = { 2, 2, }; static int x1500_i2c1_c_funcs[] = { 0, 0, }; @@ -1268,11 +1268,11 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), - INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), - INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit), - INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit), + INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), + INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), @@ -1288,10 +1288,10 @@ static const struct group_desc x1500_groups[] = { static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *x1500_uart1_groups[] = { - "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", + "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; -static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; static const char *x1500_i2c0_groups[] = { "i2c0-data", }; static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; static const char *x1500_i2c2_groups[] = { "i2c2-data", }; @@ -1307,7 +1307,7 @@ static const struct function_desc x1500_functions[] = { { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, - { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), }, + { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, From patchwork Wed Nov 20 13:59:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11253979 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8AA9D109A for ; Wed, 20 Nov 2019 14:00:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6174E2251E for ; Wed, 20 Nov 2019 14:00:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="rKTAGlhL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731532AbfKTOAN (ORCPT ); Wed, 20 Nov 2019 09:00:13 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25853 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727988AbfKTOAM (ORCPT ); Wed, 20 Nov 2019 09:00:12 -0500 ARC-Seal: i=1; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574258386; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=6671; bh=mLd0p/IiAqoYY8pkaDZzxBiDU673Irin2aMUWGw37wU=; b=rKTAGlhLSeY+nuAbCN2jzvHMTxY+Xba46wB0BJiy+4S6rvO+BoNteWhZw/KKMHgn MQppfbPD6pHPNbOFTJFjbTzg9cIKZ8yx7PeUYTuuWdJeU5OkDu9+QY+hP9JM37tl5Ld otWiJbA2OpqJdE/H0Zhq8LWFXvJ7taorGfzFKT2Y= Received: from zhouyanjie-virtual-machine.localdomain (171.221.112.99 [171.221.112.99]) by mx.zohomail.com with SMTPS id 1574258384969998.7896304911886; Wed, 20 Nov 2019 05:59:44 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paulburton@kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, paul@crapouillou.net, robh+dt@kernel.org, mark.rutland@arm.com, syq@debian.org Subject: [PATCH v2 2/4] pinctrl: Ingenic: Add missing parts for X1000 and X1500. Date: Wed, 20 Nov 2019 21:59:01 +0800 Message-Id: <1574258343-122458-3-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> References: <1573804011-2176-1-git-send-email-zhouyanjie@zoho.com> <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org 1.Add pinctrl drivers for the SPI flash controller (SFC) of X1000 and X1500. 2.Add pinctrl driver for the synchronous serial interface (SSI) of X1000. Signed-off-by: Zhou Yanjie --- drivers/pinctrl/pinctrl-ingenic.c | 64 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 059e39a..d578a74 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1031,6 +1031,23 @@ static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; +static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; +static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; +static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; +static int x1000_ssi_dt_d_pins[] = { 0x62, }; +static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; +static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; +static int x1000_ssi_dr_d_pins[] = { 0x63, }; +static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; +static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; +static int x1000_ssi_clk_d_pins[] = { 0x60, }; +static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; +static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; +static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; +static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; +static int x1000_ssi_ce0_d_pins[] = { 0x61, }; +static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; +static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; @@ -1081,6 +1098,23 @@ static int x1000_uart1_data_d_funcs[] = { 1, 1, }; static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; static int x1000_uart2_data_a_funcs[] = { 2, 2, }; static int x1000_uart2_data_d_funcs[] = { 0, 0, }; +static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int x1000_ssi_dt_a_22_funcs[] = { 2, }; +static int x1000_ssi_dt_a_29_funcs[] = { 2, }; +static int x1000_ssi_dt_d_funcs[] = { 0, }; +static int x1000_ssi_dr_a_23_funcs[] = { 2, }; +static int x1000_ssi_dr_a_28_funcs[] = { 2, }; +static int x1000_ssi_dr_d_funcs[] = { 0, }; +static int x1000_ssi_clk_a_24_funcs[] = { 2, }; +static int x1000_ssi_clk_a_26_funcs[] = { 2, }; +static int x1000_ssi_clk_d_funcs[] = { 0, }; +static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; +static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; +static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; +static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; +static int x1000_ssi_ce0_d_funcs[] = { 0, }; +static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; +static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; @@ -1119,6 +1153,23 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), + INGENIC_PIN_GROUP("sfc", x1000_sfc), + INGENIC_PIN_GROUP("ssi_dt_a_22", x1000_ssi_dt_a_22), + INGENIC_PIN_GROUP("ssi_dt_a_29", x1000_ssi_dt_a_29), + INGENIC_PIN_GROUP("ssi_dt_d", x1000_ssi_dt_d), + INGENIC_PIN_GROUP("ssi_dr_a_23", x1000_ssi_dr_a_23), + INGENIC_PIN_GROUP("ssi_dr_a_28", x1000_ssi_dr_a_28), + INGENIC_PIN_GROUP("ssi_dr_d", x1000_ssi_dr_d), + INGENIC_PIN_GROUP("ssi_clk_a_24", x1000_ssi_clk_a_24), + INGENIC_PIN_GROUP("ssi_clk_a_26", x1000_ssi_clk_a_26), + INGENIC_PIN_GROUP("ssi_clk_d", x1000_ssi_clk_d), + INGENIC_PIN_GROUP("ssi_gpc_a_20", x1000_ssi_gpc_a_20), + INGENIC_PIN_GROUP("ssi_gpc_a_31", x1000_ssi_gpc_a_31), + INGENIC_PIN_GROUP("ssi_ce0_a_25", x1000_ssi_ce0_a_25), + INGENIC_PIN_GROUP("ssi_ce0_a_27", x1000_ssi_ce0_a_27), + INGENIC_PIN_GROUP("ssi_ce0_d", x1000_ssi_ce0_d), + INGENIC_PIN_GROUP("ssi_ce1_a_21", x1000_ssi_ce1_a_21), + INGENIC_PIN_GROUP("ssi_ce1_a_30", x1000_ssi_ce1_a_30), INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), @@ -1152,6 +1203,15 @@ static const char *x1000_uart1_groups[] = { "uart1-data-a", "uart1-data-d", "uart1-hwflow", }; static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; +static const char *x1000_sfc_groups[] = { "sfc", }; +static const char *x1000_ssi_groups[] = { + "ssi_dt_a_22", "ssi_dt_a_29", "ssi_dt_d", + "ssi_dr_a_23", "ssi_dr_a_28", "ssi_dr_d", + "ssi_clk_a_24", "ssi_clk_a_26", "ssi_clk_d", + "ssi_gpc_a_20", "ssi_gpc_a_31", + "ssi_ce0_a_25", "ssi_ce0_a_27", "ssi_ce0_d", + "ssi_ce1_a_21", "ssi_ce1_a_30", "ssi_ce0_d", +}; static const char *x1000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", }; @@ -1182,6 +1242,8 @@ static const struct function_desc x1000_functions[] = { { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, + { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, + { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, @@ -1271,6 +1333,7 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), + INGENIC_PIN_GROUP("sfc", x1000_sfc), INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), @@ -1307,6 +1370,7 @@ static const struct function_desc x1500_functions[] = { { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, + { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, From patchwork Wed Nov 20 13:59:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11253981 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5519B109A for ; Wed, 20 Nov 2019 14:00:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3422C2235D for ; Wed, 20 Nov 2019 14:00:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="OSY6b+FN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731545AbfKTOAZ (ORCPT ); Wed, 20 Nov 2019 09:00:25 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25860 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727988AbfKTOAZ (ORCPT ); Wed, 20 Nov 2019 09:00:25 -0500 ARC-Seal: i=1; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574258392; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=1932; bh=g3a/uS3jZ22BWDXCg5h4jhLEdvlvnseJjI5K5JF+3VU=; b=OSY6b+FNll1VbamGWaK6ITKwX0VWTaEMP2a3W8gX8qkwuMzmDdbLINopUJ7YjzxK PCrvbs2KkCq8Rz/6PTY62FCxQwYsHjvTwkGLPEdxa2GH7KkYdZdXfBw5iu4ONDqbM0g DuBHwW81OV+MdcTLmEBa8pUFESWl8F3BMg+tcEgo= Received: from zhouyanjie-virtual-machine.localdomain (171.221.112.99 [171.221.112.99]) by mx.zohomail.com with SMTPS id 1574258390783834.3197646662344; Wed, 20 Nov 2019 05:59:50 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paulburton@kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, paul@crapouillou.net, robh+dt@kernel.org, mark.rutland@arm.com, syq@debian.org Subject: [PATCH v2 3/4] dt-bindings: pinctrl: Add bindings for Ingenic X1830. Date: Wed, 20 Nov 2019 21:59:02 +0800 Message-Id: <1574258343-122458-4-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> References: <1573804011-2176-1-git-send-email-zhouyanjie@zoho.com> <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add the pinctrl bindings for the X1830 Soc from Ingenic. Signed-off-by: Zhou Yanjie --- Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index 0014d98..d9b2100 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -10,9 +10,9 @@ GPIO port configuration registers and it is typical to refer to pins using the naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO -ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 -contains 6 GPIO ports, PA to PF, for a total of 192 pins. +PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830 +contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the +jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -28,6 +28,7 @@ Required properties: - "ingenic,x1000-pinctrl" - "ingenic,x1000e-pinctrl" - "ingenic,x1500-pinctrl" + - "ingenic,x1830-pinctrl" - reg: Address range of the pinctrl registers. @@ -40,6 +41,7 @@ Required properties for sub-nodes (GPIO chips): - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" - "ingenic,x1000-gpio" + - "ingenic,x1830-gpio" - reg: The GPIO bank number. - interrupt-controller: Marks the device node as an interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. From patchwork Wed Nov 20 13:59:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 11253983 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CEAF56C1 for ; Wed, 20 Nov 2019 14:00:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 921CF2235D for ; Wed, 20 Nov 2019 14:00:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=zoho.com header.i=zhouyanjie@zoho.com header.b="KAVtHAy6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730565AbfKTOAk (ORCPT ); Wed, 20 Nov 2019 09:00:40 -0500 Received: from sender4-pp-o98.zoho.com ([136.143.188.98]:25867 "EHLO sender4-pp-o98.zoho.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727988AbfKTOAk (ORCPT ); Wed, 20 Nov 2019 09:00:40 -0500 ARC-Seal: i=1; a=rsa-sha256; t=1574258400; cv=none; d=zohomail.com; s=zohoarc; b=YYLtCYA2qgvEfAgM5moO8VR/XMhk7N6Ok3zvQQ9MquT4j5nDGGzqhyY6dFmHbcq9FaGqA/14KMxSYyGOtMJMzZfWWUPbzCSoqSz+mAiWR7NH8t03bMLX9j0pSpvRLGGy6z+MwRQr8zGhuoHyzG9RPSs9Jq03FsQ5/01yEv8Jge0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1574258400; h=Cc:Date:From:In-Reply-To:Message-ID:References:Subject:To; bh=t2lhFpkqd5698+2WbfNipy/3xTYR78xDHIcfmYxuKEg=; b=HqcmNfMw2MFuAEothV7Zw7u7nJfZANnr2jt+43ewVz/uWJHUhbMvvxBMI4NLRCtUa4HfAf5xKMNZgf/E2PcxT0vvWkVxKjV3llkzBmvXNz8ZKxNDpFrUvWMTWOSsct2NJ80xK4uVTgqTq2oeYPvDjYQqSqWSRVoRWkLTN2ASpnQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=zoho.com; spf=pass smtp.mailfrom=zhouyanjie@zoho.com; dmarc=pass header.from= header.from= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=zapps768; d=zoho.com; h=from:to:cc:subject:date:message-id:in-reply-to:references; b=a/pF+8cHEq+SuJMZYnjtzfd979b69kEDacf4q0zIJ17ITLTWKcTKEveIKz7vu2vQhn2lbW/dMGH6 vhpzhp6vpwrt0DLSJYSiDR5gIG9dn9JZg1HzBnE5geUKO43ITATS DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1574258400; s=zm2019; d=zoho.com; i=zhouyanjie@zoho.com; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; l=15782; bh=t2lhFpkqd5698+2WbfNipy/3xTYR78xDHIcfmYxuKEg=; b=KAVtHAy6ilSmJM/VdPk3wZkp/Dx+Awc4wyHy+xbl3nG0Dilmgk3ReE8H9Sv1AYCO q7QenzyNw6kF5WLmZ2CiFj0IpVA5UqWtjYQ5janRxsTrFr3FdMkImLg7SXiniVP7xTI Iv+qXSkPhjuBVi/Ma0I7aUC0Gn1iAGiHDWrDgflY= Received: from zhouyanjie-virtual-machine.localdomain (171.221.112.99 [171.221.112.99]) by mx.zohomail.com with SMTPS id 1574258399968775.0086655390869; Wed, 20 Nov 2019 05:59:59 -0800 (PST) From: Zhou Yanjie To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, paulburton@kernel.org, paul.burton@mips.com, linus.walleij@linaro.org, paul@crapouillou.net, robh+dt@kernel.org, mark.rutland@arm.com, syq@debian.org Subject: [PATCH v2 4/4] pinctrl: Ingenic: Add pinctrl driver for X1830. Date: Wed, 20 Nov 2019 21:59:03 +0800 Message-Id: <1574258343-122458-5-git-send-email-zhouyanjie@zoho.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> References: <1573804011-2176-1-git-send-email-zhouyanjie@zoho.com> <1574258343-122458-1-git-send-email-zhouyanjie@zoho.com> X-ZohoMailClient: External Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add support for probing the pinctrl-ingenic driver on the X1830 Soc from Ingenic. Signed-off-by: Zhou Yanjie --- drivers/pinctrl/pinctrl-ingenic.c | 263 +++++++++++++++++++++++++++++++++++--- 1 file changed, 245 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index d578a74..554bc2c 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -28,6 +28,10 @@ #define GPIO_PIN 0x00 #define GPIO_MSK 0x20 +#define GPIO_HIZ 0x00 +#define GPIO_PULLUP 0x01 +#define GPIO_PULLDOWN 0x10 + #define JZ4740_GPIO_DATA 0x10 #define JZ4740_GPIO_PULL_DIS 0x30 #define JZ4740_GPIO_FUNC 0x40 @@ -45,6 +49,11 @@ #define X1000_GPIO_PZ_BASE 0x700 #define X1000_GPIO_PZ_GID2LD 0x7f0 +#define X1830_GPIO_PEL0 0x110 +#define X1830_GPIO_PEL1 0x120 +#define X1830_GPIO_PZ_BASE 0x7000 +#define X1830_GPIO_PZ_GID2LD 0x70f0 + #define REG_SET(x) ((x) + 0x4) #define REG_CLEAR(x) ((x) + 0x8) @@ -60,6 +69,7 @@ enum jz_version { ID_X1000, ID_X1000E, ID_X1500, + ID_X1830, }; struct ingenic_chip_info { @@ -1394,6 +1404,156 @@ static const struct ingenic_chip_info x1500_chip_info = { .pull_downs = x1000_pull_downs, }; +static const u32 x1830_pull_ups[4] = { + 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, +}; + +static const u32 x1830_pull_downs[4] = { + 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, +}; + +static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; +static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; +static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; +static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; +static int x1830_ssi0_dt_pins[] = { 0x4c, }; +static int x1830_ssi0_dr_pins[] = { 0x4b, }; +static int x1830_ssi0_clk_pins[] = { 0x4f, }; +static int x1830_ssi0_gpc_pins[] = { 0x4d, }; +static int x1830_ssi0_ce0_pins[] = { 0x50, }; +static int x1830_ssi0_ce1_pins[] = { 0x4e, }; +static int x1830_ssi1_dt_c_pins[] = { 0x53, }; +static int x1830_ssi1_dr_c_pins[] = { 0x54, }; +static int x1830_ssi1_clk_c_pins[] = { 0x57, }; +static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; +static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; +static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; +static int x1830_ssi1_dt_d_pins[] = { 0x62, }; +static int x1830_ssi1_dr_d_pins[] = { 0x63, }; +static int x1830_ssi1_clk_d_pins[] = { 0x66, }; +static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; +static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; +static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; +static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; +static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; +static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; +static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; +static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; +static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; +static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; +static int x1830_mac_pins[] = { + 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, +}; + +static int x1830_uart0_data_funcs[] = { 0, 0, }; +static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; +static int x1830_uart1_data_funcs[] = { 0, 0, }; +static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; +static int x1830_ssi0_dt_funcs[] = { 0, }; +static int x1830_ssi0_dr_funcs[] = { 0, }; +static int x1830_ssi0_clk_funcs[] = { 0, }; +static int x1830_ssi0_gpc_funcs[] = { 0, }; +static int x1830_ssi0_ce0_funcs[] = { 0, }; +static int x1830_ssi0_ce1_funcs[] = { 0, }; +static int x1830_ssi1_dt_c_funcs[] = { 1, }; +static int x1830_ssi1_dr_c_funcs[] = { 1, }; +static int x1830_ssi1_clk_c_funcs[] = { 1, }; +static int x1830_ssi1_gpc_c_funcs[] = { 1, }; +static int x1830_ssi1_ce0_c_funcs[] = { 1, }; +static int x1830_ssi1_ce1_c_funcs[] = { 1, }; +static int x1830_ssi1_dt_d_funcs[] = { 2, }; +static int x1830_ssi1_dr_d_funcs[] = { 2, }; +static int x1830_ssi1_clk_d_funcs[] = { 2, }; +static int x1830_ssi1_gpc_d_funcs[] = { 2, }; +static int x1830_ssi1_ce0_d_funcs[] = { 2, }; +static int x1830_ssi1_ce1_d_funcs[] = { 2, }; +static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; +static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; +static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; +static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; +static int x1830_i2c0_funcs[] = { 1, 1, }; +static int x1830_i2c1_funcs[] = { 0, 0, }; +static int x1830_i2c2_funcs[] = { 1, 1, }; +static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + +static const struct group_desc x1830_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), + INGENIC_PIN_GROUP("sfc", x1830_sfc), + INGENIC_PIN_GROUP("ssi0_dt", x1830_ssi0_dt), + INGENIC_PIN_GROUP("ssi0_dr", x1830_ssi0_dr), + INGENIC_PIN_GROUP("ssi0_clk", x1830_ssi0_clk), + INGENIC_PIN_GROUP("ssi0_gpc", x1830_ssi0_gpc), + INGENIC_PIN_GROUP("ssi0_ce0", x1830_ssi0_ce0), + INGENIC_PIN_GROUP("ssi0_ce1", x1830_ssi0_ce1), + INGENIC_PIN_GROUP("ssi1_dt_c", x1830_ssi1_dt_c), + INGENIC_PIN_GROUP("ssi1_dr_c", x1830_ssi1_dr_c), + INGENIC_PIN_GROUP("ssi1_clk_c", x1830_ssi1_clk_c), + INGENIC_PIN_GROUP("ssi1_gpc_c", x1830_ssi1_gpc_c), + INGENIC_PIN_GROUP("ssi1_ce0_c", x1830_ssi1_ce0_c), + INGENIC_PIN_GROUP("ssi1_ce1_c", x1830_ssi1_ce1_c), + INGENIC_PIN_GROUP("ssi1_dt_d", x1830_ssi1_dt_d), + INGENIC_PIN_GROUP("ssi1_dr_d", x1830_ssi1_dr_d), + INGENIC_PIN_GROUP("ssi1_clk_d", x1830_ssi1_clk_d), + INGENIC_PIN_GROUP("ssi1_gpc_d", x1830_ssi1_gpc_d), + INGENIC_PIN_GROUP("ssi1_ce0_d", x1830_ssi1_ce0_d), + INGENIC_PIN_GROUP("ssi1_ce1_d", x1830_ssi1_ce1_d), + INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), + INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), + INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), + INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), + INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), + INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), + INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), + INGENIC_PIN_GROUP("mac", x1830_mac), +}; + +static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x1830_uart1_groups[] = { "uart1-data", }; +static const char *x1830_sfc_groups[] = { "sfc", }; +static const char *x1830_ssi0_groups[] = { + "ssi0_dt", "ssi0_dr", "ssi0_clk", "ssi0_gpc", "ssi0_ce0", "ssi0_ce1", +}; +static const char *x1830_ssi1_groups[] = { + "ssi1_dt_c", "ssi1_dt_d", + "ssi1_dr_c", "ssi1_dr_d", + "ssi1_clk_c", "ssi1_clk_d", + "ssi1_gpc_c", "ssi1_gpc_d", + "ssi1_ce0_c", "ssi1_ce0_d", + "ssi1_ce1_c", "ssi1_ce1_d", +}; +static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; +static const char *x1830_i2c0_groups[] = { "i2c0-data", }; +static const char *x1830_i2c1_groups[] = { "i2c1-data", }; +static const char *x1830_i2c2_groups[] = { "i2c2-data", }; +static const char *x1830_mac_groups[] = { "mac", }; + +static const struct function_desc x1830_functions[] = { + { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, + { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, + { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, + { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, + { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, + { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, + { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, + { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, + { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, + { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, + { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, +}; + +static const struct ingenic_chip_info x1830_chip_info = { + .num_chips = 4, + .groups = x1830_groups, + .num_groups = ARRAY_SIZE(x1830_groups), + .functions = x1830_functions, + .num_functions = ARRAY_SIZE(x1830_functions), + .pull_ups = x1830_pull_ups, + .pull_downs = x1830_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -1422,13 +1582,20 @@ static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, else reg = REG_CLEAR(reg); - regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); + if (jzgc->jzpc->version >= ID_X1830) + regmap_write(jzgc->jzpc->map, X1830_GPIO_PZ_BASE + reg, BIT(offset)); + else + regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); } static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) { - regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD, - jzgc->gc.base / PINS_PER_GPIO_CHIP); + if (jzgc->jzpc->version >= ID_X1830) + regmap_write(jzgc->jzpc->map, X1830_GPIO_PZ_GID2LD, + jzgc->gc.base / PINS_PER_GPIO_CHIP); + else + regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD, + jzgc->gc.base / PINS_PER_GPIO_CHIP); } static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, @@ -1670,8 +1837,12 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, unsigned int idx = pin % PINS_PER_GPIO_CHIP; unsigned int offt = pin / PINS_PER_GPIO_CHIP; - regmap_write(jzpc->map, offt * 0x100 + - (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); + if (jzpc->version >= ID_X1830) + regmap_write(jzpc->map, offt * 0x1000 + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); + else + regmap_write(jzpc->map, offt * 0x100 + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); } static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, @@ -1679,14 +1850,23 @@ static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, { unsigned int idx = pin % PINS_PER_GPIO_CHIP; - regmap_write(jzpc->map, X1000_GPIO_PZ_BASE + - (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); + if (jzpc->version >= ID_X1830) + regmap_write(jzpc->map, X1830_GPIO_PZ_BASE + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); + else + regmap_write(jzpc->map, X1000_GPIO_PZ_BASE + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); } static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, unsigned int pin) { - regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP); + if (jzpc->version >= ID_X1830) + regmap_write(jzpc->map, X1830_GPIO_PZ_GID2LD, + pin / PINS_PER_GPIO_CHIP); + else + regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, + pin / PINS_PER_GPIO_CHIP); } static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, @@ -1696,7 +1876,10 @@ static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, unsigned int offt = pin / PINS_PER_GPIO_CHIP; unsigned int val; - regmap_read(jzpc->map, offt * 0x100 + reg, &val); + if (jzpc->version >= ID_X1830) + regmap_read(jzpc->map, offt * 0x1000 + reg, &val); + else + regmap_read(jzpc->map, offt * 0x100 + reg, &val); return val & BIT(idx); } @@ -1857,12 +2040,48 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, } static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, - unsigned int pin, bool enabled) + unsigned int pin, unsigned int bias) { - if (jzpc->version >= ID_JZ4760) - ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled); + if (jzpc->version >= ID_X1830) { + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + + if (bias == GPIO_HIZ) { + if (idx < (PINS_PER_GPIO_CHIP / 2)) + regmap_write(jzpc->map, offt * 0x1000 + + REG_CLEAR(X1830_GPIO_PEL0), BIT(idx * 2) * 3); + else + regmap_write(jzpc->map, offt * 0x1000 + + REG_CLEAR(X1830_GPIO_PEL1), BIT(idx % 16 * 2) * 3); + } else if (bias == GPIO_PULLUP) { + if (idx < (PINS_PER_GPIO_CHIP / 2)) { + regmap_write(jzpc->map, offt * 0x1000 + + REG_SET(X1830_GPIO_PEL0), BIT(idx * 2)); + regmap_write(jzpc->map, offt * 0x1000 + + REG_CLEAR(X1830_GPIO_PEL0), BIT(idx * 2) * 2); + } else { + regmap_write(jzpc->map, offt * 0x1000 + + REG_SET(X1830_GPIO_PEL1), BIT(idx % 16 * 2)); + regmap_write(jzpc->map, offt * 0x1000 + + REG_CLEAR(X1830_GPIO_PEL1), BIT(idx % 16 * 2) * 2); + } + } else { + if (idx < (PINS_PER_GPIO_CHIP / 2)) { + regmap_write(jzpc->map, offt * 0x1000 + + REG_CLEAR(X1830_GPIO_PEL0), BIT(idx * 2)); + regmap_write(jzpc->map, offt * 0x1000 + + REG_SET(X1830_GPIO_PEL0), BIT(idx * 2) * 2); + } else { + regmap_write(jzpc->map, offt * 0x1000 + + REG_CLEAR(X1830_GPIO_PEL1), BIT(idx % 16 * 2)); + regmap_write(jzpc->map, offt * 0x1000 + + REG_SET(X1830_GPIO_PEL1), BIT(idx % 16 * 2) * 2); + } + } + } else if (jzpc->version >= ID_JZ4760) + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); else - ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled); + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); } static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, @@ -1889,7 +2108,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_BIAS_DISABLE: dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 'A' + offt, idx); - ingenic_set_bias(jzpc, pin, false); + ingenic_set_bias(jzpc, pin, GPIO_HIZ); break; case PIN_CONFIG_BIAS_PULL_UP: @@ -1897,7 +2116,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 'A' + offt, idx); - ingenic_set_bias(jzpc, pin, true); + ingenic_set_bias(jzpc, pin, GPIO_PULLUP); break; case PIN_CONFIG_BIAS_PULL_DOWN: @@ -1905,7 +2124,7 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 'A' + offt, idx); - ingenic_set_bias(jzpc, pin, true); + ingenic_set_bias(jzpc, pin, GPIO_PULLDOWN); break; default: @@ -1987,6 +2206,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 }, + { .compatible = "ingenic,x1830-pinctrl", .data = (void *) ID_X1830 }, {}, }; @@ -1996,6 +2216,7 @@ static const struct of_device_id ingenic_gpio_of_match[] __initconst = { { .compatible = "ingenic,jz4770-gpio", }, { .compatible = "ingenic,jz4780-gpio", }, { .compatible = "ingenic,x1000-gpio", }, + { .compatible = "ingenic,x1830-gpio", }, {}, }; @@ -2018,7 +2239,10 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, return -ENOMEM; jzgc->jzpc = jzpc; - jzgc->reg_base = bank * 0x100; + if (jzpc->version >= ID_X1830) + jzgc->reg_base = bank * 0x1000; + else + jzgc->reg_base = bank * 0x100; jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); if (!jzgc->gc.label) @@ -2111,7 +2335,9 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) else jzpc->version = (enum jz_version)id->driver_data; - if (jzpc->version >= ID_X1500) + if (jzpc->version >= ID_X1830) + chip_info = &x1830_chip_info; + else if (jzpc->version >= ID_X1500) chip_info = &x1500_chip_info; else if (jzpc->version >= ID_X1000E) chip_info = &x1000e_chip_info; @@ -2208,6 +2434,7 @@ static const struct platform_device_id ingenic_pinctrl_ids[] = { { "x1000-pinctrl", ID_X1000 }, { "x1000e-pinctrl", ID_X1000E }, { "x1500-pinctrl", ID_X1500 }, + { "x1830-pinctrl", ID_X1830 }, {}, };