From patchwork Thu Nov 21 03:20:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anvesh Salveru X-Patchwork-Id: 11255261 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B96B5913 for ; Thu, 21 Nov 2019 03:21:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8F46E208D4 for ; Thu, 21 Nov 2019 03:21:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="FEB9UpPF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727534AbfKUDUl (ORCPT ); Wed, 20 Nov 2019 22:20:41 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:18898 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727515AbfKUDUk (ORCPT ); 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Thu, 21 Nov 2019 12:20:37 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20191121032036epcas5p1ec12cabed1104c131a3cab202a180c21~ZD1z1c92w2857128571epcas5p1J; Thu, 21 Nov 2019 03:20:36 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20191121032036epsmtrp1a6336e44477a887e1a22d9c76edaada5~ZD1z0sUHs0943209432epsmtrp1C; Thu, 21 Nov 2019 03:20:36 +0000 (GMT) X-AuditID: b6c32a4a-3cbff70000001133-5c-5dd60285df84 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 16.1C.03654.48206DD5; Thu, 21 Nov 2019 12:20:36 +0900 (KST) Received: from ubuntu.sa.corp.samsungelectronics.net (unknown [107.108.83.125]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191121032034epsmtip25a429275ad648a37efb20d8c671e49c8~ZD1yLlJ3H2680226802epsmtip2X; Thu, 21 Nov 2019 03:20:34 +0000 (GMT) From: Anvesh Salveru To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, pankaj.dubey@samsung.com, lorenzo.pieralisi@arm.com, andrew.murray@arm.com, bhelgaas@google.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, Anvesh Salveru Subject: [PATCH v4 1/2] phy: core: add phy_property_present method Date: Thu, 21 Nov 2019 08:50:07 +0530 Message-Id: <1574306408-4360-2-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574306408-4360-1-git-send-email-anvesh.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42LZdlhTQ7eV6Vqswb7lfBbN/7ezWpzdtZDV YklThsWuux3sFiu+zGS3uPC0h83i8q45bBZn5x1ns3jz+wW7xdLrF5ksFm39wm7RuvcIuwOP x5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXps2f+Z0eP4je1MHp83yQVwRHHZpKTmZJalFunb JXBl/L93lbHgiETFgnnaDYzdIl2MHBwSAiYSax9pdjFycQgJ7GaUeL72EyOE84lR4lfbT3YI 5xujRNfZ2cxdjJxgHW/OvGGCSOxllGj5thzKaWGS+LW4lRGkik1AW+Ln0b3sILaIgLXE4fYt bCBFzAL/GCWufpkHViQs4CTxfd4isLEsAqoSp79PYAKxeQWcJXYcXccOsU5O4ua5TrAaTgEX iaZb28G2SQhcZ5O49fooG0SRi8Tuib9YIWxhiVfHt0A1S0m87G+DsvMleu8uhbJrJKbc7WCE sO0lDlyZwwIKDWYBTYn1u/RBwswCfBK9v58wQQKJV6KjTQjCVJJom1kN0SghsXj+TWigeEhc OfebGRIO0xklTr56wDqBUXYWwtAFjIyrGCVTC4pz01OLTQuM8lLL9YoTc4tL89L1kvNzNzGC U4iW1w7GZed8DjEKcDAq8fBmaFyNFWJNLCuuzD3EKMHBrCTCu+f6lVgh3pTEyqrUovz4otKc 1OJDjNIcLErivJNYr8YICaQnlqRmp6YWpBbBZJk4OKUaGLeK6vMzyMxqr+bozD/QFjx7Xav+ k23x2uZqZYnNHbs2pVRHm5c1z+yMUitlCEt62vpS3Xm982GBosvWB38WNE1bMv2l25ymyT57 L+2NdTi1wviIi2sf98lfckqsjW8sHRIs1QzecT+9uYJX+tjxZTcnpLc+T3n6uvzAsr2im7Yo i5W8XD3zthJLcUaioRZzUXEiAI+ob8UdAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWy7bCSvG4L07VYg5ufVCya/29ntTi7ayGr xZKmDItddzvYLVZ8mcluceFpD5vF5V1z2CzOzjvOZvHm9wt2i6XXLzJZLNr6hd2ide8Rdgce jzXz1jB67Jx1l91jwaZSj02rOtk8+rasYvTYsv8zo8fxG9uZPD5vkgvgiOKySUnNySxLLdK3 S+DK+H/vKmPBEYmKBfO0Gxi7RboYOTkkBEwk3px5w9TFyMUhJLCbUeLYnUWMEAkJiS97v7JB 2MISK/89Z4coamKS+LJgIhNIgk1AW+Ln0b3sILaIgK3E/UeTWUGKmAW6mCTWnt4ClhAWcJL4 Pm8RM4jNIqAqcfr7BLBmXgFniR1H17FDbJCTuHmuE6yGU8BFounWdrAaIaCa3Vdusk5g5FvA yLCKUTK1oDg3PbfYsMAwL7Vcrzgxt7g0L10vOT93EyM4hLU0dzBeXhJ/iFGAg1GJhzdD42qs EGtiWXFl7iFGCQ5mJRHePdevxArxpiRWVqUW5ccXleakFh9ilOZgURLnfZp3LFJIID2xJDU7 NbUgtQgmy8TBKdXAKPE0atG+vUq2HXO+xbJeUrjkYHc2Nedm776oLguhT56xjzkqdVTnWe9I NWuXLFm26JLcrqVHb67l8ZDtYDjw4Pe0D2f+R2b9NBFSZjf4yfyqVrN6T+tR5l9MXdZnJ1tw 7Gg+GPIv/+O1U5/nCVSKs805H/1g9dbJcd85e0N17rvqTNY86VlYqMRSnJFoqMVcVJwIAFhr 3ihdAgAA X-CMS-MailID: 20191121032036epcas5p1ec12cabed1104c131a3cab202a180c21 X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20191121032036epcas5p1ec12cabed1104c131a3cab202a180c21 References: <1574306408-4360-1-git-send-email-anvesh.s@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In some platforms, we need information of phy properties in the controller drivers. This patch adds a new phy_property_present() method which can be used to check if some property exists in PHY or not. In case of DesignWare PCIe controller, we need to write into controller register to specify about ZRX-DC compliance property of the PHY, which reduces the power consumption during lower power states. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- drivers/phy/phy-core.c | 26 ++++++++++++++++++++++++++ include/linux/phy/phy.h | 8 ++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index b04f4fe..0a62eca 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -420,6 +420,32 @@ int phy_calibrate(struct phy *phy) EXPORT_SYMBOL_GPL(phy_calibrate); /** + * phy_property_present() - checks if the property is present in PHY + * @phy: the phy returned by phy_get() + * @property: name of the property to check + * + * Used to check if the given property is present in PHY. PHY drivers + * can implement this callback function to expose PHY properties to + * controller drivers. + * + * Returns: true if property exists, false otherwise + */ +bool phy_property_present(struct phy *phy, const char *property) +{ + bool ret; + + if (!phy || !phy->ops->property_present) + return false; + + mutex_lock(&phy->mutex); + ret = phy->ops->property_present(phy, property); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_property_present); + +/** * phy_configure() - Changes the phy parameters * @phy: the phy returned by phy_get() * @opts: New configuration to apply diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 15032f14..3dd8f3c 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -61,6 +61,7 @@ union phy_configure_opts { * @reset: resetting the phy * @calibrate: calibrate the phy * @release: ops to be performed while the consumer relinquishes the PHY + * @property_present: check if some property is present in PHY * @owner: the module owner containing the ops */ struct phy_ops { @@ -103,6 +104,7 @@ struct phy_ops { int (*reset)(struct phy *phy); int (*calibrate)(struct phy *phy); void (*release)(struct phy *phy); + bool (*property_present)(struct phy *phy, const char *property); struct module *owner; }; @@ -217,6 +219,7 @@ static inline enum phy_mode phy_get_mode(struct phy *phy) } int phy_reset(struct phy *phy); int phy_calibrate(struct phy *phy); +bool phy_property_present(struct phy *phy, const char *property); static inline int phy_get_bus_width(struct phy *phy) { return phy->attrs.bus_width; @@ -354,6 +357,11 @@ static inline int phy_calibrate(struct phy *phy) return -ENOSYS; } +static inline bool phy_property_present(struct phy *phy, const char *property) +{ + return false; +} + static inline int phy_configure(struct phy *phy, union phy_configure_opts *opts) { From patchwork Thu Nov 21 03:20:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anvesh Salveru X-Patchwork-Id: 11255245 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30B89112B for ; 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Thu, 21 Nov 2019 03:20:41 +0000 (GMT) X-AuditID: b6c32a4a-3b3ff70000001133-67-5dd60289765d Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2new.samsung.com (Symantec Messaging Gateway) with SMTP id E1.CE.03814.88206DD5; Thu, 21 Nov 2019 12:20:41 +0900 (KST) Received: from ubuntu.sa.corp.samsungelectronics.net (unknown [107.108.83.125]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20191121032039epsmtip28cdd1dc39af89a4660c7300bb6a97ae6~ZD12Tw9m82815928159epsmtip2D; Thu, 21 Nov 2019 03:20:39 +0000 (GMT) From: Anvesh Salveru To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, pankaj.dubey@samsung.com, lorenzo.pieralisi@arm.com, andrew.murray@arm.com, bhelgaas@google.com, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, Anvesh Salveru Subject: [PATCH v4 2/2] PCI: dwc: add support to handle ZRX-DC Compliant PHYs Date: Thu, 21 Nov 2019 08:50:08 +0530 Message-Id: <1574306408-4360-3-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574306408-4360-1-git-send-email-anvesh.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgleLIzCtJLcpLzFFi42LZdlhTU7eT6VqswecdEhbN/7ezWpzdtZDV YklThsWuux3sFiu+zGS3uPC0h83i8q45bBZn5x1ns3jz+wW7xdLrF5ksFm39wm7RuvcIuwOP x5p5axg9ds66y+6xYFOpx6ZVnWwefVtWMXps2f+Z0eP4je1MHp83yQVwRHHZpKTmZJalFunb JXBlHOydy1jQJ1Sx4Vt1A+Nm/i5GDg4JAROJptMZXYxcHEICuxkl7vx9wAjhfGKU6F7dxwzh fGOUOLrmJRNMx9zfORDxvYwSG95uYO1i5ARyWpgkOn9agNhsAtoSP4/uZQexRQSsJQ63b2ED aWAW+McocfXLPEaQhLCAv8T5vrVsIDaLgKrEhTXbwOK8As4Srw9MBotLCMhJ3DzXyQxicwq4 SDTd2s4EMkhC4DqbxKpnnVBFLhIHVs6HsoUlXh3fwg5hS0l8frcXKp4v0Xt3KVS8RmLK3Q5G CNte4sCVOSwgnzELaEqs36UPEmYW4JPo/f0E6mFeiY42IQhTSaJtZjVEo4TE4vk3mSFsD4l/ W2ZAw2o6o8SrmSdYJzDKzkIYuoCRcRWjZGpBcW56arFpgVFearlecWJucWleul5yfu4mRnD6 0PLawbjsnM8hRgEORiUe3gyNq7FCrIllxZW5hxglOJiVRHj3XL8SK8SbklhZlVqUH19UmpNa fIhRmoNFSZx3EuvVGCGB9MSS1OzU1ILUIpgsEwenVAPjhPNyiaH8Qnc+vP/su83Q6JljsXvx +dSE0t2/bQ5kJV49fzxVLHKhq+pS2/vhTDy/Y2yuOlqH8jm8Xij6qb4j2WraY+v2Kr03LHfn u9j+Ug14VfnzscjhBjZ3Li2fZ0HqHakakfM6Kowz2i4uZ5izvSIpZMJW5Sniu6d/Fs6VDTK4 +lQwwlaJpTgj0VCLuag4EQDe6bCxGwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJLMWRmVeSWpSXmKPExsWy7bCSvG4n07VYg42nmSya/29ntTi7ayGr xZKmDItddzvYLVZ8mcluceFpD5vF5V1z2CzOzjvOZvHm9wt2i6XXLzJZLNr6hd2ide8Rdgce jzXz1jB67Jx1l91jwaZSj02rOtk8+rasYvTYsv8zo8fxG9uZPD5vkgvgiOKySUnNySxLLdK3 S+DKONg7l7GgT6hiw7fqBsbN/F2MHBwSAiYSc3/ndDFycQgJ7GaUWLr0AnsXIydQXELiy96v bBC2sMTKf8/ZIYqamCRubLsElmAT0Jb4eXQvWIOIgK3E/UeTWUGKmAW6mCTWnt4ClhAW8JWY faqPBcRmEVCVuLBmGyOIzSvgLPH6wGSoDXISN891MoPYnAIuEk23tjOB2EJANbuv3GSdwMi3 gJFhFaNkakFxbnpusWGBUV5quV5xYm5xaV66XnJ+7iZGcABrae1gPHEi/hCjAAejEg9vhsbV WCHWxLLiytxDjBIczEoivHuuX4kV4k1JrKxKLcqPLyrNSS0+xCjNwaIkziuffyxSSCA9sSQ1 OzW1ILUIJsvEwSnVwGjZsu3f5SC/6SLqCR11edLP+pRWvKlhCedd+fLUu4n9BxV3L5yYILuI JSatICr8/zW+1XvOPd7wyuHg08cT1/AZxHz9ZKpwKbWncLeAWUKLWCbffE6LwlKHerWWFoMe 01o/rWX2fupGH//ztB7YzrO4IIP7NMPhVd4FGYHpCkGL3ft9bZ4JKbEUZyQaajEXFScCANJD jUxcAgAA X-CMS-MailID: 20191121032041epcas5p433066ebc6a07b73a1949da26e55e9b2f X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20191121032041epcas5p433066ebc6a07b73a1949da26e55e9b2f References: <1574306408-4360-1-git-send-email-anvesh.s@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Many platforms use DesignWare controller but the PHY can be different in different platforms. If the PHY is compliant is to ZRX-DC specification it helps in low power consumption during power states. If current data rate is 8.0 GT/s or higher and PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states. DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY. Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable to specify this property to the controller. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 820488d..36a01b7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci) PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + + if (pci->phy_zrxdc_compliant) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5a18e94..f43f986 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -60,6 +60,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0) + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) #define PCIE_ATU_REGION_OUTBOUND 0 @@ -249,6 +252,7 @@ struct dw_pcie { void __iomem *atu_base; u32 num_viewport; u8 iatu_unroll_enabled; + bool phy_zrxdc_compliant; struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops;