From patchwork Thu Jul 26 15:35:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546039 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F1C8A639 for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 784602B7BF for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 765D02B7BA; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17C982B7C0 for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731671AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45326 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731764AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y0063XaVaC01TbN9b; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008UH-0s; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIT-0002cd-Vh; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 01/11] clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider Date: Thu, 26 Jul 2018 17:35:07 +0200 Message-Id: <20180726153517.10020-2-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a clock type and macro for defining clocks using the OSC EXTAL predivider combined with a fixed divider. On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and thus must be specified in the configuration structure. Inspired by a patch in the BSP by Takeshi Kihara . Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by. --- drivers/clk/renesas/rcar-gen3-cpg.c | 7 +++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 628b63b85d3f09c5..7533a51c679bfd54 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -563,6 +563,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK); + case CLK_TYPE_GEN3_OSC: + /* + * Clock combining OSC EXTAL predivider and a fixed divider + */ + div = cpg_pll_config->osc_prediv * core->div; + break; + default: return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index ea4f8fc3c4c972e7..d7d84d9e4a1c9c8b 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PE, CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, + CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ @@ -33,6 +34,8 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ (_parent_sscg) << 16 | (_parent_clean), \ .div = (_div_sscg) << 16 | (_div_clean)) +#define DEF_GEN3_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) struct rcar_gen3_cpg_pll_config { u8 extal_div; @@ -40,6 +43,7 @@ struct rcar_gen3_cpg_pll_config { u8 pll1_div; u8 pll3_mult; u8 pll3_div; + u8 osc_prediv; }; #define CPG_RCKCR 0x240 From patchwork Thu Jul 26 15:35:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FE2014E0 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1EAEA2B776 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1AC282AFF3; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2A552B7B6 for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731649AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:40410 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731732AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by xavier.telenet-ops.be with bizsmtp id FTbN1y0033XaVaC01TbNHX; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008UJ-1U; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002cf-0Z; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 02/11] clk: renesas: r8a7795: Add OSC EXTAL predivider configuration Date: Thu, 26 Jul 2018 17:35:08 +0200 Message-Id: <20180726153517.10020-3-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car H3 ES2.0. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car H3 SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara . Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rebase. --- drivers/clk/renesas/r8a7795-cpg-mssr.c | 66 +++++++++++++------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index ccaea9e1849d9330..ca8cb0eed950161c 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -73,7 +73,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), @@ -113,7 +113,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), - DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8), DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; @@ -284,25 +284,25 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = { */ /* - * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC * 14 13 19 17 (MHz) - *------------------------------------------------------------------- - * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 - * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + *------------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 * 0 0 1 0 Prohibited setting - * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 - * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 - * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 * 0 1 1 0 Prohibited setting - * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 - * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 - * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 * 1 0 1 0 Prohibited setting - * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 - * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 - * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 * 1 1 1 0 Prohibited setting - * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ (((md) & BIT(13)) >> 11) | \ @@ -310,23 +310,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = { (((md) & BIT(17)) >> 17)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { - /* EXTAL div PLL1 mult/div PLL3 mult/div */ - { 1, 192, 1, 192, 1, }, - { 1, 192, 1, 128, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 192, 1, 192, 1, }, - { 1, 160, 1, 160, 1, }, - { 1, 160, 1, 106, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 160, 1, 160, 1, }, - { 1, 128, 1, 128, 1, }, - { 1, 128, 1, 84, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 128, 1, 128, 1, }, - { 2, 192, 1, 192, 1, }, - { 2, 192, 1, 128, 1, }, - { 0, /* Prohibited setting */ }, - { 2, 192, 1, 192, 1, }, + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 192, 1, 128, 1, 16, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 160, 1, 106, 1, 19, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 128, 1, 128, 1, 24, }, + { 1, 128, 1, 84, 1, 24, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, 24, }, + { 2, 192, 1, 192, 1, 32, }, + { 2, 192, 1, 128, 1, 32, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, 32, }, }; static const struct soc_device_attribute r8a7795es1[] __initconst = { From patchwork Thu Jul 26 15:35:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546073 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38E5014E0 for ; Thu, 26 Jul 2018 15:35:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 26A9A2B776 for ; Thu, 26 Jul 2018 15:35:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 224742B713; Thu, 26 Jul 2018 15:35:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F1F02B7A5 for ; Thu, 26 Jul 2018 15:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731231AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:40422 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731662AbeGZQwp (ORCPT ); Thu, 26 Jul 2018 12:52:45 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by xavier.telenet-ops.be with bizsmtp id FTbN1y0043XaVaC01TbNHY; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008UO-2I; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002ci-1E; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 03/11] clk: renesas: r8a7796: Add OSC EXTAL predivider configuration Date: Thu, 26 Jul 2018 17:35:09 +0200 Message-Id: <20180726153517.10020-4-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.0.53, the CPG_RCKCR register was removed in R-Car M3-W ES1.1. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car M3-W SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara . Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rebase. --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 66 +++++++++++++------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 6a4ef3d04aa060bc..7e98fb8b1074c298 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -73,7 +73,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), @@ -112,7 +112,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250), - DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8), DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; @@ -256,25 +256,25 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = { */ /* - * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC * 14 13 19 17 (MHz) - *------------------------------------------------------------------- - * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 - * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + *------------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 * 0 0 1 0 Prohibited setting - * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 - * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 - * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 * 0 1 1 0 Prohibited setting - * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 - * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 - * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 * 1 0 1 0 Prohibited setting - * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 - * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 - * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 * 1 1 1 0 Prohibited setting - * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ (((md) & BIT(13)) >> 11) | \ @@ -282,23 +282,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = { (((md) & BIT(17)) >> 17)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { - /* EXTAL div PLL1 mult/div PLL3 mult/div */ - { 1, 192, 1, 192, 1, }, - { 1, 192, 1, 128, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 192, 1, 192, 1, }, - { 1, 160, 1, 160, 1, }, - { 1, 160, 1, 106, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 160, 1, 160, 1, }, - { 1, 128, 1, 128, 1, }, - { 1, 128, 1, 84, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 128, 1, 128, 1, }, - { 2, 192, 1, 192, 1, }, - { 2, 192, 1, 128, 1, }, - { 0, /* Prohibited setting */ }, - { 2, 192, 1, 192, 1, }, + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 192, 1, 128, 1, 16, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 160, 1, 106, 1, 19, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 128, 1, 128, 1, 24, }, + { 1, 128, 1, 84, 1, 24, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, 24, }, + { 2, 192, 1, 192, 1, 32, }, + { 2, 192, 1, 128, 1, 32, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a7796_cpg_mssr_init(struct device *dev) From patchwork Thu Jul 26 15:35:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9340AA65F for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A9C12B5DC for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 78B5D2B775; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F79A2B7AF for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731803AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:40440 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731730AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by xavier.telenet-ops.be with bizsmtp id FTbN1y0063XaVaC01TbNHZ; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008US-2x; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002cl-1v; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 04/11] clk: renesas: r8a77965: Add OSC EXTAL predivider configuration Date: Thu, 26 Jul 2018 17:35:10 +0200 Message-Id: <20180726153517.10020-5-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC and RINT RCLK clocks. Hence augment the configuration structure with all documented predivider values. According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car M3-N does not have the CPG_RCKCR register. Change the OSC and RINT clock definitions to use the OSC EXTAL predivider instead, which is supported on all R-Car M3-N SoC revisions. Inspired by a patch in the BSP by Takeshi Kihara . Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rebase. --- drivers/clk/renesas/r8a77965-cpg-mssr.c | 66 ++++++++++++------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 7a7eb9658058a09e..c596e2afaeeb3ea2 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -68,7 +68,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), @@ -106,7 +106,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250), - DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8), DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; @@ -253,25 +253,25 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = { */ /* - * MD EXTAL PLL0 PLL1 PLL3 PLL4 + * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC * 14 13 19 17 (MHz) - *----------------------------------------------------------- - * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 - * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 + *----------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16 + * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16 * 0 0 1 0 Prohibited setting - * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 - * 0 1 0 0 20 x 1 x150 x160 x160 x120 - * 0 1 0 1 20 x 1 x150 x160 x106 x120 + * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16 + * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19 + * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19 * 0 1 1 0 Prohibited setting - * 0 1 1 1 20 x 1 x150 x160 x160 x120 - * 1 0 0 0 25 x 1 x120 x128 x128 x96 - * 1 0 0 1 25 x 1 x120 x128 x84 x96 + * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19 + * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24 + * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24 * 1 0 1 0 Prohibited setting - * 1 0 1 1 25 x 1 x120 x128 x128 x96 - * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 - * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 + * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24 + * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32 + * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32 * 1 1 1 0 Prohibited setting - * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 + * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ (((md) & BIT(13)) >> 11) | \ @@ -279,23 +279,23 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = { (((md) & BIT(17)) >> 17)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { - /* EXTAL div PLL1 mult/div PLL3 mult/div */ - { 1, 192, 1, 192, 1, }, - { 1, 192, 1, 128, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 192, 1, 192, 1, }, - { 1, 160, 1, 160, 1, }, - { 1, 160, 1, 106, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 160, 1, 160, 1, }, - { 1, 128, 1, 128, 1, }, - { 1, 128, 1, 84, 1, }, - { 0, /* Prohibited setting */ }, - { 1, 128, 1, 128, 1, }, - { 2, 192, 1, 192, 1, }, - { 2, 192, 1, 128, 1, }, - { 0, /* Prohibited setting */ }, - { 2, 192, 1, 192, 1, }, + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 192, 1, 128, 1, 16, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 160, 1, 106, 1, 19, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 128, 1, 128, 1, 24, }, + { 1, 128, 1, 84, 1, 24, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, 24, }, + { 2, 192, 1, 192, 1, 32, }, + { 2, 192, 1, 128, 1, 32, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a77965_cpg_mssr_init(struct device *dev) From patchwork Thu Jul 26 15:35:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546061 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5340BA661 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 438192B6E0 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40DFF2B7BA; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B9E252B76D for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731730AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45344 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731784AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y00B3XaVaC01TbN9c; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008UW-3o; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002co-2d; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 05/11] clk: renesas: r8a77980: Add OSC predivider configuration and clock Date: Thu, 26 Jul 2018 17:35:11 +0200 Message-Id: <20180726153517.10020-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the OSC clock. Hence augment the configuration structure with all documented predivider values. Add the OSC clock using the configured predivider. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Fix predivider for 27 MHz EXTAL (table under Table 8.2e wrongly uses 25 MHz). --- drivers/clk/renesas/r8a77980-cpg-mssr.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index d7ebd9ec00594fc8..a8b8d8613b46dd3c 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -96,6 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), + + DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8), }; static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { @@ -171,23 +173,23 @@ static const unsigned int r8a77980_crit_mod_clks[] __initconst = { */ /* - * MD EXTAL PLL2 PLL1 PLL3 + * MD EXTAL PLL2 PLL1 PLL3 OSC * 14 13 (MHz) - * -------------------------------------------------- - * 0 0 16.66 x 1 x240 x192 x192 - * 0 1 20 x 1 x200 x160 x160 - * 1 0 27 x 1 x148 x118 x118 - * 1 1 33.33 / 2 x240 x192 x192 + * -------------------------------------------------------- + * 0 0 16.66 x 1 x240 x192 x192 /16 + * 0 1 20 x 1 x200 x160 x160 /19 + * 1 0 27 x 1 x148 x118 x118 /26 + * 1 1 33.33 / 2 x240 x192 x192 /32 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { - /* EXTAL div PLL1 mult/div PLL3 mult/div */ - { 1, 192, 1, 192, 1, }, - { 1, 160, 1, 160, 1, }, - { 1, 118, 1, 118, 1, }, - { 2, 192, 1, 192, 1, }, + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 118, 1, 118, 1, 26, }, + { 2, 192, 1, 192, 1, 32, }, }; static int __init r8a77980_cpg_mssr_init(struct device *dev) From patchwork Thu Jul 26 15:35:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCCFE1805 for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC0112B7C2 for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B9BF12B6D7; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5299F2B6D7 for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731518AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:40452 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731721AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by xavier.telenet-ops.be with bizsmtp id FTbN1y00A3XaVaC01TbNHg; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Ub-5H; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002cr-3P; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 06/11] clk: renesas: cpg-mssr: Add support for fixed rate clocks Date: Thu, 26 Jul 2018 17:35:12 +0200 Message-Id: <20180726153517.10020-7-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for defining fixed rate clocks, to be used for on-chip oscillators. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by. --- drivers/clk/renesas/renesas-cpg-mssr.c | 5 +++++ drivers/clk/renesas/renesas-cpg-mssr.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index f4b013e9352d9efc..e04338932786bc14 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, } break; + case CLK_TYPE_FR: + clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, + core->mult); + break; + default: if (info->cpg_clk_register) clk = info->cpg_clk_register(dev, core, info, diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 642f720b9b055337..87bb8f368d4ecd18 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -38,6 +38,7 @@ enum clk_types { CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */ CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */ + CLK_TYPE_FR, /* Fixed Rate Clock */ /* Custom definitions start here */ CLK_TYPE_CUSTOM, @@ -56,6 +57,8 @@ enum clk_types { DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset) #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1) +#define DEF_RATE(_name, _id, _rate) \ + DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate) /* * Definitions of Module Clocks From patchwork Thu Jul 26 15:35:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80ACCA662 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D2F32B690 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B0F02B7AD; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAB632B6A8 for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731784AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45368 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731798AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y00F3XaVaC01TbN9e; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Uf-6W; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002cu-51; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 07/11] clk: renesas: rcar-gen3: Add support for RCKSEL clock selection Date: Thu, 26 Jul 2018 17:35:13 +0200 Message-Id: <20180726153517.10020-8-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a clock type and macro for defining clocks where the parent and divider are selected based on the value of the RCKCR.CKSEL bit. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Drop extra blank line. --- drivers/clk/renesas/rcar-gen3-cpg.c | 23 ++++++++++++++++++++--- drivers/clk/renesas/rcar-gen3-cpg.h | 7 ++++++- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 7533a51c679bfd54..19a77822757d29de 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -1,7 +1,7 @@ /* * R-Car Gen3 Clock Pulse Generator * - * Copyright (C) 2015-2016 Glider bvba + * Copyright (C) 2015-2018 Glider bvba * * Based on clk-rcar-gen3.c * @@ -31,6 +31,8 @@ #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 +#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ + struct cpg_simple_notifier { struct notifier_block nb; void __iomem *reg; @@ -444,7 +446,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, unsigned int div = 1; u32 value; - parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */ + parent = clks[core->parent & 0xffff]; /* some types use high bits */ if (IS_ERR(parent)) return ERR_CAST(parent); @@ -524,7 +526,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, if (clk_get_rate(clks[cpg_clk_extalr])) { parent = clks[cpg_clk_extalr]; - value |= BIT(15); + value |= CPG_RCKCR_CKSEL; } writel(value, csn->reg); @@ -570,6 +572,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, div = cpg_pll_config->osc_prediv * core->div; break; + case CLK_TYPE_GEN3_RCKSEL: + /* + * Clock selectable between two parents and two fixed dividers + * using RCKCR.CKSEL + */ + if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) { + div = core->div & 0xffff; + } else { + parent = clks[core->parent >> 16]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + div = core->div >> 16; + } + break; + default: return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index d7d84d9e4a1c9c8b..7c49aebf9dd12490 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -1,7 +1,7 @@ /* * R-Car Gen3 Clock Pulse Generator * - * Copyright (C) 2015-2016 Glider bvba + * Copyright (C) 2015-2018 Glider bvba * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,6 +24,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ + CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ @@ -37,6 +38,10 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) +#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ + (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) + struct rcar_gen3_cpg_pll_config { u8 extal_div; u8 pll1_mult; From patchwork Thu Jul 26 15:35:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D669A639 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C3442B7CA for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 264952B624; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 953FC2B7CA for ; Thu, 26 Jul 2018 15:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731600AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45384 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731805AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y00G3XaVaC01TbN9f; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Ug-7e; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002cx-6H; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 08/11] clk: renesas: r8a77990: Correct RCLK handling Date: Thu, 26 Jul 2018 17:35:14 +0200 Message-Id: <20180726153517.10020-9-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rename "r_int" to ".r", and "oco" to ".oco", as they are internal clocks. As Figure 8.1g "Block Diagram of CPG (R-Car E3)" shows 1/61 and 1/4 dividers after the On-Chip Oscillator, I assume the OCO runs at 8 MHz. --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 9e14f1486fbb93cc..9437219efdd98e34 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -44,6 +44,8 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RINT, + CLK_OCO, /* Module Clocks */ MOD_CLK_BASE @@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + + DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), + /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), @@ -100,8 +106,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), - DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1), - DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1), + + DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2), DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), @@ -111,6 +117,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), + + DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), }; static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { From patchwork Thu Jul 26 15:35:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546037 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B583A65F for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A1552B785 for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 47C3E2B75A; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D2242B75A for ; Thu, 26 Jul 2018 15:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731750AbeGZQwp (ORCPT ); Thu, 26 Jul 2018 12:52:45 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45398 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731809AbeGZQwp (ORCPT ); Thu, 26 Jul 2018 12:52:45 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y00L3XaVaC01TbN9m; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Un-9D; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002d0-7O; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 09/11] clk: renesas: r8a77995: Correct RCLK handling Date: Thu, 26 Jul 2018 17:35:15 +0200 Message-Id: <20180726153517.10020-10-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rename "r_int" to ".r", and "oco" to ".oco", as they are internal clocks. As Figure 8.1f "Block Diagram of CPG (R-Car D3)" shows 1/61 and 1/4 dividers after the On-Chip Oscillator, I assume the OCO runs at 8 MHz. --- drivers/clk/renesas/r8a77995-cpg-mssr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index ea4cafbe6e851aca..49e6a0de54916e2d 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -46,6 +46,8 @@ enum clk_ids { CLK_S3, CLK_SDSRC, CLK_SSPSRC, + CLK_RINT, + CLK_OCO, /* Module Clocks */ MOD_CLK_BASE @@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + + DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), + /* Core Clock Outputs */ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), @@ -90,8 +96,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), - DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), - DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), + + DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), @@ -102,6 +108,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), + + DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), }; static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { From patchwork Thu Jul 26 15:35:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4976914E0 for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 372472B7BA for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34E422B78B; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2E612B75E for ; Thu, 26 Jul 2018 15:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731686AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from andre.telenet-ops.be ([195.130.132.53]:43466 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731518AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by andre.telenet-ops.be with bizsmtp id FTbN1y00C3XaVaC01TbNPR; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Ur-AK; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002d3-8w; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 10/11] clk: renesas: rcar-gen3: Add support for mode pin clock selection Date: Thu, 26 Jul 2018 17:35:16 +0200 Message-Id: <20180726153517.10020-11-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Make the existing support for selecting between clean and SSCG clocks using MD12 more generic, to allow using other mode pins for arbitrary clock selection. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by. --- drivers/clk/renesas/rcar-gen3-cpg.c | 10 ++++------ drivers/clk/renesas/rcar-gen3-cpg.h | 13 +++++++++---- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 19a77822757d29de..4346fdeef01bbeae 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -539,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, parent = clks[cpg_clk_extalr]; break; - case CLK_TYPE_GEN3_PE: + case CLK_TYPE_GEN3_MDSEL: /* - * Peripheral clock with a fixed divider, selectable between - * clean and spread spectrum parents using MD12 + * Clock selectable between two parents and two fixed dividers + * using a mode pin */ - if (cpg_mode & BIT(12)) { - /* Clean */ + if (cpg_mode & BIT(core->offset)) { div = core->div & 0xffff; } else { - /* SCCG */ parent = clks[core->parent >> 16]; if (IS_ERR(parent)) return ERR_CAST(parent); diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 7c49aebf9dd12490..04dc45d15874abf6 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -20,7 +20,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PLL4, CLK_TYPE_GEN3_SD, CLK_TYPE_GEN3_R, - CLK_TYPE_GEN3_PE, + CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ @@ -30,11 +30,16 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) +#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ + (_parent0) << 16 | (_parent1), \ + .div = (_div0) << 16 | (_div1), .offset = _md) + #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ _div_clean) \ - DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ - (_parent_sscg) << 16 | (_parent_clean), \ - .div = (_div_sscg) << 16 | (_div_clean)) + DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ + _parent_clean, _div_clean) + #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) From patchwork Thu Jul 26 15:35:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546077 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD639157A for ; Thu, 26 Jul 2018 15:35:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD4222B795 for ; Thu, 26 Jul 2018 15:35:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CA3A32B6F8; Thu, 26 Jul 2018 15:35:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CC6F2B720 for ; Thu, 26 Jul 2018 15:35:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731773AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from andre.telenet-ops.be ([195.130.132.53]:43482 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731758AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by andre.telenet-ops.be with bizsmtp id FTbN1y00E3XaVaC01TbNPS; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Uv-BM; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002d6-9x; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 11/11] clk: renesas: r8a77980: Add RCLK for watchdog timer Date: Thu, 26 Jul 2018 17:35:17 +0200 Message-Id: <20180726153517.10020-12-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip Oscillator using mode pin MD19. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rename "oco" to ".oco", as it is an internal clock. As Figure 8.1e "Block Diagram of CPG (R-Car V3H)" does not show any divider after the On-Chip Oscillator, I assume the OCO runs at 32768 Hz. If this turns out to be incorrect, the OCO clock rate and divider can be updated later without any impact, as the OCO is an internal clock. --- drivers/clk/renesas/r8a77980-cpg-mssr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index a8b8d8613b46dd3c..acf2b4dded4c6cf0 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -41,6 +41,7 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_OCO, /* Module Clocks */ MOD_CLK_BASE @@ -64,6 +65,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), @@ -98,6 +100,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8), + DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), }; static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { @@ -119,6 +122,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), DEF_MOD("sdif", 314, R8A77980_CLK_SD0), DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2), + DEF_MOD("rwdt", 402, R8A77980_CLK_R), DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),