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[24.31.245.230]) by smtp.gmail.com with ESMTPSA id x82sm1333854oix.29.2019.11.21.13.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 13:44:21 -0800 (PST) From: Larry Finger To: kvalo@codeaurora.org Cc: linux-wireless@vger.kernel.org, pkshih@realtek.com, Larry Finger Subject: [PATCH 1/4] rtlwifi: rtl8192de: Remove unused GET_XXX and SET_XXX macros Date: Thu, 21 Nov 2019 15:44:14 -0600 Message-Id: <20191121214417.29676-2-Larry.Finger@lwfinger.net> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121214417.29676-1-Larry.Finger@lwfinger.net> References: <20191121214417.29676-1-Larry.Finger@lwfinger.net> MIME-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org As the first step in converting from macros that get/set information in the RX and TX descriptors, unused macros are being removed. Signed-off-by: Larry Finger --- .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 329 +----------------- 1 file changed, 3 insertions(+), 326 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h index 635989e15282..40746125f1ae 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h @@ -42,8 +42,6 @@ SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) #define SET_TX_DESC_OFFSET(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) -#define SET_TX_DESC_BMC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val) #define SET_TX_DESC_HTC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val) #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ @@ -52,31 +50,9 @@ SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) #define SET_TX_DESC_LINIP(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) -#define SET_TX_DESC_NO_ACM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) -#define SET_TX_DESC_GF(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) #define SET_TX_DESC_OWN(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) -#define GET_TX_DESC_PKT_SIZE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 0, 16) -#define GET_TX_DESC_OFFSET(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 16, 8) -#define GET_TX_DESC_BMC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 24, 1) -#define GET_TX_DESC_HTC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 25, 1) -#define GET_TX_DESC_LAST_SEG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 26, 1) -#define GET_TX_DESC_FIRST_SEG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 27, 1) -#define GET_TX_DESC_LINIP(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 28, 1) -#define GET_TX_DESC_NO_ACM(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 29, 1) -#define GET_TX_DESC_GF(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 30, 1) #define GET_TX_DESC_OWN(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 31, 1) @@ -84,136 +60,35 @@ SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val) #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val) -#define SET_TX_DESC_BK(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val) #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val) #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val) -#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val) -#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val) -#define SET_TX_DESC_PIFS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val) #define SET_TX_DESC_RATE_ID(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val) -#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val) -#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val) #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val) #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val) -#define GET_TX_DESC_MACID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 0, 5) -#define GET_TX_DESC_AGG_ENABLE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 5, 1) -#define GET_TX_DESC_AGG_BREAK(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 6, 1) -#define GET_TX_DESC_RDG_ENABLE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 7, 1) -#define GET_TX_DESC_QUEUE_SEL(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 8, 5) -#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 13, 1) -#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 14, 1) -#define GET_TX_DESC_PIFS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 15, 1) -#define GET_TX_DESC_RATE_ID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 16, 4) -#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 20, 1) -#define GET_TX_DESC_EN_DESC_ID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 21, 1) -#define GET_TX_DESC_SEC_TYPE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 22, 2) -#define GET_TX_DESC_PKT_OFFSET(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 24, 8) - -#define SET_TX_DESC_RTS_RC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val) -#define SET_TX_DESC_DATA_RC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val) -#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val) #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val) -#define SET_TX_DESC_RAW(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val) -#define SET_TX_DESC_CCX(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val) #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val) -#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val) -#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val) -#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val) -#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val) -#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val) - -#define GET_TX_DESC_RTS_RC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 0, 6) -#define GET_TX_DESC_DATA_RC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 6, 6) -#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 14, 2) -#define GET_TX_DESC_MORE_FRAG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 17, 1) -#define GET_TX_DESC_RAW(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 18, 1) -#define GET_TX_DESC_CCX(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 19, 1) -#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 20, 3) -#define GET_TX_DESC_ANTSEL_A(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 24, 1) -#define GET_TX_DESC_ANTSEL_B(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 25, 1) -#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 26, 2) -#define GET_TX_DESC_TX_ANTL(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 28, 2) -#define GET_TX_DESC_TX_ANT_HT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 30, 2) - -#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val) -#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val) + #define SET_TX_DESC_SEQ(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val) #define SET_TX_DESC_PKT_ID(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val) -#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 0, 8) -#define GET_TX_DESC_TAIL_PAGE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 8, 8) -#define GET_TX_DESC_SEQ(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 16, 12) -#define GET_TX_DESC_PKT_ID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 28, 4) - #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val) -#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val) #define SET_TX_DESC_QOS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val) #define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val) #define SET_TX_DESC_USE_RATE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val) -#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val) #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val) #define SET_TX_DESC_CTS2SELF(__pdesc, __val) \ @@ -222,18 +97,8 @@ SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val) #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val) -#define SET_TX_DESC_PORT_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val) -#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val) -#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val) #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val) -#define SET_TX_DESC_TX_STBC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val) -#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val) #define SET_TX_DESC_DATA_BW(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val) #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ @@ -245,158 +110,29 @@ #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val) -#define GET_TX_DESC_RTS_RATE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 0, 5) -#define GET_TX_DESC_AP_DCFE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 5, 1) -#define GET_TX_DESC_QOS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 6, 1) -#define GET_TX_DESC_HWSEQ_EN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 7, 1) -#define GET_TX_DESC_USE_RATE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 8, 1) -#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 9, 1) -#define GET_TX_DESC_DISABLE_FB(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 10, 1) -#define GET_TX_DESC_CTS2SELF(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 11, 1) -#define GET_TX_DESC_RTS_ENABLE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 12, 1) -#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 13, 1) -#define GET_TX_DESC_PORT_ID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 14, 1) -#define GET_TX_DESC_WAIT_DCTS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 18, 1) -#define GET_TX_DESC_CTS2AP_EN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 19, 1) -#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 20, 2) -#define GET_TX_DESC_TX_STBC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 22, 2) -#define GET_TX_DESC_DATA_SHORT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 24, 1) -#define GET_TX_DESC_DATA_BW(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 25, 1) -#define GET_TX_DESC_RTS_SHORT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 26, 1) -#define GET_TX_DESC_RTS_BW(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 27, 1) -#define GET_TX_DESC_RTS_SC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 28, 2) -#define GET_TX_DESC_RTS_STBC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 30, 2) - #define SET_TX_DESC_TX_RATE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val) #define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val) -#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val) #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val) #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val) -#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val) -#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val) - -#define GET_TX_DESC_TX_RATE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 0, 6) -#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 6, 1) -#define GET_TX_DESC_CCX_TAG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 7, 1) -#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 8, 5) -#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 13, 4) -#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 17, 1) -#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 18, 6) -#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 24, 8) - -#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val) -#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val) -#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val) + #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val) -#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val) -#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val) -#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val) -#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val) - -#define GET_TX_DESC_TXAGC_A(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 0, 5) -#define GET_TX_DESC_TXAGC_B(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 5, 5) -#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 10, 1) -#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 11, 5) -#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 16, 4) -#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 20, 4) -#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 24, 4) -#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 28, 4) #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val) -#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val) -#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val) -#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val) -#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val) - -#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+28, 0, 16) -#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+28, 16, 4) -#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+28, 20, 4) -#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+28, 24, 4) -#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+28, 28, 4) #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val) -#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val) #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+32, 0, 32) -#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+36, 0, 32) #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val) -#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val) - -#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+40, 0, 32) -#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+44, 0, 32) #define GET_RX_DESC_PKT_LEN(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 0, 14) @@ -406,22 +142,12 @@ SHIFT_AND_MASK_LE(__pdesc, 15, 1) #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 16, 4) -#define GET_RX_DESC_SECURITY(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 20, 3) -#define GET_RX_DESC_QOS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 23, 1) #define GET_RX_DESC_SHIFT(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 24, 2) #define GET_RX_DESC_PHYST(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 26, 1) #define GET_RX_DESC_SWDEC(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 27, 1) -#define GET_RX_DESC_LS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 28, 1) -#define GET_RX_DESC_FS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 29, 1) -#define GET_RX_DESC_EOR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 30, 1) #define GET_RX_DESC_OWN(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc, 31, 1) @@ -432,44 +158,10 @@ #define SET_RX_DESC_OWN(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) -#define GET_RX_DESC_MACID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 0, 5) -#define GET_RX_DESC_TID(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 5, 4) -#define GET_RX_DESC_HWRSVD(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 9, 5) #define GET_RX_DESC_PAGGR(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+4, 14, 1) #define GET_RX_DESC_FAGGR(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+4, 15, 1) -#define GET_RX_DESC_A1_FIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 16, 4) -#define GET_RX_DESC_A2_FIT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 20, 4) -#define GET_RX_DESC_PAM(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 24, 1) -#define GET_RX_DESC_PWR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 25, 1) -#define GET_RX_DESC_MD(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 26, 1) -#define GET_RX_DESC_MF(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 27, 1) -#define GET_RX_DESC_TYPE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 28, 2) -#define GET_RX_DESC_MC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 30, 1) -#define GET_RX_DESC_BC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 31, 1) -#define GET_RX_DESC_SEQ(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 0, 12) -#define GET_RX_DESC_FRAG(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 12, 4) -#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 16, 14) -#define GET_RX_DESC_NEXT_IND(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 30, 1) -#define GET_RX_DESC_RSVD(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+8, 31, 1) #define GET_RX_DESC_RXMCS(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+12, 0, 6) @@ -479,29 +171,14 @@ SHIFT_AND_MASK_LE(__pdesc+12, 8, 1) #define GET_RX_DESC_BW(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+12, 9, 1) -#define GET_RX_DESC_HTC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 10, 1) -#define GET_RX_DESC_HWPC_ERR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 14, 1) -#define GET_RX_DESC_HWPC_IND(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 15, 1) -#define GET_RX_DESC_IV0(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 16, 16) - -#define GET_RX_DESC_IV1(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+16, 0, 32) + #define GET_RX_DESC_TSFL(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+20, 0, 32) #define GET_RX_DESC_BUFF_ADDR(__pdesc) \ SHIFT_AND_MASK_LE(__pdesc+24, 0, 32) -#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+28, 0, 32) - #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val) -#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val) #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ memset((void *)__pdesc, 0, \ From patchwork Thu Nov 21 21:44:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Larry Finger X-Patchwork-Id: 11256913 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F307930 for ; Thu, 21 Nov 2019 21:44:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E2A80206D8 for ; Thu, 21 Nov 2019 21:44:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LRjvdp9T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726852AbfKUVo0 (ORCPT ); Thu, 21 Nov 2019 16:44:26 -0500 Received: from mail-ot1-f67.google.com ([209.85.210.67]:45327 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726539AbfKUVoZ (ORCPT ); Thu, 21 Nov 2019 16:44:25 -0500 Received: by mail-ot1-f67.google.com with SMTP id r24so4323561otk.12 for ; Thu, 21 Nov 2019 13:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UauNR8xWixEkWPrqJnX3toknjEptaFQ9yfGVzgeqdSc=; b=LRjvdp9TXjZvgpctmsqN/6rJI1kCoKCfZedVyLuSfA3UNTStAZ6VtPaImWPTimrDh/ 4dXgoTCJKs7qX8lQmb24wBM541Dk3yrbkxsjulbSDejK4Bh+oyse1UaQzlwTHppNonE7 1np0Bs/Gj7ezWHcuNlw/4BcAgNeV+sFmxeFPNEI6fRgHBPbgXKNm6gFNkf2f9k2fpBif ZUu4g1deLgn76DacUb9KcphBgFI9Lc6t/tKFpy8ezut+H5svDX2cka4aPI4CtEp9OK1I AEk4MhYK2ruj1aMdOWy2mnITBD5MVX7Rs43xvkU+/mcFO0FUkKp/DyOF0EKazSVQD1IC Whuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UauNR8xWixEkWPrqJnX3toknjEptaFQ9yfGVzgeqdSc=; b=awVKJpq7XNRyVT5QJ+pEai/ckM06OHHVda9kQJVidaeW10B1qmCgAKKHYzGfGQPpQJ a+gNt1Z/H/Jh2A9lxzgw6BELquoDY7AUEdKIGdFc9zRvC37I1+0roqHf5n8w4nVjVLVo v00lCuNHY6I2dHyiay9e86LJU0w+/t59iT2tikoii2Ifl5peegDXdrFWpLBiT9LXDLwv j5hOVNejJONRxSI107qoobpKst8DmtocFJwuPR55w1Oq9+qxL8Kx2J45OsSr5W8m1bAY PPuVsSWEA0YVc10mvT1aMYIa4J2q1uq2D45AVCW2TYSmwv5bE485Iip/OFMRll3nTvZ0 xpOg== X-Gm-Message-State: APjAAAWtIgyry8QhHuhSrvYxu/eiUZ0FG9d34fsfrzba7a7hj2CVBACg XgLezS2BohvaNL7eHo2ZyYY= X-Google-Smtp-Source: APXvYqwpQBG1qCTqH9rjBPQTCqUxiW3Y3QHFbNno8kCuEszNS1rsjD+tlYJ25dIuH63Ri4BGhdQZFQ== X-Received: by 2002:a9d:854:: with SMTP id 78mr8188464oty.284.1574372662564; Thu, 21 Nov 2019 13:44:22 -0800 (PST) Received: from localhost.localdomain (cpe-24-31-245-230.kc.res.rr.com. [24.31.245.230]) by smtp.gmail.com with ESMTPSA id x82sm1333854oix.29.2019.11.21.13.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 13:44:22 -0800 (PST) From: Larry Finger To: kvalo@codeaurora.org Cc: linux-wireless@vger.kernel.org, pkshih@realtek.com, Larry Finger Subject: [PATCH 2/4] rtlwifi: rtl8192de: Replace local bit manipulation macros Date: Thu, 21 Nov 2019 15:44:15 -0600 Message-Id: <20191121214417.29676-3-Larry.Finger@lwfinger.net> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121214417.29676-1-Larry.Finger@lwfinger.net> References: <20191121214417.29676-1-Larry.Finger@lwfinger.net> MIME-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org This driver uses a set of local macros to manipulate the RX and TX descriptors, which are all little-endian quantities. These macros are replaced by the bitfield macros le32p_replace_bits() and le32_get_bits(). In several places, the macros operated on an entire 32-bit word. In these cases, a direct read or replacement is used. Signed-off-by: Larry Finger --- .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 160 ++++++++---------- 1 file changed, 69 insertions(+), 91 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h index 40746125f1ae..5ff1000b2400 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h @@ -14,171 +14,149 @@ #define USB_HWDESC_HEADER_LEN 32 #define CRCLENGTH 4 -/* Define a macro that takes a le32 word, converts it to host ordering, - * right shifts by a specified count, creates a mask of the specified - * bit count, and extracts that number of bits. - */ - -#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \ - ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \ - BIT_LEN_MASK_32(__mask)) - -/* Define a macro that clears a bit field in an le32 word and - * sets the specified value into that bit field. The resulting - * value remains in le32 ordering; however, it is properly converted - * to host ordering for the clear and set operations before conversion - * back to le32. - */ - -#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \ - (*(__le32 *)(__pdesc) = \ - (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \ - (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \ - (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift))))); - /* macros to read/write various fields in RX or TX descriptors */ #define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(15, 0)) #define SET_TX_DESC_OFFSET(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(23, 16)) #define SET_TX_DESC_HTC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(25)) #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(26)) #define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(27)) #define SET_TX_DESC_LINIP(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(28)) #define SET_TX_DESC_OWN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)) #define GET_TX_DESC_OWN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 31, 1) + le32_get_bits(*(__le32 *)__pdesc, BIT(31)) #define SET_TX_DESC_MACID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(4, 0)) #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(5)) #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(7)) #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(12, 8)) #define SET_TX_DESC_RATE_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(19, 16)) #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(23, 22)) #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val) + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(30, 26)) #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 8), __val, BIT(17)) #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val) + le32p_replace_bits((__le32 *)(__pdesc + 8), __val, GENMASK(22, 20)) #define SET_TX_DESC_SEQ(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val) + le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(27, 16)) #define SET_TX_DESC_PKT_ID(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val) + le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(31, 28)) #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(4, 0)) #define SET_TX_DESC_QOS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(6)) #define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(7)) #define SET_TX_DESC_USE_RATE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(8)) #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(10)) #define SET_TX_DESC_CTS2SELF(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(11)) #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(12)) #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(13)) #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(21, 20)) #define SET_TX_DESC_DATA_BW(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(25)) #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(26)) #define SET_TX_DESC_RTS_BW(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(27)) #define SET_TX_DESC_RTS_SC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(29, 28)) #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val) + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(31, 30)) #define SET_TX_DESC_TX_RATE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val) + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(5, 0)) #define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val) + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, BIT(6)) #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val) + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(12, 8)) #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val) + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(16, 13)) #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val) + le32p_replace_bits((__le32 *)(__pdesc + 24), __val, GENMASK(15, 11)) #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val) + le32p_replace_bits((__le32 *)(__pdesc + 28), __val, GENMASK(15, 0)) #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val) + *(__le32 *)(__pdesc + 32) = cpu_to_le32(__val) #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+32, 0, 32) + le32_to_cpu(*(__le32 *)(__pdesc + 32)) #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val) + *(__le32 *)(__pdesc + 40) = cpu_to_le32(__val) #define GET_RX_DESC_PKT_LEN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 0, 14) + le32_get_bits(*(__le32 *)__pdesc, GENMASK(13, 0)) #define GET_RX_DESC_CRC32(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 14, 1) + le32_get_bits(*(__le32 *)__pdesc, BIT(14)) #define GET_RX_DESC_ICV(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 15, 1) + le32_get_bits(*(__le32 *)__pdesc, BIT(15)) #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 16, 4) + le32_get_bits(*(__le32 *)__pdesc, GENMASK(19, 16)) #define GET_RX_DESC_SHIFT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 24, 2) + le32_get_bits(*(__le32 *)__pdesc, GENMASK(25, 24)) #define GET_RX_DESC_PHYST(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 26, 1) + le32_get_bits(*(__le32 *)__pdesc, BIT(26)) #define GET_RX_DESC_SWDEC(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 27, 1) + le32_get_bits(*(__le32 *)__pdesc, BIT(27)) #define GET_RX_DESC_OWN(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc, 31, 1) + le32_get_bits(*(__le32 *)__pdesc, BIT(31)) #define SET_RX_DESC_PKT_LEN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(13, 0)) #define SET_RX_DESC_EOR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(30)) #define SET_RX_DESC_OWN(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)) #define GET_RX_DESC_PAGGR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 14, 1) + le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(14)) #define GET_RX_DESC_FAGGR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+4, 15, 1) + le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(15)) #define GET_RX_DESC_RXMCS(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 0, 6) + le32_get_bits(*(__le32 *)(__pdesc + 12), GENMASK(5, 0)) #define GET_RX_DESC_RXHT(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 6, 1) + le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(6)) #define GET_RX_DESC_SPLCP(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 8, 1) + le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(8)) #define GET_RX_DESC_BW(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+12, 9, 1) + le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(9)) #define GET_RX_DESC_TSFL(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+20, 0, 32) + le32_to_cpu(*(__le32 *)(__pdesc + 20)) #define GET_RX_DESC_BUFF_ADDR(__pdesc) \ - SHIFT_AND_MASK_LE(__pdesc+24, 0, 32) + le32_to_cpu(*(__le32 *)(__pdesc + 24)) #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ - SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val) + *(__le32 *)(__pdesc + 24) = cpu_to_le32(__val) #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ memset((void *)__pdesc, 0, \ @@ -186,19 +164,19 @@ /* For 92D early mode */ #define SET_EARLYMODE_PKTNUM(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr, 0, 3, __value) + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0)) #define SET_EARLYMODE_LEN0(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr, 4, 12, __value) + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4)) #define SET_EARLYMODE_LEN1(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr, 16, 12, __value) + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16)) #define SET_EARLYMODE_LEN2_1(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr, 28, 4, __value) + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28)) #define SET_EARLYMODE_LEN2_2(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr+4, 0, 8, __value) + le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0)) #define SET_EARLYMODE_LEN3(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr+4, 8, 12, __value) + le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8)) #define SET_EARLYMODE_LEN4(__paddr, __value) \ - SET_BITS_OFFSET_LE(__paddr+4, 20, 12, __value) + le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20)) struct rx_fwinfo_92d { u8 gain_trsw[4]; From patchwork Thu Nov 21 21:44:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Larry Finger X-Patchwork-Id: 11256917 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7DF013A4 for ; Thu, 21 Nov 2019 21:44:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7E3CD206D8 for ; Thu, 21 Nov 2019 21:44:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="G6d948on" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbfKUVo1 (ORCPT ); Thu, 21 Nov 2019 16:44:27 -0500 Received: from mail-ot1-f68.google.com ([209.85.210.68]:38952 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726510AbfKUVo0 (ORCPT ); Thu, 21 Nov 2019 16:44:26 -0500 Received: by mail-ot1-f68.google.com with SMTP id w24so4374770otk.6 for ; Thu, 21 Nov 2019 13:44:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Egz7PsCpUyrlde1Qs2W2+KETuDhv/NJBZ9Q816D/sNY=; b=G6d948on4rA/kziOHeClDLcqIwRJ1y9up2ptoj346w96qQecMC3KMvz6PeJp7ofWyt FFR7sCFodY2AZN1QgZHuNcUWjftaCWpRJD65uaYeaaDxOmdARkScZdUzddyrq/iGjEXm OL6p02DmP4Otz2N2iEM5okpMsCopWGLTLyQviu2zN8uTr5rKtdhDTWOuySy4tMQtA4EQ BaoxhcUo5vhVqFDsCTcjksz1vmXBAWpPONL+MebtPJ4ErxvXIen13tUG3/j0AYwLwN/O iUhI6f95Eqlc5bBDED1mp4SgA1hilCZo3GueDepKPyrk17hFBjhCN9ulnAJM2BPajLDZ nCXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Egz7PsCpUyrlde1Qs2W2+KETuDhv/NJBZ9Q816D/sNY=; b=ElBv1h6hHi6M6h6m4XqVTErsrceQ60r+Xrs8k/r5I85cIYGErcfnMbRwm92+FCcsq9 mOxqgl0dcp/3LLLJuh/47dcJMq3bONog9OAeb5cHMspYtsIflZrWveWoi+NNdSh69KPs ZIxeJinc+S+BoYc3TxTvUyNPFqjQY0NMaMZG7RJMJbHzQCvd4xVTDo0n7qtvgjcDb78v rB5GGN+VyTQ3jTeXcmsrqn3e13pkp7kzFiPqGybvcF1zDiQTe2Cwd23TQ1gunnvLN9FI q5+Wks07Ty0m4eGxfu1a7aqi3Kf5l4BRmh2jwmH4WxeGJGvV4rRPirsud6GgXC/BWgy7 jHfQ== X-Gm-Message-State: APjAAAXphjBlFoBySmhjc85IYdtTKuWTnMyS53y4x5oERv1qbMl5iFgA rUetfSBxKJo3+OZK+t6cO+Eyl8gz X-Google-Smtp-Source: APXvYqwlBT1O+S6ZBKCccypPz425FTvAka7eKQbjc0wu89ODc8v6N1q/KX7pRwYHjKFH5RMsRYDEzQ== X-Received: by 2002:a9d:7985:: with SMTP id h5mr7829216otm.20.1574372663515; Thu, 21 Nov 2019 13:44:23 -0800 (PST) Received: from localhost.localdomain (cpe-24-31-245-230.kc.res.rr.com. [24.31.245.230]) by smtp.gmail.com with ESMTPSA id x82sm1333854oix.29.2019.11.21.13.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 13:44:22 -0800 (PST) From: Larry Finger To: kvalo@codeaurora.org Cc: linux-wireless@vger.kernel.org, pkshih@realtek.com, Larry Finger Subject: [PATCH 3/4] rtlwifi: rtl8192de: Convert macros that set descriptor Date: Thu, 21 Nov 2019 15:44:16 -0600 Message-Id: <20191121214417.29676-4-Larry.Finger@lwfinger.net> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121214417.29676-1-Larry.Finger@lwfinger.net> References: <20191121214417.29676-1-Larry.Finger@lwfinger.net> MIME-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org As a first step in the conversion, the macros that set the RX and TX descriptors are converted to static inline routines, and the names are changed from upper to lower case. To minimize the changes in a given step, the input descriptor information is left as as a byte array (u8 *), even though it should be a little-endian word array (__le32 *). That will be changed in the next patch. Several places where checkpatch.pl complains about a space after a cast and other warnings are fixed. Signed-off-by: Larry Finger --- .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 229 ++++---- .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 498 ++++++++++++------ 2 files changed, 458 insertions(+), 269 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c index 92c9fb45f800..18361f22337d 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c @@ -438,49 +438,49 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, struct ieee80211_rx_status *rx_status, - u8 *p_desc, struct sk_buff *skb) + u8 *pdesc, struct sk_buff *skb) { struct rx_fwinfo_92d *p_drvinfo; - struct rx_desc_92d *pdesc = (struct rx_desc_92d *)p_desc; - u32 phystatus = GET_RX_DESC_PHYST(pdesc); + u32 phystatus = get_rx_desc_physt(pdesc); - stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc); - stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) * + stats->length = (u16)get_rx_desc_pkt_len(pdesc); + stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) * RX_DRV_INFO_SIZE_UNIT; - stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03); - stats->icv = (u16) GET_RX_DESC_ICV(pdesc); - stats->crc = (u16) GET_RX_DESC_CRC32(pdesc); + stats->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03); + stats->icv = (u16)get_rx_desc_icv(pdesc); + stats->crc = (u16)get_rx_desc_crc32(pdesc); stats->hwerror = (stats->crc | stats->icv); - stats->decrypted = !GET_RX_DESC_SWDEC(pdesc); - stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc); - stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc); - stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1); - stats->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1) - && (GET_RX_DESC_FAGGR(pdesc) == 1)); - stats->timestamp_low = GET_RX_DESC_TSFL(pdesc); - stats->rx_is40mhzpacket = (bool)GET_RX_DESC_BW(pdesc); - stats->is_ht = (bool)GET_RX_DESC_RXHT(pdesc); + stats->decrypted = !get_rx_desc_swdec(pdesc); + stats->rate = (u8)get_rx_desc_rxmcs(pdesc); + stats->shortpreamble = (u16)get_rx_desc_splcp(pdesc); + stats->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1); + stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(pdesc) == 1) && + (get_rx_desc_faggr(pdesc) == 1)); + stats->timestamp_low = get_rx_desc_tsfl(pdesc); + stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(pdesc); + stats->is_ht = (bool)get_rx_desc_rxht(pdesc); rx_status->freq = hw->conf.chandef.chan->center_freq; rx_status->band = hw->conf.chandef.chan->band; - if (GET_RX_DESC_CRC32(pdesc)) + if (get_rx_desc_crc32(pdesc)) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; - if (!GET_RX_DESC_SWDEC(pdesc)) + if (!get_rx_desc_swdec(pdesc)) rx_status->flag |= RX_FLAG_DECRYPTED; - if (GET_RX_DESC_BW(pdesc)) + if (get_rx_desc_bw(pdesc)) rx_status->bw = RATE_INFO_BW_40; - if (GET_RX_DESC_RXHT(pdesc)) + if (get_rx_desc_rxht(pdesc)) rx_status->encoding = RX_ENC_HT; rx_status->flag |= RX_FLAG_MACTIME_START; if (stats->decrypted) rx_status->flag |= RX_FLAG_DECRYPTED; rx_status->rate_idx = rtlwifi_rate_mapping(hw, stats->is_ht, false, stats->rate); - rx_status->mactime = GET_RX_DESC_TSFL(pdesc); + rx_status->mactime = get_rx_desc_tsfl(pdesc); if (phystatus) { p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + stats->rx_bufshift); _rtl92de_translate_rx_signal_stuff(hw, - skb, stats, pdesc, + skb, stats, + (struct rx_desc_92d *)pdesc, p_drvinfo); } /*rx_status->qual = stats->signal; */ @@ -493,13 +493,13 @@ static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc, { memset(virtualaddress, 0, 8); - SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num); - SET_EARLYMODE_LEN0(virtualaddress, ptcb_desc->empkt_len[0]); - SET_EARLYMODE_LEN1(virtualaddress, ptcb_desc->empkt_len[1]); - SET_EARLYMODE_LEN2_1(virtualaddress, ptcb_desc->empkt_len[2] & 0xF); - SET_EARLYMODE_LEN2_2(virtualaddress, ptcb_desc->empkt_len[2] >> 4); - SET_EARLYMODE_LEN3(virtualaddress, ptcb_desc->empkt_len[3]); - SET_EARLYMODE_LEN4(virtualaddress, ptcb_desc->empkt_len[4]); + set_earlymode_pktnum(virtualaddress, ptcb_desc->empkt_num); + set_earlymode_len0(virtualaddress, ptcb_desc->empkt_len[0]); + set_earlymode_len1(virtualaddress, ptcb_desc->empkt_len[1]); + set_earlymode_len2_1(virtualaddress, ptcb_desc->empkt_len[2] & 0xF); + set_earlymode_len2_2(virtualaddress, ptcb_desc->empkt_len[2] >> 4); + set_earlymode_len3(virtualaddress, ptcb_desc->empkt_len[3]); + set_earlymode_len4(virtualaddress, ptcb_desc->empkt_len[4]); } void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, @@ -556,8 +556,8 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, } if (firstseg) { if (rtlhal->earlymode_enable) { - SET_TX_DESC_PKT_OFFSET(pdesc, 1); - SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN + + set_tx_desc_pkt_offset(pdesc, 1); + set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN + EM_HDR_LEN); if (ptcb_desc->empkt_num) { RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD, @@ -567,60 +567,61 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, (u8 *)(skb->data)); } } else { - SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); + set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); } /* 5G have no CCK rate */ if (rtlhal->current_bandtype == BAND_ON_5G) if (ptcb_desc->hw_rate < DESC_RATE6M) ptcb_desc->hw_rate = DESC_RATE6M; - SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate); + set_tx_desc_tx_rate(pdesc, ptcb_desc->hw_rate); if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble) - SET_TX_DESC_DATA_SHORTGI(pdesc, 1); + set_tx_desc_data_shortgi(pdesc, 1); if (rtlhal->macphymode == DUALMAC_DUALPHY && ptcb_desc->hw_rate == DESC_RATEMCS7) - SET_TX_DESC_DATA_SHORTGI(pdesc, 1); + set_tx_desc_data_shortgi(pdesc, 1); if (info->flags & IEEE80211_TX_CTL_AMPDU) { - SET_TX_DESC_AGG_ENABLE(pdesc, 1); - SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14); + set_tx_desc_agg_enable(pdesc, 1); + set_tx_desc_max_agg_num(pdesc, 0x14); } - SET_TX_DESC_SEQ(pdesc, seq_number); - SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable && - !ptcb_desc->cts_enable) ? 1 : 0)); - SET_TX_DESC_HW_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable + set_tx_desc_seq(pdesc, seq_number); + set_tx_desc_rts_enable(pdesc, + ((ptcb_desc->rts_enable && + !ptcb_desc->cts_enable) ? 1 : 0)); + set_tx_desc_hw_rts_enable(pdesc, ((ptcb_desc->rts_enable || ptcb_desc->cts_enable) ? 1 : 0)); - SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0)); - SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0)); + set_tx_desc_cts2self(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0)); + set_tx_desc_rts_stbc(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0)); /* 5G have no CCK rate */ if (rtlhal->current_bandtype == BAND_ON_5G) if (ptcb_desc->rts_rate < DESC_RATE6M) ptcb_desc->rts_rate = DESC_RATE6M; - SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate); - SET_TX_DESC_RTS_BW(pdesc, 0); - SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc); - SET_TX_DESC_RTS_SHORT(pdesc, ((ptcb_desc->rts_rate <= + set_tx_desc_rts_rate(pdesc, ptcb_desc->rts_rate); + set_tx_desc_rts_bw(pdesc, 0); + set_tx_desc_rts_sc(pdesc, ptcb_desc->rts_sc); + set_tx_desc_rts_short(pdesc, ((ptcb_desc->rts_rate <= DESC_RATE54M) ? (ptcb_desc->rts_use_shortpreamble ? 1 : 0) : (ptcb_desc->rts_use_shortgi ? 1 : 0))); if (bw_40) { if (ptcb_desc->packet_bw) { - SET_TX_DESC_DATA_BW(pdesc, 1); - SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3); + set_tx_desc_data_bw(pdesc, 1); + set_tx_desc_tx_sub_carrier(pdesc, 3); } else { - SET_TX_DESC_DATA_BW(pdesc, 0); - SET_TX_DESC_TX_SUB_CARRIER(pdesc, + set_tx_desc_data_bw(pdesc, 0); + set_tx_desc_tx_sub_carrier(pdesc, mac->cur_40_prime_sc); } } else { - SET_TX_DESC_DATA_BW(pdesc, 0); - SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0); + set_tx_desc_data_bw(pdesc, 0); + set_tx_desc_tx_sub_carrier(pdesc, 0); } - SET_TX_DESC_LINIP(pdesc, 0); - SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb_len); + set_tx_desc_linip(pdesc, 0); + set_tx_desc_pkt_size(pdesc, (u16)skb_len); if (sta) { u8 ampdu_density = sta->ht_cap.ampdu_density; - SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density); + set_tx_desc_ampdu_density(pdesc, ampdu_density); } if (info->control.hw_key) { struct ieee80211_key_conf *keyconf; @@ -630,61 +631,61 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, case WLAN_CIPHER_SUITE_WEP40: case WLAN_CIPHER_SUITE_WEP104: case WLAN_CIPHER_SUITE_TKIP: - SET_TX_DESC_SEC_TYPE(pdesc, 0x1); + set_tx_desc_sec_type(pdesc, 0x1); break; case WLAN_CIPHER_SUITE_CCMP: - SET_TX_DESC_SEC_TYPE(pdesc, 0x3); + set_tx_desc_sec_type(pdesc, 0x3); break; default: - SET_TX_DESC_SEC_TYPE(pdesc, 0x0); + set_tx_desc_sec_type(pdesc, 0x0); break; } } - SET_TX_DESC_PKT_ID(pdesc, 0); - SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel); - SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F); - SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF); - SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ? + set_tx_desc_pkt_id(pdesc, 0); + set_tx_desc_queue_sel(pdesc, fw_qsel); + set_tx_desc_data_rate_fb_limit(pdesc, 0x1F); + set_tx_desc_rts_rate_fb_limit(pdesc, 0xF); + set_tx_desc_disable_fb(pdesc, ptcb_desc->disable_ratefallback ? 1 : 0); - SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0); + set_tx_desc_use_rate(pdesc, ptcb_desc->use_driver_rate ? 1 : 0); /* Set TxRate and RTSRate in TxDesc */ /* This prevent Tx initial rate of new-coming packets */ /* from being overwritten by retried packet rate.*/ if (!ptcb_desc->use_driver_rate) { - SET_TX_DESC_RTS_RATE(pdesc, 0x08); - /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */ + set_tx_desc_rts_rate(pdesc, 0x08); + /* set_tx_desc_tx_rate(pdesc, 0x0b); */ } if (ieee80211_is_data_qos(fc)) { if (mac->rdg_en) { RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "Enable RDG function\n"); - SET_TX_DESC_RDG_ENABLE(pdesc, 1); - SET_TX_DESC_HTC(pdesc, 1); + set_tx_desc_rdg_enable(pdesc, 1); + set_tx_desc_htc(pdesc, 1); } } } - SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0)); - SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0)); - SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len); - SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); + set_tx_desc_first_seg(pdesc, (firstseg ? 1 : 0)); + set_tx_desc_last_seg(pdesc, (lastseg ? 1 : 0)); + set_tx_desc_tx_buffer_size(pdesc, (u16)buf_len); + set_tx_desc_tx_buffer_address(pdesc, mapping); if (rtlpriv->dm.useramask) { - SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index); - SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id); + set_tx_desc_rate_id(pdesc, ptcb_desc->ratr_index); + set_tx_desc_macid(pdesc, ptcb_desc->mac_id); } else { - SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index); - SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index); + set_tx_desc_rate_id(pdesc, 0xC + ptcb_desc->ratr_index); + set_tx_desc_macid(pdesc, ptcb_desc->ratr_index); } if (ieee80211_is_data_qos(fc)) - SET_TX_DESC_QOS(pdesc, 1); + set_tx_desc_qos(pdesc, 1); if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) { - SET_TX_DESC_HWSEQ_EN(pdesc, 1); - SET_TX_DESC_PKT_ID(pdesc, 8); + set_tx_desc_hwseq_en(pdesc, 1); + set_tx_desc_pkt_id(pdesc, 8); } - SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1)); + set_tx_desc_more_frag(pdesc, (lastseg ? 0 : 1)); RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); } @@ -709,40 +710,40 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, } CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE); if (firstseg) - SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); + set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); /* 5G have no CCK rate * Caution: The macros below are multi-line expansions. * The braces are needed no matter what checkpatch says */ if (rtlhal->current_bandtype == BAND_ON_5G) { - SET_TX_DESC_TX_RATE(pdesc, DESC_RATE6M); + set_tx_desc_tx_rate(pdesc, DESC_RATE6M); } else { - SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M); + set_tx_desc_tx_rate(pdesc, DESC_RATE1M); } - SET_TX_DESC_SEQ(pdesc, 0); - SET_TX_DESC_LINIP(pdesc, 0); - SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue); - SET_TX_DESC_FIRST_SEG(pdesc, 1); - SET_TX_DESC_LAST_SEG(pdesc, 1); - SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)skb->len); - SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); - SET_TX_DESC_RATE_ID(pdesc, 7); - SET_TX_DESC_MACID(pdesc, 0); - SET_TX_DESC_PKT_SIZE(pdesc, (u16) (skb->len)); - SET_TX_DESC_FIRST_SEG(pdesc, 1); - SET_TX_DESC_LAST_SEG(pdesc, 1); - SET_TX_DESC_OFFSET(pdesc, 0x20); - SET_TX_DESC_USE_RATE(pdesc, 1); + set_tx_desc_seq(pdesc, 0); + set_tx_desc_linip(pdesc, 0); + set_tx_desc_queue_sel(pdesc, fw_queue); + set_tx_desc_first_seg(pdesc, 1); + set_tx_desc_last_seg(pdesc, 1); + set_tx_desc_tx_buffer_size(pdesc, (u16)skb->len); + set_tx_desc_tx_buffer_address(pdesc, mapping); + set_tx_desc_rate_id(pdesc, 7); + set_tx_desc_macid(pdesc, 0); + set_tx_desc_pkt_size(pdesc, (u16)(skb->len)); + set_tx_desc_first_seg(pdesc, 1); + set_tx_desc_last_seg(pdesc, 1); + set_tx_desc_offset(pdesc, 0x20); + set_tx_desc_use_rate(pdesc, 1); if (!ieee80211_is_data_qos(fc) && ppsc->fwctrl_lps) { - SET_TX_DESC_HWSEQ_EN(pdesc, 1); - SET_TX_DESC_PKT_ID(pdesc, 8); + set_tx_desc_hwseq_en(pdesc, 1); + set_tx_desc_pkt_id(pdesc, 8); } RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, "H2C Tx Cmd Content", pdesc, TX_DESC_SIZE); wmb(); - SET_TX_DESC_OWN(pdesc, 1); + set_tx_desc_own(pdesc, 1); } void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, @@ -752,10 +753,10 @@ void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, switch (desc_name) { case HW_DESC_OWN: wmb(); - SET_TX_DESC_OWN(pdesc, 1); + set_tx_desc_own(pdesc, 1); break; case HW_DESC_TX_NEXTDESC_ADDR: - SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val); + set_tx_desc_next_desc_address(pdesc, *(u32 *)val); break; default: WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", @@ -766,16 +767,16 @@ void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, switch (desc_name) { case HW_DESC_RXOWN: wmb(); - SET_RX_DESC_OWN(pdesc, 1); + set_rx_desc_own(pdesc, 1); break; case HW_DESC_RXBUFF_ADDR: - SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val); + set_rx_desc_buff_addr(pdesc, *(u32 *)val); break; case HW_DESC_RXPKT_LEN: - SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val); + set_rx_desc_pkt_len(pdesc, *(u32 *)val); break; case HW_DESC_RXERO: - SET_RX_DESC_EOR(pdesc, 1); + set_rx_desc_eor(pdesc, 1); break; default: WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", @@ -793,10 +794,10 @@ u64 rtl92de_get_desc(struct ieee80211_hw *hw, if (istx) { switch (desc_name) { case HW_DESC_OWN: - ret = GET_TX_DESC_OWN(p_desc); + ret = get_tx_desc_own(p_desc); break; case HW_DESC_TXBUFF_ADDR: - ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc); + ret = get_tx_desc_tx_buffer_address(p_desc); break; default: WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", @@ -806,13 +807,13 @@ u64 rtl92de_get_desc(struct ieee80211_hw *hw, } else { switch (desc_name) { case HW_DESC_OWN: - ret = GET_RX_DESC_OWN(p_desc); + ret = get_rx_desc_own(p_desc); break; case HW_DESC_RXPKT_LEN: - ret = GET_RX_DESC_PKT_LEN(p_desc); - break; + ret = get_rx_desc_pkt_len(p_desc); + break; case HW_DESC_RXBUFF_ADDR: - ret = GET_RX_DESC_BUFF_ADDR(p_desc); + ret = get_rx_desc_buff_addr(p_desc); break; default: WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h index 5ff1000b2400..fe81196e46b7 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h @@ -16,167 +16,355 @@ /* macros to read/write various fields in RX or TX descriptors */ -#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(15, 0)) -#define SET_TX_DESC_OFFSET(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(23, 16)) -#define SET_TX_DESC_HTC(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(25)) -#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(26)) -#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(27)) -#define SET_TX_DESC_LINIP(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(28)) -#define SET_TX_DESC_OWN(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)) - -#define GET_TX_DESC_OWN(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, BIT(31)) - -#define SET_TX_DESC_MACID(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(4, 0)) -#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(5)) -#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(7)) -#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(12, 8)) -#define SET_TX_DESC_RATE_ID(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(19, 16)) -#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(23, 22)) -#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(30, 26)) - -#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 8), __val, BIT(17)) -#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 8), __val, GENMASK(22, 20)) - -#define SET_TX_DESC_SEQ(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(27, 16)) -#define SET_TX_DESC_PKT_ID(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(31, 28)) - -#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(4, 0)) -#define SET_TX_DESC_QOS(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(6)) -#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(7)) -#define SET_TX_DESC_USE_RATE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(8)) -#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(10)) -#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(11)) -#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(12)) -#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(13)) -#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(21, 20)) -#define SET_TX_DESC_DATA_BW(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(25)) -#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(26)) -#define SET_TX_DESC_RTS_BW(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(27)) -#define SET_TX_DESC_RTS_SC(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(29, 28)) -#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(31, 30)) - -#define SET_TX_DESC_TX_RATE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(5, 0)) -#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, BIT(6)) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(12, 8)) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(16, 13)) - -#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 24), __val, GENMASK(15, 11)) - -#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ - le32p_replace_bits((__le32 *)(__pdesc + 28), __val, GENMASK(15, 0)) - -#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ - *(__le32 *)(__pdesc + 32) = cpu_to_le32(__val) - -#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ - le32_to_cpu(*(__le32 *)(__pdesc + 32)) - -#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ - *(__le32 *)(__pdesc + 40) = cpu_to_le32(__val) - -#define GET_RX_DESC_PKT_LEN(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, GENMASK(13, 0)) -#define GET_RX_DESC_CRC32(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, BIT(14)) -#define GET_RX_DESC_ICV(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, BIT(15)) -#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, GENMASK(19, 16)) -#define GET_RX_DESC_SHIFT(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, GENMASK(25, 24)) -#define GET_RX_DESC_PHYST(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, BIT(26)) -#define GET_RX_DESC_SWDEC(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, BIT(27)) -#define GET_RX_DESC_OWN(__pdesc) \ - le32_get_bits(*(__le32 *)__pdesc, BIT(31)) - -#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(13, 0)) -#define SET_RX_DESC_EOR(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(30)) -#define SET_RX_DESC_OWN(__pdesc, __val) \ - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)) - -#define GET_RX_DESC_PAGGR(__pdesc) \ - le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(14)) -#define GET_RX_DESC_FAGGR(__pdesc) \ - le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(15)) - -#define GET_RX_DESC_RXMCS(__pdesc) \ - le32_get_bits(*(__le32 *)(__pdesc + 12), GENMASK(5, 0)) -#define GET_RX_DESC_RXHT(__pdesc) \ - le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(6)) -#define GET_RX_DESC_SPLCP(__pdesc) \ - le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(8)) -#define GET_RX_DESC_BW(__pdesc) \ - le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(9)) - -#define GET_RX_DESC_TSFL(__pdesc) \ - le32_to_cpu(*(__le32 *)(__pdesc + 20)) - -#define GET_RX_DESC_BUFF_ADDR(__pdesc) \ - le32_to_cpu(*(__le32 *)(__pdesc + 24)) -#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ - *(__le32 *)(__pdesc + 24) = cpu_to_le32(__val) +static inline void set_tx_desc_pkt_size(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(15, 0)); +} + +static inline void set_tx_desc_offset(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(23, 16)); +} + +static inline void set_tx_desc_htc(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(25)); +} + +static inline void set_tx_desc_last_seg(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(26)); +} + +static inline void set_tx_desc_first_seg(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(27)); +} + +static inline void set_tx_desc_linip(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(28)); +} + +static inline void set_tx_desc_own(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)); +} + +static inline u32 get_tx_desc_own(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, BIT(31)); +} + +static inline void set_tx_desc_macid(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(4, 0)); +} + +static inline void set_tx_desc_agg_enable(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(5)); +} + +static inline void set_tx_desc_rdg_enable(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(7)); +} + +static inline void set_tx_desc_queue_sel(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(12, 8)); +} + +static inline void set_tx_desc_rate_id(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(19, 16)); +} + +static inline void set_tx_desc_sec_type(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(23, 22)); +} + +static inline void set_tx_desc_pkt_offset(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(30, 26)); +} + +static inline void set_tx_desc_more_frag(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 8), __val, BIT(17)); +} + +static inline void set_tx_desc_ampdu_density(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 8), __val, GENMASK(22, 20)); +} + +static inline void set_tx_desc_seq(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(27, 16)); +} + +static inline void set_tx_desc_pkt_id(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(31, 28)); +} + +static inline void set_tx_desc_rts_rate(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(4, 0)); +} + +static inline void set_tx_desc_qos(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(6)); +} + +static inline void set_tx_desc_hwseq_en(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(7)); +} + +static inline void set_tx_desc_use_rate(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(8)); +} + +static inline void set_tx_desc_disable_fb(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(10)); +} + +static inline void set_tx_desc_cts2self(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(11)); +} + +static inline void set_tx_desc_rts_enable(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(12)); +} + +static inline void set_tx_desc_hw_rts_enable(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(13)); +} + +static inline void set_tx_desc_tx_sub_carrier(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(21, 20)); +} + +static inline void set_tx_desc_data_bw(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(25)); +} + +static inline void set_tx_desc_rts_short(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(26)); +} + +static inline void set_tx_desc_rts_bw(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(27)); +} + +static inline void set_tx_desc_rts_sc(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(29, 28)); +} + +static inline void set_tx_desc_rts_stbc(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(31, 30)); +} + +static inline void set_tx_desc_tx_rate(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(5, 0)); +} + +static inline void set_tx_desc_data_shortgi(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, BIT(6)); +} + +static inline void set_tx_desc_data_rate_fb_limit(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(12, 8)); +} + +static inline void set_tx_desc_rts_rate_fb_limit(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(16, 13)); +} + +static inline void set_tx_desc_max_agg_num(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 24), __val, GENMASK(15, 11)); +} + +static inline void set_tx_desc_tx_buffer_size(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)(__pdesc + 28), __val, GENMASK(15, 0)); +} + +static inline void set_tx_desc_tx_buffer_address(u8 *__pdesc, u32 __val) +{ + *(__le32 *)(__pdesc + 32) = cpu_to_le32(__val); +} + +static inline u32 get_tx_desc_tx_buffer_address(u8 *__pdesc) +{ + return le32_to_cpu(*(__le32 *)(__pdesc + 32)); +} + +static inline void set_tx_desc_next_desc_address(u8 *__pdesc, u32 __val) +{ + *(__le32 *)(__pdesc + 40) = cpu_to_le32(__val); +} + +static inline u32 get_rx_desc_pkt_len(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, GENMASK(13, 0)); +} + +static inline u32 get_rx_desc_crc32(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, BIT(14)); +} + +static inline u32 get_rx_desc_icv(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, BIT(15)); +} + +static inline u32 get_rx_desc_drv_info_size(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, GENMASK(19, 16)); +} + +static inline u32 get_rx_desc_shift(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, GENMASK(25, 24)); +} + +static inline u32 get_rx_desc_physt(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, BIT(26)); +} + +static inline u32 get_rx_desc_swdec(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, BIT(27)); +} + +static inline u32 get_rx_desc_own(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)__pdesc, BIT(31)); +} + +static inline void set_rx_desc_pkt_len(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(13, 0)); +} + +static inline void set_rx_desc_eor(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(30)); +} + +static inline void set_rx_desc_own(u8 *__pdesc, u32 __val) +{ + le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)); +} + +static inline u32 get_rx_desc_paggr(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(14)); +} + +static inline u32 get_rx_desc_faggr(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(15)); +} + +static inline u32 get_rx_desc_rxmcs(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)(__pdesc + 12), GENMASK(5, 0)); +} + +static inline u32 get_rx_desc_rxht(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(6)); +} + +static inline u32 get_rx_desc_splcp(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(8)); +} + +static inline u32 get_rx_desc_bw(u8 *__pdesc) +{ + return le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(9)); +} + +static inline u32 get_rx_desc_tsfl(u8 *__pdesc) +{ + return le32_to_cpu(*(__le32 *)(__pdesc + 20)); +} + +static inline u32 get_rx_desc_buff_addr(u8 *__pdesc) +{ + return le32_to_cpu(*(__le32 *)(__pdesc + 24)); +} + +static inline void set_rx_desc_buff_addr(u8 *__pdesc, u32 __val) +{ + *(__le32 *)(__pdesc + 24) = cpu_to_le32(__val); +} #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ memset((void *)__pdesc, 0, \ min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)) /* For 92D early mode */ -#define SET_EARLYMODE_PKTNUM(__paddr, __value) \ - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0)) -#define SET_EARLYMODE_LEN0(__paddr, __value) \ - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4)) -#define SET_EARLYMODE_LEN1(__paddr, __value) \ - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16)) -#define SET_EARLYMODE_LEN2_1(__paddr, __value) \ - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28)) -#define SET_EARLYMODE_LEN2_2(__paddr, __value) \ - le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0)) -#define SET_EARLYMODE_LEN3(__paddr, __value) \ - le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8)) -#define SET_EARLYMODE_LEN4(__paddr, __value) \ - le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20)) +static inline void set_earlymode_pktnum(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0)); +} + +static inline void set_earlymode_len0(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4)); +} + +static inline void set_earlymode_len1(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16)); +} + +static inline void set_earlymode_len2_1(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28)); +} + +static inline void set_earlymode_len2_2(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0)); +} + +static inline void set_earlymode_len3(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8)); +} + +static inline void set_earlymode_len4(u8 *__paddr, u32 __value) +{ + le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20)); +} struct rx_fwinfo_92d { u8 gain_trsw[4]; From patchwork Thu Nov 21 21:44:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Larry Finger X-Patchwork-Id: 11256915 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F268713A4 for ; Thu, 21 Nov 2019 21:44:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C1C29206D8 for ; Thu, 21 Nov 2019 21:44:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GSI50kU1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbfKUVo1 (ORCPT ); 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[24.31.245.230]) by smtp.gmail.com with ESMTPSA id x82sm1333854oix.29.2019.11.21.13.44.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 13:44:23 -0800 (PST) From: Larry Finger To: kvalo@codeaurora.org Cc: linux-wireless@vger.kernel.org, pkshih@realtek.com, Larry Finger Subject: [PATCH 4/4] rtlwifi: rtl8192de: Convert inline routines to little-endian words Date: Thu, 21 Nov 2019 15:44:17 -0600 Message-Id: <20191121214417.29676-5-Larry.Finger@lwfinger.net> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191121214417.29676-1-Larry.Finger@lwfinger.net> References: <20191121214417.29676-1-Larry.Finger@lwfinger.net> MIME-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org In this step, the read/write routines for the descriptors are converted to use __le32 quantities, thus a lot of casts can be removed. Callback routines still use the 8-bit arrays, but these are changed within the specified routine. Signed-off-by: Larry Finger --- .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 25 +- .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 284 +++++++++--------- 2 files changed, 159 insertions(+), 150 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c index 18361f22337d..bb64612654b9 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c @@ -438,8 +438,9 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, struct ieee80211_rx_status *rx_status, - u8 *pdesc, struct sk_buff *skb) + u8 *pdesc8, struct sk_buff *skb) { + __le32 *pdesc = (__le32 *)pdesc8; struct rx_fwinfo_92d *p_drvinfo; u32 phystatus = get_rx_desc_physt(pdesc); @@ -489,8 +490,10 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, } static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc, - u8 *virtualaddress) + u8 *virtualaddress8) { + __le32 *virtualaddress = (__le32 *)virtualaddress8; + memset(virtualaddress, 0, 8); set_earlymode_pktnum(virtualaddress, ptcb_desc->empkt_num); @@ -503,7 +506,7 @@ static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc, } void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, - struct ieee80211_hdr *hdr, u8 *pdesc_tx, + struct ieee80211_hdr *hdr, u8 *pdesc8, u8 *pbd_desc_tx, struct ieee80211_tx_info *info, struct ieee80211_sta *sta, struct sk_buff *skb, @@ -514,7 +517,7 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); struct rtl_hal *rtlhal = rtl_hal(rtlpriv); struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); - u8 *pdesc = pdesc_tx; + __le32 *pdesc = (__le32 *)pdesc8; u16 seq_number; __le16 fc = hdr->frame_control; unsigned int buf_len = 0; @@ -549,7 +552,7 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, "DMA mapping error\n"); return; } - CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92d)); + clear_pci_tx_desc_content(pdesc, sizeof(struct tx_desc_92d)); if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) { firstseg = true; lastseg = true; @@ -690,7 +693,7 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, } void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, - u8 *pdesc, bool firstseg, + u8 *pdesc8, bool firstseg, bool lastseg, struct sk_buff *skb) { struct rtl_priv *rtlpriv = rtl_priv(hw); @@ -702,13 +705,14 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, skb->data, skb->len, PCI_DMA_TODEVICE); struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); __le16 fc = hdr->frame_control; + __le32 *pdesc = (__le32 *)pdesc8; if (pci_dma_mapping_error(rtlpci->pdev, mapping)) { RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "DMA mapping error\n"); return; } - CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE); + clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE); if (firstseg) set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); /* 5G have no CCK rate @@ -746,9 +750,11 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, set_tx_desc_own(pdesc, 1); } -void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, +void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, u8 desc_name, u8 *val) { + __le32 *pdesc = (__le32 *)pdesc8; + if (istx) { switch (desc_name) { case HW_DESC_OWN: @@ -787,8 +793,9 @@ void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, } u64 rtl92de_get_desc(struct ieee80211_hw *hw, - u8 *p_desc, bool istx, u8 desc_name) + u8 *p_desc8, bool istx, u8 desc_name) { + __le32 *p_desc = (__le32 *)p_desc8; u32 ret = 0; if (istx) { diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h index fe81196e46b7..80bf73fe37d1 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h @@ -16,354 +16,356 @@ /* macros to read/write various fields in RX or TX descriptors */ -static inline void set_tx_desc_pkt_size(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_pkt_size(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(15, 0)); + le32p_replace_bits(__pdesc, __val, GENMASK(15, 0)); } -static inline void set_tx_desc_offset(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_offset(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(23, 16)); + le32p_replace_bits(__pdesc, __val, GENMASK(23, 16)); } -static inline void set_tx_desc_htc(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_htc(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(25)); + le32p_replace_bits(__pdesc, __val, BIT(25)); } -static inline void set_tx_desc_last_seg(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_last_seg(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(26)); + le32p_replace_bits(__pdesc, __val, BIT(26)); } -static inline void set_tx_desc_first_seg(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_first_seg(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(27)); + le32p_replace_bits(__pdesc, __val, BIT(27)); } -static inline void set_tx_desc_linip(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_linip(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(28)); + le32p_replace_bits(__pdesc, __val, BIT(28)); } -static inline void set_tx_desc_own(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_own(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)); + le32p_replace_bits(__pdesc, __val, BIT(31)); } -static inline u32 get_tx_desc_own(u8 *__pdesc) +static inline u32 get_tx_desc_own(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, BIT(31)); + return le32_get_bits(*__pdesc, BIT(31)); } -static inline void set_tx_desc_macid(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_macid(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(4, 0)); + le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0)); } -static inline void set_tx_desc_agg_enable(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_agg_enable(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(5)); + le32p_replace_bits((__pdesc + 1), __val, BIT(5)); } -static inline void set_tx_desc_rdg_enable(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rdg_enable(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, BIT(7)); + le32p_replace_bits((__pdesc + 1), __val, BIT(7)); } -static inline void set_tx_desc_queue_sel(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_queue_sel(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(12, 8)); + le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8)); } -static inline void set_tx_desc_rate_id(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rate_id(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(19, 16)); + le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16)); } -static inline void set_tx_desc_sec_type(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_sec_type(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(23, 22)); + le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22)); } -static inline void set_tx_desc_pkt_offset(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_pkt_offset(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 4), __val, GENMASK(30, 26)); + le32p_replace_bits((__pdesc + 1), __val, GENMASK(30, 26)); } -static inline void set_tx_desc_more_frag(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_more_frag(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 8), __val, BIT(17)); + le32p_replace_bits((__pdesc + 2), __val, BIT(17)); } -static inline void set_tx_desc_ampdu_density(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_ampdu_density(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 8), __val, GENMASK(22, 20)); + le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20)); } -static inline void set_tx_desc_seq(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_seq(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(27, 16)); + le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16)); } -static inline void set_tx_desc_pkt_id(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_pkt_id(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 12), __val, GENMASK(31, 28)); + le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28)); } -static inline void set_tx_desc_rts_rate(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_rate(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(4, 0)); + le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0)); } -static inline void set_tx_desc_qos(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_qos(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(6)); + le32p_replace_bits((__pdesc + 4), __val, BIT(6)); } -static inline void set_tx_desc_hwseq_en(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_hwseq_en(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(7)); + le32p_replace_bits((__pdesc + 4), __val, BIT(7)); } -static inline void set_tx_desc_use_rate(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_use_rate(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(8)); + le32p_replace_bits((__pdesc + 4), __val, BIT(8)); } -static inline void set_tx_desc_disable_fb(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_disable_fb(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(10)); + le32p_replace_bits((__pdesc + 4), __val, BIT(10)); } -static inline void set_tx_desc_cts2self(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_cts2self(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(11)); + le32p_replace_bits((__pdesc + 4), __val, BIT(11)); } -static inline void set_tx_desc_rts_enable(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_enable(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(12)); + le32p_replace_bits((__pdesc + 4), __val, BIT(12)); } -static inline void set_tx_desc_hw_rts_enable(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_hw_rts_enable(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(13)); + le32p_replace_bits((__pdesc + 4), __val, BIT(13)); } -static inline void set_tx_desc_tx_sub_carrier(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_tx_sub_carrier(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(21, 20)); + le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20)); } -static inline void set_tx_desc_data_bw(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_data_bw(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(25)); + le32p_replace_bits((__pdesc + 4), __val, BIT(25)); } -static inline void set_tx_desc_rts_short(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_short(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(26)); + le32p_replace_bits((__pdesc + 4), __val, BIT(26)); } -static inline void set_tx_desc_rts_bw(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_bw(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, BIT(27)); + le32p_replace_bits((__pdesc + 4), __val, BIT(27)); } -static inline void set_tx_desc_rts_sc(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_sc(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(29, 28)); + le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28)); } -static inline void set_tx_desc_rts_stbc(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_stbc(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 16), __val, GENMASK(31, 30)); + le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30)); } -static inline void set_tx_desc_tx_rate(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_tx_rate(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(5, 0)); + le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); } -static inline void set_tx_desc_data_shortgi(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_data_shortgi(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, BIT(6)); + le32p_replace_bits((__pdesc + 5), __val, BIT(6)); } -static inline void set_tx_desc_data_rate_fb_limit(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_data_rate_fb_limit(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(12, 8)); + le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8)); } -static inline void set_tx_desc_rts_rate_fb_limit(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_rts_rate_fb_limit(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 20), __val, GENMASK(16, 13)); + le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13)); } -static inline void set_tx_desc_max_agg_num(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_max_agg_num(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 24), __val, GENMASK(15, 11)); + le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11)); } -static inline void set_tx_desc_tx_buffer_size(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_tx_buffer_size(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)(__pdesc + 28), __val, GENMASK(15, 0)); + le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0)); } -static inline void set_tx_desc_tx_buffer_address(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_tx_buffer_address(u32 *__pdesc, u32 __val) { - *(__le32 *)(__pdesc + 32) = cpu_to_le32(__val); + *(__pdesc + 8) = cpu_to_le32(__val); } -static inline u32 get_tx_desc_tx_buffer_address(u8 *__pdesc) +static inline u32 get_tx_desc_tx_buffer_address(u32 *__pdesc) { - return le32_to_cpu(*(__le32 *)(__pdesc + 32)); + return le32_to_cpu(*(__pdesc + 8)); } -static inline void set_tx_desc_next_desc_address(u8 *__pdesc, u32 __val) +static inline void set_tx_desc_next_desc_address(u32 *__pdesc, u32 __val) { - *(__le32 *)(__pdesc + 40) = cpu_to_le32(__val); + *(__pdesc + 10) = cpu_to_le32(__val); } -static inline u32 get_rx_desc_pkt_len(u8 *__pdesc) +static inline u32 get_rx_desc_pkt_len(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, GENMASK(13, 0)); + return le32_get_bits(*__pdesc, GENMASK(13, 0)); } -static inline u32 get_rx_desc_crc32(u8 *__pdesc) +static inline u32 get_rx_desc_crc32(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, BIT(14)); + return le32_get_bits(*__pdesc, BIT(14)); } -static inline u32 get_rx_desc_icv(u8 *__pdesc) +static inline u32 get_rx_desc_icv(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, BIT(15)); + return le32_get_bits(*__pdesc, BIT(15)); } -static inline u32 get_rx_desc_drv_info_size(u8 *__pdesc) +static inline u32 get_rx_desc_drv_info_size(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, GENMASK(19, 16)); + return le32_get_bits(*__pdesc, GENMASK(19, 16)); } -static inline u32 get_rx_desc_shift(u8 *__pdesc) +static inline u32 get_rx_desc_shift(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, GENMASK(25, 24)); + return le32_get_bits(*__pdesc, GENMASK(25, 24)); } -static inline u32 get_rx_desc_physt(u8 *__pdesc) +static inline u32 get_rx_desc_physt(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, BIT(26)); + return le32_get_bits(*__pdesc, BIT(26)); } -static inline u32 get_rx_desc_swdec(u8 *__pdesc) +static inline u32 get_rx_desc_swdec(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, BIT(27)); + return le32_get_bits(*__pdesc, BIT(27)); } -static inline u32 get_rx_desc_own(u8 *__pdesc) +static inline u32 get_rx_desc_own(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)__pdesc, BIT(31)); + return le32_get_bits(*__pdesc, BIT(31)); } -static inline void set_rx_desc_pkt_len(u8 *__pdesc, u32 __val) +static inline void set_rx_desc_pkt_len(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, GENMASK(13, 0)); + le32p_replace_bits(__pdesc, __val, GENMASK(13, 0)); } -static inline void set_rx_desc_eor(u8 *__pdesc, u32 __val) +static inline void set_rx_desc_eor(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(30)); + le32p_replace_bits(__pdesc, __val, BIT(30)); } -static inline void set_rx_desc_own(u8 *__pdesc, u32 __val) +static inline void set_rx_desc_own(u32 *__pdesc, u32 __val) { - le32p_replace_bits((__le32 *)__pdesc, __val, BIT(31)); + le32p_replace_bits(__pdesc, __val, BIT(31)); } -static inline u32 get_rx_desc_paggr(u8 *__pdesc) +static inline u32 get_rx_desc_paggr(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(14)); + return le32_get_bits(*(__pdesc + 1), BIT(14)); } -static inline u32 get_rx_desc_faggr(u8 *__pdesc) +static inline u32 get_rx_desc_faggr(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)(__pdesc + 4), BIT(15)); + return le32_get_bits(*(__pdesc + 1), BIT(15)); } -static inline u32 get_rx_desc_rxmcs(u8 *__pdesc) +static inline u32 get_rx_desc_rxmcs(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)(__pdesc + 12), GENMASK(5, 0)); + return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0)); } -static inline u32 get_rx_desc_rxht(u8 *__pdesc) +static inline u32 get_rx_desc_rxht(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(6)); + return le32_get_bits(*(__pdesc + 3), BIT(6)); } -static inline u32 get_rx_desc_splcp(u8 *__pdesc) +static inline u32 get_rx_desc_splcp(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(8)); + return le32_get_bits(*(__pdesc + 3), BIT(8)); } -static inline u32 get_rx_desc_bw(u8 *__pdesc) +static inline u32 get_rx_desc_bw(u32 *__pdesc) { - return le32_get_bits(*(__le32 *)(__pdesc + 12), BIT(9)); + return le32_get_bits(*(__pdesc + 3), BIT(9)); } -static inline u32 get_rx_desc_tsfl(u8 *__pdesc) +static inline u32 get_rx_desc_tsfl(u32 *__pdesc) { - return le32_to_cpu(*(__le32 *)(__pdesc + 20)); + return le32_to_cpu(*(__pdesc + 5)); } -static inline u32 get_rx_desc_buff_addr(u8 *__pdesc) +static inline u32 get_rx_desc_buff_addr(u32 *__pdesc) { - return le32_to_cpu(*(__le32 *)(__pdesc + 24)); + return le32_to_cpu(*(__pdesc + 6)); } -static inline void set_rx_desc_buff_addr(u8 *__pdesc, u32 __val) +static inline void set_rx_desc_buff_addr(u32 *__pdesc, u32 __val) { - *(__le32 *)(__pdesc + 24) = cpu_to_le32(__val); + *(__pdesc + 6) = cpu_to_le32(__val); } -#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ - memset((void *)__pdesc, 0, \ - min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)) +static inline void clear_pci_tx_desc_content(__le32 *__pdesc, u32 _size) +{ + memset((void *)__pdesc, 0, + min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)); +} /* For 92D early mode */ -static inline void set_earlymode_pktnum(u8 *__paddr, u32 __value) +static inline void set_earlymode_pktnum(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(2, 0)); + le32p_replace_bits(__paddr, __value, GENMASK(2, 0)); } -static inline void set_earlymode_len0(u8 *__paddr, u32 __value) +static inline void set_earlymode_len0(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(15, 4)); + le32p_replace_bits(__paddr, __value, GENMASK(15, 4)); } -static inline void set_earlymode_len1(u8 *__paddr, u32 __value) +static inline void set_earlymode_len1(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(27, 16)); + le32p_replace_bits(__paddr, __value, GENMASK(27, 16)); } -static inline void set_earlymode_len2_1(u8 *__paddr, u32 __value) +static inline void set_earlymode_len2_1(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)__paddr, __value, GENMASK(31, 28)); + le32p_replace_bits(__paddr, __value, GENMASK(31, 28)); } -static inline void set_earlymode_len2_2(u8 *__paddr, u32 __value) +static inline void set_earlymode_len2_2(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(7, 0)); + le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0)); } -static inline void set_earlymode_len3(u8 *__paddr, u32 __value) +static inline void set_earlymode_len3(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(19, 8)); + le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8)); } -static inline void set_earlymode_len4(u8 *__paddr, u32 __value) +static inline void set_earlymode_len4(u32 *__paddr, u32 __value) { - le32p_replace_bits((__le32 *)(__paddr + 4), __value, GENMASK(31, 20)); + le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20)); } struct rx_fwinfo_92d {