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[216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:02 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 1/7] thermal: sun8i: add thermal driver for H6/H5/H3/A64/A83T/R40 Date: Tue, 26 Nov 2019 21:29:29 -0800 Message-Id: <20191127052935.1719897-2-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Yangtao Li This patch adds the support for allwinner thermal sensor, within allwinner SoC. It will register sensors for thermal framework and use device tree to bind cooling device. Signed-off-by: Yangtao Li Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick Acked-by: Maxime Ripard --- MAINTAINERS | 7 + drivers/thermal/Kconfig | 14 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_thermal.c | 643 ++++++++++++++++++++++++++++++++ 4 files changed, 665 insertions(+) create mode 100644 drivers/thermal/sun8i_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index 66cc549ac327..da34f3f2e80b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -688,6 +688,13 @@ L: linux-crypto@vger.kernel.org S: Maintained F: drivers/crypto/allwinner/ +ALLWINNER THERMAL DRIVER +M: Yangtao Li +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +F: drivers/thermal/sun8i_thermal.c + ALLWINNER VPU DRIVER M: Maxime Ripard M: Paul Kocialkowski diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 001a21abcc28..0b0422e89adb 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -262,6 +262,20 @@ config SPEAR_THERMAL Enable this to plug the SPEAr thermal sensor driver into the Linux thermal framework. +config SUN8I_THERMAL + tristate "Allwinner sun8i thermal driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on HAS_IOMEM + depends on NVMEM + depends on OF + depends on RESET_CONTROLLER + help + Support for the sun8i thermal sensor driver into the Linux thermal + framework. + + To compile this driver as a module, choose M here: the + module will be called sun8i-thermal. + config ROCKCHIP_THERMAL tristate "Rockchip thermal driver" depends on ARCH_ROCKCHIP || COMPILE_TEST diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 74a37c7f847a..fa6f8b206281 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -31,6 +31,7 @@ thermal_sys-$(CONFIG_DEVFREQ_THERMAL) += devfreq_cooling.o obj-y += broadcom/ obj-$(CONFIG_THERMAL_MMIO) += thermal_mmio.o obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o +obj-$(CONFIG_SUN8I_THERMAL) += sun8i_thermal.o obj-$(CONFIG_ROCKCHIP_THERMAL) += rockchip_thermal.o obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c new file mode 100644 index 000000000000..e86b64f51196 --- /dev/null +++ b/drivers/thermal/sun8i_thermal.c @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Thermal sensor driver for Allwinner SOC + * Copyright (C) 2019 Yangtao Li + * + * Based on the work of Icenowy Zheng + * Based on the work of Ondrej Jirman + * Based on the work of Josef Gajdusek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_SENSOR_NUM 4 + +#define FT_TEMP_MASK GENMASK(11, 0) +#define TEMP_CALIB_MASK GENMASK(11, 0) +#define CALIBRATE_DEFAULT 0x800 + +#define SUN8I_THS_CTRL0 0x00 +#define SUN8I_THS_CTRL2 0x40 +#define SUN8I_THS_IC 0x44 +#define SUN8I_THS_IS 0x48 +#define SUN8I_THS_MFC 0x70 +#define SUN8I_THS_TEMP_CALIB 0x74 +#define SUN8I_THS_TEMP_DATA 0x80 + +#define SUN50I_THS_CTRL0 0x00 +#define SUN50I_H6_THS_ENABLE 0x04 +#define SUN50I_H6_THS_PC 0x08 +#define SUN50I_H6_THS_DIC 0x10 +#define SUN50I_H6_THS_DIS 0x20 +#define SUN50I_H6_THS_MFC 0x30 +#define SUN50I_H6_THS_TEMP_CALIB 0xa0 +#define SUN50I_H6_THS_TEMP_DATA 0xc0 + +#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x)) +#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) +#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) + +#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) +#define SUN50I_THS_FILTER_EN BIT(2) +#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) +#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) +#define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x) + +/* millidegree celsius */ +#define THS_EFUSE_CP_FT_MASK 0x3000 +#define THS_EFUSE_CP_FT_BIT 12 +#define THS_CALIBRATION_IN_FT 1 + +struct ths_device; + +struct tsensor { + struct ths_device *tmdev; + struct thermal_zone_device *tzd; + int id; +}; + +struct ths_thermal_chip { + bool has_mod_clk; + bool has_bus_clk_reset; + int sensor_num; + int offset; + int scale; + int ft_deviation; + int temp_data_base; + int (*calibrate)(struct ths_device *tmdev, + u16 *caldata, int callen); + int (*init)(struct ths_device *tmdev); + int (*irq_ack)(struct ths_device *tmdev); + int (*calc_temp)(struct ths_device *tmdev, + int id, int reg); +}; + +struct ths_device { + const struct ths_thermal_chip *chip; + struct device *dev; + struct regmap *regmap; + struct reset_control *reset; + struct clk *bus_clk; + struct clk *mod_clk; + struct tsensor sensor[MAX_SENSOR_NUM]; + u32 cp_ft_flag; +}; + +/* Temp Unit: millidegree Celsius */ +static int sun8i_ths_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + return tmdev->chip->offset - (reg * tmdev->chip->scale / 10); +} + +static int sun50i_h5_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + if (reg >= 0x500) + return -1191 * reg / 10 + 223000; + else if (!id) + return -1452 * reg / 10 + 259000; + else + return -1590 * reg / 10 + 276000; +} + +static int sun8i_ths_get_temp(void *data, int *temp) +{ + struct tsensor *s = data; + struct ths_device *tmdev = s->tmdev; + int val = 0; + + regmap_read(tmdev->regmap, tmdev->chip->temp_data_base + + 0x4 * s->id, &val); + + /* ths have no data yet */ + if (!val) + return -EAGAIN; + + *temp = tmdev->chip->calc_temp(tmdev, s->id, val); + /* + * According to the original sdk, there are some platforms(rarely) + * that add a fixed offset value after calculating the temperature + * value. We can't simply put it on the formula for calculating the + * temperature above, because the formula for calculating the + * temperature above is also used when the sensor is calibrated. If + * do this, the correct calibration formula is hard to know. + */ + *temp += tmdev->chip->ft_deviation; + + return 0; +} + +static const struct thermal_zone_of_device_ops ths_ops = { + .get_temp = sun8i_ths_get_temp, +}; + +static const struct regmap_config config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, + .max_register = 0xfc, +}; + +static int sun8i_h3_irq_ack(struct ths_device *tmdev) +{ + int i, state, ret = 0; + + regmap_read(tmdev->regmap, SUN8I_THS_IS, &state); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & SUN8I_THS_DATA_IRQ_STS(i)) { + regmap_write(tmdev->regmap, SUN8I_THS_IS, + SUN8I_THS_DATA_IRQ_STS(i)); + ret |= BIT(i); + } + } + + return ret; +} + +static int sun50i_h6_irq_ack(struct ths_device *tmdev) +{ + int i, state, ret = 0; + + regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) { + regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS, + SUN50I_H6_THS_DATA_IRQ_STS(i)); + ret |= BIT(i); + } + } + + return ret; +} + +static irqreturn_t sun8i_irq_thread(int irq, void *data) +{ + struct ths_device *tmdev = data; + int i, state; + + state = tmdev->chip->irq_ack(tmdev); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & BIT(i)) + thermal_zone_device_update(tmdev->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + return IRQ_HANDLED; +} + +static int sun8i_h3_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + int i; + + if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num) + return -EINVAL; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int offset = (i % 2) << 4; + + regmap_update_bits(tmdev->regmap, + SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)), + 0xfff << offset, + caldata[i] << offset); + } + + return 0; +} + +static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + struct device *dev = tmdev->dev; + int i, ft_temp; + + if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) + return -EINVAL; + + /* + * efuse layout: + * + * 0 11 16 32 + * +-------+-------+-------+ + * |temp| |sensor0|sensor1| + * +-------+-------+-------+ + * + * The calibration data on the H6 is the ambient temperature and + * sensor values that are filled during the factory test stage. + * + * The unit of stored FT temperature is 0.1 degreee celusis. + * + * We need to calculate a delta between measured and caluclated + * register values and this will become a calibration offset. + */ + ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; + tmdev->cp_ft_flag = (caldata[0] & THS_EFUSE_CP_FT_MASK) + >> THS_EFUSE_CP_FT_BIT; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int sensor_reg = caldata[i + 1]; + int cdata, offset; + int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated + * temperature from sensor reading at factory temperature + * minus actual factory temperature) * 14.88 (scale from + * temperature to register values) + */ + cdata = CALIBRATE_DEFAULT - + ((sensor_temp - ft_temp) * 10 / tmdev->chip->scale); + if (cdata & ~TEMP_CALIB_MASK) { + /* + * Calibration value more than 12-bit, but calibration + * register is 12-bit. In this case, ths hardware can + * still work without calibration, although the data + * won't be so accurate. + */ + dev_warn(dev, "sensor%d is not calibrated.\n", i); + continue; + } + + offset = (i % 2) * 16; + regmap_update_bits(tmdev->regmap, + SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), + 0xfff << offset, + cdata << offset); + } + + return 0; +} + +static int sun8i_ths_calibrate(struct ths_device *tmdev) +{ + struct nvmem_cell *calcell; + struct device *dev = tmdev->dev; + u16 *caldata; + size_t callen; + int ret = 0; + + calcell = devm_nvmem_cell_get(dev, "calibration"); + if (IS_ERR(calcell)) { + if (PTR_ERR(calcell) == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* + * Even if the external calibration data stored in sid is + * not accessible, the THS hardware can still work, although + * the data won't be so accurate. + * + * The default value of calibration register is 0x800 for + * every sensor, and the calibration value is usually 0x7xx + * or 0x8xx, so they won't be away from the default value + * for a lot. + * + * So here we do not return error if the calibartion data is + * not available, except the probe needs deferring. + */ + goto out; + } + + caldata = nvmem_cell_read(calcell, &callen); + if (IS_ERR(caldata)) { + ret = PTR_ERR(caldata); + goto out; + } + + tmdev->chip->calibrate(tmdev, caldata, callen); + + kfree(caldata); +out: + return ret; +} + +static int sun8i_ths_resource_init(struct ths_device *tmdev) +{ + struct device *dev = tmdev->dev; + struct platform_device *pdev = to_platform_device(dev); + struct resource *mem; + void __iomem *base; + int ret; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, mem); + if (IS_ERR(base)) + return PTR_ERR(base); + + tmdev->regmap = devm_regmap_init_mmio(dev, base, &config); + if (IS_ERR(tmdev->regmap)) + return PTR_ERR(tmdev->regmap); + + if (tmdev->chip->has_bus_clk_reset) { + tmdev->reset = devm_reset_control_get(dev, 0); + if (IS_ERR(tmdev->reset)) + return PTR_ERR(tmdev->reset); + + tmdev->bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(tmdev->bus_clk)) + return PTR_ERR(tmdev->bus_clk); + } + + if (tmdev->chip->has_mod_clk) { + tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod"); + if (IS_ERR(tmdev->mod_clk)) + return PTR_ERR(tmdev->mod_clk); + } + + ret = reset_control_deassert(tmdev->reset); + if (ret) + return ret; + + ret = clk_prepare_enable(tmdev->bus_clk); + if (ret) + goto assert_reset; + + ret = clk_set_rate(tmdev->mod_clk, 24000000); + if (ret) + goto bus_disable; + + ret = clk_prepare_enable(tmdev->mod_clk); + if (ret) + goto bus_disable; + + ret = sun8i_ths_calibrate(tmdev); + if (ret) + goto mod_disable; + + return 0; + +mod_disable: + clk_disable_unprepare(tmdev->mod_clk); +bus_disable: + clk_disable_unprepare(tmdev->bus_clk); +assert_reset: + reset_control_assert(tmdev->reset); + + return ret; +} + +static int sun8i_h3_thermal_init(struct ths_device *tmdev) +{ + int val; + + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN8I_THS_MFC, + SUN50I_THS_FILTER_EN | + SUN50I_THS_FILTER_TYPE(1)); + /* + * clkin = 24MHz + * filter_samples = 4 + * period = 0.25s + * + * x = period * clkin / 4096 / filter_samples - 1 + * = 365 + */ + val = GENMASK(7 + tmdev->chip->sensor_num, 8); + regmap_write(tmdev->regmap, SUN8I_THS_IC, + SUN50I_H6_THS_PC_TEMP_PERIOD(365) | val); + /* + * T_acq = 20us + * clkin = 24MHz + * + * x = T_acq * clkin - 1 + * = 479 + */ + regmap_write(tmdev->regmap, SUN8I_THS_CTRL0, + SUN8I_THS_CTRL0_T_ACQ0(479)); + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN8I_THS_CTRL2, + SUN8I_THS_CTRL2_T_ACQ1(479) | val); + + return 0; +} + +/* + * Without this undocummented value, the returned temperatures would + * be higher than real ones by about 20C. + */ +#define SUN50I_H6_CTRL0_UNK 0x0000002f + +static int sun50i_h6_thermal_init(struct ths_device *tmdev) +{ + int val; + + /* + * T_acq = 20us + * clkin = 24MHz + * + * x = T_acq * clkin - 1 + * = 479 + */ + regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, + SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, + SUN50I_THS_FILTER_EN | + SUN50I_THS_FILTER_TYPE(1)); + /* + * clkin = 24MHz + * filter_samples = 4 + * period = 0.25s + * + * x = period * clkin / 4096 / filter_samples - 1 + * = 365 + */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_PC, + SUN50I_H6_THS_PC_TEMP_PERIOD(365)); + /* enable sensor */ + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val); + /* thermal data interrupt enable */ + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val); + + return 0; +} + +static int sun8i_ths_register(struct ths_device *tmdev) +{ + int i; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + tmdev->sensor[i].tmdev = tmdev; + tmdev->sensor[i].id = i; + tmdev->sensor[i].tzd = + devm_thermal_zone_of_sensor_register(tmdev->dev, + i, + &tmdev->sensor[i], + &ths_ops); + if (IS_ERR(tmdev->sensor[i].tzd)) + return PTR_ERR(tmdev->sensor[i].tzd); + } + + return 0; +} + +static int sun8i_ths_probe(struct platform_device *pdev) +{ + struct ths_device *tmdev; + struct device *dev = &pdev->dev; + int ret, irq; + + tmdev = devm_kzalloc(dev, sizeof(*tmdev), GFP_KERNEL); + if (!tmdev) + return -ENOMEM; + + tmdev->dev = dev; + tmdev->chip = of_device_get_match_data(&pdev->dev); + if (!tmdev->chip) + return -EINVAL; + + platform_set_drvdata(pdev, tmdev); + + ret = sun8i_ths_resource_init(tmdev); + if (ret) + return ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = tmdev->chip->init(tmdev); + if (ret) + return ret; + + ret = sun8i_ths_register(tmdev); + if (ret) + return ret; + + /* + * Avoid entering the interrupt handler, the thermal device is not + * registered yet, we deffer the registration of the interrupt to + * the end. + */ + ret = devm_request_threaded_irq(dev, irq, NULL, + sun8i_irq_thread, + IRQF_ONESHOT, "ths", tmdev); + if (ret) + return ret; + + return ret; +} + +static int sun8i_ths_remove(struct platform_device *pdev) +{ + struct ths_device *tmdev = platform_get_drvdata(pdev); + + clk_disable_unprepare(tmdev->mod_clk); + clk_disable_unprepare(tmdev->bus_clk); + reset_control_assert(tmdev->reset); + + return 0; +} + +static const struct ths_thermal_chip sun8i_a83t_ths = { + .sensor_num = 3, + .scale = 705, + .offset = 191668, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun8i_h3_ths = { + .sensor_num = 1, + .scale = 1211, + .offset = 217000, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun8i_r40_ths = { + .sensor_num = 3, + .offset = 251086, + .scale = 1130, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_a64_ths = { + .sensor_num = 3, + .offset = 253890, + .scale = 1170, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_h5_ths = { + .sensor_num = 2, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun50i_h5_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_h6_ths = { + .sensor_num = 2, + .has_bus_clk_reset = true, + .ft_deviation = 7000, + .offset = 187744, + .scale = 672, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun50i_h6_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct of_device_id of_ths_match[] = { + { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, + { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths }, + { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths }, + { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, + { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, of_ths_match); + +static struct platform_driver ths_driver = { + .probe = sun8i_ths_probe, + .remove = sun8i_ths_remove, + .driver = { + .name = "sun8i-thermal", + .of_match_table = of_ths_match, + }, +}; +module_platform_driver(ths_driver); + +MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SOC"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Nov 27 05:29:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11263457 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 465401390 for ; Wed, 27 Nov 2019 05:30:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0E51C2084B for ; Wed, 27 Nov 2019 05:30:35 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:03 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 2/7] dt-bindings: thermal: add YAML schema for sun8i-thermal driver bindings Date: Tue, 26 Nov 2019 21:29:30 -0800 Message-Id: <20191127052935.1719897-3-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Yangtao Li sun8i-thermal driver supports thermal sensor in wide range of Allwinner SoCs. Add YAML schema for its bindings. Signed-off-by: Yangtao Li Signed-off-by: Vasily Khoruzhick --- .../thermal/allwinner,sun8i-a83t-ths.yaml | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml new file mode 100644 index 000000000000..e622f0a4be90 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/allwinner,sun8i-a83t-ths.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SUN8I Thermal Controller Device Tree Bindings + +maintainers: + - Yangtao Li + +properties: + compatible: + oneOf: + - const: allwinner,sun8i-a83t-ths + - const: allwinner,sun8i-h3-ths + - const: allwinner,sun8i-r40-ths + - const: allwinner,sun50i-a64-ths + - const: allwinner,sun50i-h5-ths + - const: allwinner,sun50i-h6-ths + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + anyOf: + - items: + - const: bus + - const: mod + - items: + - const: bus + + '#thermal-sensor-cells': + enum: [ 0, 1 ] + description: | + Definition depends on soc version: + + For "allwinner,sun8i-h3-ths", + value must be 0. + For all other compatibles + value must be 1. + + nvmem-cells: + maxItems: 1 + items: + - description: Calibration data for thermal sensors + + nvmem-cell-names: + items: + - const: calibration + +required: + - compatible + - reg + - interrupts + - '#thermal-sensor-cells' + +examples: + - | + ths_a83t: ths@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + - | + ths_h3: ths@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + clocks = <&ccu 0>, <&ccu 1>; + clock-names = "bus", "mod"; + resets = <&ccu 2>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + - | + ths_h6: ths@5070400 { + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + clocks = <&ccu 0>; + clock-names = "bus"; + resets = <&ccu 2>; + interrupts = <0 15 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + +... From patchwork Wed Nov 27 05:29:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11263455 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3709615AB for ; Wed, 27 Nov 2019 05:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0AB792084B for ; Wed, 27 Nov 2019 05:30:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mhEmJx9h" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726470AbfK0FaG (ORCPT ); Wed, 27 Nov 2019 00:30:06 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:41347 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726219AbfK0FaF (ORCPT ); Wed, 27 Nov 2019 00:30:05 -0500 Received: by mail-pg1-f193.google.com with SMTP id l26so60549pgb.8; Tue, 26 Nov 2019 21:30:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=irJ5JXDAAWtDIqC+IX6BV3MY5DktCoDeX+ljdjsD0XI=; b=mhEmJx9hcwu5d1h9HTaGxnILMXdc/7kSoKUUBfqVL0r1k5OXwgnv8wBTxtEFm7Osky BFg1rZoQso8y0b6302pp7BaU6+l+veKvr2d2k2iM9ye60J0mT9tzXyyvA0jRbtNO2KzX lOq5tGLsjneCg9GQMW/nq6V5gV7PSiMxUD0S2YbTNYlq5pZ+mCIMmN+GQPRZdXawACG0 St975uAtwxmbBvx8FfOv9jB0VDJXxkgm+CeqXCFg+Klenk6sTyMuIFK/ADzAwSy0H6bG CFgWgJacIFBmfjca5oLZD5f4LJyyKsjICugTWvcXlMJPGHkJ33kkPALH0jtrNDtwIcPz YEpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=irJ5JXDAAWtDIqC+IX6BV3MY5DktCoDeX+ljdjsD0XI=; b=HfasC3yCll+lZTH537H9OtK5cheipYXWDEL8snloZPFZ2um8QnTKJYTVKWpe6XCtt9 F/BagAjKPS5F2akhIhEDcVHXaICByQT4WrP+94aQZGMwlkVFWwRDilW8cmpg07VuraO/ 59vuFWd7vbyynU2Lh7ZH97XVWfcY8ze3iIGJJ2kMsZSYQJNjrq5CTvU+92Av0GPpR7ae Lx6YNs7bowqyPTJw/TGL3F3hk8aTpEdEOpMIpMkADSXYrr/CFsf0i4Fs5VO3Y+utmKeh O80WMrSANj/y6Rx9EtRwD6t6ggJTC+ccI4rHJ/Ly1Gjd/BG8Od9oWmq2pCj4D1FFooki WVNg== X-Gm-Message-State: APjAAAW1GJecPZsAdWNZ5Xn501jC7Rv+RrCciGQUOqL+MRyRcnB8zflH EhRstXcefj7tqDl3G2AQ/So= X-Google-Smtp-Source: APXvYqz8sVivaA2EbLiosDrKvBFKz+ssRSlkYw2TUmhAhOCKERRFiVZSgC2YBw7AstdoX0IbBoWQPg== X-Received: by 2002:a63:2b51:: with SMTP id r78mr2801429pgr.4.1574832605006; Tue, 26 Nov 2019 21:30:05 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:04 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 3/7] ARM: dts: sun8i-a83t: Add thermal sensor and thermal zones Date: Tue, 26 Nov 2019 21:29:31 -0800 Message-Id: <20191127052935.1719897-4-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There are three sensors, two for each CPU cluster, one for GPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm/boot/dts/sun8i-a83t.dtsi | 36 +++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 74bb053cf23c..902fee8be688 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -50,6 +50,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -581,6 +582,12 @@ sid: eeprom@1c14000 { compatible = "allwinner,sun8i-a83t-sid"; reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 8>; + }; }; usb_otg: usb@1c19000 { @@ -1156,5 +1163,34 @@ #address-cells = <1>; #size-cells = <0>; }; + + ths: ths@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = ; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; }; }; From patchwork Wed Nov 27 05:29:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11263447 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D399F15AB for ; Wed, 27 Nov 2019 05:30:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B0D4E207DD for ; Wed, 27 Nov 2019 05:30:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JI9vifZO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726858AbfK0FaI (ORCPT ); Wed, 27 Nov 2019 00:30:08 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:46306 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726655AbfK0FaI (ORCPT ); Wed, 27 Nov 2019 00:30:08 -0500 Received: by mail-pg1-f193.google.com with SMTP id k1so1837079pga.13; Tue, 26 Nov 2019 21:30:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vhMu4ADnQOnOcJ6BIbNumeV+R111igTahrNXaoaT2bg=; b=JI9vifZO/hlNlsVdVbkQAosj4wct0Y/Ey9lvPG25NoShcDsu71L11PV96pOoMZL980 5OITy+OqvSpfCMS4dHDjs+M9mEvAXpC1wPk0vzK5SAaM6xGy2F32057VuoCjH5P0Mz5I ksBf/dHPnPYiBp+jVZIbJmg4T7Zr0L6frm4tgTZYPA8/Vjnhg/Lif+jKoCRmIpVec24Z 3nRW0I5i/LWRo5q9smCmOtu9ecJtC0384AvF8Fa+hGl43nnexUQHchB5yX3mvbZS9Ope U6ptKcW6pV6EGCxhP/yzZs150YOd+LEMO6ovqiDy1R75y2l6o8Jw8oWjT2MA1Im1z1b8 XYLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vhMu4ADnQOnOcJ6BIbNumeV+R111igTahrNXaoaT2bg=; b=VNj6vkzPDe2c2aqnRYSD5sUBUN2yaYtLSXY9uD3jGNejFIgk3W9Ds87ErmVGfKAXU6 //KBTWG3Y5vQgx/YQTEytwQO9kOzZXsov3swsKJbquLYe46Ty6wRnvUyvPIo2d5/4tdt 44/lu6ue2mLkBgpGPN9QIdd9pVk+pot+I5g9j6md1cXH0IqL0a8NeNt5+EJ6Fmb1di54 H4vI+hv8G50T/g2UHO6wHSf46D/FRGZVaswpxkDm4iWWkZBNQRo0mI1oz93z6VaeKaD8 lclBZrmc0rfNocJmMZkkSOvWQ+mAOHilc2sA9NKgHDTRQTASPJUK9Fos+/6j8xiGcaIE 77+g== X-Gm-Message-State: APjAAAWognbgcMZR6V9Os3mUDX0cxSuwqGGfsLVhT6W5qaw+5AOVs+qY j90JjR9cD6vx8FDlDmtspIw= X-Google-Smtp-Source: APXvYqzVeWRQSqkKyH0MFBGH6b0eZNxA9y0WDKi5fRr/9ehuoyu+hi9MIjxq+m8LFWvRCkkg2Ut39Q== X-Received: by 2002:a62:b40b:: with SMTP id h11mr44293621pfn.57.1574832605993; Tue, 26 Nov 2019 21:30:05 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:05 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 4/7] ARM: dts: sun8i-h3: Add thermal sensor and thermal zones Date: Tue, 26 Nov 2019 21:29:32 -0800 Message-Id: <20191127052935.1719897-5-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There is just one sensor for the CPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm/boot/dts/sun8i-h3.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index e37c30e811d3..42fd0418d678 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -177,6 +177,26 @@ assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; + + ths: ths@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; }; }; @@ -234,4 +254,10 @@ &sid { compatible = "allwinner,sun8i-h3-sid"; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 4>; + }; }; From patchwork Wed Nov 27 05:29:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11263445 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA08A1390 for ; Wed, 27 Nov 2019 05:30:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8892D2084B for ; Wed, 27 Nov 2019 05:30:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TH8Cv41K" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726719AbfK0FaI (ORCPT ); Wed, 27 Nov 2019 00:30:08 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:43295 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726558AbfK0FaH (ORCPT ); Wed, 27 Nov 2019 00:30:07 -0500 Received: by mail-pf1-f193.google.com with SMTP id h14so196207pfe.10; Tue, 26 Nov 2019 21:30:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K9R7+DQrvs6TQPapCAJo0gk7ntwM61doRyvwyArb+eI=; b=TH8Cv41KFqnO7YoWhF3rUR1KCNUQJDWeIWCGHjxg+IoW5wMeCB2YlPG+nzKRWR7hf0 MxQ0cDN93bo4wWlrE9FvswOP05pIKVpdcEhRj0WcRGaQYcb3WLXGFM9YlVQCJ1UI/0u7 Lp8gLjpxu1/xO7JUwotlfW0WFz1XiwHhSHACilfn7HOzTcXC7QMiGQjcnqNFhU13Mdle 5SFBHc0iO4GABmm+pWKmStDq/jZF9s4RXg0VWfeP5X/+bZaWSZy0ihRODHIc+W8K8bpN CXEfV5zgzQ0zp9rAkPfkqpjFp+H/FLGZQZ/ZHOFzBLoaIhMxC7sDnUeHJ+OeSU7sRv7b 02DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K9R7+DQrvs6TQPapCAJo0gk7ntwM61doRyvwyArb+eI=; b=DtTXgQRbsZRJ7OdosyAKb3zQWATHuPl+Oh8vPn6cmT30MiC9LNvhAF2/J4eYFrDlhd kdLH68w1PDwJUxpMGb8qkDRA3ZdIqogmm0oRzTUSXBC21oonOczQZpIgaX7MSqh2Jdsl SdTpmnuDDkmZN5z+A/M+d7ZKlDNwasEszQ80YhIqinCnYbIL3TpHsIKC0K2zuDMox0rt mtAJ3Ilpo77/PfOKlZJUSQkxqGoagkRN1vxijOHCapZvNsdVByoJacjOomMiSA9rcRgZ hYECPwURssylD6ITRH9nfvMXMpou710Zqj3XNfDgvRvEOK7gb16oczm0TCeDOZtq/tW1 ckng== X-Gm-Message-State: APjAAAWlaqGqSH5WmvWmvBZ1FwjflYkqp/CUlV2jVyHW2VeVhLtR9WDD UMOLC2c9jBTlD5W/l5HBH98= X-Google-Smtp-Source: APXvYqxTI+MD/D0kvl0k+/tjZfeKHHZWlWyAB8qP26s2p6gtSih/hYSQl8OXFDwnSnq2wB0zXiS2ug== X-Received: by 2002:aa7:90d5:: with SMTP id k21mr45284823pfk.178.1574832606794; Tue, 26 Nov 2019 21:30:06 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:06 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 5/7] arm64: dts: allwinner: sun50i-h5: Add thermal sensor and thermal zones Date: Tue, 26 Nov 2019 21:29:33 -0800 Message-Id: <20191127052935.1719897-6-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There are two sensors, one for CPU, one for GPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index f002a496d7cb..27fb0d2fc9a7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -167,6 +167,32 @@ assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; + + ths: ths@1c25000 { + compatible = "allwinner,sun50i-h5-ths"; + reg = <0x01c25000 0x400>; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; }; }; @@ -212,4 +238,10 @@ &sid { compatible = "allwinner,sun50i-h5-sid"; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 4>; + }; }; From patchwork Wed Nov 27 05:29:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11263451 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E8AE15AB for ; Wed, 27 Nov 2019 05:30:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E1B0520835 for ; Wed, 27 Nov 2019 05:30:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fYLCla6V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727047AbfK0FaV (ORCPT ); Wed, 27 Nov 2019 00:30:21 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:37304 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfK0FaI (ORCPT ); Wed, 27 Nov 2019 00:30:08 -0500 Received: by mail-pl1-f193.google.com with SMTP id bb5so9227110plb.4; Tue, 26 Nov 2019 21:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=es+5okh9NS8TG2ZO2TIeJ4gr7E8aOMvh1xmhynBOxJ0=; b=fYLCla6VxiSdLxhIX+tOV9FiLnql2QSoN0V37eLRAwt/jUaz1fVC07pqIjcXCWloxI jc7L9C4W2UhhYd/QumnwLyI3s1blAn/R7lDsICqQ0uWV5vLr8HiKZYIh+UOo9XIhCV6c jOwWm8ctIIjtZLWE3H4I8upcwgZWEPKm/NMv5mAEmkFzyoXAFjyZDO0mPEDs7uqyipPU ohTlRSE54YOCLys+z02lkvZiIC9VEagy8yJquEBXKgHAwGdyGdhGoGBBX4sETQCpoDLn 3DDREwO2KDrLy14DRMK49F+qJrg1el63Ci5fOnB4tUbVrYnGS9bEKfIa+4jQ5Dgc/MyX jx4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=es+5okh9NS8TG2ZO2TIeJ4gr7E8aOMvh1xmhynBOxJ0=; b=KUG6EITOmst5/v3rfPF/jkO4RuC5Sk16Xv0dOY1pp7obkh8/wCRGwWmkFuZSfLFyfV jYuNmE07QXQ529KfB/oKKgvcFZZyJ5Ax/UAihdLBDhpH+X2tXqNzUDVlHDNdE/5De/J3 xJqG47Du9C+vy5MEXXuxPxYJfm38Y9rF7oZ2btvRktE/YJq5uKjJjpMje1O86TI1tZlh GDqr2TpS3B2KF8z3EDlQr4dVLc5xSHEusjS7QlpRnpIaeJRK9QSDCJ5kABzNGKXKZA5a O3QiZIY92+b7bC4iW72OXXHjrtPY74+cpuE3n/1U1JvdZNMpQb2vHDA24ihFRKc1iWYe KTww== X-Gm-Message-State: APjAAAUK+Z5WKLWJx1xUZfQDPiZfavvRtK20tuFeihC9TEkYauhzu7z5 DtF0oxw11fLv4eHIrpO9FJM= X-Google-Smtp-Source: APXvYqxqWeCIs+6yPmdynGT8mgYF35CDJXNWdDsV9G7Ufe6WhLxoqDLju9vn+6ZrizPnQ0hgDtcZsg== X-Received: by 2002:a17:90a:a607:: with SMTP id c7mr3716982pjq.61.1574832607717; Tue, 26 Nov 2019 21:30:07 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:07 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 6/7] arm64: dts: allwinner: sun50i-h6: Add thermal sensor and thermal zones Date: Tue, 26 Nov 2019 21:29:34 -0800 Message-Id: <20191127052935.1719897-7-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There are two sensors, one for CPU, one for GPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 0d5ea19336a1..18288387762f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -210,6 +211,12 @@ sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x6>; + }; }; watchdog: watchdog@30090a0 { @@ -792,5 +799,31 @@ #address-cells = <1>; #size-cells = <0>; }; + + ths: ths@5070400 { + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; }; }; From patchwork Wed Nov 27 05:29:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11263443 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4FBD71390 for ; Wed, 27 Nov 2019 05:30:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2D800207DD for ; Wed, 27 Nov 2019 05:30:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Gxdw2rKq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725861AbfK0FaP (ORCPT ); Wed, 27 Nov 2019 00:30:15 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33759 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726873AbfK0FaJ (ORCPT ); Wed, 27 Nov 2019 00:30:09 -0500 Received: by mail-pg1-f196.google.com with SMTP id 6so5667315pgk.0; Tue, 26 Nov 2019 21:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x/g/N4KzHVV4RuzvNHUGZqmzy45B3KGb/OK0/1dB9T8=; b=Gxdw2rKqQP1tFFYTh/7YkqTFLDu3h8wGRO7A1pwADtbKv2Icos2XLtwyzFORJg/COV TGLg+lJEUAZMQtn6c/DFzattserk6a18kPE5ZaGOBFHdH+5MrZecQxb6/iQh3dbUrT8u hdlMKJw3tj/OITbVx3catDXjgCa6Lb2AWMv0s/4UQzk91IWq2EN3SZQILiAtMa4BcQ2g CEBOf6ALxwOV0q2OndJ+0UwkdUHDI7Nu3zV/2kzhFWqRZQPfCP4rUcgLPteBn5Fxh/24 jDN2vJM4bRSFNsu0p62O3obzwE92hYEy7tibnNz/X2KCALhL0CwRtQDB/Tb7pBcvQ0be wNZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x/g/N4KzHVV4RuzvNHUGZqmzy45B3KGb/OK0/1dB9T8=; b=oiOLqhLHR+2n6qhdMV4fhBr8fQci/Vten/w50JtPe6o+c+JpPddWRw6ElpTTA6NQI/ Yxol+UoFSUoxg2/jQUp+U0GEVzWxEFClPV9sagar36l8oD2ySr3hfOqeon8gIWHcv4El m4WSzfd0mXYZCwv67YOF3dna/gIbCB184lV4Pxi+PURKgYUse77IFZZuw1XANCDnlQ3G VCeRnjuT0CnfoOpQEkUKKCWukf3OdjBF8IROyh/psSPAKP2AtGzxyJn77SikdVYHuM47 IIUaGk/kpmXe1ZECXbsXnrLEG8KRWr3mcnb7XIGYRMx3OR6bVA5PBf55jN4NKi+g6WAb UAUA== X-Gm-Message-State: APjAAAVUgH5hm6VKo9ARufkbqAF8nvthgWH2BDyUjWu/2oU9ii0RAUXI gV7TYpgBnjar6GjKWQm0XiI= X-Google-Smtp-Source: APXvYqytlD1vXHcdOuDq5LuRIkSh1p/G+80uJlZCuAO/WdysYgSu7XidkxJyqo2lBaGefFezyXGcUA== X-Received: by 2002:aa7:8517:: with SMTP id v23mr44949740pfn.75.1574832608526; Tue, 26 Nov 2019 21:30:08 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id p38sm4360825pjp.27.2019.11.26.21.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2019 21:30:08 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Eduardo Valentin , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v6 7/7] arm64: dts: allwinner: a64: Add thermal sensors and thermal zones Date: Tue, 26 Nov 2019 21:29:35 -0800 Message-Id: <20191127052935.1719897-8-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191127052935.1719897-1-anarsoul@gmail.com> References: <20191127052935.1719897-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org A64 has 3 thermal sensors: 1 for CPU, 2 for GPU. Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 70f4cce6be43..59ef6410c6e0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -49,6 +49,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -202,6 +203,29 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu0_thermal: gpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + + gpu1_thermal: gpu1-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -476,6 +500,12 @@ sid: eeprom@1c14000 { compatible = "allwinner,sun50i-a64-sid"; reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 0x6>; + }; }; usb_otg: usb@1c19000 { @@ -792,6 +822,18 @@ status = "disabled"; }; + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun50i-a64-ths"; + reg = <0x01c25000 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>;