From patchwork Thu Sep 20 10:06:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 10607313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 575A8913 for ; Thu, 20 Sep 2018 10:07:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 41D902D07C for ; Thu, 20 Sep 2018 10:07:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 357CA2D08D; Thu, 20 Sep 2018 10:07:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 705892D07C for ; Thu, 20 Sep 2018 10:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y+SuFJ+BYQOxnzM48Zjr2BfTV5hfm2bnJRMjvjj4jC0=; b=MCvstG6twsRgKq nd/FX4zYaBAveDrm7SiqaZn5lWIgXGdYS1ZxzrUiOUMOfa77FhXpdi+axcLuWZ5xWjlSlQAW0gMnt ff0Dhsh7H2MpfH5uPgEnZzz7uzu1wwGikyeZFiw7fYXUyB90jTTYSryy+wE+NZBxxDkmKYsIC0Zl1 D6WnvRvjzzvtnraeG0u75BzaGGUExTkqoMJXra9BPhlkPoqPxu+nJbidt7VH+0v4za1ajqKgjEoqT 4DG903sVlC8bGdNOfKcjmWuP+slOnMEOiWqRmYWsyyyB2ijgU0Qp0TmBdOrTuYtzfraK8XadTuJEB o2GLNyb5CycdCRH/VDJg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vrz-0001op-BZ; Thu, 20 Sep 2018 10:07:35 +0000 Received: from mail-eopbgr50076.outbound.protection.outlook.com ([40.107.5.76] helo=EUR03-VE1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vrt-0001nl-Pd for linux-arm-kernel@lists.infradead.org; Thu, 20 Sep 2018 10:07:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7UoHKzRUM4Rc1K65M2cWPvUaeNiIh/eVzAHvLglLFMc=; b=IFQunbaNAJzKvdHeAmC166M5dxElW83QVQ1LtOyIcIyYRfs9SYqauXnEjcvwql7traQuWTBTP+aT8TxgKzFUv7DkW6+er0bq0AfmaKly5jnGLX1emtzUZxdFqpzbzDc+u808JmSM+QBbYYajX1AdgDHt8e00nZMc+LWljDF9+4U= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; Received: from fsr-ub1664-175.ea.freescale.net (95.76.156.53) by VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.17; Thu, 20 Sep 2018 10:07:10 +0000 From: Abel Vesa To: Lucas Stach , Sascha Hauer , Dong Aisheng , Fabio Estevam , Anson Huang , Andrey Smirnov , Rob Herring Subject: [PATCH v7 2/5] clk: imx: add fractional PLL output clock Date: Thu, 20 Sep 2018 13:06:37 +0300 Message-Id: <1537438000-20313-3-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> References: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> MIME-Version: 1.0 X-Originating-IP: [95.76.156.53] X-ClientProxiedBy: AM3PR05CA0108.eurprd05.prod.outlook.com (2603:10a6:207:1::34) To VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 576b1c26-00fd-4ccc-d87e-08d61ee0d4ef X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:VI1PR04MB1616; X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 3:e+0UFPI0T8iDXPHEgn/juAH7jH0k507EDSs9k/8zG9NTDYIsF18JCMQ0C66W7XxaTSBcWlJzJ6rdtgxpu+g+GabMlEhdtg/Rpn+zG1H8+lOiaasLm1k5ADBoI7EQVFtIWnER5q7XIvzDAPA7UFBsNg7qZRlOeGlpHg7277c+ksH22Xw3ou1+uPI7dtRTuTPnkNQWSAh9WQHrlLeuI0G5/BBhrf9gRUC/nlq8rlpQo6apDQB22eNMxR8CfPEXBr7J; 25:0vXbDH6Td+p7dC+I+JPJgl2TlT4GBc4BIWNX0v6jn8pRgPC1AdX8/XTYxIYl8D8C6SU5yXGZaES86I8JpVtuusp3ocZ5cq1Rn7FuOGwbqBsWkKwCMn/udyt4FqmJOlwk7M9xzsGrle+GwhmfAbm9d3I1OatslAZhZTH9fK6TQUa6jsX/m35OoevihAdn6uQn2EuNd9gA/UOS4LS5gVvF160q9/eXnQqtuCE9TEtyyDwWAoSDTS0qFjyts1FAX4hlZEhSgFeL/Vi2X2F77OFhWTBdKS02u2lIuFosiS2KjcpIazAGuJAhT8+pdpIdLiTVHu8g7MDgIU7rdX3GZEh+MixweaVHgiPKu6gX+1txNrw=; 31:EEpmsyadpXCJ1RFtXwYumf5bkjQ+etQ1Jk2mWyz2KNmmcxxBojXKAvZm0JzYdf1fEcHZ/FeNWIq/pNFfPnCgV3hPhq31YYpVHdld0BdHM4TmAjIJxnkFBYHN+VtfgOBcqaDiI1fHWv/YMVovSqht7sfgAWMnsWZVWu0qdp+7/CPykKcRvNYa2A1kRMfm7tPzeNHkDlG2RlYFth29igCExiBwiAJ81Cf0KAUUBY8gXsk= X-MS-TrafficTypeDiagnostic: VI1PR04MB1616: X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 20:xw5NH5upBxQE3NTS25ZaSh8w/q/4LanG8UqhQz2GwNWSbTpT0NwvjBT9uEyiSaMVwo275YyHZe0E08Bim5mGuXN4tUKaL3jJqfl71tHq5CcR8z3YbqxfIqqzXGmfpJhTfU+iPyj3bEZ4X9I1ZT3fLBJ0lgAtmT/D4zgq2iWF2lbWZYBqloJ6lSbdqcwkN31T3QFcq/iCgoaZd1PTzObkCqHjLwgPz1EvM7Q+7UXLhRKk29owhA86QFXHJjxuwCK0+Gf/ACczxLAAQbpoe0dB7HvgYAuMQCEPxhd9ICCtzOMDoDUIUQacdKNr4fDOE8zAcNtACizqXhG319JB9sCshbH2+CWHb0is3VhT8ws0XKqWhokMFTbUFj0ygR+VRf1BjsrxQM1cO3YgM/ljnEpNlamwJswVxxRrd+dCtMXjhvloIo4363hcaKKlol41VCHGEJWSTiEYpxqBlKKz2mc/DGKX92aHUHzVNnOTompAEAlzY8t2rD+q8SDdwgfUTHtU; 4:82cUSNyEcKcvyqUUmt5BErCNbFiJtjCnDXGyVvPHzrayTP3FIxat/18evxV+dsvt5ietL4s4enyrHHJlCQVi3Ns35yDVYiKvrV0OwwK53z8kPuxbpr7eoZN+wMX2/XTp9cZvl+1JxYopcDr5oSVo9Qdjal70PMUWpj+PimsPkVX7N35vAG0B0Vfqjkb6QKHWjP+geiCKeViQcu1z75dsJoJBnJ8WcVN8SWd1wvwZbMcA+DAAsVisTwQusPLPo1xYwckA8cy5p1D/KXMBaZVs6ntyKJw2r94bnkVYOeDNhIKDom1TMSYBj27cynU1Zjgd X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(93006095)(93001095)(10201501046)(3002001)(6055026)(149027)(150027)(6041310)(20161123558120)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123564045)(201708071742011)(7699051); SRVR:VI1PR04MB1616; BCL:0; PCL:0; RULEID:; SRVR:VI1PR04MB1616; X-Forefront-PRVS: 0801F2E62B X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(366004)(396003)(39860400002)(136003)(346002)(376002)(199004)(189003)(8676002)(36756003)(6666003)(8936002)(5660300001)(2906002)(50226002)(3846002)(68736007)(50466002)(53936002)(6116002)(66066001)(86362001)(478600001)(97736004)(14444005)(39060400002)(6506007)(6512007)(25786009)(316002)(486006)(51416003)(52116002)(6486002)(386003)(476003)(446003)(7736002)(2616005)(4326008)(16586007)(16526019)(47776003)(81156014)(44832011)(7416002)(186003)(48376002)(110136005)(54906003)(26005)(305945005)(81166006)(105586002)(106356001)(76176011)(956004)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB1616; H:fsr-ub1664-175.ea.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; VI1PR04MB1616; 23:5hFMcz7BhvgIhN9j+P3HwGdFoSy+UozFwAxStmDGb?= BXLU7Gz7cbRVVGdiIxBe2H654iJ5sHek8k8tUFQuLxGFcIzSLjATDlMO8L8wu/JrKW6ZfolqwiT1RyP3od+iRTeZqI7kv8Xd4sGXjh4V+EtQzwyLJH5t8Y/Yh5Phq4Pn+lS/aEV/xtvHREvOFp573ovz2FrFqHl61J1h7I6ESWvoFoiFtVVaO0YnjDlBdvMe/VqadbqfnGVsP8bHkiLhDua0qkMIrqwgCE57ZhZKr2sKrlcXPNF1X5I4gP9yWEmsBXQmEME9rMdfvXLIH+TBaPOT4BNLvStx8CHqsRafszUHIlrnjMmJ66Lj+VsjnNUH5o/4HKDC14W2rsqEGWD7fTy50vRUxMzGGN5UXFbCRF+Fi7hlVd+ACRwBDmRG9fbuvsMGXOh3WEiV9dSIRHsLBcXhKZZXu3hxIcLL5mJFuTF0uu9wnQeOabSs7oyXIUbZQqFZwHwunLagfiyzIVBKMVtOyT3HbzbCb86CLWqUskmq9UfcE48M+aXTWUVt+1NeD/ovXDmaAUhjB372k6YEKJqf1MMtPWySfrsXOZcpygHE5kAm+nEBdXW7pe56/Jq25R1EvwYFORgFLUBdBdD+WMzmFaldc3vNu+0vJR9nnFZhcnnJ1BZpr8gwFRXJKfwe16495vLhmFVUzzkXqEA8klXdt2IJyVQhnUfFj2Ajf8pU4/ZZ88PGu4IZKcSUZjdF5E9rzjg6wG2+pJU/AR+VTTWV1jh2HJW5cp7F7+xo1pnOJs3MnmPCzokwXJ+rCZ6GFOJMp5p7fb32zCLJ7K8TCLHM4h7h7YwGsbfIoNTGldfXykc+rbylvq9oeOqX8rxR9nVxrC/FDd3dBDa1tU5FuSFipVugDaJ1u7Qi2hZVbfZpNAUBBSCrpUs2WDjh23veI0zI4nWknMJpz7x0ZmZSB1DRZS4I/ASX+fn1/1Er3aCoPfNUFSba/ZXSytQvRGHgnirDrqZunymNiurQG25ZAoLhh3IAFAGFoULxsbKETlpNMwZ6+uMmR0r13PyH2apJK4HWxjjttX3TIOfhujPNC/r/yyVau1fzmUnARYwl4khr8VqFkoiiIgXWyMKkXs3jlBlj7bWBwX0DA58Qi9F6IRixmrgh3QVNIc/mcZU0Q7q5tfZGqHhskcSdyvx9r6vBNI0QDng+HEXMzpQAgtRVTgmtJWcf+3rSu29z4f4piyMbKPv8aOExnnfMLD1jfdlYiSrYMKPUuU1KQw89pnvhwCu X-Microsoft-Antispam-Message-Info: c3XVPajemmHjVm5rHnpr3CGE5vxT685l+9TOPBfzkSr2GIGPHsL92CsOvrbLZ/r4wDkbKOZCDOibkAI/wuFNschbj/kedOmNE2FSzp9A4dZZsHG+ZNEO4Gg8uDmtF89jgrLvmu3I3CE3BGim1GrJssH8qXsuQcUs+5ik1OhGcjhYYbpjuXa9Wc5y03nzKnPwnor4r7j8HPrmft1qY+JzEnHYH2Zc0tXvYTgIGCd46tjDPHyo2ygk5r7VQ0xpkJ8YBw78ucAHE4O6g47DPPjFYskSBmIP47rxYHv0N1BT8Lfc88o4NUgGosfjob1VtUfJNLWBWY5Xy9XhG7kP1rai7sTsO/qv4JjCo6tZCd1k7Rk= X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 6:p+cr9d1Di87aOTayeUIzOye/9wORSJqq3FJzuCXYTaQJFP0ERS5i2CEO9DCW5n0pjkJ0kwpqDtNRvGJoJDrc7Tn99rBzpg3z046vQ16jedoFwQwi2Q4yzQDrV4w6f7qilhk8FswlFAq4L1HRrxYXymsy5CoU5F1WOEW12iaFr5lcmLuWEy+hspztBwzoJVyB7ViaOeNaLD+09ZRkjdoXWIejQm3M9usdP4sX7lU1iNaVK+QrX+BSNyXn4gvo3Sloh+Hmo742InTVrFXnkgbmSVMMj7/VAisULtQwPiORHx0wtk84ZEEjhY5h33jXBN8G5h3rZahqFKkaDNyHKXO8RFhkDYMTxDFpDIFCLCSruRn5z2eoT9BYYbsnPyyHHZKXc6qbXcHeZgtvsyNcZi/SVdN4/+z3LrSCi97j+y0SPyf+cJ3KMiPs9gl5HZSWZLyLNw0tsH0M08P4EfAiERvkeg==; 5:fAPu6n7VPSBDzd/YDwJqjuR/JfpNDJGr1b0tt7ihTupM2UfaM3R1njZpmf8BNWkTNW2siVrjOGj6lytD/CQplhpfimxZZECqUrLtRuLeHoxWhsqXEG7IZid3T865NPJizUvSGs/u6inNkPQhWCaUEMTVH3iv6MjtYIuie2yKk50=; 7:z1EWUabo/m4HMYplpz+I8Mqk0Z8qHfTsK8vS7UkT7OfptYLxNDMLF52L5m7dNHGBg28/5hUxNGV1Ev0HXnJ7238QJZ/+PkJnTWUTGvBs374oXI13MAhHwy977IlgQPcM2fBW4Nt1vDI3OkgM8f1x6nHyfrGFv9S528aBko7htdY5YknPIh4KGsJ+ggICZ4n/ZppFHuW4MZmW9QsDcL5J3CIB8sIBYz65m2D9WBnvPAu0Kci4jzlONKtTfst2nu7x SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2018 10:07:10.0879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 576b1c26-00fd-4ccc-d87e-08d61ee0d4ef X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1616 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_030729_998961_87FCDFDC X-CRM114-Status: GOOD ( 18.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , Stephen Boyd , Michael Turquette , open list , "open list:COMMON CLK FRAMEWORK" , Abel Vesa , linux-imx@nxp.com, Shawn Guo , Sascha Hauer , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lucas Stach This is a new clock type introduced on i.MX8. Signed-off-by: Lucas Stach Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-frac-pll.c | 230 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 3 + 3 files changed, 234 insertions(+) create mode 100644 drivers/clk/imx/clk-frac-pll.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 8c3baa7..4893c1f 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -6,6 +6,7 @@ obj-y += \ clk-cpu.o \ clk-fixup-div.o \ clk-fixup-mux.o \ + clk-frac-pll.o \ clk-gate-exclusive.o \ clk-gate2.o \ clk-pllv1.o \ diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c new file mode 100644 index 0000000..c80c6ed --- /dev/null +++ b/drivers/clk/imx/clk-frac-pll.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP. + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLL_CFG0 0x0 +#define PLL_CFG1 0x4 + +#define PLL_LOCK_STATUS BIT(31) +#define PLL_PD 19 +#define PLL_PD_MASK BIT(PLL_PD) +#define PLL_BYPASS 14 +#define PLL_BYPASS_MASK BIT(PLL_BYPASS) +#define PLL_NEWDIV_VAL BIT(12) +#define PLL_NEWDIV_ACK BIT(11) +#define PLL_FRAC_DIV_MASK 0xffffff +#define PLL_INT_DIV_MASK 0x7f +#define PLL_OUTPUT_DIV_MASK 0x1f +#define PLL_FRAC_DENOM 0x1000000 + +struct clk_frac_pll { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw) + +static int clk_wait_lock(struct clk_frac_pll *pll) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(10); + u32 val; + + /* Wait for PLL to lock */ + do { + if (readl_relaxed(pll->base) & PLL_LOCK_STATUS) + break; + if (time_after(jiffies, timeout)) + break; + } while (1); + + return readl_poll_timeout(pll->base, val, + val & PLL_LOCK_STATUS, 0, 1000); +} + +static int clk_wait_ack(struct clk_frac_pll *pll) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(50); + u32 val; + + /* return directly if the pll is in powerdown or in bypass */ + if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) + return 0; + + /* Wait for the pll's divfi and divff to be reloaded */ + do { + if (readl_relaxed(pll->base) & PLL_NEWDIV_ACK) + break; + if (time_after(jiffies, timeout)) + break; + } while (1); + + return readl_poll_timeout(pll->base, val, + val & PLL_NEWDIV_ACK, 0, 1000); +} + +static int clk_pll_prepare(struct clk_hw *hw) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); + + return clk_wait_lock(pll); +} + +static void clk_pll_unprepare(struct clk_hw *hw) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); +} + +static int clk_pll_is_prepared(struct clk_hw *hw) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + return (val & PLL_PD_MASK) ? 0 : 1; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val, divff, divfi, divq; + u64 temp64; + + val = readl_relaxed(pll->base + PLL_CFG0); + divq = ((val & PLL_OUTPUT_DIV_MASK) + 1) * 2; + val = readl_relaxed(pll->base + PLL_CFG1); + divff = (val >> 7) & PLL_FRAC_DIV_MASK; + divfi = (val & PLL_INT_DIV_MASK); + + temp64 = (u64)parent_rate * 8; + temp64 *= divff; + do_div(temp64, PLL_FRAC_DENOM); + temp64 /= divq; + + return parent_rate * 8 * (divfi + 1) / divq + (unsigned long)temp64; +} + +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + u32 divff, divfi; + u64 temp64; + + parent_rate *= 8; + rate *= 2; + divfi = rate / parent_rate; + temp64 = (u64)(rate - divfi * parent_rate); + temp64 *= PLL_FRAC_DENOM; + do_div(temp64, parent_rate); + divff = temp64; + + temp64 = (u64)parent_rate; + temp64 *= divff; + do_div(temp64, PLL_FRAC_DENOM); + + return (parent_rate * divfi + (unsigned long)temp64) / 2; +} + +/* + * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero + * (means the PLL output will be divided by 2). So the PLL output can use + * the below formula: + * pllout = parent_rate * 8 / 2 * DIVF_VAL; + * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24. + */ +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(hw); + u32 val, divfi, divff; + u64 temp64; + int ret; + + parent_rate *= 8; + rate *= 2; + divfi = rate / parent_rate; + temp64 = (u64) (rate - divfi * parent_rate); + temp64 *= PLL_FRAC_DENOM; + do_div(temp64, parent_rate); + divff = temp64; + + val = readl_relaxed(pll->base + PLL_CFG1); + val &= ~((PLL_FRAC_DIV_MASK << 7) | (PLL_INT_DIV_MASK)); + val |= ((divff << 7) | (divfi - 1)); + writel_relaxed(val, pll->base + PLL_CFG1); + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~0x1f; + writel_relaxed(val, pll->base + PLL_CFG0); + + /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */ + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_NEWDIV_VAL; + writel_relaxed(val, pll->base + PLL_CFG0); + + ret = clk_wait_ack(pll); + + /* clear the NEV_DIV_VAL */ + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_NEWDIV_VAL; + writel_relaxed(val, pll->base + PLL_CFG0); + + return ret; +} + +static const struct clk_ops clk_frac_pll_ops = { + .prepare = clk_pll_prepare, + .unprepare = clk_pll_unprepare, + .is_prepared = clk_pll_is_prepared, + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, + .set_rate = clk_pll_set_rate, +}; + +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, + void __iomem *base) +{ + struct clk_init_data init; + struct clk_frac_pll *pll; + struct clk *clk; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + init.name = name; + init.ops = &clk_frac_pll_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 8076ec0..13daf1c 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -27,6 +27,9 @@ struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, struct clk *imx_clk_pllv2(const char *name, const char *parent, void __iomem *base); +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, + void __iomem *base); + enum imx_pllv3_type { IMX_PLLV3_GENERIC, IMX_PLLV3_SYS, From patchwork Thu Sep 20 10:06:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 10607321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B92F913 for ; Thu, 20 Sep 2018 10:08:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0985E2CD12 for ; Thu, 20 Sep 2018 10:08:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F1D2D2CD27; Thu, 20 Sep 2018 10:08:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F3A52CD12 for ; Thu, 20 Sep 2018 10:08:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qyRhcomJbw7JARakiMcjcKPM+c12gKcAp4NrUptP1N4=; b=aoZyj1O7wAQpEm MiRkJzojTTJFVUcrdvxrxsVv8ft/Zw11tPhc/eSkgdmebMDj398TEhk+EcYzZYCLRXxzf0OLBLNO0 jl83dXxtXt7fCsjnzwbscbjUOi0e7L/yq59y3F3OCyWzLfiVL7IDE5HQ9EKA2Nrgjg/jOQqha6u1s jvjS6BjLvTwzDMTL4JEGdmCcQ7R18Ij56G1X6e7NZ3qWfbHlne7/OmVnt7tRHdJNf6yzQGMkfDAjP iDmgAoA+05sDlDnkL/Z3fG87K4+R5dnTZivLbgYJ4C0djqa2yU3cx/7m0rZTONCP+Xxo1EUxoE8WN QwDPM2QiIST5fYSccNXg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vsW-00023O-U9; Thu, 20 Sep 2018 10:08:08 +0000 Received: from mail-eopbgr50076.outbound.protection.outlook.com ([40.107.5.76] helo=EUR03-VE1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vrw-0001nl-A2 for linux-arm-kernel@lists.infradead.org; Thu, 20 Sep 2018 10:07:34 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OKunZGfg6mMYdV+XMBrRxjs5w4PNvBNiaagUaJakTgY=; b=uSYnv9j2NIi8pW2aqi+7ivI8/PuiQWVHRuHpP/tXLEnmhBCpmTfnSm3mL7ZYuNB2yM1TKaX9wqDkJzDLePhY64h5quF+iIi4FBrws/gHwzU/BaGfMkrRAJHE2Oo3wwGFxrdjRxOHsGKuzaUwVfV7FISF0QzlcH6BUaojnyJ1S0s= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; Received: from fsr-ub1664-175.ea.freescale.net (95.76.156.53) by VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.17; Thu, 20 Sep 2018 10:07:13 +0000 From: Abel Vesa To: Lucas Stach , Sascha Hauer , Dong Aisheng , Fabio Estevam , Anson Huang , Andrey Smirnov , Rob Herring Subject: [PATCH v7 3/5] clk: imx: add SCCG PLL type Date: Thu, 20 Sep 2018 13:06:38 +0300 Message-Id: <1537438000-20313-4-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> References: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> MIME-Version: 1.0 X-Originating-IP: [95.76.156.53] X-ClientProxiedBy: AM3PR05CA0108.eurprd05.prod.outlook.com (2603:10a6:207:1::34) To VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4587b589-9689-4d8c-6aca-08d61ee0d707 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:VI1PR04MB1616; X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 3:mEXJGlle5oBGoiAf6rlvWiK+IEldI840YGmwCTY0nUg9lP80uNYUwFE5nsUvXdk0D+DV+NsI/Le0B8phClUo+Hz9uVS18lngdbs0k/ADEHG3fQzy2+LiUMTvN/N70YUEhyGckPQ4+MBLv8G/rdMkNyXqRvUQP/lzovKnnWoTJ6M5rWXvB+LALPGVemTRXoSqQ2hh+MEo878P6Cp+rLXv7momZDanoMkcpDspHBjNETi5gd8/NWLYFrc8+lEyGlmR; 25:f29OVr3Ktl0bdjlKUqojuRVJakuU3dHT8GqTkIG3dsUF1MkXoFevvOjgbqBiFUxRiviTFtf+qBVA+KmdS8gtYg6gEDnhP1QYEHhzn6c8MeDFHag2AoN6er+WW5rfOzN+8lB14So4yD/7GpjU/jXKDoOuYR1M11pyOIy/xW2vUCRmSGtCXkHf4i2ua7XydF0U6QbNnmllVxt5Hlr0TMbZ2B4Djc1ECwCTSVIGzjq4GTric90CN0EMf08flaJvx74ynFX4arOpOA9QkiZEx/Cl79imHGlttZVk1hL3mANZk37FRKAw6waokpkoTaY4uC+8YWttJOIiQ1Gi2xlBNW1obQ==; 31:0fC6IWHiXcSRxS+2BgVo8FAvozfcvMnud6UVbcxZ1ySEQH1KMQSa9QT/1clgFj2/zwdVLmUFGCKdGK7bqN3gNiL1hiFmlVRpc3ntK7D+vzjU67jzPiywWP988ooTk6ir8uniiFRNeGpv5OeJgJ1B2bmVw74Hj1bBGxX+75YRGvTkVsJtGNWCziGcAK5ziriZFUoINvvNw8mwVKhYxHeDJgqxUyIChG8p53GQCaR7JtM= X-MS-TrafficTypeDiagnostic: VI1PR04MB1616: X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 20:XmTk7p9gMDtQKmpNrsi9pmYQHJRkENqiyjh8qm5YYrPi7em3uSlGVx01S3EhBX9kUcl3iTqEWX1cdrNp7/38+PfNdmY0UE+JedP9Qe3yBeWZPG2PqNFYP4iroE9mATyHf1/f4+3zZeWh7OhF0cDIhcUrOSKQVh34284h9pqzbcXIY5rTFIf3phKMhh8qT1ID2rkaveGQ5PJEIh1aQR1HHZlpj5xl/Y7v2fgcgcARy4othoFVwhIcY/4V41L5AH8aEP1ndcaEy2fKzE3Goj7ClVDBbj7B1Y8vG7OXLWfqdM7YVUihMUCMAE4sHdrsCOzeqEK4Zot8m5OHl3Zszwln4WZ6/CFC0+yj7IGiKIQ6JE+ESuLtx+SqCnBUr9VmZQGCz90gkcpGShf4D6PTeAXuBi/cEvIkQA4jpKiEU6w+klFW7HAB8IRPFntRV9UZQEUNbqno63gHV1+vzG9EqYJ3cglPRFZZE4D8tgMoHBsypVcX44kbo28iXqaYOLzVtPxu; 4:C7cqTOsIDBs8XAhDO/1M4aZY4PW2rmmGoaQsdj6QulFcIunSwqaKR26e+r5cMCZidKtK6CVYRuZacqQxbVSYlF9kF4O0HA4po/HpjxXJ8hU3qzeviBjrtutf2zOaTvvH64eyWCOiA5e/f88fAqkMWA5Owo5njHnF22x7g37lbgKlQ2wVli6kopZwuxbKVuG9bgrOPIi7NgyvkRsIGwi/ErVtE4fpxgrfCKZWCflw2isE6ZMiOMcNAOQPa4Vp46Sets/r1XJBpZDkuPA0WwqhT6osvHT3xSpsyZyYNfwLPTBIumRzpR16r4n0PVb3oR7A X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(93006095)(93001095)(10201501046)(3002001)(6055026)(149027)(150027)(6041310)(20161123558120)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123564045)(201708071742011)(7699051); SRVR:VI1PR04MB1616; BCL:0; PCL:0; RULEID:; SRVR:VI1PR04MB1616; X-Forefront-PRVS: 0801F2E62B X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(366004)(396003)(39860400002)(136003)(346002)(376002)(199004)(189003)(8676002)(36756003)(6666003)(8936002)(5660300001)(2906002)(50226002)(3846002)(68736007)(50466002)(53936002)(6116002)(217873002)(66066001)(86362001)(478600001)(97736004)(14444005)(39060400002)(6506007)(6512007)(25786009)(316002)(486006)(51416003)(52116002)(6486002)(386003)(476003)(446003)(7736002)(2616005)(4326008)(16586007)(16526019)(47776003)(81156014)(44832011)(7416002)(186003)(48376002)(110136005)(54906003)(26005)(305945005)(81166006)(105586002)(106356001)(76176011)(956004)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB1616; H:fsr-ub1664-175.ea.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; VI1PR04MB1616; 23:0Vequ5dle+fG+YKSlZcCW2oUT27/EaQmQIA45AVTi?= R8JEOObZiO2GMrZBKI6uZsNp0FSwgctzhM3K1eP3R3pVFG3OB3BdJIBbaXgap30qNLLEw2a9dScAcMXHLhqHprXBWS5kXei4+26eUC4EppC/AZR70nJmiNYjcv9WclfH6Pr+UTaiL28JBBCefZb8NFj3ds8yqX3zl/oYKA9UQWqN941Apla9ouAWk9cvBj/OWCAtz36QuGrVJTBkJ29uxgyg8XAS4fYuoDOagKn3FG+3CPgQBRZoqROCvncIjNPflIKPOKyX8sL9lYV8jyxiHEYhOYWzDFeKAGt73E7kJ3csCvjpNGVhcIA7qOVd0PZ2vM2sLNbLqtpiwfryePZN3yy9ZBjb0HwWAm4hkVAbho8BUvYeLJouRDBXQp+PLuZcb9AlvsvyaASrbnHnogOsjr1E2Je/koDQxvU3ai50Vm3BaskomxL6tox8hVnp1RP0kKa1/g7+97CLMTkMl4YodqOKQ5NpUPcVJyf+9HMUQcny3njOkIex7M92Xn7wdVugzRQSPVdBfz7L/Rm7vVBWnQbGm5lTAuiId5arIEcbl/fEBSEvAqv6/9dvUGwu56eHlP6HlqMzELjZ6yFM7myaXEhHAZFcCLw3W1LfsNTVu/3UBTbA5hFcGGjPrmXwbiBgEsGMWUnHL9CPNtkhh3gVRTgGSMQ3EzJAayE55O0cMTk1dNju7aKQhHxv078vQw0ZzlXpYrvqJRZd1/XFsXvTtmkUEf4bEK2rVAs/RKz7Fkie+K0Q8McdavEmvu4SshEgQQwYVIS6Xlv9H3uu2lVVGiSn+M/uIK/A2KQuBsb8bUzD8kHCuJ3aLKtsQSgQ5QL6T9V7R9IB5n9QaCnr3uskkEQjeHY7m9KgKCnvcGcSyR4QP8lay/1H8eFxA4ISxyMPxB0rmpQkpI6Tj15JPx2peh6iqBDRIieWaGDqGQcOhOKEsP0lUg59V3v3qfodGWLra+oH0OXLOtAgptJXRbCpTO2AerjDninKk4bke7picMipi+8HGZb1aJOFIaM5xyF6+VBtiLcQviQUaggoDgL7Huusq/xFn6/5cLcQkDFsXfLsFRyds0QpeSvyWEpT2FGYetg5lQa5GKqKMf0PNqvzwfaOi7PopNPjujnsdCVL0/vM4Zl+5WkW4Z2luHeu8fvCHKTZcl+2ZMNyPWpHSV0WfuWUffwc9xnG1qlUfRbO/S989q/RUt+EF3GEZgmZu78t+LOnKbgLGQxAgwxTIy40xjaZlCHam6L+LS/9Z/hRxv2Pw== X-Microsoft-Antispam-Message-Info: MHnz7F092JzouV0y67vsY/qSvDYN3rOptWU3smCddcCZzBqQFjQOprJaGVv83cyXvImLaBncSZTH9h57lTMh4RzgpClSnfh7+WacDSSYiLFXzwSZ0SqyFeWedCZW3aThE5q3CPS2+qf60N+nTn9LGuvO3TUlc9bIr7ZrjJ+yH2XenzGUE5IgYWXGb0sokMfytLbXDfOuUnVjy/dVbmAWMVQKQJx2Y+z8rNBy6uAAeKVfT9tBsR7KTiXPO3/U5jBdGtqEkq+sF/VY9iofO7SqTQMmzfk7oBjQzijy6P5EkNeuw9i9yA3nOZVYwGKNUtsywTxIsUR5ModThPm55Mi0V+ca5vSlKpk+BJpaERwG5ss= X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 6:YMeoTdQpNWsL4bX4+0sCCKBEaGmX7Byl9WnpmJIOXSu/wJ/c+bXjS8THMBKUCE5akKtSIeJeQ5AYzfm1Tu1IjXDvIpeSRYRecVm0F1+XCOYXXg1WvC2P/aUFVaKehnEWIGZH1a0/b2IVU2x+76kMuZNOBFd98+vTc30/QUsX6sns3+7y9XB3akERa0R+qtNzxSSZnj25rbiLzhlnlyXYrp2b1CRk4Hcmbbt9lEALc9uCQ1+r2fgxBO5d9lq9SIvmRDQdEonfsoDSh3u/4ZvF5FXZWjBqKvL3X9wc9HeY/GX1HYApOGjuz/PoRoDyLK0W+5USDGaLC3EECnb0ItGPa/lCNIGT57L9/ff5obSLqXf4AZXbJ94XQy18WurbJqFo9oooUQCWnXLcz2oUdxdV64wzPGazqzzQU/hs4aJpuITOhq0c/fQZHGDgGDW9wYyTG7PVWe4bJ0fhKsSQYlhAmg==; 5:rHjsQKS/WWxEQYZpNW/0WALD/8DNJqhtgkURv52jwa8Pdz2byP5MeurkSDOD60Xr3bxSqOFyZdqvCju2kq4Sd9SMqDkVCkIn3Av/MVQLA2pKFJMe5a8MI/DNNDeMBbGVcWTRavPLGNn7ATwlcI7142cbxTyZMaMqa8Z1orAEeTU=; 7:ZBi3+7dFLFKumSDSShts55Noetnrai9nXAYf6atymUhDjoU9tCl5OsQn1UO9TbfI5CICSF2Vc6yrrdEfmmFMuPVDEjFc/Q3Pcelu8SpdR0TaCkok84Q6MHBohX1xH40jxOn+I0bTC7io25+eygiYBDTzinyb/KaQSnT5so0Y6sPAV/DjPmfSIIdhyOsGsxqDDN4UWFoHWGrU1kgDoWlYYgVuPUfLe6DnRgzyWYP2g7+pQg4Wx5Ysdyw3k4mX5ZZW SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2018 10:07:13.4907 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4587b589-9689-4d8c-6aca-08d61ee0d707 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1616 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_030732_505170_517EA0E7 X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , Stephen Boyd , Michael Turquette , open list , "open list:COMMON CLK FRAMEWORK" , Abel Vesa , linux-imx@nxp.com, Shawn Guo , Sascha Hauer , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lucas Stach The SCCG is a new PLL type introduced on i.MX8. Add support for this. The driver currently misses the PLL lock check, as the preliminary documentation mentions lock configurations, but is quiet about where to find the actual lock status signal. Signed-off-by: Lucas Stach Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-sccg-pll.c | 246 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 9 ++ 3 files changed, 257 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-sccg-pll.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 4893c1f..b87513c 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -12,7 +12,8 @@ obj-y += \ clk-pllv1.o \ clk-pllv2.o \ clk-pllv3.o \ - clk-pfd.o + clk-pfd.o \ + clk-sccg-pll.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c new file mode 100644 index 0000000..8d87ba5 --- /dev/null +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 NXP. + */ + +#include +#include +#include +#include +#include + +#include "clk.h" + +/* PLL CFGs */ +#define PLL_CFG0 0x0 +#define PLL_CFG1 0x4 +#define PLL_CFG2 0x8 + +#define PLL_DIVF1_SHIFT 13 +#define PLL_DIVF2_SHIFT 7 +#define PLL_DIVF_MASK 0x3f + +#define PLL_DIVR1_SHIFT 25 +#define PLL_DIVR2_SHIFT 19 +#define PLL_DIVR1_MASK 0x3 +#define PLL_DIVR2_MASK 0x3f +#define PLL_REF_SHIFT 0 +#define PLL_REF_MASK 0x3 + +#define PLL_LOCK_MASK BIT(31) +#define PLL_PD_MASK BIT(7) + +#define OSC_25M 25000000 +#define OSC_27M 27000000 + +struct clk_sccg_pll { + struct clk_hw hw; + void __iomem *base; +}; + +#define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw) + +static int clk_pll_wait_lock(struct clk_sccg_pll *pll) +{ + /* max lock time is 70us */ + int retry = 7; + + /* Wait for PLL to lock */ + do { + if (readl_relaxed(pll->base) & PLL_LOCK_MASK) + break; + udelay(10); + retry--; + } while (retry); + + return retry ? 0 : -ETIMEDOUT; +} + +static int clk_pll1_is_prepared(struct clk_hw *hw) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + return (val & PLL_PD_MASK) ? 0 : 1; +} + +static unsigned long clk_pll1_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val, divf; + + val = readl_relaxed(pll->base + PLL_CFG2); + divf = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK; + + return parent_rate * 2 * (divf + 1); +} + +static long clk_pll1_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + u32 div; + + div = rate / (parent_rate * 2); + + return parent_rate * div * 2; +} + +static int clk_pll1_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + u32 divf; + + divf = rate / (parent_rate * 2); + + val = readl_relaxed(pll->base + PLL_CFG2); + val &= ~(PLL_DIVF_MASK << PLL_DIVF1_SHIFT); + val |= (divf - 1) << PLL_DIVF1_SHIFT; + writel_relaxed(val, pll->base + PLL_CFG2); + + return clk_pll_wait_lock(pll); +} + +static int clk_pll1_prepare(struct clk_hw *hw) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); + + return clk_pll_wait_lock(pll); +} + +static void clk_pll1_unprepare(struct clk_hw *hw) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); + +} + +static unsigned long clk_pll2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + u32 val, ref, divr1, divf1, divr2, divf2; + u64 temp64; + + val = readl_relaxed(pll->base + PLL_CFG0); + switch ((val >> PLL_REF_SHIFT) & PLL_REF_MASK) { + case 0: + ref = OSC_25M; + break; + case 1: + ref = OSC_27M; + break; + default: + ref = OSC_25M; + break; + } + + val = readl_relaxed(pll->base + PLL_CFG2); + divr1 = (val >> PLL_DIVR1_SHIFT) & PLL_DIVR1_MASK; + divr2 = (val >> PLL_DIVR2_SHIFT) & PLL_DIVR2_MASK; + divf1 = (val >> PLL_DIVF1_SHIFT) & PLL_DIVF_MASK; + divf2 = (val >> PLL_DIVF2_SHIFT) & PLL_DIVF_MASK; + + temp64 = ref * 2; + temp64 *= (divf1 + 1) * (divf2 + 1); + + do_div(temp64, (divr1 + 1) * (divr2 + 1)); + + return (unsigned long)temp64; +} + +static long clk_pll2_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u32 div; + unsigned long parent_rate = *prate; + + div = rate / (parent_rate); + + return parent_rate * div; +} + +static int clk_pll2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + u32 val; + u32 divf; + struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); + + divf = rate / (parent_rate); + + val = readl_relaxed(pll->base + PLL_CFG2); + val &= ~(PLL_DIVF_MASK << PLL_DIVF2_SHIFT); + val |= (divf - 1) << PLL_DIVF2_SHIFT; + writel_relaxed(val, pll->base + PLL_CFG2); + + return clk_pll_wait_lock(pll); +} + +static const struct clk_ops clk_sccg_pll1_ops = { + .is_prepared = clk_pll1_is_prepared, + .recalc_rate = clk_pll1_recalc_rate, + .round_rate = clk_pll1_round_rate, + .set_rate = clk_pll1_set_rate, +}; + +static const struct clk_ops clk_sccg_pll2_ops = { + .prepare = clk_pll1_prepare, + .unprepare = clk_pll1_unprepare, + .recalc_rate = clk_pll2_recalc_rate, + .round_rate = clk_pll2_round_rate, + .set_rate = clk_pll2_set_rate, +}; + +struct clk *imx_clk_sccg_pll(const char *name, + const char *parent_name, + void __iomem *base, + enum imx_sccg_pll_type pll_type) +{ + struct clk_sccg_pll *pll; + struct clk *clk; + struct clk_init_data init; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + init.name = name; + switch (pll_type) { + case SCCG_PLL1: + init.ops = &clk_sccg_pll1_ops; + break; + case SCCG_PLL2: + init.ops = &clk_sccg_pll2_ops; + break; + default: + kfree(pll); + return ERR_PTR(-EINVAL); + } + + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + pll->hw.init = &init; + + clk = clk_register(NULL, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 13daf1c..12b3fd6 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -21,6 +21,11 @@ enum imx_pllv1_type { IMX_PLLV1_IMX35, }; +enum imx_sccg_pll_type { + SCCG_PLL1, + SCCG_PLL2, +}; + struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, const char *parent, void __iomem *base); @@ -30,6 +35,10 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent, struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, void __iomem *base); +struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, + void __iomem *base, + enum imx_sccg_pll_type pll_type); + enum imx_pllv3_type { IMX_PLLV3_GENERIC, IMX_PLLV3_SYS, From patchwork Thu Sep 20 10:06:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 10607323 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B2A71390 for ; Thu, 20 Sep 2018 10:09:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4FF5E2D052 for ; Thu, 20 Sep 2018 10:09:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 43BD42D05A; Thu, 20 Sep 2018 10:09:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ABEB92D052 for ; Thu, 20 Sep 2018 10:09:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=q+k7gw7h6oIgOaxz4eR7z7P3ZGkRPvbpqM8u4/jtuDs=; b=OK6E9LQa8WBItZ zd0ZlyiNt534GWRpCtyytYMXeXHfoXw6aRT9wtEK7Rz5FzEKOO7CRxv+hKTAjDOjTu1K0Bi2l1Y9N nYMDlwTFmoeq8tuM8hG+AcjucHu9/Vp3OQOJZ22scvJxI6tqT965IoNadKEzoscw92UxtPeyBwFG6 SbiksB8LK69WBaVDiZkBdJ/kKIbghf+1qwtmyLNVfxZawOnQ9lcB3OI9731R0kyHo8+9LrqTqQXWj x4D6+Im31o2jAn+jfCM+8PCIw/fAOhcyuKYT1xdHFWIluQQ0ZZzeClM7ZVgxd8qx7E2/bI/CnnWhS 0rchc4GE1K4GRKXH9iFg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vtJ-0002O9-3p; Thu, 20 Sep 2018 10:08:57 +0000 Received: from mail-eopbgr50076.outbound.protection.outlook.com ([40.107.5.76] helo=EUR03-VE1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vry-0001nl-HJ for linux-arm-kernel@lists.infradead.org; Thu, 20 Sep 2018 10:07:47 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rC4qgReWlVeM8uhBhAJndkxM5a15OApDARGqfn1YQLM=; b=VUWy4zGTp55KbnfKoILozgMREtOxwSlRxAIg2qc+j/JtNuPc3mcUXB1sBXLkTb0ofoWvqG1KtwLdLSC368kBPC/kzqbMW4jGrQB/cAIT8Oet9tDZQTH0bhbB9rOpVuVnddzWNa6oAx6mdwWtAVjuVVMoWXb7aqv8uphqmgb2PTs= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; Received: from fsr-ub1664-175.ea.freescale.net (95.76.156.53) by VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.17; Thu, 20 Sep 2018 10:07:17 +0000 From: Abel Vesa To: Lucas Stach , Sascha Hauer , Dong Aisheng , Fabio Estevam , Anson Huang , Andrey Smirnov , Rob Herring Subject: [PATCH v7 4/5] clk: imx: add imx composite clock Date: Thu, 20 Sep 2018 13:06:39 +0300 Message-Id: <1537438000-20313-5-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> References: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> MIME-Version: 1.0 X-Originating-IP: [95.76.156.53] X-ClientProxiedBy: AM3PR05CA0108.eurprd05.prod.outlook.com (2603:10a6:207:1::34) To VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac7544c1-e5a9-4ccf-8b51-08d61ee0d984 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:VI1PR04MB1616; X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 3:3UBxY7rJV4zEIDtxUoFFmytd9aF0SF3nF0yh8hQh+CO0HLr8nQm9E0jpzC0lHu2zYNAK6ylBfCUMAjla5ktQ67kLiI0Hftro8KUHqlEBTgAn8xMUkx8Yagk/qYyccYZ+QDC5e8pAnaO8Oo/c0FJTrMAonXFngeDelP1H3Fd0KqzfElKH7gs+BTgkuvBJGRI8rZ4xhTUOCxVKUgVFBBeSrJ2ts1m/dERr9vW36DL6SiEK9K8ZGybujL0vBASf+6Jy; 25:77H47DG9yo2EKhg7JgH5ZTFip/dnqEHJuGzjUajZa9n0POYY1bS9WLfmABAfKbl3rE4jehctQ71bUruB0hVfUk2sL93CscSFZOtYToib9GEY8UnAFk4gmzJ+SRU7HfrqkdvvXFVpOCTzF4FizmSHcYwRlimKKGuE+NIteII7Azyqb32IHMp7cCJwT/NFwAMpk5J3tmTTETea3hFBD+ZVaAFAl71BMg2DPFkrtxd2M4lWJFk4DuWJjQsgM7ueGcPiQ+ny5Md3NOM154aGAF5rYMvP5yLny0rrahsPTx6gGplydao2snEBWzTo99MMtc4pJ1Q6lCa5SHRuHuflxXZ/Fw==; 31:U9tJQ4NnBkW6nPYzpMNViW5HH5GTjJBi6zzjTCRyYkiK2cuQxL5Fz9DfeR8d92Qv4Mhmso/zTGyA8gqm6lqUkE37kmgqBrkaMFxyXHDqOeG+x1CQa4b3RwSspd9+YK5gAHfehK3a3Fk5fpfbggyv2BCAanVdS4xhAM6TbwyQK9PpAOM5ecoXfypoV7af4b7yhy3FmNYmREMz1OggP4G805beVAJlyy85V+DC0uVCg+Q= X-MS-TrafficTypeDiagnostic: VI1PR04MB1616: X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 20:Aa1eV1jJqtSkDMkRzaVpTLB4tYN9gXHk/bzJYgH9yW3qozFN4yY5JdwTr08UX0bX51z8iE3DXN5HXjzYmVnDGe2+hDgPZJhaNfzRhXV3VMf3mHsvmLKgMO+rON6Emd3icnA3HzcmamPFd54kfo110syJuOl9yY3TH0W43HGXt7MQdjAL9efizGVGANlZ3kaAmAM8ozOXe0n6FwkPm03LjFaaXs/0LKMKlQk7vWhFwlnRIhG5HuB1jJyC4x6mKA2YJoMMQyt06+wLObXhM7vJU85y4Co4PQuX/796ogOc9t888OjXQ+J19a4YGhIzc9hO4zlmiryhVBeL8mWxotpnuVFJUL6S7qBSmnsjW2m4/ryIuJxxxRVXgY8CfpcZ+S7Wnbz8+QTRY61rqyNz8YKqx3tb3lKTIupwJV28aMcGNRA/xbJR3m31vW2Fb7lcql7nhD0lR2IEDhBONTGz8ZMAwwWdSLI9WXY/lvu9IdZBrc1YLLyDyEDCzu/XWAiPU1Im; 4:1ri6+SRUNqVFvI30dCtQ52fxdbKmXo9IXCaGyVQa+H8a+0QgfUz3TjN46iM4wkG0kqdodl8eIlhmkNPOCGwKNnIf583mQMNVRJYn5VpKv6CaVoUKbswBYUKpiBjEkq+mr3cIufeY84wTDGQBS4Mk8do9JlVYwXvriDBBmFbkye8Pnbcqt9S4UgcuUJRyecTKrMz2EILFAhzYX10b5aQG/hnCdWCOErWKesoIWmcpEz4u1BwqDzbzX8L7tYFCsueV/ELUSwzXJKjohSGwH0eCKlpMGTSbppyuVH8hcFZhOps8CEV8LEtBeCf1YsHbV5sI X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(93006095)(93001095)(10201501046)(3002001)(6055026)(149027)(150027)(6041310)(20161123558120)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123564045)(201708071742011)(7699051); SRVR:VI1PR04MB1616; BCL:0; PCL:0; RULEID:; SRVR:VI1PR04MB1616; X-Forefront-PRVS: 0801F2E62B X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(366004)(396003)(39860400002)(136003)(346002)(376002)(199004)(189003)(8676002)(36756003)(6666003)(8936002)(5660300001)(2906002)(50226002)(3846002)(68736007)(50466002)(53936002)(6116002)(66066001)(575784001)(86362001)(478600001)(97736004)(14444005)(39060400002)(6506007)(6512007)(25786009)(316002)(486006)(51416003)(52116002)(6486002)(386003)(476003)(446003)(7736002)(2616005)(4326008)(16586007)(16526019)(47776003)(81156014)(44832011)(7416002)(186003)(48376002)(110136005)(54906003)(26005)(305945005)(81166006)(105586002)(106356001)(76176011)(956004)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB1616; H:fsr-ub1664-175.ea.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; VI1PR04MB1616; 23:qDplKN9bHgfJ4tEv8y/q8vW/wFlolomIVG3fxIXWC?= hVa7jVy99lCY1Q/nvu3ncq7ltPz/4aQr+zYQZq5lbVHaMi1fgFcVxZmuuP9X/pasGtBZIo9xF+8JylGKT5346ZXbhqaDdn7b2kPUA06tpqFXlQUf8S7qvF15AIR59hO+jcPV6JT/GRonHz0zl6ljPhI1U9L3g1TwKbdePktR9kLYYWHU1JbFVGs3o4lwayZt9sSAl5JzIeH4NA5wdjVw3UnQboUXeZjjRQgM7vM4y6P1KLnoWNXF3BTFlBzI06MZVoDTQXEWaUQzNHnXu7BjAsAnSod9Q3auQ3+D4BxliXS57ggMDUybWZqVLVjzLmfnDTb3UXm54EDwi/0ijt4jPpL9L5zB3//xI/UtWSjPgmG1x8WD3kQMF5JwecDMenDEAu+noUTFr9o3djFp+WpUj587IT0nnvtra66SgI7Uqp0O0chFyS/MNNJ6bfvqrBeViHYRpbnmXs/rXjnCg+SL6bgjIqyKa4Avg3yRzqGBaL5ZwSC+ByCAXTPH/OpYqLjk8+3gP2/R2u2MikP3gzHtNbe35cp24vIYu2wBYwG1GUBqaXon39yo4ucE9qbGysrpy/JddXFjEk+e/EVUw2pjZhBL18xQXTW5Pwt/HDGZQXvQtT+HayjudgL/kmwb6jiYSgmvuV/XRf7TqoW46++BXM4a9m0RTM9+LU8iWmylcSQ5Yhuj6TxNZI+FppsKSz3AAGo+mccBHh5J6ULxSz2Z3n6X/y6Dn94+IHnOKrvzXH3dlwNlfd++dTn2QIG2myiHl0QauogtgXuboa5TSM8JdjlLGaR9ZBWp0AdccjVoJ0RbS9LcNLM841wS7OoPNBP3sAmZKLbDpOD10tqZQCKTeaMJxHKuWjeQlBMUlKqeR9xyFCFEHtQO5TMQufl6w4XglWfECmQmFhq7wUPkfliRAudgG17Aj5DZK/wqLX+erp9/+IN+2Y+MFLOSGBjJpmPVVptKS++vvRl3yKsW+Upe7J+59KjljQyG/euqegrgOIkLxO8XwIAtYy/BFAjzv29B2M2ccbG3X35a19Nv/MkQ9rjB/PDwNu7g76sf6tLOZkMEF7G3PnrcILrQN67MGuTGFljoW+zqDBYvCpSnCLAhzmex5OY6gFKp/r1run4gs1hMWBECTm0P2QbKDAeNM290qXIYXyQNTmsSmoiVujap13u/YJokS96mKOTRAEdO9CXZYdMtDFZNIBqmc8FC7CT91pRlI031oNwafHS+1jydI2DmQpATkRts9FrryqijOk9AQ== X-Microsoft-Antispam-Message-Info: fO5mGYT2iskzbwweRWPMV/I4PC2+fOjPdkbiiEW6JGlDnnKSIwMuy8U34dwzzxxixx+WNjTugybvIukxK9C3ly7PqjenlblIMzn8n8wCF4b/n8pxm1Pb++yDfniDrxEe283iMSAwpGz9Tp9LMCz6Q2lJ5Xk4pM3YTiX3IZKlm7nQ7VHelmU0nMJFbz/bsOa0M9sqrZQCkkVkZGa6JoiGta+5Kz2J/HdBEJ0u92itSDO3/yKmfamXMX3PDSxDmwnLeIMGqDYi4DXjh6zb8PuX49fgXH508R8g1PDMaPCFA9OZES/6M1xi42fKszGmtgmiTfWyuPGpV9Dqs6sbprHBKTq4ObxM0VMviKZ0VQI91V0= X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 6:SF+LrJ4ck5+v9bDTU3sHWqKiFl/75ewhhP3LOYvNXi0jmkFO9ujaP2LNDKcJU6I5rRYdzZEZfBTFhdpSjCVstYCud88ZPoAg1b3/eMQIyrwdYbDRqF457bd3tKReME9cOuwN6HbQqaBd78XPB8c4axiObDyf6JaBBvrVg8shw9HHu6gPak7TZbz926J6MgNKP1AHKk8brFVtT9SRDFHjILYT25K6mP44A1Up+pQjTtl3os33ni9o59kQ8Lrq8dJPQy3Ms4bP8KGbNiI0+LGuO02HzoS/VWAdkgETmvue/zY++9KR1hXOcnerBM/9BRPINlLm1u5c2EEJXwRmTIDJVP7g0delGy0GkxFV5wbx0S0mN+8SJ/SxVDf7wHDmaG+gFDGaBsr546U80W6pWATl9cVBGx9Sxudb2+11S4R0oGgsoTLk+ZdAXXSROycypf1dnTygmDiBrFOoLb8wed+Mfg==; 5:ZAr29qFuEbS3lcdydXODbhqwjW48UcYAaMjitN8H9mm9wE6VFcfe+hLSDnSMdIvBQUpfq7NzGoRsb/QB9678ViEbNOyXeX69fAlQHHDykhJXjTWCztApMDT4Pv30t2FCws7QTYNcXl0BW4WQaNeNXfmB+6XcCoWLQXBFiRxvWqI=; 7:GDiUl6GlTtyJh/r3lBwmZZj6pq+/Czd0JBmJf49a55GBStfZwGsxvD/tXhjjTy0xk3e7wsRuBn0GdE0IeWHaVB2jShTHr+tl50NyWbrtxarcyLxBXy5080w1eaYMTSYsOjsiiYsYkxl7X/GTcwhCgF8Hp/DlkYFWA8cxhTW4IplUi0vfCuxfZexQiy51mEySiGf+8Gf16NhvnZUKpqT33FhNaiL/eQR3czk/ORxo2lgFsmiAR9DEcjMeJvaHB72y SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2018 10:07:17.7643 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac7544c1-e5a9-4ccf-8b51-08d61ee0d984 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1616 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_030734_623742_ED9D85D0 X-CRM114-Status: GOOD ( 15.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , Stephen Boyd , Michael Turquette , open list , "open list:COMMON CLK FRAMEWORK" , Abel Vesa , linux-imx@nxp.com, Shawn Guo , Sascha Hauer , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Since a lot of clocks on imx8 are formed by a mux, gate, predivider and divider, the idea here is to combine all of those into one composite clock, but we need to deal with both predivider and divider at the same time and therefore we add the imx_clk_composite_divider_ops and register the composite clock with those. Signed-off-by: Abel Vesa Suggested-by: Sascha Hauer --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-composite.c | 155 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 11 +++ 3 files changed, 167 insertions(+) create mode 100644 drivers/clk/imx/clk-composite.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b87513c..4fabb0a 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -3,6 +3,7 @@ obj-y += \ clk.o \ clk-busy.o \ + clk-composite.o \ clk-cpu.o \ clk-fixup-div.o \ clk-fixup-mux.o \ diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c new file mode 100644 index 0000000..40c2aa8 --- /dev/null +++ b/drivers/clk/imx/clk-composite.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#include "clk.h" + +#define PCG_PREDIV_SHIFT 16 +#define PCG_PREDIV_WIDTH 3 + +#define PCG_DIV_SHIFT 0 +#define PCG_DIV_WIDTH 6 + +#define PCG_PCS_SHIFT 24 +#define PCG_PCS_MASK 0x7 + +#define PCG_CGC_SHIFT 28 + +static unsigned long imx_clk_composite_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned long prediv_rate; + unsigned int prediv_value; + unsigned int div_value; + + prediv_value = clk_readl(divider->reg) >> divider->shift; + prediv_value &= clk_div_mask(divider->width); + + prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value, + NULL, divider->flags, + divider->width); + + div_value = clk_readl(divider->reg) >> PCG_DIV_SHIFT; + div_value &= clk_div_mask(PCG_DIV_WIDTH); + + return divider_recalc_rate(hw, prediv_rate, div_value, NULL, + divider->flags, PCG_DIV_WIDTH); +} + +static long imx_clk_composite_divider_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned long prediv_rate; + + prediv_rate = divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); + return divider_round_rate(hw, rate, &prediv_rate, divider->table, + PCG_DIV_WIDTH, divider->flags); +} + +static int imx_clk_composite_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned long prediv_rate; + unsigned long flags = 0; + int prediv_value; + int div_value; + u32 val; + + prediv_value = divider_get_val(rate, parent_rate, NULL, + PCG_PREDIV_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); + if (prediv_value < 0) + return prediv_value; + + prediv_rate = DIV_ROUND_UP_ULL((u64)parent_rate, prediv_value + 1); + + div_value = divider_get_val(rate, prediv_rate, NULL, + PCG_DIV_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); + if (div_value < 0) + return div_value; + + spin_lock_irqsave(divider->lock, flags); + + val = clk_readl(divider->reg); + val &= ~((clk_div_mask(divider->width) << divider->shift) | + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); + + val |= (u32)prediv_value << divider->shift; + val |= (u32)div_value << PCG_DIV_SHIFT; + clk_writel(val, divider->reg); + + spin_unlock_irqrestore(divider->lock, flags); + + return 0; +} + +static const struct clk_ops imx_clk_composite_divider_ops = { + .recalc_rate = imx_clk_composite_divider_recalc_rate, + .round_rate = imx_clk_composite_divider_round_rate, + .set_rate = imx_clk_composite_divider_set_rate, +}; + +struct clk *imx_clk_composite_flags(const char *name, + const char **parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + struct clk *clk; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + mux_hw = &mux->hw; + mux->reg = reg; + mux->shift = PCG_PCS_SHIFT; + mux->mask = PCG_PCS_MASK; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + kfree(mux); + return ERR_PTR(-ENOMEM); + } + div_hw = &div->hw; + div->reg = reg; + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + div->lock = &imx_ccm_lock; + div->flags = CLK_DIVIDER_ROUND_CLOSEST; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + kfree(mux); + kfree(div); + return ERR_PTR(-ENOMEM); + } + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = PCG_CGC_SHIFT; + + clk = clk_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ops, div_hw, + &imx_clk_composite_divider_ops, gate_hw, + &clk_gate_ops, flags); + if (IS_ERR(clk)) { + kfree(mux); + kfree(div); + kfree(gate); + } + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 12b3fd6..74d8d46 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -232,4 +232,15 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +struct clk *imx_clk_composite_flags(const char *name, const char **parent_names, + int num_parents, void __iomem *reg, unsigned long flags); + +#define imx_clk_composite(name, parent_names, reg) \ + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + +#define imx_clk_composite_critical(name, parent_names, reg) \ + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \ + CLK_IS_CRITICAL | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + #endif From patchwork Thu Sep 20 10:06:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 10607327 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB94F161F for ; Thu, 20 Sep 2018 10:09:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C39282D05F for ; Thu, 20 Sep 2018 10:09:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B4E202D069; Thu, 20 Sep 2018 10:09:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 754E92D065 for ; Thu, 20 Sep 2018 10:09:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MitCqTnEwikp6JKwU4gkSjoCSRHxBY+RtPAsykFkJ3g=; b=SMplBp1qk6mCDk 2v3hClIBUQpqIRks83W7vT4A2a+BMa3DZvzpe7AAcFmx4hHHx1Ei6Fxstc1AAsKQ4xSyICG/LaeQL IApKM2KLV0ctkW27Gt7nDWp3qzDKe7PZ/6dcW05yxsQOxXmtyEWveUwIVRCqDObOc2WuplAXvSZGE NSoq4Uq+QlNOel542lmURtSvc0TH8hsStXg/E99sRBigL/o6/96e01Wd9g2JRNE5pgiV0kNdeWzJd XLXvSpfcjoSMGZcknbYTJnyFUXN8B/9xHawG4kN3lkXtIP5fQZEgA+fvYjj1nZJgZGRt1kPX4TCHZ JJrCUbP8r08NQKxHvBCg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vtz-0002gW-Lx; Thu, 20 Sep 2018 10:09:40 +0000 Received: from mail-eopbgr50076.outbound.protection.outlook.com ([40.107.5.76] helo=EUR03-VE1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g2vsB-0001nl-Pw for linux-arm-kernel@lists.infradead.org; Thu, 20 Sep 2018 10:08:47 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Xy0BCdRmUsFqAC9sbR15aXgdeuNcqTFYYKJeVUvqhwA=; b=XPDZK0UdSjv9HKU1WcXdtxAdZlbSiE39lBotpnQt/EpLdZ1o2OUaRi33e5OiPohmqQSihcv9jWs2e/pO608YJuwKBf2amNESGN+vzCVcErUTNM++5taFm74To5SeWwgG/VhtaOhPoj+xuYXsj66MvIqAFlQVLtLaiGLUcEtAtQI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; Received: from fsr-ub1664-175.ea.freescale.net (95.76.156.53) by VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.17; Thu, 20 Sep 2018 10:07:21 +0000 From: Abel Vesa To: Lucas Stach , Sascha Hauer , Dong Aisheng , Fabio Estevam , Anson Huang , Andrey Smirnov , Rob Herring Subject: [PATCH v7 5/5] clk: imx: add clock driver for i.MX8MQ CCM Date: Thu, 20 Sep 2018 13:06:40 +0300 Message-Id: <1537438000-20313-6-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> References: <1537438000-20313-1-git-send-email-abel.vesa@nxp.com> MIME-Version: 1.0 X-Originating-IP: [95.76.156.53] X-ClientProxiedBy: AM3PR05CA0108.eurprd05.prod.outlook.com (2603:10a6:207:1::34) To VI1PR04MB1616.eurprd04.prod.outlook.com (2a01:111:e400:596b::22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 92a10757-d34f-4894-483c-08d61ee0db7b X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:VI1PR04MB1616; X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 3:5/8ovzbPjaDnQVvMe2RHIFqddtWSC3JH6+OiXR4Da4GDTxAiKGI4IDrnp3LgiPNqEwRWrBMsMMYrbdU8bwkLMbn21WnUfTj73FXf9n7py6DMn8zrMhxJoHRuHStwQisXzw9v2u9cQMOE2srFjf01CNm9+MT9ccHMu8Jd0AAWMTvObiH+wGXaJHJRmOHuMgSobxb22rJdOM0WO+OLt8CkxB0dMUN8E7dToOaQV01qik+iw0rVDJ0fgSXJXL+zuDTF; 25:Dc4AUr5xbX+WuySfmuRdWJhRUbw0KHQJxOKIrUmi+RGCmoK5N1hgo0yMnQBqhhcFJ7t/hDWodAIUwpT0hGuXZgcIMEQWOFFSI1dkbgRSPhSYSpl1VsvBvcM+uEMAyUTn+AOziz48JhjUSw4Pqpg+5Vwn4hH2+t5HkwmGgXc1qcy35ZsUh65oIChHN0nvSUdjYP12OzGRBW7TnfqxRkvetSvnI98a2JwYVN64jlKvfvrRznwKqp5veqNmA3cHowAQFrvR3qh/mTfjkVVkuXsTyjPbEYh7K9QmTPfwJosqkPZQNoZTnS9L3y7jsEhgWP+7H5JNnmHZehayEIWmg/azchuUxSTP1VxE+rRNpCwrvFU=; 31:LtLYldnuXw+jv+X7nZ5juu4pq8j0VLSzffCrcF99mrHKTfWErhiPIedRUmcFPVDfmM7FmatSK4HqUCgEgm1pmGOXOjCP2RCxiqXjlIUEpME4BQd4+pdD9P3jTesGDJprIpEe9/kEPKLGtxFJWvRdBt/LKVzCWAnjJTkoQCROhLm4205k/+RmpWVkRCtZnSAKDZ5Cj+XeDINwPglzOjIRExzQiXxIf2OB6gQNZ89xE5c= X-MS-TrafficTypeDiagnostic: VI1PR04MB1616: X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 20:gp50OOtRmmwGcnhnUG+sf1GWhchov7UBGqF+o3QaIIQMt6lbBwgEI5Zc0M9ZBvcZS6tVxHNb1RPfSN6L7lvws5PaGSHxH178yL2YphofGBCVbQ/LNHfmzojmLDMzDmTozLvU5hQWYfKYoupZPYmaMI4TRO/wMaQDgaMuwoaupiC2nnJ5ceNL4zDK+QQshEg02Jp5Geeh7hILFB1YMbpPuPngveAJjiqnsOGU7XzbRCDuRZtg4RRgmEec5JFVRgzC33B3EmweUHK5mBKV26aNELGiSkpYQC1yuIxAeCd9c2u/3hrmbxyXzSfwMaEhcs9V7W+s3KlNYelcUO/oWLDS2cqm46nxgQy0sylZvnUTyOShSTmtdKRJFi1jheCNkEt6whMyn/hXH3pC5coqqaJy9id9qGG4OJtNdI/7MsbhWrpzaAPDKnVsrT9dYb9SWrqtABFc/lD33G754qQ/T6CxuoSWgNr8iFPa7zkWrrVrAF12/0/Cr4gvRKVBHZtdER3b; 4:6jEd8FeJP4Fvrr/tJrJ1vkQq5TV9PSJP+EyTgL528b1y+a7uLrrg+WOFJpZuAk+rY9bad9p4G/BY6krvZr0/NtaX1uutCEQhkOYtNkbsmbXuUgUzYJ7kkQ2AfsJcrj92LDYx+R1K95SLKS5CnhVocVLobSt7DC0l2R6bwqEvNlf7xzXbs4z3AxC5+nCDo9YrT28GQjnmhyUjrhWovVjzUnpuNT09v5lnwP5fm6UyJgyFMvE7fxWstTPl2m5GsXVBeNAwVJrC4au4GsLeqevxFnHHiI0MrSienZ7pHQm9JIM5Ncs+1qCqbevFSA/MWV/h X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(93006095)(93001095)(10201501046)(3002001)(6055026)(149027)(150027)(6041310)(20161123558120)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123564045)(201708071742011)(7699051); SRVR:VI1PR04MB1616; BCL:0; PCL:0; RULEID:; SRVR:VI1PR04MB1616; X-Forefront-PRVS: 0801F2E62B X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(366004)(396003)(39860400002)(136003)(346002)(376002)(199004)(189003)(8676002)(36756003)(6666003)(8936002)(5660300001)(2906002)(50226002)(3846002)(68736007)(50466002)(53936002)(6116002)(66066001)(575784001)(86362001)(478600001)(97736004)(14444005)(39060400002)(6506007)(6512007)(25786009)(316002)(486006)(51416003)(52116002)(6486002)(386003)(476003)(446003)(7736002)(2616005)(4326008)(16586007)(16526019)(47776003)(81156014)(44832011)(7416002)(186003)(48376002)(110136005)(54906003)(26005)(53946003)(305945005)(81166006)(105586002)(106356001)(76176011)(956004)(11346002)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB1616; H:fsr-ub1664-175.ea.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; VI1PR04MB1616; 23:5iptNUuVGZ6nZ6Ehlyx+l0Cxf9DWQROFtUixHI59E?= hcGq9sJGm+llo8eOIo4YF8jZROgv9cxXDhvcINyErMFH84KnVZqMESYdMKHwVPwDxLp/j1z5zF22W1WAK4kTcG2fb2uPij/yDSW1Y1dzBAi7J7jz163j6KqE6otETJq3ZOmo9oLwgD2AvvtSkkV3ic+SBV3t5CStfanbx6yVJ3R5QqR8lcRiCeILovOT1aKkP2S7uMFj5mSJZBr2lj5/K14VDtCRFFsR8GI6CRMXcdqv7WWYOHB5D4/oKVNJOTuSmCw7pfeM4c/bE0zgc2LHegOLCB8hNPH/WFsYPNz2L4jX8bFHsApSkif483RlGtYe9aEnBaKrXxPfiwCeAQ+Yuk6zuj6i/qwt2wmVTtK8Vub9qseLn7NgI5S+OhzARl6eR8bkIFGnSMh2XcJLcg9JlPJrEEp9sSjBd3WBwOt9CnhhtLqaeEdw/5Z703LhVOkegj0QH37yEUQmfJA3Aw7b5cgJO++mUpEOV1ZCpOexAFnu8TIlek6m544bgSleYLiJXGgxdL4/0zJPez+cAWB5F61/yKpwPmCaaZ22L42jKfjdbJD6obZu8HlhZsrAAadN1auz032rZ/DfBCOBR4hg5C2BliUAR4C2iAoBybJuhetUsFvGBtuwoyOeQwJJCdQbIwDYLqN58k0B1HwyvjYpDL16MQjQJ2mzgzJ0AABcDWmrdELuiIsygSmiSHAKkAgBp6A4uOh+fqrYZSpKr187XD64pJLq/NhCHnk/z/G0HzDufjb5VOEudM/UVxslBpRcsGvgVsXt9dDry/c3oPZKUQ9eBG5RdEciVxYLSNDVpO3qyqHfHdSz9+ay9JG/PyhwlGmprbLA97xkzXMKzqBWnfkTRQCZWbRUKg2OKV4EFSs6cMY0vB/QI8KrbLOnDDMIGmRpQDYSggjoeUVYUOmknV9Ts2CfF63eraOa7C8oYhlEnBPKo87CSddCh8Iq9RHSH15VjgY3hfzXg0tIaMTgbNQGs0fXBSZZUS2Ru6NURRWO99fwEf2Ml9zA8uRLGrh8QVyIcc3BnRATL2E9XJM3dtErh566KMyJ+H05qloOU+UZlH0tgE1ZRat0xBeND5sRBuH0EAQarwC9kjun0YNrSxLrNJw5bWrdHy5vk8XQwAY+YAsy0IeDFMIBPhMbXbfe77nlhtRWyCI0HXVULDhuYAX5R+0viXAuvKGGehO2Jbcb+c3jUPqkWUymX3qctqGGk0zPHowh31eU+pGOvRQE9oPSyzU0wjmy9xC4Rx4aQQT+pPM6qMQ3AygXc5xiDMqRVGckMah0meW9mN1gbho3buP X-Microsoft-Antispam-Message-Info: 5E5gU79K8vGNgTesELP4u/+uvtnpgJj+qhBS+BR8sdb5vfqLHMFq+My+JnqMml/2P6ACNS+OiUAM0qBuCeTkwylUAQ401W4PaPeip4SQ/+//XTvl/IlSz0qxM3DzQlnlqvSoYA61T4rL8JC81RfimPYXh+aYNLCnXYtBbd5MkYaXaaKFnl/EPnwrLf5GjfvXq4qNqJt7gZiLYgNUTCVaFOoQSFT7emHU2tY1ItgNF3YYgaa6HNBNcXkZF2afPrC3O8VU4rciN6eznW5Y+fvai5N7nzr23T/Y2W6MlI5fCGZ/L/qgTQPirBPvUKwpyV1+NKM3t5WTg0Z2tGaflE04u6mSTpWSmaSCh4KnxrSoXhQ= X-Microsoft-Exchange-Diagnostics: 1; VI1PR04MB1616; 6:UpF2QPdmLQy4cBPPVRFfDoyzj6f8VqkGXpHduZb3/82lgEt4ZlMbhv83ZliExEiAkH6IaSQHf0h1M6z29kDazUEue+Z9iVt3s9GoIq6/bX+Sl9AjLK2s5MuzH38h0uhY0KRHCdLfBwOjnHYGvkJtJv9QhXO6rKvwmT3l2+dOmnVaB5ZG5Zl24YY+TYoYQM+nLIq29oPIl3BeEb5K83AmMLRvHT9DCypo5BsXizUhqmomrL+AUzCuNoJs4JUVmYE/Hq64TqGeXq0f72GG1NteTZxNWF54KB3WTz4CafRoPhsxxALD/vESXPez9jAP7FiyLPOa8FUzvttUBix78U9+D+Pfp0T0zCv0wC+gbjW0JvzfV953yZ0P3IQjc9FfKxP13COkJMWxYxTuHsp0GbIFTcpAxk+w7a3re55mJlDuvXhmwbSP12mez3siD+nNoNLRhgDiPd5UnbNOsNFJ2lhamQ==; 5:1wSEh20mm7MjM6lz1WMoQc0j99r2uOzcBPzZbNn9a4y8vlSND0Ykns4heORlJwLHiMcCu3K7ANPqrbvhOy3F0YqsksPQEXGeA0cbRp4RRdjBqPwnFM9uP8h3ex6sdohHaVrK7HD63SjOunhM3XI4ahbeUOZy1ISCFxnvqboGupY=; 7:/IP3ewkea8eqKFKzOgmcVgSNLUxwad89BSxVOmTcvUd8qxDhFu15rgFGxP9WjBkcp0Qw9ovfZITSAxXXsKIF785XAHDiOmE3AMTZD3xmuYjJ8IWzdl6cruRvdH0YLQcYQbdvutyJQ40tOnu4RusX2ku5bf9TypgVktMurh5mZZeTBQzYUjJEvvtMcpGk+OaCMrQdmLLMpijLEtaSAZ+MCplKvtaRP2IaSLF73IpSPLuF5Yo45KJdzpIC7xhDK20v SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2018 10:07:21.0560 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92a10757-d34f-4894-483c-08d61ee0db7b X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1616 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_030748_119858_E1416EAE X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Abel Vesa , Stephen Boyd , Michael Turquette , open list , "open list:COMMON CLK FRAMEWORK" , Abel Vesa , linux-imx@nxp.com, Shawn Guo , Sascha Hauer , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lucas Stach Add driver for the Clock Control Module found on i.MX8MQ. This is largely based on the downstream driver from Anson Huang and Bai Ping at NXP, plus the imx composite clock from Abel Vesa at NXP, with only some small adaptions to mainline from me. Signed-off-by: Lucas Stach Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx8mq.c | 602 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 36 +++ 3 files changed, 639 insertions(+) create mode 100644 drivers/clk/imx/clk-imx8mq.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 4fabb0a..64e695c 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o +obj-$(CONFIG_SOC_IMX8MQ) += clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c new file mode 100644 index 0000000..aadb523 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mq.c @@ -0,0 +1,602 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP. + * Copyright (C) 2017 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static u32 share_count_sai1; +static u32 share_count_sai2; +static u32 share_count_sai3; +static u32 share_count_sai4; +static u32 share_count_sai5; +static u32 share_count_sai6; +static u32 share_count_dcss; +static u32 share_count_nand; + +static struct clk *clks[IMX8MQ_CLK_END]; + +static const char *pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", }; +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; + +static const char *sys1_pll1_out_sels[] = {"sys1_pll1", "sys1_pll1_ref_sel", }; +static const char *sys2_pll1_out_sels[] = {"sys2_pll1", "sys1_pll1_ref_sel", }; +static const char *sys3_pll1_out_sels[] = {"sys3_pll1", "sys3_pll1_ref_sel", }; +static const char *dram_pll1_out_sels[] = {"dram_pll1", "dram_pll1_ref_sel", }; + +static const char *sys1_pll2_out_sels[] = {"sys1_pll2_div", "sys1_pll1_ref_sel", }; +static const char *sys2_pll2_out_sels[] = {"sys2_pll2_div", "sys2_pll1_ref_sel", }; +static const char *sys3_pll2_out_sels[] = {"sys3_pll2_div", "sys2_pll1_ref_sel", }; +static const char *dram_pll2_out_sels[] = {"dram_pll2_div", "dram_pll1_ref_sel", }; + +/* CCM ROOT */ +static const char *imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", + "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", }; + +static const char *imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", + "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", }; + +static const char *imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m", + "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",}; + +static const char *imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m", + "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", }; + +static const char *imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m", + "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", }; + +static const char *imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", }; + +static const char *imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", }; + +static const char *imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", + "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; + +static const char *imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m", + "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m", + "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m", + "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m", + "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m", + "sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"}; + +static const char *imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m", + "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", }; + +static const char *imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; + +static const char *imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; + +static const char *imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; + +static const char *imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; + +static const char *imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; + +static const char *imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", }; + +static const char *imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out", + "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; + +static const char *imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; + +static const char *imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; + +static const char *imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; + +static const char *imx8mq_sai2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_sai3_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_sai4_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; + +static const char *imx8mq_sai5_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_sai6_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_spdif1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext2", "clk_ext3", }; + +static const char *imx8mq_spdif2_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext3", "clk_ext4", }; + +static const char *imx8mq_enet_ref_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_500m", "sys2_pll_100m", + "sys1_pll_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", }; + +static const char *imx8mq_enet_timer_sels[] = {"osc_25m", "sys2_pll_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4", "video_pll1_out", }; + +static const char *imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "sys2_pll_125m", "sys2_pll_500m", + "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m", + "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", }; + +static const char *imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; + +static const char *imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; + +static const char *imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", + "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; + +static const char *imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; + +static const char *imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", + "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", + "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", + "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; + +static const char *imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; + +static const char *imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", + "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; + +static const char *imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m", + "sys1_pll_80m", "audio_pll1_out", "clk_ext1", }; + +static const char *imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out", + "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", }; + +static const char *imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m", + "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", }; + +static const char *imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", + "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", + "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", }; + +static const char *imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", + "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", }; + +static const char *imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out", + "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; + +static const char *imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", + "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; +static const char *imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; + +static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", "audio_pll1_out", + "video_pll1_out", "ckil", }; + +static struct clk_onecell_data clk_data; + +static void __init imx8mq_clocks_init(struct device_node *ccm_node) +{ + struct device_node *np; + void __iomem *base; + int i; + + clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(ccm_node, "ckil"); + clks[IMX8MQ_CLK_25M] = of_clk_get_by_name(ccm_node, "osc_25m"); + clks[IMX8MQ_CLK_27M] = of_clk_get_by_name(ccm_node, "osc_27m"); + clks[IMX8MQ_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1"); + clks[IMX8MQ_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2"); + clks[IMX8MQ_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3"); + clks[IMX8MQ_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4"); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6); + clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6); + clks[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_divider("vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6); + clks[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_divider("audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6); + clks[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_divider("audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6); + clks[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_divider("video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6); + clks[IMX8MQ_SYS1_PLL1_REF_DIV] = imx_clk_divider("sys1_pll1_ref_div", "sys1_pll1_ref_sel", base + 0x38, 25, 3); + clks[IMX8MQ_SYS2_PLL1_REF_DIV] = imx_clk_divider("sys2_pll1_ref_div", "sys2_pll1_ref_sel", base + 0x44, 25, 3); + clks[IMX8MQ_SYS3_PLL1_REF_DIV] = imx_clk_divider("sys3_pll1_ref_div", "sys3_pll1_ref_sel", base + 0x50, 25, 3); + clks[IMX8MQ_DRAM_PLL1_REF_DIV] = imx_clk_divider("dram_pll1_ref_div", "dram_pll1_ref_sel", base + 0x68, 25, 3); + + clks[IMX8MQ_ARM_PLL] = imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", base + 0x28); + clks[IMX8MQ_GPU_PLL] = imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", base + 0x18); + clks[IMX8MQ_VPU_PLL] = imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", base + 0x20); + clks[IMX8MQ_AUDIO_PLL1] = imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", base + 0x0); + clks[IMX8MQ_AUDIO_PLL2] = imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", base + 0x8); + clks[IMX8MQ_VIDEO_PLL1] = imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", base + 0x10); + clks[IMX8MQ_SYS1_PLL1] = imx_clk_sccg_pll("sys1_pll1", "sys1_pll1_ref_div", base + 0x30, SCCG_PLL1); + clks[IMX8MQ_SYS2_PLL1] = imx_clk_sccg_pll("sys2_pll1", "sys2_pll1_ref_div", base + 0x3c, SCCG_PLL1); + clks[IMX8MQ_SYS3_PLL1] = imx_clk_sccg_pll("sys3_pll1", "sys3_pll1_ref_div", base + 0x48, SCCG_PLL1); + clks[IMX8MQ_DRAM_PLL1] = imx_clk_sccg_pll("dram_pll1", "dram_pll1_ref_div", base + 0x60, SCCG_PLL1); + + clks[IMX8MQ_SYS1_PLL2] = imx_clk_sccg_pll("sys1_pll2", "sys1_pll1_out_div", base + 0x30, SCCG_PLL2); + clks[IMX8MQ_SYS2_PLL2] = imx_clk_sccg_pll("sys2_pll2", "sys2_pll1_out_div", base + 0x3c, SCCG_PLL2); + clks[IMX8MQ_SYS3_PLL2] = imx_clk_sccg_pll("sys3_pll2", "sys3_pll1_out_div", base + 0x48, SCCG_PLL2); + clks[IMX8MQ_DRAM_PLL2] = imx_clk_sccg_pll("dram_pll2", "dram_pll1_out_div", base + 0x60, SCCG_PLL2); + + /* PLL divs */ + clks[IMX8MQ_SYS1_PLL1_OUT_DIV] = imx_clk_divider("sys1_pll1_out_div", "sys1_pll1_out", base + 0x38, 19, 6); + clks[IMX8MQ_SYS2_PLL1_OUT_DIV] = imx_clk_divider("sys2_pll1_out_div", "sys2_pll1_out", base + 0x44, 19, 6); + clks[IMX8MQ_SYS3_PLL1_OUT_DIV] = imx_clk_divider("sys3_pll1_out_div", "sys3_pll1_out", base + 0x50, 19, 6); + clks[IMX8MQ_DRAM_PLL1_OUT_DIV] = imx_clk_divider("dram_pll1_out_div", "dram_pll1_out", base + 0x68, 19, 6); + clks[IMX8MQ_SYS1_PLL2_DIV] = imx_clk_divider("sys1_pll2_div", "sys1_pll2", base + 0x38, 1, 6); + clks[IMX8MQ_SYS2_PLL2_DIV] = imx_clk_divider("sys2_pll2_div", "sys2_pll2", base + 0x44, 1, 6); + clks[IMX8MQ_SYS3_PLL2_DIV] = imx_clk_divider("sys3_pll2_div", "sys3_pll2", base + 0x50, 1, 6); + clks[IMX8MQ_DRAM_PLL2_DIV] = imx_clk_divider("dram_pll2_div", "dram_pll2", base + 0x68, 1, 6); + + /* PLL bypass out */ + clks[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_mux("arm_pll_bypass", base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels)); + clks[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_mux("gpu_pll_bypass", base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); + clks[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_mux("vpu_pll_bypass", base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); + clks[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_mux("audio_pll1_bypass", base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); + clks[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_mux("audio_pll2_bypass", base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); + clks[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_mux("video_pll1_bypass", base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); + + clks[IMX8MQ_SYS1_PLL1_OUT] = imx_clk_mux("sys1_pll1_out", base + 0x30, 5, 1, sys1_pll1_out_sels, ARRAY_SIZE(sys1_pll1_out_sels)); + clks[IMX8MQ_SYS2_PLL1_OUT] = imx_clk_mux("sys2_pll1_out", base + 0x3c, 5, 1, sys2_pll1_out_sels, ARRAY_SIZE(sys2_pll1_out_sels)); + clks[IMX8MQ_SYS3_PLL1_OUT] = imx_clk_mux("sys3_pll1_out", base + 0x48, 5, 1, sys3_pll1_out_sels, ARRAY_SIZE(sys3_pll1_out_sels)); + clks[IMX8MQ_DRAM_PLL1_OUT] = imx_clk_mux("dram_pll1_out", base + 0x60, 5, 1, dram_pll1_out_sels, ARRAY_SIZE(dram_pll1_out_sels)); + clks[IMX8MQ_SYS1_PLL2_OUT] = imx_clk_mux("sys1_pll2_out", base + 0x30, 4, 1, sys1_pll2_out_sels, ARRAY_SIZE(sys1_pll2_out_sels)); + clks[IMX8MQ_SYS2_PLL2_OUT] = imx_clk_mux("sys2_pll2_out", base + 0x3c, 4, 1, sys2_pll2_out_sels, ARRAY_SIZE(sys2_pll2_out_sels)); + clks[IMX8MQ_SYS3_PLL2_OUT] = imx_clk_mux("sys3_pll2_out", base + 0x48, 4, 1, sys3_pll2_out_sels, ARRAY_SIZE(sys3_pll2_out_sels)); + clks[IMX8MQ_DRAM_PLL2_OUT] = imx_clk_mux("dram_pll2_out", base + 0x60, 4, 1, dram_pll2_out_sels, ARRAY_SIZE(dram_pll2_out_sels)); + + /* unbypass all the plls */ + clk_set_parent(clks[IMX8MQ_GPU_PLL_BYPASS], clks[IMX8MQ_GPU_PLL]); + clk_set_parent(clks[IMX8MQ_VPU_PLL_BYPASS], clks[IMX8MQ_VPU_PLL]); + clk_set_parent(clks[IMX8MQ_AUDIO_PLL1_BYPASS], clks[IMX8MQ_AUDIO_PLL1]); + clk_set_parent(clks[IMX8MQ_AUDIO_PLL2_BYPASS], clks[IMX8MQ_AUDIO_PLL2]); + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_BYPASS], clks[IMX8MQ_VIDEO_PLL1]); + clk_set_parent(clks[IMX8MQ_SYS3_PLL1_OUT], clks[IMX8MQ_SYS3_PLL1]); + clk_set_parent(clks[IMX8MQ_SYS3_PLL2_OUT], clks[IMX8MQ_SYS3_PLL2_DIV]); + + /* PLL OUT GATE */ + clks[IMX8MQ_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x28, 21); + clks[IMX8MQ_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x18, 21); + clks[IMX8MQ_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x20, 21); + clks[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base + 0x0, 21); + clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21); + clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21); + clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_gate("sys1_pll_out", "sys1_pll2_out", base + 0x30, 9); + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_gate("sys2_pll_out", "sys2_pll2_out", base + 0x3c, 9); + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_gate("sys3_pll_out", "sys3_pll2_out", base + 0x48, 9); + clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll2_out", base + 0x60, 9); + + /* SYS PLL fixed output */ + clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20); + clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10); + clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8); + clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6); + clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5); + clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4); + clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3); + clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2); + clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1); + + clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20); + clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10); + clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8); + clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6); + clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5); + clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4); + clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3); + clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2); + clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1); + + np = ccm_node; + base = of_iomap(np, 0); + WARN_ON(!base); + /* CORE */ + clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)); + clks[IMX8MQ_CLK_VPU_SRC] = imx_clk_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels)); + clks[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels)); + clks[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels)); + clks[IMX8MQ_CLK_A53_CG] = imx_clk_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL); + clks[IMX8MQ_CLK_VPU_CG] = imx_clk_gate3("vpu_cg", "vpu_src", base + 0x8100, 28); + clks[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28); + clks[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28); + + clks[IMX8MQ_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); + clks[IMX8MQ_CLK_VPU_DIV] = imx_clk_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3); + clks[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); + clks[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); + + /* BUS */ + clks[IMX8MQ_CLK_MAIN_AXI] = imx_clk_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800); + clks[IMX8MQ_CLK_ENET_AXI] = imx_clk_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880); + clks[IMX8MQ_CLK_NAND_USDHC_BUS] = imx_clk_composite("nand_usdhc_bus", imx8mq_nand_usdhc_sels, base + 0x8900); + clks[IMX8MQ_CLK_VPU_BUS] = imx_clk_composite("vpu_bus", imx8mq_vpu_bus_sels, base + 0x8980); + clks[IMX8MQ_CLK_DISP_AXI] = imx_clk_composite("disp_axi", imx8mq_disp_axi_sels, base + 0x8a00); + clks[IMX8MQ_CLK_DISP_APB] = imx_clk_composite("disp_apb", imx8mq_disp_apb_sels, base + 0x8a80); + clks[IMX8MQ_CLK_DISP_RTRM] = imx_clk_composite("disp_rtrm", imx8mq_disp_rtrm_sels, base + 0x8b00); + clks[IMX8MQ_CLK_USB_BUS] = imx_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80); + clks[IMX8MQ_CLK_GPU_AXI] = imx_clk_composite("gpu_axi", imx8mq_gpu_axi_sels, base + 0x8c00); + clks[IMX8MQ_CLK_GPU_AHB] = imx_clk_composite("gpu_ahb", imx8mq_gpu_ahb_sels, base + 0x8c80); + clks[IMX8MQ_CLK_NOC] = imx_clk_composite_critical("noc", imx8mq_noc_sels, base + 0x8d00); + clks[IMX8MQ_CLK_NOC_APB] = imx_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80); + + /* AHB */ + clks[IMX8MQ_CLK_AHB] = imx_clk_composite("ahb", imx8mq_ahb_sels, base + 0x9000); + clks[IMX8MQ_CLK_AUDIO_AHB] = imx_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100); + + /* IPG */ + clks[IMX8MQ_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); + clks[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); + + /* IP */ + clks[IMX8MQ_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); + + clks[IMX8MQ_CLK_DRAM_ALT] = imx_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000); + clks[IMX8MQ_CLK_DRAM_APB] = imx_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080); + clks[IMX8MQ_CLK_VPU_G1] = imx_clk_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100); + clks[IMX8MQ_CLK_VPU_G2] = imx_clk_composite("vpu_g2", imx8mq_vpu_g2_sels, base + 0xa180); + clks[IMX8MQ_CLK_DISP_DTRC] = imx_clk_composite("disp_dtrc", imx8mq_disp_dtrc_sels, base + 0xa200); + clks[IMX8MQ_CLK_DISP_DC8000] = imx_clk_composite("disp_dc8000", imx8mq_disp_dc8000_sels, base + 0xa280); + clks[IMX8MQ_CLK_PCIE1_CTRL] = imx_clk_composite("pcie1_ctrl", imx8mq_pcie1_ctrl_sels, base + 0xa300); + clks[IMX8MQ_CLK_PCIE1_PHY] = imx_clk_composite("pcie1_phy", imx8mq_pcie1_phy_sels, base + 0xa380); + clks[IMX8MQ_CLK_PCIE1_AUX] = imx_clk_composite("pcie1_aux", imx8mq_pcie1_aux_sels, base + 0xa400); + clks[IMX8MQ_CLK_DC_PIXEL] = imx_clk_composite("dc_pixel", imx8mq_dc_pixel_sels, base + 0xa480); + clks[IMX8MQ_CLK_LCDIF_PIXEL] = imx_clk_composite("lcdif_pixel", imx8mq_lcdif_pixel_sels, base + 0xa500); + clks[IMX8MQ_CLK_SAI1] = imx_clk_composite("sai1", imx8mq_sai1_sels, base + 0xa580); + clks[IMX8MQ_CLK_SAI2] = imx_clk_composite("sai2", imx8mq_sai2_sels, base + 0xa600); + clks[IMX8MQ_CLK_SAI3] = imx_clk_composite("sai3", imx8mq_sai3_sels, base + 0xa680); + clks[IMX8MQ_CLK_SAI4] = imx_clk_composite("sai4", imx8mq_sai4_sels, base + 0xa700); + clks[IMX8MQ_CLK_SAI5] = imx_clk_composite("sai5", imx8mq_sai5_sels, base + 0xa780); + clks[IMX8MQ_CLK_SAI6] = imx_clk_composite("sai6", imx8mq_sai6_sels, base + 0xa800); + clks[IMX8MQ_CLK_SPDIF1] = imx_clk_composite("spdif1", imx8mq_spdif1_sels, base + 0xa880); + clks[IMX8MQ_CLK_SPDIF2] = imx_clk_composite("spdif2", imx8mq_spdif2_sels, base + 0xa900); + clks[IMX8MQ_CLK_ENET_REF] = imx_clk_composite("enet_ref", imx8mq_enet_ref_sels, base + 0xa980); + clks[IMX8MQ_CLK_ENET_TIMER] = imx_clk_composite("enet_timer", imx8mq_enet_timer_sels, base + 0xaa00); + clks[IMX8MQ_CLK_ENET_PHY_REF] = imx_clk_composite("enet_phy", imx8mq_enet_phy_sels, base + 0xaa80); + clks[IMX8MQ_CLK_NAND] = imx_clk_composite("nand", imx8mq_nand_sels, base + 0xab00); + clks[IMX8MQ_CLK_QSPI] = imx_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80); + clks[IMX8MQ_CLK_USDHC1] = imx_clk_composite("usdhc1", imx8mq_usdhc1_sels, base + 0xac00); + clks[IMX8MQ_CLK_USDHC2] = imx_clk_composite("usdhc2", imx8mq_usdhc2_sels, base + 0xac80); + clks[IMX8MQ_CLK_I2C1] = imx_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00); + clks[IMX8MQ_CLK_I2C2] = imx_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80); + clks[IMX8MQ_CLK_I2C3] = imx_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00); + clks[IMX8MQ_CLK_I2C4] = imx_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80); + clks[IMX8MQ_CLK_UART1] = imx_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00); + clks[IMX8MQ_CLK_UART2] = imx_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80); + clks[IMX8MQ_CLK_UART3] = imx_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000); + clks[IMX8MQ_CLK_UART4] = imx_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080); + clks[IMX8MQ_CLK_USB_CORE_REF] = imx_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100); + clks[IMX8MQ_CLK_USB_PHY_REF] = imx_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180); + clks[IMX8MQ_CLK_ECSPI1] = imx_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280); + clks[IMX8MQ_CLK_ECSPI2] = imx_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300); + clks[IMX8MQ_CLK_PWM1] = imx_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380); + clks[IMX8MQ_CLK_PWM2] = imx_clk_composite("pwm2", imx8mq_pwm2_sels, base + 0xb400); + clks[IMX8MQ_CLK_PWM3] = imx_clk_composite("pwm3", imx8mq_pwm3_sels, base + 0xb480); + clks[IMX8MQ_CLK_PWM4] = imx_clk_composite("pwm4", imx8mq_pwm4_sels, base + 0xb500); + clks[IMX8MQ_CLK_GPT1] = imx_clk_composite("gpt1", imx8mq_gpt1_sels, base + 0xb580); + clks[IMX8MQ_CLK_WDOG] = imx_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900); + clks[IMX8MQ_CLK_WRCLK] = imx_clk_composite("wrclk", imx8mq_wrclk_sels, base + 0xb980); + clks[IMX8MQ_CLK_CLKO2] = imx_clk_composite("clko2", imx8mq_clko2_sels, base + 0xba80); + clks[IMX8MQ_CLK_DSI_CORE] = imx_clk_composite("dsi_core", imx8mq_dsi_core_sels, base + 0xbb00); + clks[IMX8MQ_CLK_DSI_PHY_REF] = imx_clk_composite("dsi_phy_ref", imx8mq_dsi_phy_sels, base + 0xbb80); + clks[IMX8MQ_CLK_DSI_DBI] = imx_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00); + clks[IMX8MQ_CLK_DSI_ESC] = imx_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80); + clks[IMX8MQ_CLK_DSI_AHB] = imx_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200); + clks[IMX8MQ_CLK_CSI1_CORE] = imx_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00); + clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80); + clks[IMX8MQ_CLK_CSI1_ESC] = imx_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00); + clks[IMX8MQ_CLK_CSI2_CORE] = imx_clk_composite("csi2_core", imx8mq_csi2_core_sels, base + 0xbe80); + clks[IMX8MQ_CLK_CSI2_PHY_REF] = imx_clk_composite("csi2_phy_ref", imx8mq_csi2_phy_sels, base + 0xbf00); + clks[IMX8MQ_CLK_CSI2_ESC] = imx_clk_composite("csi2_esc", imx8mq_csi2_esc_sels, base + 0xbf80); + clks[IMX8MQ_CLK_PCIE2_CTRL] = imx_clk_composite("pcie2_ctrl", imx8mq_pcie2_ctrl_sels, base + 0xc000); + clks[IMX8MQ_CLK_PCIE2_PHY] = imx_clk_composite("pcie2_phy", imx8mq_pcie2_phy_sels, base + 0xc080); + clks[IMX8MQ_CLK_PCIE2_AUX] = imx_clk_composite("pcie2_aux", imx8mq_pcie2_aux_sels, base + 0xc100); + clks[IMX8MQ_CLK_ECSPI3] = imx_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180); + + /*FIXME, the doc is not ready now */ + clks[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); + clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); + clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); + clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); + clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0); + clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); + clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); + clks[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); + clks[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); + clks[IMX8MQ_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); + clks[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); + clks[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0); + clks[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_gate4("pcie2_root_clk", "pcie2_ctrl", base + 0x4640, 0); + clks[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); + clks[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); + clks[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); + clks[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); + clks[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); + clks[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); + clks[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); + clks[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_gate2_shared2("sai1_root_clk", "sai1", base + 0x4330, 0, &share_count_sai1); + clks[IMX8MQ_CLK_SAI1_IPG] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_audio_root", base + 0x4330, 0, &share_count_sai1); + clks[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); + clks[IMX8MQ_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root", base + 0x4340, 0, &share_count_sai2); + clks[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); + clks[IMX8MQ_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root", base + 0x4350, 0, &share_count_sai3); + clks[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_gate2_shared2("sai4_root_clk", "sai4", base + 0x4360, 0, &share_count_sai4); + clks[IMX8MQ_CLK_SAI4_IPG] = imx_clk_gate2_shared2("sai4_ipg_clk", "ipg_audio_root", base + 0x4360, 0, &share_count_sai4); + clks[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); + clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); + clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); + clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); + clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); + clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); + clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); + clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); + clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); + clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0); + clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0); + clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0); + clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); + clks[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); + clks[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); + clks[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); + clks[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); + clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0); + clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss); + clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL); + clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); + clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0); + clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0); + clks[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); + clks[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); + + clks[IMX8MQ_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc_25m", 1, 8); + clks[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); + + for (i = 0; i < IMX8MQ_CLK_END; i++) + if (IS_ERR(clks[i])) + pr_err("i.MX8mq clk %u register failed with %ld\n", + i, PTR_ERR(clks[i])); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + clk_set_parent(clks[IMX8MQ_CLK_AHB], clks[IMX8MQ_SYS1_PLL_133M]); + clk_set_parent(clks[IMX8MQ_CLK_NAND_USDHC_BUS], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_AUDIO_AHB], clks[IMX8MQ_SYS2_PLL_500M]); + + /* config video_pll1 clock */ + clk_set_parent(clks[IMX8MQ_VIDEO_PLL1_REF_SEL], clks[IMX8MQ_CLK_27M]); + clk_set_rate(clks[IMX8MQ_VIDEO_PLL1], 593999999); + + /* increase NOC clock to achieve best DDR access performance */ + clk_set_rate(clks[IMX8MQ_CLK_NOC], clk_get_rate(clks[IMX8MQ_SYS1_PLL_800M])); + + /* set pcie root's parent clk source */ + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); + clk_set_parent(clks[IMX8MQ_CLK_PCIE1_PHY], clks[IMX8MQ_SYS2_PLL_100M]); + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_CTRL], clks[IMX8MQ_SYS2_PLL_250M]); + clk_set_parent(clks[IMX8MQ_CLK_PCIE2_PHY], clks[IMX8MQ_SYS2_PLL_100M]); + + clk_set_parent(clks[IMX8MQ_CLK_CSI1_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI1_ESC], clks[IMX8MQ_SYS1_PLL_800M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_CORE], clks[IMX8MQ_SYS1_PLL_266M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_PHY_REF], clks[IMX8MQ_SYS2_PLL_1000M]); + clk_set_parent(clks[IMX8MQ_CLK_CSI2_ESC], clks[IMX8MQ_SYS1_PLL_800M]); +} + +CLK_OF_DECLARE(imx8mq, "fsl,imx8mq-ccm", imx8mq_clocks_init); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 74d8d46..c389f1c 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -128,6 +128,15 @@ static inline struct clk *imx_clk_divider2(const char *name, const char *parent, reg, shift, width, 0, &imx_ccm_lock); } +static inline struct clk *imx_clk_divider2_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, u8 width, + unsigned long flags) +{ + return clk_register_divider(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -195,6 +204,15 @@ static inline struct clk *imx_clk_gate3(const char *name, const char *parent, reg, shift, 0, &imx_ccm_lock); } +static inline struct clk *imx_clk_gate3_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned long flags) +{ + return clk_register_gate(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_gate4(const char *name, const char *parent, void __iomem *reg, u8 shift) { @@ -203,6 +221,15 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent, reg, shift, 0x3, 0, &imx_ccm_lock, NULL); } +static inline struct clk *imx_clk_gate4_flags(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned long flags) +{ + return clk_register_gate2(NULL, name, parent, + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, 0x3, 0, &imx_ccm_lock, NULL); +} + static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, int num_parents) { @@ -228,6 +255,15 @@ static inline struct clk *imx_clk_mux_flags(const char *name, &imx_ccm_lock); } +static inline struct clk *imx_clk_mux2_flags(const char *name, + void __iomem *reg, u8 shift, u8 width, const char **parents, + int num_parents, unsigned long flags) +{ + return clk_register_mux(NULL, name, parents, num_parents, + flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, + reg, shift, width, 0, &imx_ccm_lock); +} + struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step);