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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id f10sm34347813pfd.28.2019.12.02.06.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:45:49 -0800 (PST) From: Jun Nie To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, p.zabel@pengutronix.de, opensource@jilayne.com, swinslow@gmail.com, jun.nie@linaro.org, allison@lohutok.net, yuehaibing@huawei.com, tglx@linutronix.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, xuejiancheng@hisilicon.com Subject: [PATCH 1/3] dt-bindings: clock: Update Hisilicon reset doc Date: Mon, 2 Dec 2019 22:45:22 +0800 Message-Id: <20191202144524.5391-2-jun.nie@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202144524.5391-1-jun.nie@linaro.org> References: <20191202144524.5391-1-jun.nie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_064550_617842_D4CFE7FE X-CRM114-Status: GOOD ( 14.88 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:444 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Document the update of Hisilicon reset operation extension. Signed-off-by: Jun Nie --- .../devicetree/bindings/clock/hisi-crg.txt | 12 ++++---- include/dt-bindings/reset/hisilicon-resets.h | 28 +++++++++++++++++++ 2 files changed, 35 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/reset/hisilicon-resets.h diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt index cc60b3d423f3..fd8b0a964806 100644 --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt @@ -26,19 +26,21 @@ to specify the clock which they consume. All these identifier could be found in . -- #reset-cells: should be 2. +- #reset-cells: should be 3. A reset signal can be controlled by writing a bit register in the CRG module. -The reset specifier consists of two cells. The first cell represents the +The reset specifier consists of three cells. The first cell represents the register offset relative to the base address. The second cell represents the -bit index in the register. +bit index in the register. The third represent the flags to operation type. + +All reset flags could be found in Example: CRG nodes CRG: clock-reset-controller@12010000 { compatible = "hisilicon,hi3519-crg"; reg = <0x12010000 0x10000>; #clock-cells = <1>; - #reset-cells = <2>; + #reset-cells = <3>; }; Example: consumer nodes @@ -46,5 +48,5 @@ i2c0: i2c@12110000 { compatible = "hisilicon,hi3519-i2c"; reg = <0x12110000 0x1000>; clocks = <&CRG HI3519_I2C0_RST>; - resets = <&CRG 0xe4 0>; + resets = <&CRG 0xe4 0 (HISI_ASSERT_SET | HISI_DEASSERT_CLEAR)>; }; diff --git a/include/dt-bindings/reset/hisilicon-resets.h b/include/dt-bindings/reset/hisilicon-resets.h new file mode 100644 index 000000000000..983e42a0c318 --- /dev/null +++ b/include/dt-bindings/reset/hisilicon-resets.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Hisilicon Reset definitions + * + * Copyright (c) 2019 HiSilicon Technologies Co., Ltd. + */ + +#ifndef __DT_BINDINGS_RESET_HISILICON_H__ +#define __DT_BINDINGS_RESET_HISILICON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define HISI_ASSERT_NONE (1 << 0) +#define HISI_DEASSERT_NONE (1 << 1) + +/* When set this function is activated by polling/setting/clearing this bit */ +#define HISI_ASSERT_SET (1 << 2) +#define HISI_DEASSERT_SET (1 << 3) +#define HISI_ASSERT_CLEAR (0 << 4) +#define HISI_DEASSERT_CLEAR (0 << 5) +#define HISI_ASSERT_POLL (0 << 6) +#define HISI_DEASSERT_POLL (0 << 7) + +#define HISI_RESET_DEFAULT (HISI_ASSERT_SET | HISI_DEASSERT_CLEAR) + +#endif From patchwork Mon Dec 2 14:45:23 2019 Content-Type: text/plain; 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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id f10sm34347813pfd.28.2019.12.02.06.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:45:56 -0800 (PST) From: Jun Nie To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, p.zabel@pengutronix.de, opensource@jilayne.com, swinslow@gmail.com, jun.nie@linaro.org, allison@lohutok.net, yuehaibing@huawei.com, tglx@linutronix.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, xuejiancheng@hisilicon.com Subject: [PATCH 2/3] reset: hisilicon: Extend reset operation type Date: Mon, 2 Dec 2019 22:45:23 +0800 Message-Id: <20191202144524.5391-3-jun.nie@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202144524.5391-1-jun.nie@linaro.org> References: <20191202144524.5391-1-jun.nie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_064558_533399_51F74798 X-CRM114-Status: GOOD ( 14.65 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:442 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Extend reset operations to support combination of three type flags: ASSERT/DEASSERT SET/CLEAR POLL. Signed-off-by: Jun Nie --- drivers/clk/hisilicon/reset.c | 58 ++++++++++++++++++++++++++++++++--- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c index 93cee17db8b1..de7d186b0894 100644 --- a/drivers/clk/hisilicon/reset.c +++ b/drivers/clk/hisilicon/reset.c @@ -2,20 +2,25 @@ /* * Hisilicon Reset Controller Driver * - * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd. + * Copyright (c) 2015-2019 HiSilicon Technologies Co., Ltd. */ #include +#include #include #include #include #include #include + +#include #include "reset.h" #define HISI_RESET_BIT_MASK 0x1f #define HISI_RESET_OFFSET_SHIFT 8 #define HISI_RESET_OFFSET_MASK 0xffff00 +#define HISI_RESET_FLAG_SHIFT 24 +#define HISI_RESET_FLAG_MASK 0xff000000 struct hisi_reset_controller { spinlock_t lock; @@ -30,14 +35,17 @@ struct hisi_reset_controller { static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev, const struct of_phandle_args *reset_spec) { + unsigned long flags; u32 offset; u8 bit; + flags = (reset_spec->args[2] << HISI_RESET_FLAG_SHIFT) + & HISI_RESET_FLAG_MASK; offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT) & HISI_RESET_OFFSET_MASK; bit = reset_spec->args[1] & HISI_RESET_BIT_MASK; - return (offset | bit); + return (flags | offset | bit); } static int hisi_reset_assert(struct reset_controller_dev *rcdev, @@ -48,13 +56,33 @@ static int hisi_reset_assert(struct reset_controller_dev *rcdev, u32 offset, reg; u8 bit; + flags = (id & HISI_RESET_FLAG_MASK) >> HISI_RESET_FLAG_SHIFT; + if (flags & HISI_ASSERT_NONE) + return -ENOTSUPP; /* assert not supported for this reset */ + offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT; bit = id & HISI_RESET_BIT_MASK; + pr_devel("%s %s to %s 0x%x:bit[%d]\n", __func__, + flags & HISI_ASSERT_POLL ? "poll" : "", + flags & HISI_ASSERT_SET ? "set":"clear", offset, bit); + + if (flags & HISI_ASSERT_POLL) { + if (flags & HISI_ASSERT_SET) + return readl_poll_timeout(rstc->membase + offset, + reg, reg & BIT(bit), 0, 5000); + else + return readl_poll_timeout(rstc->membase + offset, + reg, !(reg & BIT(bit)), + 0, 5000); + } + spin_lock_irqsave(&rstc->lock, flags); reg = readl(rstc->membase + offset); - writel(reg | BIT(bit), rstc->membase + offset); + /* Default is setting to assert for no flag case. */ + reg = (flags & HISI_ASSERT_CLEAR) ? reg & ~BIT(bit) : reg | BIT(bit); + writel(reg, rstc->membase + offset); spin_unlock_irqrestore(&rstc->lock, flags); @@ -69,13 +97,33 @@ static int hisi_reset_deassert(struct reset_controller_dev *rcdev, u32 offset, reg; u8 bit; + flags = (id & HISI_RESET_FLAG_MASK) >> HISI_RESET_FLAG_SHIFT; + if (flags & HISI_DEASSERT_NONE) + return -ENOTSUPP; /* deassert not supported for this reset */ + offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT; bit = id & HISI_RESET_BIT_MASK; + pr_devel("%s %s to %s 0x%x:bit[%d]\n", __func__, + flags & HISI_DEASSERT_POLL ? "poll" : "", + flags & HISI_DEASSERT_SET ? "clear":"set", offset, bit); + + if (flags & HISI_DEASSERT_POLL) { + if (flags & HISI_DEASSERT_SET) + return readl_poll_timeout(rstc->membase + offset, + reg, reg & BIT(bit), 0, 5000); + else + return readl_poll_timeout(rstc->membase + offset, + reg, !(reg & BIT(bit)), + 0, 5000); + } + spin_lock_irqsave(&rstc->lock, flags); reg = readl(rstc->membase + offset); - writel(reg & ~BIT(bit), rstc->membase + offset); + /* Default is clearing to deasseart for no flag case. */ + reg = (flags & HISI_DEASSERT_SET) ? reg | BIT(bit) : reg & ~BIT(bit); + writel(reg, rstc->membase + offset); spin_unlock_irqrestore(&rstc->lock, flags); @@ -103,7 +151,7 @@ struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev) rstc->rcdev.owner = THIS_MODULE; rstc->rcdev.ops = &hisi_reset_ops; rstc->rcdev.of_node = pdev->dev.of_node; - rstc->rcdev.of_reset_n_cells = 2; + rstc->rcdev.of_reset_n_cells = 3; rstc->rcdev.of_xlate = hisi_reset_of_xlate; reset_controller_register(&rstc->rcdev); From patchwork Mon Dec 2 14:45:24 2019 Content-Type: text/plain; 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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id f10sm34347813pfd.28.2019.12.02.06.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:46:02 -0800 (PST) From: Jun Nie To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, p.zabel@pengutronix.de, opensource@jilayne.com, swinslow@gmail.com, jun.nie@linaro.org, allison@lohutok.net, yuehaibing@huawei.com, tglx@linutronix.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, xuejiancheng@hisilicon.com Subject: [PATCH 3/3] ARM: dts: Update reset for hi3519 and hi3798cv200 Date: Mon, 2 Dec 2019 22:45:24 +0800 Message-Id: <20191202144524.5391-4-jun.nie@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202144524.5391-1-jun.nie@linaro.org> References: <20191202144524.5391-1-jun.nie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191202_064604_664770_80F31C9B X-CRM114-Status: GOOD ( 11.77 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Update reset for hi3519 and hi3798cv200 as driver is extended to support configurable reset operation type. Signed-off-by: Jun Nie --- arch/arm/boot/dts/hi3519.dtsi | 2 +- .../arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 47 +++++++++++-------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi index 410409a0ed66..2335c8443d2d 100644 --- a/arch/arm/boot/dts/hi3519.dtsi +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -37,7 +37,7 @@ crg: clock-reset-controller@12010000 { compatible = "hisilicon,hi3519-crg"; #clock-cells = <1>; - #reset-cells = <2>; + #reset-cells = <3>; reg = <0x12010000 0x10000>; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 13821a0ff524..0a30aaae6bf2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -9,8 +9,10 @@ #include #include #include +#include #include + / { compatible = "hisilicon,hi3798cv200"; interrupt-parent = <&gic>; @@ -86,7 +88,7 @@ compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; reg = <0x8a22000 0x1000>; #clock-cells = <1>; - #reset-cells = <2>; + #reset-cells = <3>; gmacphyrst: reset-controller { compatible = "ti,syscon-reset"; @@ -103,7 +105,7 @@ compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; reg = <0x8000000 0x1000>; #clock-cells = <1>; - #reset-cells = <2>; + #reset-cells = <3>; }; perictrl: peripheral-controller@8a20000 { @@ -118,20 +120,22 @@ compatible = "hisilicon,hi3798cv200-usb2-phy"; reg = <0x120 0x4>; clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; - resets = <&crg 0xbc 4>; + resets = <&crg 0xbc 4 HISI_RESET_DEFAULT>; #address-cells = <1>; #size-cells = <0>; usb2_phy1_port0: phy@0 { reg = <0>; #phy-cells = <0>; - resets = <&crg 0xbc 8>; + resets = <&crg 0xbc 8 + HISI_RESET_DEFAULT>; }; usb2_phy1_port1: phy@1 { reg = <1>; #phy-cells = <0>; - resets = <&crg 0xbc 9>; + resets = <&crg 0xbc 9 + HISI_RESET_DEFAULT>; }; }; @@ -139,14 +143,15 @@ compatible = "hisilicon,hi3798cv200-usb2-phy"; reg = <0x124 0x4>; clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; - resets = <&crg 0xbc 6>; + resets = <&crg 0xbc 6 HISI_RESET_DEFAULT>; #address-cells = <1>; #size-cells = <0>; usb2_phy2_port0: phy@0 { reg = <0>; #phy-cells = <0>; - resets = <&crg 0xbc 10>; + resets = <&crg 0xbc 10 + HISI_RESET_DEFAULT>; }; }; @@ -155,7 +160,7 @@ reg = <0x850 0x8>; #phy-cells = <1>; clocks = <&crg HISTB_COMBPHY0_CLK>; - resets = <&crg 0x188 4>; + resets = <&crg 0x188 4 HISI_RESET_DEFAULT>; assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; assigned-clock-rates = <100000000>; hisilicon,fixed-mode = ; @@ -166,7 +171,7 @@ reg = <0x858 0x8>; #phy-cells = <1>; clocks = <&crg HISTB_COMBPHY1_CLK>; - resets = <&crg 0x188 12>; + resets = <&crg 0x188 12 HISI_RESET_DEFAULT>; assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; assigned-clock-rates = <100000000>; hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; @@ -306,7 +311,7 @@ clocks = <&crg HISTB_SDIO0_CIU_CLK>, <&crg HISTB_SDIO0_BIU_CLK>; clock-names = "ciu", "biu"; - resets = <&crg 0x9c 4>; + resets = <&crg 0x9c 4 HISI_RESET_DEFAULT>; reset-names = "reset"; status = "disabled"; }; @@ -320,7 +325,7 @@ <&crg HISTB_MMC_SAMPLE_CLK>, <&crg HISTB_MMC_DRV_CLK>; clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - resets = <&crg 0xa0 4>; + resets = <&crg 0xa0 4 HISI_RESET_DEFAULT>; reset-names = "reset"; status = "disabled"; }; @@ -525,8 +530,8 @@ clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>; clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 8>, - <&crg 0xcc 10>, + resets = <&crg 0xcc 8 HISI_RESET_DEFAULT>, + <&crg 0xcc 10 HISI_RESET_DEFAULT>, <&gmacphyrst 0>; reset-names = "mac_core", "mac_ifc", "phy"; status = "disabled"; @@ -540,8 +545,8 @@ clocks = <&crg HISTB_ETH1_MAC_CLK>, <&crg HISTB_ETH1_MACIF_CLK>; clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 9>, - <&crg 0xcc 11>, + resets = <&crg 0xcc 9 HISI_RESET_DEFAULT>, + <&crg 0xcc 11 HISI_RESET_DEFAULT>, <&gmacphyrst 1>; reset-names = "mac_core", "mac_ifc", "phy"; status = "disabled"; @@ -578,7 +583,9 @@ <&crg HISTB_PCIE_SYS_CLK>, <&crg HISTB_PCIE_BUS_CLK>; clock-names = "aux", "pipe", "sys", "bus"; - resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; + resets = <&crg 0x18c 6 HISI_RESET_DEFAULT>, + <&crg 0x18c 5 HISI_RESET_DEFAULT>, + <&crg 0x18c 4 HISI_RESET_DEFAULT>; reset-names = "soft", "sys", "bus"; phys = <&combphy1 PHY_TYPE_PCIE>; phy-names = "phy"; @@ -593,7 +600,7 @@ <&crg HISTB_USB2_12M_CLK>, <&crg HISTB_USB2_48M_CLK>; clock-names = "bus", "clk12", "clk48"; - resets = <&crg 0xb8 12>; + resets = <&crg 0xb8 12 HISI_RESET_DEFAULT>; reset-names = "bus"; phys = <&usb2_phy1_port0>; phy-names = "usb"; @@ -608,9 +615,9 @@ <&crg HISTB_USB2_PHY_CLK>, <&crg HISTB_USB2_UTMI_CLK>; clock-names = "bus", "phy", "utmi"; - resets = <&crg 0xb8 12>, - <&crg 0xb8 16>, - <&crg 0xb8 13>; + resets = <&crg 0xb8 12 HISI_RESET_DEFAULT>, + <&crg 0xb8 16 HISI_RESET_DEFAULT>, + <&crg 0xb8 13 HISI_RESET_DEFAULT>; reset-names = "bus", "phy", "utmi"; phys = <&usb2_phy1_port0>; phy-names = "usb";