From patchwork Mon Dec 2 20:31:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11269901 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E1BF112B for ; Mon, 2 Dec 2019 20:31:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4CB2020848 for ; Mon, 2 Dec 2019 20:31:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ibwwyX4C" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727420AbfLBUbn (ORCPT ); Mon, 2 Dec 2019 15:31:43 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:56508 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727417AbfLBUbn (ORCPT ); Mon, 2 Dec 2019 15:31:43 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB2KVU2q064017; Mon, 2 Dec 2019 14:31:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575318690; bh=WJ7/iDoH+LgZm+FTh1H3GU4VY8iNBVP3eVx3nZf37Js=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ibwwyX4C1bE891UNaonAVXRMx4ZwTY4Gfe3ExB59ZVRB+mLyo1AiwGq6KFphTiRhN /3OjZmoSlmWh35JsB26bZKAmsWRt8+I2j25SZdzbPV3bGOMeTTpazJGhcIydY9WL42 45wOkoCc7Sg+If53ly5IkB5/r9mqlBKq7RX7ypKo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB2KVU89001490 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Dec 2019 14:31:30 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 2 Dec 2019 14:31:30 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 2 Dec 2019 14:31:30 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB2KVOPm106889; Mon, 2 Dec 2019 14:31:27 -0600 From: Peter Ujfalusi To: CC: , , , , , , , Subject: [PATCH 1/3] dmaengine: ti: k3-udma: Correct completed descriptor's residue value Date: Mon, 2 Dec 2019 22:31:26 +0200 Message-ID: <20191202203128.14348-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191202203128.14348-1-peter.ujfalusi@ti.com> References: <0191128105945.13071-1-peter.ujfalusi@ti.com> <20191202203128.14348-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The residue should show the number of _not_ completed bytes, so it has to be 0 when the full transfer is completed. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index c1450b0a8224..1b929f7a84d4 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2784,13 +2784,14 @@ static void udma_desc_pre_callback(struct virt_dma_chan *vc, if (cppi5_desc_get_type(desc_vaddr) == CPPI5_INFO0_DESC_TYPE_VAL_HOST) { - result->residue = cppi5_hdesc_get_pktlen(desc_vaddr); - if (result->residue == d->residue) - result->result = DMA_TRANS_NOERROR; - else + result->residue = d->residue - + cppi5_hdesc_get_pktlen(desc_vaddr); + if (result->residue) result->result = DMA_TRANS_ABORTED; + else + result->result = DMA_TRANS_NOERROR; } else { - result->residue = d->residue; + result->residue = 0; result->result = DMA_TRANS_NOERROR; } } From patchwork Mon Dec 2 20:31:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11269907 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0DEF7930 for ; Mon, 2 Dec 2019 20:31:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DED4224651 for ; Mon, 2 Dec 2019 20:31:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MOrDhfh9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727545AbfLBUbu (ORCPT ); Mon, 2 Dec 2019 15:31:50 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:48646 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727522AbfLBUbs (ORCPT ); Mon, 2 Dec 2019 15:31:48 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB2KVY1S116144; Mon, 2 Dec 2019 14:31:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575318694; bh=I4zArTwz2+uyo5cLd8GOGGyuu7Ob1n/MUYmaFykEDf0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MOrDhfh9Qab1FfK0q8D3QSJmCj8WSAEX4pWScE4+rTh0ADTkMuBdWERv1hbkfI2NN LVuwk5sQyE3eO3ffhdzP95BisKvguwfMq3lvOmrEtM/qFPFdCe14294GQwgU4oIglk 0GZArIFKa0b56G2vwJVniDgOk7zOjGxqu8jazy5U= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB2KVYZZ116964 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Dec 2019 14:31:34 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 2 Dec 2019 14:31:33 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 2 Dec 2019 14:31:32 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB2KVOPn106889; Mon, 2 Dec 2019 14:31:30 -0600 From: Peter Ujfalusi To: CC: , , , , , , , Subject: [PATCH 2/3] dmaengine: ti: k3-udma: Workaround for stale transfers Date: Mon, 2 Dec 2019 22:31:27 +0200 Message-ID: <20191202203128.14348-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191202203128.14348-1-peter.ujfalusi@ti.com> References: <0191128105945.13071-1-peter.ujfalusi@ti.com> <20191202203128.14348-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org If the client does issue_pending between terminte_all+synchronize and free_chan_resources, we need to make sure that it has been handled and cleared up. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 1b929f7a84d4..3aede5db9604 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2842,6 +2842,10 @@ static void udma_free_chan_resources(struct dma_chan *chan) struct udma_dev *ud = to_udma_dev(chan->device); udma_terminate_all(chan); + if (uc->terminated_desc) { + udma_reset_chan(uc, false); + udma_reset_rings(uc); + } if (uc->irq_num_ring > 0) { free_irq(uc->irq_num_ring, uc); From patchwork Mon Dec 2 20:31:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11269909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5E22112B for ; Mon, 2 Dec 2019 20:31:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B99C320848 for ; Mon, 2 Dec 2019 20:31:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mFUq2q2P" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727554AbfLBUbq (ORCPT ); Mon, 2 Dec 2019 15:31:46 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:40430 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727522AbfLBUbq (ORCPT ); Mon, 2 Dec 2019 15:31:46 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xB2KVa8I017066; Mon, 2 Dec 2019 14:31:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1575318696; bh=NofGx1mubkA1EF/TY40DJFtjPM3r2emRLLltVThbzP8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mFUq2q2P8wJLFE2MQBK5ogk/TlxF0z+0paKs0DaMBRaVo80E4zrbybKpgt9xkdn0R GUXzmnKPT/j2voBnFCODZtQ3Mmgk3IMX27vPLLunqEpmmFQRei4bMqQ4EkdJISVUN2 kAJkhbwPjp0tmmzqRNQ/nlKJHlhrQKmtVlZohYr0= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xB2KVaV3116999 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Dec 2019 14:31:36 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 2 Dec 2019 14:31:35 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 2 Dec 2019 14:31:35 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xB2KVOPo106889; Mon, 2 Dec 2019 14:31:33 -0600 From: Peter Ujfalusi To: CC: , , , , , , , Subject: [PATCH 3/3] dmaengine: ti: k3-udma: Fix early TX completion against PDMAs Date: Mon, 2 Dec 2019 22:31:28 +0200 Message-ID: <20191202203128.14348-4-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191202203128.14348-1-peter.ujfalusi@ti.com> References: <0191128105945.13071-1-peter.ujfalusi@ti.com> <20191202203128.14348-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org If the peripheral is disabled (or it is not able to send out data) the UDMAP will complete a 'short' transfer. In other words: if the amount of data can fit into PSI-L and PDMA (and peripheral FIFO) then UDMAP will send out the data and return as the transfer is completed, however the peripheral did not actually received all the data. It was wrong to issue a normal teardown on the channel for several reasons: UDMAP is not processing any packet so it will just return the TDCM and if the peripheral is not consuming data from PDMA then we will have constant flood of TDCMs (interrupts). After the teardown the channel will be in reset state and we would need to reset the rings as well, but it can not be done in interrupt context. If the peripheral is just slow to consume data or even there is a delay between starting the DMA then we will have again issues detecting the state. We could set force teardown, but that will make PDMA to discard the data which is not correct in case of slow or delayed transfer start on the peripheral. The only solution is to use a work and check the progress in there after the descriptor is returned and the UDMA and PDMA counters are not showing the same number of bytes processed. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma.c | 74 ++++++++++++++++++++++++++++++---------- 1 file changed, 56 insertions(+), 18 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 3aede5db9604..39ca371a67dd 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -165,10 +165,15 @@ struct udma_desc { enum udma_chan_state { UDMA_CHAN_IS_IDLE = 0, /* not active, no teardown is in progress */ UDMA_CHAN_IS_ACTIVE, /* Normal operation */ - UDMA_CHAN_IS_ACTIVE_FLUSH, /* Flushing for delayed tx */ UDMA_CHAN_IS_TERMINATING, /* channel is being terminated */ }; +struct udma_tx_drain { + struct delayed_work work; + unsigned long jiffie; + u32 residue; +}; + struct udma_chan { struct virt_dma_chan vc; struct dma_slave_config cfg; @@ -193,6 +198,8 @@ struct udma_chan { enum udma_chan_state state; struct completion teardown_completed; + struct udma_tx_drain tx_drain; + u32 bcnt; /* number of bytes completed since the start of the channel */ u32 in_ring_cnt; /* number of descriptors in flight */ @@ -928,22 +935,51 @@ static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d) peer_bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG); bcnt = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG); - if (peer_bcnt < bcnt) + if (peer_bcnt < bcnt) { + uc->tx_drain.residue = bcnt - peer_bcnt; + uc->tx_drain.jiffie = jiffies; return false; + } return true; } -static void udma_flush_tx(struct udma_chan *uc) +static void udma_check_tx_completion(struct work_struct *work) { - if (uc->dir != DMA_MEM_TO_DEV) - return; + struct udma_chan *uc = container_of(work, typeof(*uc), + tx_drain.work.work); + bool desc_done = true; + u32 residue_diff; + unsigned long jiffie_diff, delay; + + if (uc->desc) { + residue_diff = uc->tx_drain.residue; + jiffie_diff = uc->tx_drain.jiffie; + desc_done = udma_is_desc_really_done(uc, uc->desc); + } + + if (!desc_done) { + jiffie_diff = uc->tx_drain.jiffie - jiffie_diff; + residue_diff -= uc->tx_drain.residue; + if (residue_diff) { + /* Try to guess when we should check next time */ + residue_diff /= jiffie_diff; + delay = uc->tx_drain.residue / residue_diff / 3; + if (jiffies_to_msecs(delay) < 5) + delay = 0; + } else { + /* No progress, check again in 1 second */ + delay = HZ; + } - uc->state = UDMA_CHAN_IS_ACTIVE_FLUSH; + schedule_delayed_work(&uc->tx_drain.work, delay); + } else if (uc->desc) { + struct udma_desc *d = uc->desc; - udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, - UDMA_CHAN_RT_CTL_EN | - UDMA_CHAN_RT_CTL_TDOWN); + uc->bcnt += d->residue; + udma_start(uc); + vchan_cookie_complete(&d->vd); + } } static irqreturn_t udma_ring_irq_handler(int irq, void *data) @@ -973,11 +1009,7 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data) if (!uc->desc) udma_start(uc); - if (uc->state != UDMA_CHAN_IS_ACTIVE_FLUSH) - goto out; - else if (uc->desc) - paddr = udma_curr_cppi5_desc_paddr(uc->desc, - uc->desc->desc_idx); + goto out; } d = udma_udma_desc_from_paddr(uc, paddr); @@ -997,7 +1029,7 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data) vchan_cyclic_callback(&d->vd); } } else { - bool desc_done = true; + bool desc_done = false; if (d == uc->desc) { desc_done = udma_is_desc_really_done(uc, d); @@ -1006,10 +1038,9 @@ static irqreturn_t udma_ring_irq_handler(int irq, void *data) uc->bcnt += d->residue; udma_start(uc); } else { - udma_flush_tx(uc); + schedule_delayed_work(&uc->tx_drain.work, + 0); } - } else if (d == uc->terminated_desc) { - uc->terminated_desc = NULL; } if (desc_done) @@ -1818,6 +1849,8 @@ static int udma_alloc_chan_resources(struct dma_chan *chan) udma_reset_rings(uc); + INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, + udma_check_tx_completion); return 0; err_irq_free: @@ -2727,6 +2760,7 @@ static int udma_terminate_all(struct dma_chan *chan) uc->terminated_desc = uc->desc; uc->desc = NULL; uc->terminated_desc->terminated = true; + cancel_delayed_work(&uc->tx_drain.work); } uc->paused = false; @@ -2760,6 +2794,7 @@ static void udma_synchronize(struct dma_chan *chan) if (udma_is_chan_running(uc)) dev_warn(uc->ud->dev, "chan%d refused to stop!\n", uc->id); + cancel_delayed_work_sync(&uc->tx_drain.work); udma_reset_rings(uc); } @@ -2847,6 +2882,9 @@ static void udma_free_chan_resources(struct dma_chan *chan) udma_reset_rings(uc); } + cancel_delayed_work_sync(&uc->tx_drain.work); + destroy_delayed_work_on_stack(&uc->tx_drain.work); + if (uc->irq_num_ring > 0) { free_irq(uc->irq_num_ring, uc);