From patchwork Tue Dec 3 04:57:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 11270437 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 927F41805 for ; Tue, 3 Dec 2019 04:57:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6832E2084B for ; Tue, 3 Dec 2019 04:57:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="IgneEgiu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727084AbfLCE5j (ORCPT ); Mon, 2 Dec 2019 23:57:39 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:53399 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727079AbfLCE5h (ORCPT ); Mon, 2 Dec 2019 23:57:37 -0500 Received: by mail-wm1-f66.google.com with SMTP id u18so1562888wmc.3 for ; Mon, 02 Dec 2019 20:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DNbjBu2ZoQvj/Rdtwyfg9/ny54LKUFtnkpIxH0rGJgw=; b=IgneEgiudM4dhaaT84m2HLx76XXFsgx7G+w69ktuYbVN+4NPtabS6SzrKMZeVV/o+0 IJ1aQAetS7xf6kvwH2UJizjzP3es1gKKH6RB+glnvQAT2HHMa53vqr8OgzDBUfej0Z9i 2Fypg52a+TW8NLIts/3Eii9AR91WnOK2oxu7s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DNbjBu2ZoQvj/Rdtwyfg9/ny54LKUFtnkpIxH0rGJgw=; b=uar3PdwmpJZ9ZslrzmXhOUOe6CUTb1UijD1Q/3qCfI/0L0Zd9HrrKJerz7ag5XonW2 rGrV4qad6aj8io8o0hG5fLbsQ3PoxQkRTDk/QIqgEqDOD+BkMpRuOpKygbqzBo6uHUj8 A3tr0nYIRVbbH87d+QJj5S4EcHDt4kqd6VoScYqeKsjAhd8EiZpg5tu4vNcH2jUG2LfV y9WuxyZWzKrLujURh7wJBksnn8WJp+6mMegbvpZ6dY71gCHNttsgVg9syRXajZTnXTey SxIjB1x+ZLNcovQ79JXmGc3PjFduCSEKpf0BxTSrf98aSMgyEP0/Clfv59lYmNOefaTG +16g== X-Gm-Message-State: APjAAAU0X+Xz8kJwSXA3njrJ+4bxpXMLuypofqEXcx77B1gyhThxoR87 vqQySgBLlqqEl7K1GHXmPukkug== X-Google-Smtp-Source: APXvYqy1L/hk7jc6Vua1eOQ6zF9HW6W5OyAgAMHGiBpjQlMl56SBWkEWvpdI05EBRsPwMIKUCJzloA== X-Received: by 2002:a1c:7c06:: with SMTP id x6mr33613750wmc.34.1575349055230; Mon, 02 Dec 2019 20:57:35 -0800 (PST) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id k4sm1667807wmk.26.2019.12.02.20.57.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Dec 2019 20:57:34 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 1/6] dt-bindings: pci: Update iProc PCI binding for INTx support Date: Tue, 3 Dec 2019 10:27:01 +0530 Message-Id: <1575349026-8743-2-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Update the iProc PCIe binding document for better modeling of the legacy interrupt (INTx) support Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 48 ++++++++++++++++++---- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index df065aa..d3f833a 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -13,9 +13,6 @@ controller, used in Stingray PAXB-based root complex is used for external endpoint devices. PAXC-based root complex is connected to emulated endpoint devices internal to the ASIC - reg: base address and length of the PCIe controller I/O register space -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map, standard PCI properties to define the - mapping of the PCIe interface to interrupt numbers - linux,pci-domain: PCI domain ID. Should be unique for each host controller - bus-range: PCI bus numbers covered - #address-cells: set to <3> @@ -41,6 +38,21 @@ Required: - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal address used by the iProc PCIe core (not the PCIe address) +Legacy interrupt (INTx) support (optional): + +Note INTx is for PAXB only. +- interrupt-map-mask and interrupt-map, standard PCI properties to define +the mapping of the PCIe interface to interrupt numbers + +In addition, a sub-node that describes the legacy interrupt controller built +into the PCIe controller. +This sub-node must have the following properties: + - compatible: must be "brcm,iproc-intc" + - interrupt-controller: claims itself as an interrupt controller for INTx + - #interrupt-cells: set to <1> + - interrupts: interrupt line wired to the generic GIC for INTx support + - interrupt-parent: Phandle to the parent interrupt controller + MSI support (optional): For older platforms without MSI integrated in the GIC, iProc PCIe core provides @@ -77,8 +89,11 @@ Example: reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -98,6 +113,14 @@ Example: msi-parent = <&msi0>; + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + /* iProc event queue based MSI */ msi0: msi@18012000 { compatible = "brcm,iproc-msi"; @@ -115,8 +138,11 @@ Example: reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -130,4 +156,12 @@ Example: phys = <&phy 1 6>; phy-names = "pcie-phy"; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; From patchwork Tue Dec 3 04:57:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 11270445 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D74AE1805 for ; Tue, 3 Dec 2019 04:57:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A9BBC20803 for ; Tue, 3 Dec 2019 04:57:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="NC7qCtI/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727123AbfLCE5n (ORCPT ); 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Mon, 02 Dec 2019 20:57:40 -0800 (PST) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id k4sm1667807wmk.26.2019.12.02.20.57.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Dec 2019 20:57:40 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 2/6] PCI: iproc: Add INTx support with better modeling Date: Tue, 3 Dec 2019 10:27:02 +0530 Message-Id: <1575349026-8743-3-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Add PCIe legacy interrupt INTx support to the iProc PCIe driver by modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC, INTD share the same interrupt line connected to the GIC in the system, while the status of each INTx can be obtained through the INTX CSR register Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- drivers/pci/controller/pcie-iproc.c | 100 +++++++++++++++++++++++++++++++++++- drivers/pci/controller/pcie-iproc.h | 6 +++ 2 files changed, 104 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c index 2d457bf..e90c22e 100644 --- a/drivers/pci/controller/pcie-iproc.c +++ b/drivers/pci/controller/pcie-iproc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -270,6 +271,7 @@ enum iproc_pcie_reg { /* enable INTx */ IPROC_PCIE_INTX_EN, + IPROC_PCIE_INTX_CSR, /* outbound address mapping */ IPROC_PCIE_OARR0, @@ -314,6 +316,7 @@ static const u16 iproc_pcie_reg_paxb_bcma[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_LINK_STATUS] = 0xf0c, }; @@ -325,6 +328,7 @@ static const u16 iproc_pcie_reg_paxb[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -341,6 +345,7 @@ static const u16 iproc_pcie_reg_paxb_v2[] = { [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, [IPROC_PCIE_INTX_EN] = 0x330, + [IPROC_PCIE_INTX_CSR] = 0x334, [IPROC_PCIE_OARR0] = 0xd20, [IPROC_PCIE_OMAP0] = 0xd40, [IPROC_PCIE_OARR1] = 0xd28, @@ -846,9 +851,95 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) return link_is_active ? 0 : -ENODEV; } -static void iproc_pcie_enable(struct iproc_pcie *pcie) +static int iproc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) { + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = iproc_pcie_intx_map, +}; + +static void iproc_pcie_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct iproc_pcie *pcie; + struct device *dev; + unsigned long status; + u32 bit, virq; + + chained_irq_enter(chip, desc); + pcie = irq_desc_get_handler_data(desc); + dev = pcie->dev; + + /* go through INTx A, B, C, D until all interrupts are handled */ + do { + status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR); + for_each_set_bit(bit, &status, PCI_NUM_INTX) { + virq = irq_find_mapping(pcie->irq_domain, bit); + if (virq) + generic_handle_irq(virq); + else + dev_err(dev, "unexpected INTx%u\n", bit); + } + } while ((status & SYS_RC_INTX_MASK) != 0); + + chained_irq_exit(chip, desc); +} + +static int iproc_pcie_intx_enable(struct iproc_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node; + int ret; + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); + /* + * BCMA devices do not map INTx the same way as platform devices. All + * BCMA needs is the above code to enable INTx + */ + + node = of_get_compatible_child(dev->of_node, "brcm,iproc-intc"); + if (node) + pcie->irq = of_irq_get(node, 0); + + if (!node || pcie->irq <= 0) + return 0; + + /* set IRQ handler */ + irq_set_chained_handler_and_data(pcie->irq, iproc_pcie_isr, pcie); + + /* add IRQ domain for INTx */ + pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX, + &intx_domain_ops, pcie); + if (!pcie->irq_domain) { + dev_err(dev, "failed to add INTx IRQ domain\n"); + ret = -ENOMEM; + goto err_rm_handler_data; + } + + return 0; + +err_rm_handler_data: + of_node_put(node); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + + return ret; +} + +static void iproc_pcie_intx_disable(struct iproc_pcie *pcie) +{ + iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, 0x0); + + if (pcie->irq <= 0) + return; + + irq_domain_remove(pcie->irq_domain); + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); } static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie, @@ -1537,7 +1628,11 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) goto err_power_off_phy; } - iproc_pcie_enable(pcie); + ret = iproc_pcie_intx_enable(pcie); + if (ret) { + dev_err(dev, "failed to enable INTx\n"); + goto err_power_off_phy; + } if (IS_ENABLED(CONFIG_PCI_MSI)) if (iproc_pcie_msi_enable(pcie)) @@ -1582,6 +1677,7 @@ int iproc_pcie_remove(struct iproc_pcie *pcie) pci_remove_root_bus(pcie->root_bus); iproc_pcie_msi_disable(pcie); + iproc_pcie_intx_disable(pcie); phy_power_off(pcie->phy); phy_exit(pcie->phy); diff --git a/drivers/pci/controller/pcie-iproc.h b/drivers/pci/controller/pcie-iproc.h index 4f03ea5..103e568 100644 --- a/drivers/pci/controller/pcie-iproc.h +++ b/drivers/pci/controller/pcie-iproc.h @@ -74,6 +74,9 @@ struct iproc_msi; * @ib: inbound mapping related parameters * @ib_map: outbound mapping region related parameters * + * @irq: interrupt line wired to the generic GIC for INTx + * @irq_domain: IRQ domain for INTx + * * @need_msi_steer: indicates additional configuration of the iProc PCIe * controller is required to steer MSI writes to external interrupt controller * @msi: MSI data @@ -102,6 +105,9 @@ struct iproc_pcie { struct iproc_pcie_ib ib; const struct iproc_pcie_ib_map *ib_map; + int irq; + struct irq_domain *irq_domain; + bool need_msi_steer; struct iproc_msi *msi; }; From patchwork Tue Dec 3 04:57:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 11270441 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05DC3159A for ; Tue, 3 Dec 2019 04:57:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D96EC20862 for ; Tue, 3 Dec 2019 04:57:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="DsnYNBcD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727187AbfLCE5r (ORCPT ); Mon, 2 Dec 2019 23:57:47 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:36777 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727177AbfLCE5r (ORCPT ); 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Mon, 02 Dec 2019 20:57:46 -0800 (PST) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id k4sm1667807wmk.26.2019.12.02.20.57.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Dec 2019 20:57:45 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 3/6] arm: dts: Change PCIe INTx mapping for Cygnus Date: Tue, 3 Dec 2019 10:27:03 +0530 Message-Id: <1575349026-8743-4-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-cygnus.dtsi | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 2dac3ef..ca23e82 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -264,8 +264,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -292,6 +295,14 @@ , ; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -299,8 +310,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -327,6 +341,14 @@ , ; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; dma0: dma@18018000 { From patchwork Tue Dec 3 04:57:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 11270443 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 522E314B7 for ; Tue, 3 Dec 2019 04:57:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3206F2073C for ; Tue, 3 Dec 2019 04:57:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="AWQOz60q" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727205AbfLCE5x (ORCPT ); Mon, 2 Dec 2019 23:57:53 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:38594 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727200AbfLCE5x (ORCPT ); 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Mon, 02 Dec 2019 20:57:51 -0800 (PST) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id k4sm1667807wmk.26.2019.12.02.20.57.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Dec 2019 20:57:50 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 4/6] arm: dts: Change PCIe INTx mapping for NSP Date: Tue, 3 Dec 2019 10:27:04 +0530 Message-Id: <1575349026-8743-5-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-nsp.dtsi | 45 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index da6d70f..6d73221 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -529,8 +529,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -559,6 +562,14 @@ ; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -566,8 +577,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -596,6 +610,14 @@ ; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie2: pcie@18014000 { @@ -603,8 +625,11 @@ reg = <0x18014000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; linux,pci-domain = <2>; @@ -633,6 +658,14 @@ ; brcm,pcie-msi-inten; }; + + pcie2_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; thermal-zones { From patchwork Tue Dec 3 04:57:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 11270447 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82A43159A for ; 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Mon, 02 Dec 2019 20:57:56 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 5/6] arm: dts: Change PCIe INTx mapping for HR2 Date: Tue, 3 Dec 2019 10:27:05 +0530 Message-Id: <1575349026-8743-6-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm/boot/dts/bcm-hr2.dtsi | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index e4d4973..d840190 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -299,8 +299,11 @@ reg = <0x18012000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -328,6 +331,14 @@ ; brcm,pcie-msi-inten; }; + + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie1: pcie@18013000 { @@ -335,8 +346,11 @@ reg = <0x18013000 0x1000>; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; linux,pci-domain = <1>; @@ -364,5 +378,13 @@ ; brcm,pcie-msi-inten; }; + + pcie1_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; }; From patchwork Tue Dec 3 04:57:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 11270451 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3CDE13B6 for ; Tue, 3 Dec 2019 04:58:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C2D85206E0 for ; Tue, 3 Dec 2019 04:58:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="JyHSTtEq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727184AbfLCE6E (ORCPT ); Mon, 2 Dec 2019 23:58:04 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:47049 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727261AbfLCE6D (ORCPT ); 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Mon, 02 Dec 2019 20:58:02 -0800 (PST) Received: from mannams-OptiPlex-7010.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id k4sm1667807wmk.26.2019.12.02.20.57.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Dec 2019 20:58:01 -0800 (PST) From: Srinath Mannam To: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Ray Jui , Rob Herring , Mark Rutland , Andy Shevchenko , Arnd Bergmann Cc: bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ray Jui , Srinath Mannam Subject: [PATCH v3 6/6] arm64: dts: Change PCIe INTx mapping for NS2 Date: Tue, 3 Dec 2019 10:27:06 +0530 Message-Id: <1575349026-8743-7-git-send-email-srinath.mannam@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> References: <1575349026-8743-1-git-send-email-srinath.mannam@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ray Jui Change the PCIe INTx mapping to model the 4 INTx interrupts in the IRQ domain of the iProc PCIe controller itself Signed-off-by: Ray Jui Signed-off-by: Srinath Mannam --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 28 ++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 15f7b0e..489bfd5 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -117,8 +117,11 @@ dma-coherent; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; linux,pci-domain = <0>; @@ -140,6 +143,13 @@ phy-names = "pcie-phy"; msi-parent = <&v2m0>; + pcie0_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie4: pcie@50020000 { @@ -148,8 +158,11 @@ dma-coherent; #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; linux,pci-domain = <4>; @@ -171,6 +184,13 @@ phy-names = "pcie-phy"; msi-parent = <&v2m0>; + pcie4_intc: interrupt-controller { + compatible = "brcm,iproc-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; pcie8: pcie@60c00000 {