From patchwork Tue Dec 3 15:17:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 11271523 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CB68112B for ; Tue, 3 Dec 2019 15:34:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 25AB7207DD for ; Tue, 3 Dec 2019 15:34:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 25AB7207DD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C5F16E80B; Tue, 3 Dec 2019 15:34:21 +0000 (UTC) X-Original-To: dri-devel@freedesktop.org Delivered-To: dri-devel@freedesktop.org X-Greylist: delayed 990 seconds by postgrey-1.36 at gabe; Tue, 03 Dec 2019 15:34:20 UTC Received: from a27-18.smtp-out.us-west-2.amazonses.com (a27-18.smtp-out.us-west-2.amazonses.com [54.240.27.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8C916E80B for ; Tue, 3 Dec 2019 15:34:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 99223C447A0 From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH] arm: dts: sc7180: Add A618 gpu dt blob Date: Tue, 3 Dec 2019 15:17:49 +0000 Message-ID: <0101016ecc56c744-6557703a-b027-4bc8-aa26-e27dd96c81eb-000000@us-west-2.amazonses.com> X-Mailer: git-send-email 1.9.1 X-SES-Outgoing: 2019.12.03-54.240.27.18 Feedback-ID: 1.us-west-2.CZuq2qbDmUIuT3qdvXlRHZZCpfZqZ4GtG9v3VKgRyF0=:AmazonSES X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=zsmsymrwgfyinv5wlfyidntwsjeeldzt; d=codeaurora.org; t=1575386269; h=From:To:Cc:Subject:Date:Message-Id; bh=a+ZeEDIVNB9eGTEKRl0WtwhCV5OviwdJ9UgvQi9PSGI=; b=awv2F4INfuLjW4Joh0RRp5rJjc5WUevQzJ4Y4r9oRyzI2oqdWyLEqHz3+pjN4YWq hrWaLgzoEQDBpyEmP6tu4Nb5nMYXujsYlgCVd5b1kik4M65YHg0Gji3RUIjlBafGrCB 8zHFgeEahimVrFpKyNAymgJYWUxkuNBVU9dJ8Wp0= X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=gdwg2y3kokkkj5a55z2ilkup5wp5hhxx; d=amazonses.com; t=1575386269; h=From:To:Cc:Subject:Date:Message-Id:Feedback-ID; bh=a+ZeEDIVNB9eGTEKRl0WtwhCV5OviwdJ9UgvQi9PSGI=; b=bGkHf8WfWgv6TTjHy+NAiY7SNzyGetqP82SUX4aPNrJi+HY9rrZTlq3aKdeCrEex R6X8p+eAKr7xK4Rlj7kTQkuRD5Qgok0OjlTLghCAtv13+EfgmBmsheN6wirUyMNbf4h eZ9ViQ1FELakg+kY5BaZp37TRFzwSoV/qr8kaKpQ= X-Mailman-Original-Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org X-Mailman-Original-Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Sharat Masetty , dri-devel@freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c3db2e5..31223d0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -18,6 +18,8 @@ #include #include #include +#include +#include / { interrupt-parent = <&intc>; @@ -733,6 +735,120 @@ #power-domain-cells = <1>; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x1000>, + <0 0x5061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + interconnects = <&gem_noc 35 &mc_virt 512>; + + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x5040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk"; + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu"; + + reg = <0 0x506a000 0 0x31000>, + <0 0xb290000 0 0x10000>, + <0 0xb490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc CX_GDSC>; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>;