From patchwork Tue Dec 3 17:56:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11271797 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8252B112B for ; Tue, 3 Dec 2019 17:56:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6609B2064B for ; Tue, 3 Dec 2019 17:56:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6609B2064B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 03F576EA57; Tue, 3 Dec 2019 17:56:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 860776EA57 for ; Tue, 3 Dec 2019 17:56:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 09:56:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,274,1571727600"; d="scan'208";a="201083035" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga007.jf.intel.com with SMTP; 03 Dec 2019 09:56:09 -0800 Received: by stinkbox (sSMTP sendmail emulation); Tue, 03 Dec 2019 19:56:08 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Dec 2019 19:56:08 +0200 Message-Id: <20191203175608.17200-1-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: s/HAS_128_BYTE_Y_TILING/!HAS_512_BYTE_Y_TILING/ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä 512B Y tiling is the special case so perhaps makes sense to flip the flag around and adjust the code accordingly. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 +--- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 2 +- 5 files changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1f1cd7578706..f37c11437cfc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1972,10 +1972,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 128; /* fall through */ case I915_FORMAT_MOD_Y_TILED: - if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) - return 128; - else + if (HAS_512_BYTE_Y_TILING(dev_priv)) return 512; + else + return 128; case I915_FORMAT_MOD_Yf_TILED_CCS: if (color_plane == 1) return 128; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c index 1fa592d82af5..e4655366ee00 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c @@ -145,7 +145,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj, } if (IS_GEN(i915, 2) || - (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) + (tiling == I915_TILING_Y && !HAS_512_BYTE_Y_TILING(i915))) tile_width = 128; else tile_width = 512; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 6ce9167f8c9f..ccd4a4c3f6dc 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -276,7 +276,7 @@ setup_tile_size(struct tile *tile, struct drm_i915_private *i915) tile->width = 128; tile->size = 11; } else if (tile->tiling == I915_TILING_Y && - HAS_128_BYTE_Y_TILING(i915)) { + !HAS_512_BYTE_Y_TILING(i915)) { tile->height = 32; tile->width = 128; tile->size = 12; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 14744c114475..0c0519844c8a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1674,9 +1674,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ - !(IS_I915G(dev_priv) || \ - IS_I915GM(dev_priv))) +#define HAS_512_BYTE_Y_TILING(dev_priv) (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 71efccfde122..a716974a8182 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -142,7 +142,7 @@ static void i915_write_fence_reg(struct i915_fence_reg *fence, GEM_BUG_ON(!is_power_of_2(vma->fence_size)); GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size)); - if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence))) + if (is_y_tiled && !HAS_512_BYTE_Y_TILING(fence_to_i915(fence))) stride /= 128; else stride /= 512;