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Wed, 4 Dec 2019 00:37:03 +0000 Subject: [PATCH v3 01/18] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:01 -0600 Message-ID: <157541982144.46157.2428083754645928332.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN4PR0501CA0133.namprd05.prod.outlook.com (2603:10b6:803:2c::11) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d340fb73-7849-488f-e5bc-08d7785214d8 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; 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X86CPUTopoIDs will have individual arch ids. Next patch introduces X86CPUTopoInfo which will have all topology information(like cores, threads etc..). Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 60 ++++++++++++++++++++++---------------------- include/hw/i386/topology.h | 40 +++++++++++++++-------------- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 51b72439b4..5bd2ffccb7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2212,7 +2212,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, int idx; CPUState *cs; CPUArchId *cpu_slot; - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; X86CPU *cpu = X86_CPU(dev); CPUX86State *env = &cpu->env; MachineState *ms = MACHINE(hotplug_dev); @@ -2277,12 +2277,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } - topo.pkg_id = cpu->socket_id; - topo.die_id = cpu->die_id; - topo.core_id = cpu->core_id; - topo.smt_id = cpu->thread_id; + topo_ids.pkg_id = cpu->socket_id; + topo_ids.die_id = cpu->die_id; + topo_ids.core_id = cpu->core_id; + topo_ids.smt_id = cpu->thread_id; cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, - smp_threads, &topo); + smp_threads, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); @@ -2290,11 +2290,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, MachineState *ms = MACHINE(pcms); x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo); + smp_cores, smp_threads, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", - topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, + topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, cpu->apic_id, ms->possible_cpus->len - 1); return; } @@ -2312,34 +2312,34 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo); - if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { + smp_cores, smp_threads, &topo_ids); + if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" - " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); + " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_ids.pkg_id); return; } - cpu->socket_id = topo.pkg_id; + cpu->socket_id = topo_ids.pkg_id; - if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { + if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { error_setg(errp, "property die-id: %u doesn't match set apic-id:" - " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); + " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); return; } - cpu->die_id = topo.die_id; + cpu->die_id = topo_ids.die_id; - if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" - " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); + " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); return; } - cpu->core_id = topo.core_id; + cpu->core_id = topo_ids.core_id; - if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { + if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { error_setg(errp, "property thread-id: %u doesn't match set apic-id:" - " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); + " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo_ids.smt_id); return; } - cpu->thread_id = topo.smt_id; + cpu->thread_id = topo_ids.smt_id; if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !kvm_hv_vpindex_settable()) { @@ -2692,14 +2692,14 @@ pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) { - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; PCMachineState *pcms = PC_MACHINE(ms); assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo); - return topo.pkg_id % ms->numa_state->num_nodes; + ms->smp.threads, &topo_ids); + return topo_ids.pkg_id % ms->numa_state->num_nodes; } static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) @@ -2721,24 +2721,24 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len = max_cpus; for (i = 0; i < ms->possible_cpus->len; i++) { - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; ms->possible_cpus->cpus[i].type = ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count = 1; ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo); + ms->smp.threads, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; - ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; + ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; if (pcms->smp_dies > 1) { ms->possible_cpus->cpus[i].props.has_die_id = true; - ms->possible_cpus->cpus[i].props.die_id = topo.die_id; + ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; } ms->possible_cpus->cpus[i].props.has_core_id = true; - ms->possible_cpus->cpus[i].props.core_id = topo.core_id; + ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id = true; - ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; + ms->possible_cpus->cpus[i].props.thread_id = topo_ids.smt_id; } return ms->possible_cpus; } diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 4ff5b2da6c..6c184f3115 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -45,12 +45,12 @@ */ typedef uint32_t apic_id_t; -typedef struct X86CPUTopoInfo { +typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; unsigned core_id; unsigned smt_id; -} X86CPUTopoInfo; +} X86CPUTopoIDs; /* Return the bit width needed for 'count' IDs */ @@ -122,12 +122,12 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, - const X86CPUTopoInfo *topo) + const X86CPUTopoIDs *topo_ids) { - return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | - (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | - (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | - topo->smt_id; + return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | + (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | + (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | + topo_ids->smt_id; } /* Calculate thread/core/package IDs for a specific topology, @@ -137,12 +137,12 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, unsigned cpu_index, - X86CPUTopoInfo *topo) + X86CPUTopoIDs *topo_ids) { - topo->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); - topo->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; - topo->core_id = cpu_index / nr_threads % nr_cores; - topo->smt_id = cpu_index % nr_threads; + topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); + topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->core_id = cpu_index / nr_threads % nr_cores; + topo_ids->smt_id = cpu_index % nr_threads; } /* Calculate thread/core/package IDs for a specific topology, @@ -152,17 +152,17 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, - X86CPUTopoInfo *topo) + X86CPUTopoIDs *topo_ids) { - topo->smt_id = apicid & + topo_ids->smt_id = apicid & ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); - topo->core_id = + topo_ids->core_id = (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); - topo->die_id = + topo_ids->die_id = (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); - topo->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); + topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); } /* Make APIC ID for the CPU 'cpu_index' @@ -174,9 +174,9 @@ static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, unsigned nr_threads, unsigned cpu_index) { - X86CPUTopoInfo topo; - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids); + return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids); 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Wed, 4 Dec 2019 00:37:09 +0000 Subject: [PATCH v3 02/18] hw/i386: Introduce X86CPUTopoInfo to contain topology info From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:08 -0600 Message-ID: <157541982831.46157.16635542688144831181.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN1PR12CA0108.namprd12.prod.outlook.com (2603:10b6:802:21::43) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7ba7798e-8c8f-4ac8-8bd4-08d7785218d9 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; 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Add X86CPUTopoInfo which will have all the topology informations required to build the cpu topology. There is no functional changes. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 40 +++++++++++++++++++++++++++------------- include/hw/i386/topology.h | 38 ++++++++++++++++++++++++-------------- 2 files changed, 51 insertions(+), 27 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5bd2ffccb7..8c23b1e8c9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -878,11 +878,15 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, { MachineState *ms = MACHINE(pcms); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); + X86CPUTopoInfo topo_info; uint32_t correct_id; static bool warned; - correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, - ms->smp.threads, cpu_index); + topo_info.dies_per_pkg = pcms->smp_dies; + topo_info.cores_per_die = ms->smp.cores; + topo_info.threads_per_core = ms->smp.threads; + + correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); if (pcmc->compat_apic_id_mode) { if (cpu_index != correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -2219,6 +2223,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, PCMachineState *pcms = PC_MACHINE(hotplug_dev); unsigned int smp_cores = ms->smp.cores; unsigned int smp_threads = ms->smp.threads; + X86CPUTopoInfo topo_info; if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", @@ -2226,6 +2231,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } + topo_info.dies_per_pkg = pcms->smp_dies; + topo_info.cores_per_die = smp_cores; + topo_info.threads_per_core = smp_threads; + env->nr_dies = pcms->smp_dies; /* @@ -2281,16 +2290,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id = cpu->die_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, - smp_threads, &topo_ids); + cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms = MACHINE(pcms); - x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -2311,8 +2318,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, - smp_cores, smp_threads, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_ids.pkg_id); @@ -2694,19 +2700,28 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) { X86CPUTopoIDs topo_ids; PCMachineState *pcms = PC_MACHINE(ms); + X86CPUTopoInfo topo_info; + + topo_info.dies_per_pkg = pcms->smp_dies; + topo_info.cores_per_die = ms->smp.cores; + topo_info.threads_per_core = ms->smp.threads; assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo_ids); + &topo_info, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) { PCMachineState *pcms = PC_MACHINE(ms); - int i; unsigned int max_cpus = ms->smp.max_cpus; + X86CPUTopoInfo topo_info; + int i; + + topo_info.dies_per_pkg = pcms->smp_dies; + topo_info.cores_per_die = ms->smp.cores; + topo_info.threads_per_core = ms->smp.threads; if (ms->possible_cpus) { /* @@ -2727,8 +2742,7 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].vcpus_count = 1; ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - pcms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo_ids); + &topo_info, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; if (pcms->smp_dies > 1) { diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 6c184f3115..cf1935d548 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -52,6 +52,12 @@ typedef struct X86CPUTopoIDs { unsigned smt_id; } X86CPUTopoIDs; +typedef struct X86CPUTopoInfo { + unsigned dies_per_pkg; + unsigned cores_per_die; + unsigned threads_per_core; +} X86CPUTopoInfo; + /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -119,11 +125,13 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { + unsigned nr_dies = topo_info->dies_per_pkg; + unsigned nr_cores = topo_info->cores_per_die; + unsigned nr_threads = topo_info->threads_per_core; + return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | @@ -133,12 +141,14 @@ static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, /* Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ -static inline void x86_topo_ids_from_idx(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, unsigned cpu_index, X86CPUTopoIDs *topo_ids) { + unsigned nr_dies = topo_info->dies_per_pkg; + unsigned nr_cores = topo_info->cores_per_die; + unsigned nr_threads = topo_info->threads_per_core; + topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; topo_ids->core_id = cpu_index / nr_threads % nr_cores; @@ -149,11 +159,13 @@ static inline void x86_topo_ids_from_idx(unsigned nr_dies, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, - unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, + X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids) { + unsigned nr_dies = topo_info->dies_per_pkg; + unsigned nr_cores = topo_info->cores_per_die; + unsigned nr_threads = topo_info->threads_per_core; + topo_ids->smt_id = apicid & ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); topo_ids->core_id = @@ -169,14 +181,12 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, unsigned cpu_index) { X86CPUTopoIDs topo_ids; - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_ids); - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids); + x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); + return apicid_from_topo_ids(topo_info, &topo_ids); } #endif /* HW_I386_TOPOLOGY_H */ From patchwork Wed Dec 4 00:37:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272051 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12D34921 for ; Wed, 4 Dec 2019 01:47:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDDD420674 for ; Wed, 4 Dec 2019 01:47:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="M8/QLS2b" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BDDD420674 Authentication-Results: mail.kernel.org; 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Wed, 4 Dec 2019 00:37:16 +0000 Subject: [PATCH v3 03/18] hw/i386: Consolidate topology functions From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:15 -0600 Message-ID: <157541983500.46157.10867081966222391072.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN4PR0501CA0134.namprd05.prod.outlook.com (2603:10b6:803:2c::12) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 24fbb7aa-c013-4371-fd71-08d778521cdf X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; 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Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- include/hw/i386/topology.h | 64 ++++++++++++++------------------------------ target/i386/cpu.c | 23 ++++++++-------- 2 files changed, 32 insertions(+), 55 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index cf1935d548..ba52d49079 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count) /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_threads); + return apicid_bitwidth_for_count(topo_info->threads_per_core); } /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_cores); + return apicid_bitwidth_for_count(topo_info->cores_per_die); } /* Bit width of the Die_ID field */ -static inline unsigned apicid_die_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_dies); + return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { - return apicid_smt_width(nr_dies, nr_cores, nr_threads); + return apicid_smt_width(topo_info); } /* Bit offset of the Die_ID field */ -static inline unsigned apicid_die_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(nr_dies, nr_cores, nr_threads) + - apicid_core_width(nr_dies, nr_cores, nr_threads); + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } /* Bit offset of the Pkg_ID (socket ID) field */ -static inline unsigned apicid_pkg_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { - return apicid_die_offset(nr_dies, nr_cores, nr_threads) + - apicid_die_width(nr_dies, nr_cores, nr_threads); + return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID @@ -128,13 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies, static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { - unsigned nr_dies = topo_info->dies_per_pkg; - unsigned nr_cores = topo_info->cores_per_die; - unsigned nr_threads = topo_info->threads_per_core; - - return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) | - (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threads)) | - (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threads)) | + return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | + (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } @@ -162,19 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids) { - unsigned nr_dies = topo_info->dies_per_pkg; - unsigned nr_cores = topo_info->cores_per_die; - unsigned nr_threads = topo_info->threads_per_core; - topo_ids->smt_id = apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads)); + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); topo_ids->core_id = - (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_threads)); + (apicid >> apicid_core_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); topo_ids->die_id = - (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads)); - topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads); + (apicid >> apicid_die_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); + topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); } /* Make APIC ID for the CPU 'cpu_index' diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 07cf562d89..bc9b491557 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4551,6 +4551,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t die_offset; uint32_t limit; uint32_t signature[3]; + X86CPUTopoInfo topo_info; + + topo_info.dies_per_pkg = env->nr_dies; + topo_info.cores_per_die = cs->nr_cores; + topo_info.threads_per_core = cs->nr_threads; /* Calculate & apply limits for different index ranges */ if (index >= 0xC0000000) { @@ -4637,8 +4642,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset = apicid_die_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + die_offset = apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, (1 << die_offset), cs->nr_cores, @@ -4729,14 +4733,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: - *eax = apicid_core_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax = apicid_core_offset(&topo_info); *ebx = cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_pkg_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax = apicid_pkg_offset(&topo_info); *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -4760,20 +4762,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = cpu->apic_id; switch (count) { case 0: - *eax = apicid_core_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_core_offset(&topo_info); *ebx = cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_die_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_die_offset(&topo_info); *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax = apicid_pkg_offset(&topo_info); *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; break; From patchwork Wed Dec 4 00:37:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272039 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2B9BD138C for ; Wed, 4 Dec 2019 01:26:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E7FE02073B for ; Wed, 4 Dec 2019 01:26:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="dbwsC8yz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7FE02073B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; 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Wed, 4 Dec 2019 00:37:23 +0000 Subject: [PATCH v3 04/18] hw/i386: Introduce initialize_topo_info to initialize X86CPUTopoInfo From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:21 -0600 Message-ID: <157541984181.46157.12341489595513709747.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN1PR12CA0084.namprd12.prod.outlook.com (2603:10b6:802:21::19) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5900a764-c3e1-4e59-cdd1-08d7785220f0 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8c23b1e8c9..cafbdafa76 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -866,6 +866,15 @@ static void handle_a20_line_change(void *opaque, int irq, int level) x86_cpu_set_a20(cpu, level); } +static inline void initialize_topo_info(X86CPUTopoInfo *topo_info, + PCMachineState *pcms, + const MachineState *ms) +{ + topo_info->dies_per_pkg = pcms->smp_dies; + topo_info->cores_per_die = ms->smp.cores; + topo_info->threads_per_core = ms->smp.threads; +} + /* Calculates initial APIC ID for a specific CPU index * * Currently we need to be able to calculate the APIC ID from the CPU index @@ -882,9 +891,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, uint32_t correct_id; static bool warned; - topo_info.dies_per_pkg = pcms->smp_dies; - topo_info.cores_per_die = ms->smp.cores; - topo_info.threads_per_core = ms->smp.threads; + initialize_topo_info(&topo_info, pcms, ms); correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); if (pcmc->compat_apic_id_mode) { @@ -2231,9 +2238,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } - topo_info.dies_per_pkg = pcms->smp_dies; - topo_info.cores_per_die = smp_cores; - topo_info.threads_per_core = smp_threads; + initialize_topo_info(&topo_info, pcms, ms); env->nr_dies = pcms->smp_dies; @@ -2702,9 +2707,7 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) PCMachineState *pcms = PC_MACHINE(ms); X86CPUTopoInfo topo_info; - topo_info.dies_per_pkg = pcms->smp_dies; - topo_info.cores_per_die = ms->smp.cores; - topo_info.threads_per_core = ms->smp.threads; + initialize_topo_info(&topo_info, pcms, ms); assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, @@ -2719,10 +2722,6 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) X86CPUTopoInfo topo_info; int i; - topo_info.dies_per_pkg = pcms->smp_dies; - topo_info.cores_per_die = ms->smp.cores; - topo_info.threads_per_core = ms->smp.threads; - if (ms->possible_cpus) { /* * make sure that max_cpus hasn't changed since the first use, i.e. @@ -2734,6 +2733,9 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + sizeof(CPUArchId) * max_cpus); + + initialize_topo_info(&topo_info, pcms, ms); + ms->possible_cpus->len = max_cpus; for (i = 0; i < ms->possible_cpus->len; i++) { X86CPUTopoIDs topo_ids; From patchwork Wed Dec 4 00:37:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F3C97109A for ; Wed, 4 Dec 2019 01:59:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C699D206E4 for ; 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Wed, 4 Dec 2019 00:37:30 +0000 Subject: [PATCH v3 05/18] machine: Add SMP Sockets in CpuTopology From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:28 -0600 Message-ID: <157541984859.46157.16271709119317180051.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN4PR0501CA0145.namprd05.prod.outlook.com (2603:10b6:803:2c::23) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 440e3702-d3ac-488b-73ed-08d7785224f1 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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The socket information required to build the apic id in EPYC mode. Right now socket information is not passed to down when decoding the apic id. Add the socket information here. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/core/machine.c | 1 + hw/i386/pc.c | 1 + include/hw/boards.h | 2 ++ vl.c | 1 + 4 files changed, 5 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index 1689ad3bf8..e59b181ead 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -784,6 +784,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts) ms->smp.cpus = cpus; ms->smp.cores = cores; ms->smp.threads = threads; + ms->smp.sockets = sockets; } if (ms->smp.cpus > 1) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index cafbdafa76..17de152a77 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1473,6 +1473,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) ms->smp.cpus = cpus; ms->smp.cores = cores; ms->smp.threads = threads; + ms->smp.sockets = sockets; pcms->smp_dies = dies; } diff --git a/include/hw/boards.h b/include/hw/boards.h index de45087f34..d4fab218e6 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -256,12 +256,14 @@ typedef struct DeviceMemoryState { * @cpus: the number of present logical processors on the machine * @cores: the number of cores in one package * @threads: the number of threads in one core + * @sockets: the number of sockets on the machine * @max_cpus: the maximum number of logical processors on the machine */ typedef struct CpuTopology { unsigned int cpus; unsigned int cores; unsigned int threads; + unsigned int sockets; unsigned int max_cpus; } CpuTopology; diff --git a/vl.c b/vl.c index 4489cfb2bb..a42c24a77f 100644 --- a/vl.c +++ b/vl.c @@ -3962,6 +3962,7 @@ int main(int argc, char **argv, char **envp) current_machine->smp.max_cpus = machine_class->default_cpus; current_machine->smp.cores = 1; current_machine->smp.threads = 1; + current_machine->smp.sockets = 1; machine_class->smp_parse(current_machine, qemu_opts_find(qemu_find_opts("smp-opts"), NULL)); From patchwork Wed Dec 4 00:37:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272047 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 87BE5930 for ; Wed, 4 Dec 2019 01:44:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7E3D2068E for ; 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Wed, 4 Dec 2019 00:37:36 +0000 Subject: [PATCH v3 06/18] hw/core: Add core complex id in X86CPU topology From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:35 -0600 Message-ID: <157541985531.46157.16935250205964640126.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR05CA0012.namprd05.prod.outlook.com (2603:10b6:805:de::25) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 3618d264-d407-46e1-9fcf-08d7785228fc X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1201; 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This information is required to build the topology in EPIC mode. Signed-off-by: Babu Moger --- hw/core/machine-hmp-cmds.c | 3 +++ hw/core/machine.c | 13 +++++++++++++ hw/i386/pc.c | 10 ++++++++++ include/hw/i386/topology.h | 1 + qapi/machine.json | 7 +++++-- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 7 files changed, 35 insertions(+), 2 deletions(-) diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c index cd970cc4c5..59c91d1ce1 100644 --- a/hw/core/machine-hmp-cmds.c +++ b/hw/core/machine-hmp-cmds.c @@ -90,6 +90,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) if (c->has_die_id) { monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); } + if (c->has_llc_id) { + monitor_printf(mon, " llc-id: \"%" PRIu64 "\"\n", c->llc_id); + } if (c->has_core_id) { monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); } diff --git a/hw/core/machine.c b/hw/core/machine.c index e59b181ead..ff991e6ab5 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine, return; } + if (props->has_llc_id && !slot->props.has_llc_id) { + error_setg(errp, "llc-id is not supported"); + return; + } + /* skip slots with explicit mismatch */ if (props->has_thread_id && props->thread_id != slot->props.thread_id) { continue; @@ -696,6 +701,10 @@ void machine_set_cpu_numa_node(MachineState *machine, continue; } + if (props->has_llc_id && props->llc_id != slot->props.llc_id) { + continue; + } + if (props->has_socket_id && props->socket_id != slot->props.socket_id) { continue; } @@ -1034,6 +1043,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) if (cpu->props.has_die_id) { g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); } + + if (cpu->props.has_llc_id) { + g_string_append_printf(s, "llc-id: %"PRId64, cpu->props.llc_id); + } if (cpu->props.has_core_id) { if (s->len) { g_string_append_printf(s, ", "); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 17de152a77..df5339c102 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2294,6 +2294,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.pkg_id = cpu->socket_id; topo_ids.die_id = cpu->die_id; + topo_ids.llc_id = cpu->llc_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); @@ -2339,6 +2340,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id = topo_ids.die_id; + if (cpu->llc_id != -1 && cpu->llc_id != topo_ids.llc_id) { + error_setg(errp, "property llc-id: %u doesn't match set apic-id:" + " 0x%x (llc-id: %u)", cpu->llc_id, cpu->apic_id, topo_ids.llc_id); + return; + } + cpu->llc_id = topo_ids.llc_id; + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); @@ -2752,6 +2760,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].props.has_die_id = true; ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; } + ms->possible_cpus->cpus[i].props.has_llc_id = true; + ms->possible_cpus->cpus[i].props.llc_id = topo_ids.llc_id; ms->possible_cpus->cpus[i].props.has_core_id = true; ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id = true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index ba52d49079..1238006208 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -48,6 +48,7 @@ typedef uint32_t apic_id_t; typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; + unsigned llc_id; unsigned core_id; unsigned smt_id; } X86CPUTopoIDs; diff --git a/qapi/machine.json b/qapi/machine.json index ca26779f1a..1ca5b73418 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -646,9 +646,11 @@ # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to # @die-id: die number within node/board the CPU belongs to (Since 4.1) -# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to +# @llc-id: last level cache number within node/board the CPU belongs to (Since 4.2) +# @core-id: core number within die the CPU belongs to +# @thread-id: thread number within core the CPU belongs to # -# Note: currently there are 5 properties that could be present +# Note: currently there are 6 properties that could be present # but management should be prepared to pass through other # properties with device_add command to allow for future # interface extension. This also requires the filed names to be kept in @@ -660,6 +662,7 @@ 'data': { '*node-id': 'int', '*socket-id': 'int', '*die-id': 'int', + '*llc-id': 'int', '*core-id': 'int', '*thread-id': 'int' } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bc9b491557..3c81aa3ecd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6222,12 +6222,14 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index af57fda8e5..a56d44e405 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1711,6 +1711,7 @@ struct X86CPU { int32_t node_id; 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Wed, 4 Dec 2019 00:37:45 +0000 Subject: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:42 -0600 Message-ID: <157541986210.46157.5082551407581177819.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN4PR0501CA0152.namprd05.prod.outlook.com (2603:10b6:803:2c::30) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: c3adbe13-a5ad-436d-e758-08d778522e60 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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Signed-off-by: Babu Moger --- include/hw/boards.h | 1 + vl.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/boards.h b/include/hw/boards.h index d4fab218e6..ce5aa365cb 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -238,6 +238,7 @@ struct MachineClass { unsigned cpu_index); const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine); int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx); + void (*init_apicid_fn)(MachineState *ms); }; /** diff --git a/vl.c b/vl.c index a42c24a77f..b6af604e11 100644 --- a/vl.c +++ b/vl.c @@ -4318,6 +4318,9 @@ int main(int argc, char **argv, char **envp) current_machine->cpu_type = machine_class->default_cpu_type; if (cpu_option) { current_machine->cpu_type = parse_cpu_option(cpu_option); + if (machine_class->init_apicid_fn) { + machine_class->init_apicid_fn(current_machine); + } } parse_numa_opts(current_machine); From patchwork Wed Dec 4 00:37:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D72C921 for ; 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Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB2535.namprd12.prod.outlook.com (52.132.141.154) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.21; Wed, 4 Dec 2019 00:37:52 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3%6]) with mapi id 15.20.2495.014; Wed, 4 Dec 2019 00:37:52 +0000 Subject: [PATCH v3 08/18] hw/i386: Update structures for nodes_per_pkg From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:51 -0600 Message-ID: <157541987113.46157.12421621035195290598.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR16CA0047.namprd16.prod.outlook.com (2603:10b6:805:ca::24) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 952d456a-1099-4922-1716-08d778523273 X-MS-TrafficTypeDiagnostic: DM5PR12MB2535:|DM5PR12MB2535: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1169; 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This is required to build EPYC mode topology. Signed-off-by: Babu Moger --- hw/i386/pc.c | 4 ++++ include/hw/i386/topology.h | 1 + target/i386/cpu.c | 1 + target/i386/cpu.h | 1 + 4 files changed, 7 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index df5339c102..5dc11df922 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -870,6 +870,7 @@ static inline void initialize_topo_info(X86CPUTopoInfo *topo_info, PCMachineState *pcms, const MachineState *ms) { + topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets; topo_info->dies_per_pkg = pcms->smp_dies; topo_info->cores_per_die = ms->smp.cores; topo_info->threads_per_core = ms->smp.threads; @@ -1390,11 +1391,13 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) Object *cpu = NULL; Error *local_err = NULL; CPUX86State *env = NULL; + MachineState *ms = MACHINE(pcms); cpu = object_new(MACHINE(pcms)->cpu_type); env = &X86_CPU(cpu)->env; env->nr_dies = pcms->smp_dies; + env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets; object_property_set_uint(cpu, apic_id, "apic-id", &local_err); object_property_set_bool(cpu, true, "realized", &local_err); @@ -2242,6 +2245,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, initialize_topo_info(&topo_info, pcms, ms); env->nr_dies = pcms->smp_dies; + env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets; /* * If APIC ID is not set, diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 1238006208..cfb09312fe 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -54,6 +54,7 @@ typedef struct X86CPUTopoIDs { } X86CPUTopoIDs; typedef struct X86CPUTopoInfo { + unsigned nodes_per_pkg; unsigned dies_per_pkg; unsigned cores_per_die; unsigned threads_per_core; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3c81aa3ecd..9b2608a4c8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5996,6 +5996,7 @@ static void x86_cpu_initfn(Object *obj) FeatureWord w; env->nr_dies = 1; + env->nr_nodes = 1; cpu_set_cpustate_pointers(cpu); object_property_add(obj, "family", "int", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a56d44e405..0ef4fdb55f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1591,6 +1591,7 @@ typedef struct CPUX86State { TPRAccess tpr_access_type; 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Wed, 4 Dec 2019 00:37:59 +0000 Subject: [PATCH v3 09/18] i386: Add CPUX86Family type in CPUX86State From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:37:58 -0600 Message-ID: <157541987799.46157.8690212718301117297.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR16CA0037.namprd16.prod.outlook.com (2603:10b6:805:ca::14) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 59925e0a-6599-4943-b8ba-08d778523675 X-MS-TrafficTypeDiagnostic: DM5PR12MB2535:|DM5PR12MB2535: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; 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This will be used to differentiate generic x86 and x86 EPYC based cpu models. Signed-off-by: Babu Moger --- hw/i386/pc.c | 4 ++++ target/i386/cpu.c | 1 + target/i386/cpu.h | 7 +++++++ 3 files changed, 12 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5dc11df922..7f30104a6b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1398,6 +1398,8 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) env = &X86_CPU(cpu)->env; env->nr_dies = pcms->smp_dies; env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets; + env->family_type = strncmp(ms->cpu_type, "EPYC", 4) ? CPUX86FAMILY_DEFAULT : + CPUX86FAMILY_EPYC; object_property_set_uint(cpu, apic_id, "apic-id", &local_err); object_property_set_bool(cpu, true, "realized", &local_err); @@ -2246,6 +2248,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, env->nr_dies = pcms->smp_dies; env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets; + env->family_type = strncmp(ms->cpu_type, "EPYC", 4) ? CPUX86FAMILY_DEFAULT : + CPUX86FAMILY_EPYC; /* * If APIC ID is not set, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9b2608a4c8..5629c6d4c1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5997,6 +5997,7 @@ static void x86_cpu_initfn(Object *obj) env->nr_dies = 1; env->nr_nodes = 1; + env->family_type = CPUX86FAMILY_DEFAULT; cpu_set_cpustate_pointers(cpu); object_property_add(obj, "family", "int", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0ef4fdb55f..105744430b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1284,6 +1284,11 @@ typedef enum TPRAccess { TPR_ACCESS_WRITE, } TPRAccess; +typedef enum CPUX86Family { + CPUX86FAMILY_DEFAULT = 0, + CPUX86FAMILY_EPYC, +} CPUX86Family; + /* Cache information data structures: */ enum CacheType { @@ -1590,6 +1595,8 @@ typedef struct CPUX86State { TPRAccess tpr_access_type; + CPUX86Family family_type; + unsigned nr_dies; unsigned nr_nodes; } CPUX86State; From patchwork Wed Dec 4 00:38:04 2019 Content-Type: text/plain; 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Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB1369.namprd12.prod.outlook.com (10.168.234.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.19; Wed, 4 Dec 2019 00:38:06 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3%6]) with mapi id 15.20.2495.014; Wed, 4 Dec 2019 00:38:06 +0000 Subject: [PATCH v3 10/18] hw/386: Add EPYC mode topology decoding functions From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:04 -0600 Message-ID: <157541988471.46157.6587693720990965800.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN2PR01CA0078.prod.exchangelabs.com (2603:10b6:800::46) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: fa4fd403-23e8-44cb-d9cc-08d778523a9f X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; X-Forefront-PRVS: 0241D5F98C X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(376002)(39860400002)(136003)(346002)(396003)(366004)(189003)(199004)(2906002)(25786009)(103116003)(50466002)(6116002)(5660300002)(478600001)(7736002)(3846002)(66476007)(230700001)(66556008)(44832011)(4326008)(11346002)(966005)(99286004)(14454004)(446003)(6512007)(23676004)(316002)(58126008)(81166006)(76176011)(66946007)(386003)(6506007)(305945005)(6436002)(6486002)(81156014)(2486003)(86362001)(8936002)(52116002)(8676002)(26005)(186003)(6306002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1369; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zoYmhzj5QRLOrwhFc41Mr2Oh1liGlBR7EzjC1cUJ5Dz5uPZZd/YAaGMKD6709NCS7LU2wah9Ya7qHl5LqtwyKLtc0dTdc539RO6RDrphGmjRsDZdABVwxRgC8TC6JUhw0F7dATRzh40tDsVOOLtDCPIGDw1uyJHrPa6j2kezJ1ILE+lL8QvkuPwvEDWDS7x4qO67sQGE5PUJ0jONZPxCX6PYGb/KepZ8DJk1zdvqsPrQSFkhKEX67Ln1P0IDPoXTdIz9z9hRVQ7q7NaG5FC9bxk8BxLNDN45qPI5t47L80qdQsTP+MqrJUWrIIQv/AxVtRNcez0r8m9nGopbB3LS+sf51ZD2EbtN/0rWGXB13mb/mZlQWtlbJEfqnO3TPILnCrjvhrpvtGOZblHPiTxz02g5d1HEfJ5NoyYBmDmFDFwHptKHBqFzxkqgrNtr39Xqt4eDzCF+l+YGDERSsRqKyrPlDy+Mmqfiaw8vqC7xkNE= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: fa4fd403-23e8-44cb-d9cc-08d778523a9f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2019 00:38:06.4909 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: O3JG/HH9b96vaSsqKrr5FO37DUzEPLH2znydyyNY0epBvZeuYOQsWKikHL//Tlfs X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1369 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.94.60 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: babu.moger@amd.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" These functions add support for building EPYC mode topology given the smp details like numa nodes, cores, threads and sockets. The new apic id decoding is mostly similar to current apic id decoding except that it adds a new field llc_id when numa configured. Removes all the hardcoded values. Subsequent patches will use these functions to build the topology. Following functions are added. apicid_llc_width_epyc apicid_llc_offset_epyc apicid_pkg_offset_epyc apicid_from_topo_ids_epyc x86_topo_ids_from_idx_epyc x86_topo_ids_from_apicid_epyc x86_apicid_from_cpu_idx_epyc The topology details are available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 93 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index cfb09312fe..adb92fe9ce 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -89,6 +89,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } +/* Bit width of the llc_ID field per socket */ +static inline unsigned apicid_llc_width_epyc(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1)); +} /* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) @@ -109,6 +114,94 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } +#define LLC_OFFSET 3 /* Minimum LLC offset if numa configured */ + +/* Bit offset of the llc_ID field */ +static inline unsigned apicid_llc_offset_epyc(X86CPUTopoInfo *topo_info) +{ + unsigned offset = apicid_die_offset(topo_info) + + apicid_die_width(topo_info); + + if (topo_info->nodes_per_pkg) { + return MAX(LLC_OFFSET, offset); + } else { + return offset; + } +} + +/* Bit offset of the Pkg_ID (socket ID) field */ +static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info) +{ + return apicid_llc_offset_epyc(topo_info) + apicid_llc_width_epyc(topo_info); +} + +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID + * + * The caller must make sure core_id < nr_cores and smt_id < nr_threads. + */ +static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids) +{ + return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) | + (topo_ids->llc_id << apicid_llc_offset_epyc(topo_info)) | + (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->core_id << apicid_core_offset(topo_info)) | + topo_ids->smt_id; +} + +static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info, + unsigned cpu_index, + X86CPUTopoIDs *topo_ids) +{ + unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1); + unsigned nr_dies = topo_info->dies_per_pkg; + unsigned nr_cores = topo_info->cores_per_die; + unsigned nr_threads = topo_info->threads_per_core; + unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads), + nr_nodes); + + topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads); + topo_ids->llc_id = (cpu_index / cores_per_node) % nr_nodes; + topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->core_id = cpu_index / nr_threads % nr_cores; + topo_ids->smt_id = cpu_index % nr_threads; +} + +/* + * Calculate thread/core/package IDs for a specific topology, + * based on APIC ID + */ +static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid, + X86CPUTopoInfo *topo_info, + X86CPUTopoIDs *topo_ids) +{ + topo_ids->smt_id = apicid & + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); + topo_ids->core_id = + (apicid >> apicid_core_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + topo_ids->die_id = + (apicid >> apicid_die_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); + topo_ids->llc_id = + (apicid >> apicid_llc_offset_epyc(topo_info)) & + ~(0xFFFFFFFFUL << apicid_llc_width_epyc(topo_info)); + topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(topo_info); +} + +/* + * Make APIC ID for the CPU 'cpu_index' + * + * 'cpu_index' is a sequential, contiguous ID for the CPU. + */ +static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info, + unsigned cpu_index) +{ + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids); + return apicid_from_topo_ids_epyc(topo_info, &topo_ids); +} /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. 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Wed, 4 Dec 2019 00:38:13 +0000 Subject: [PATCH v3 11/18] i386: Cleanup and use the EPYC mode topology functions From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:11 -0600 Message-ID: <157541989177.46157.8689452600249117022.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN2PR01CA0080.prod.exchangelabs.com (2603:10b6:800::48) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6bb72f1b-6302-44fa-06ff-08d778523ed6 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3826; 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Given the sockets, nodes, cores and threads, the new functions generate apic id for EPYC mode. Removes all the hardcoded values. Signed-off-by: Babu Moger --- target/i386/cpu.c | 162 +++++++++++------------------------------------------ 1 file changed, 35 insertions(+), 127 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5629c6d4c1..e87487bae3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -338,68 +338,15 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2, } } -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case */ - return (nodes == 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores using - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will also - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <= MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes = nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { uint32_t l3_cores; + unsigned nodes = MAX(topo_info->nodes_per_pkg, 1); + assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); @@ -408,10 +355,13 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, /* L3 is shared among multiple cores */ if (cache->level == 3) { - l3_cores = cores_in_core_complex(cs->nr_cores); - *eax |= ((l3_cores * cs->nr_threads) - 1) << 14; + l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg * + topo_info->cores_per_die * + topo_info->threads_per_core), + nodes); + *eax |= (l3_cores - 1) << 14; } else { - *eax |= ((cs->nr_threads - 1) << 14); + *eax |= ((topo_info->threads_per_core - 1) << 14); } assert(cache->line_size > 0); @@ -431,55 +381,17 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core index - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes = nodes_in_socket(nr_cores); - - cores_in_ccx = cores_in_core_complex(nr_cores); - - topo->node_id = core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id = core_id % cores_in_ccx; - topo->num_nodes = nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, +static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - struct core_topology topo = {0}; - unsigned long nodes; + X86CPUTopoIDs topo_ids = {0}; + unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1); int shift; - build_core_topology(cs->nr_cores, cpu->core_id, &topo); + x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids); + *eax = cpu->apic_id; /* * CPUID_Fn8000001E_EBX @@ -496,12 +408,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * 3 Core complex id * 1:0 Core id */ - if (cs->nr_threads - 1) { - *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; - } else { - *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; - } + *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.llc_id << 3) | + (topo_ids.core_id); /* * CPUID_Fn8000001E_ECX * 31:11 Reserved @@ -510,9 +418,9 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * 2 Socket id * 1:0 Node id */ - if (topo.num_nodes <= 4) { - *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; + + if (nodes <= 4) { + *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.llc_id; } else { /* * Node id fix up. Actual hardware supports up to 4 nodes. But with @@ -527,10 +435,10 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, * number of nodes. find_last_bit returns last set bit(0 based). Left * shift(+1) the socket id to represent all the nodes. */ - nodes = topo.num_nodes - 1; + nodes -= 1; shift = find_last_bit(&nodes, 8); - *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) | - topo.node_id; + *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | + topo_ids.llc_id; } *edx = 0; } @@ -4553,6 +4461,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t signature[3]; X86CPUTopoInfo topo_info; + topo_info.nodes_per_pkg = env->nr_nodes; topo_info.dies_per_pkg = env->nr_dies; topo_info.cores_per_die = cs->nr_cores; topo_info.threads_per_core = cs->nr_threads; @@ -4972,20 +4881,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + &topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ *eax = *ebx = *ecx = *edx = 0; @@ -4994,8 +4903,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001E: assert(cpu->core_id <= 255); - encode_topo_cpuid8000001e(cs, cpu, - eax, ebx, ecx, edx); + encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx); break; case 0xC0000000: *eax = env->cpuid_xlevel2; From patchwork Wed Dec 4 00:38:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5EC8E13A4 for ; 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Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB1369.namprd12.prod.outlook.com (10.168.234.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.19; Wed, 4 Dec 2019 00:38:20 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3%6]) with mapi id 15.20.2495.014; Wed, 4 Dec 2019 00:38:20 +0000 Subject: [PATCH v3 12/18] numa: Split the numa initialization From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:18 -0600 Message-ID: <157541989879.46157.15315443378951392179.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR02CA0030.namprd02.prod.outlook.com (2603:10b6:805:a2::43) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: fa609597-2b70-4643-5108-08d7785242e5 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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At present numa node initialization and cpu initialization happens at the same time. Apic id generation happens during the cpu initialization. At this point it is not known how many numa nodes are configured. So, save the cpu indexes and move the cpu initialization inside the numa_complete_configuration. Cpu initialization is done in new function numa_node_complete_configuration. Signed-off-by: Babu Moger --- hw/core/numa.c | 62 ++++++++++++++++++++++++++++++++----------------- include/sysemu/numa.h | 5 ++++ 2 files changed, 46 insertions(+), 21 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index 038c96d4ab..ba02a41421 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -33,6 +33,7 @@ #include "qapi/error.h" #include "qapi/opts-visitor.h" #include "qapi/qapi-visit-machine.h" +#include "qapi/clone-visitor.h" #include "sysemu/qtest.h" #include "hw/core/cpu.h" #include "hw/mem/pc-dimm.h" @@ -59,11 +60,8 @@ static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one. static void parse_numa_node(MachineState *ms, NumaNodeOptions *node, Error **errp) { - Error *err = NULL; uint16_t nodenr; - uint16List *cpus = NULL; MachineClass *mc = MACHINE_GET_CLASS(ms); - unsigned int max_cpus = ms->smp.max_cpus; NodeInfo *numa_info = ms->numa_state->nodes; if (node->has_nodeid) { @@ -87,24 +85,8 @@ static void parse_numa_node(MachineState *ms, NumaNodeOptions *node, error_setg(errp, "NUMA is not supported by this machine-type"); return; } - for (cpus = node->cpus; cpus; cpus = cpus->next) { - CpuInstanceProperties props; - if (cpus->value >= max_cpus) { - error_setg(errp, - "CPU index (%" PRIu16 ")" - " should be smaller than maxcpus (%d)", - cpus->value, max_cpus); - return; - } - props = mc->cpu_index_to_instance_props(ms, cpus->value); - props.node_id = nodenr; - props.has_node_id = true; - machine_set_cpu_numa_node(ms, &props, &err); - if (err) { - error_propagate(errp, err); - return; - } - } + + numa_info[nodenr].cpu_indexes = QAPI_CLONE(uint16List, node->cpus); have_memdevs = have_memdevs ? : node->has_memdev; have_mem = have_mem ? : node->has_mem; @@ -360,12 +342,50 @@ void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, nodes[i].node_mem = size - usedmem; } + +void numa_node_complete_configuration(MachineState *ms, NodeInfo *node, + uint16_t nodenr) +{ + Error *err = NULL; + uint16List *cpus = NULL; + MachineClass *mc = MACHINE_GET_CLASS(ms); + unsigned int max_cpus = ms->smp.max_cpus; + + for (cpus = node->cpu_indexes; cpus; cpus = cpus->next) { + CpuInstanceProperties props; + if (cpus->value >= max_cpus) { + error_report("CPU index (%" PRIu16 ")" + " should be smaller than maxcpus (%d)", + cpus->value, max_cpus); + return; + } + props = mc->cpu_index_to_instance_props(ms, cpus->value); + props.node_id = nodenr; + props.has_node_id = true; + machine_set_cpu_numa_node(ms, &props, &err); + if (err) { + error_report("Numa node initialization failed"); + return; + } + } +} + void numa_complete_configuration(MachineState *ms) { int i; MachineClass *mc = MACHINE_GET_CLASS(ms); NodeInfo *numa_info = ms->numa_state->nodes; + for (i = 0; i < ms->numa_state->num_nodes; i++) { + /* + * numa_node_complete_configuration() needs to be called after all + * nodes were already parsed, because to support new epyc mode, we + * need to know the number of numa nodes in advance to generate + * apic id correctly. + */ + numa_node_complete_configuration(ms, &numa_info[i], i); + } + /* * If memory hotplug is enabled (slots > 0) but without '-numa' * options explicitly on CLI, guestes will break. diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index ae9c41d02b..91794d685f 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -19,6 +19,9 @@ struct NodeInfo { struct HostMemoryBackend *node_memdev; bool present; uint8_t distance[MAX_NODES]; + + /* These indexes are saved for numa node initialization later */ + uint16List *cpu_indexes; }; struct NumaNodeMem { @@ -41,6 +44,8 @@ typedef struct NumaState NumaState; void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp); void parse_numa_opts(MachineState *ms); void numa_complete_configuration(MachineState *ms); +void numa_node_complete_configuration(MachineState *ms, NodeInfo *node, + uint16_t nodenr); void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms); extern QemuOptsList qemu_numa_opts; void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, From patchwork Wed Dec 4 00:38:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13C5C138D for ; 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Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB1369.namprd12.prod.outlook.com (10.168.234.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.19; Wed, 4 Dec 2019 00:38:27 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3%6]) with mapi id 15.20.2495.014; Wed, 4 Dec 2019 00:38:27 +0000 Subject: [PATCH v3 13/18] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:25 -0600 Message-ID: <157541990559.46157.14383447284580991446.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR05CA0015.namprd05.prod.outlook.com (2603:10b6:805:de::28) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 98500976-a085-47c2-8689-08d7785246e3 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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This will be used to initialize with correct handlers based on the cpu model selected. x86_apicid_from_cpu_idx will be default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 5 ++++- include/hw/i386/pc.h | 5 +++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7f30104a6b..52aea4a652 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -894,7 +894,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, initialize_topo_info(&topo_info, pcms, ms); - correct_id = x86_apicid_from_cpu_idx(&topo_info, cpu_index); + correct_id = pcms->apicid_from_cpu_idx(&topo_info, cpu_index); if (pcmc->compat_apic_id_mode) { if (cpu_index != correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -2679,6 +2679,9 @@ static void pc_machine_initfn(Object *obj) pcms->pit_enabled = true; pcms->smp_dies = 1; + /* Initialize the apic id related handlers */ + pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; + pc_system_flash_create(pcms); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 37bfd95113..56aa0e45b5 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -16,6 +16,7 @@ #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/acpi_dev_interface.h" +#include "hw/i386/topology.h" #define HPET_INTCAP "hpet-intcap" @@ -67,6 +68,10 @@ struct PCMachineState { uint64_t numa_nodes; uint64_t *node_mem; + /* Apic id specific handlers */ + uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, + unsigned cpu_index); + /* Address space used by IOAPIC device. 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Wed, 4 Dec 2019 00:38:34 +0000 Subject: [PATCH v3 14/18] hw/i386: Introduce topo_ids_from_apicid handler PCMachineState From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:32 -0600 Message-ID: <157541991228.46157.16916453001605357002.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR05CA0003.namprd05.prod.outlook.com (2603:10b6:805:de::16) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: a588a01c-7f56-44f3-6096-08d778524b24 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; 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Initialize with correct handler based on mode selected. x86_apicid_from_cpu_idx will be the default handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 13 +++++++------ include/hw/i386/pc.h | 2 ++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 52aea4a652..b0d58515dd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2312,7 +2312,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, if (!cpu_slot) { MachineState *ms = MACHINE(pcms); - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -2333,7 +2333,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id:" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_ids.pkg_id); @@ -2681,6 +2681,7 @@ static void pc_machine_initfn(Object *obj) /* Initialize the apic id related handlers */ pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; + pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid; pc_system_flash_create(pcms); } @@ -2730,8 +2731,8 @@ static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) initialize_topo_info(&topo_info, pcms, ms); assert(idx < ms->possible_cpus->len); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, + &topo_info, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } @@ -2763,8 +2764,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].type = ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count = 1; ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - &topo_info, &topo_ids); + pcms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, + &topo_info, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id = true; ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id; if (pcms->smp_dies > 1) { diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 56aa0e45b5..ffc5c78164 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -71,6 +71,8 @@ struct PCMachineState { /* Apic id specific handlers */ uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, unsigned cpu_index); + void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info, + X86CPUTopoIDs *topo_ids); /* Address space used by IOAPIC device. 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Wed, 4 Dec 2019 00:38:41 +0000 Subject: [PATCH v3 15/18] hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:39 -0600 Message-ID: <157541991943.46157.2185735998555897830.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR05CA0016.namprd05.prod.outlook.com (2603:10b6:805:de::29) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: dbbd3145-a896-44b4-7fbe-08d778524f69 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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Initialize with correct handler based on the mode selected. Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids for consistency. x86_apicid_from_topo_ids will be the default handler. Signed-off-by: Babu Moger llc_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id = pcms->apicid_from_topo_ids(&topo_info, &topo_ids); } cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); @@ -2682,6 +2682,7 @@ static void pc_machine_initfn(Object *obj) /* Initialize the apic id related handlers */ pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx; pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid; + pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids; pc_system_flash_create(pcms); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ffc5c78164..0789f8b5ea 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -73,6 +73,8 @@ struct PCMachineState { unsigned cpu_index); void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids); + apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids); /* Address space used by IOAPIC device. All IOAPIC interrupts * will be translated to MSI messages in the address space. */ diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index adb92fe9ce..b2b9e93a06 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -206,7 +206,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info, * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, +static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | @@ -259,7 +259,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, { X86CPUTopoIDs topo_ids; x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); - return apicid_from_topo_ids(topo_info, &topo_ids); + return x86_apicid_from_topo_ids(topo_info, &topo_ids); } #endif /* HW_I386_TOPOLOGY_H */ From patchwork Wed Dec 4 00:38:46 2019 Content-Type: text/plain; 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Received: from DM5PR12MB2471.namprd12.prod.outlook.com (52.132.141.138) by DM5PR12MB1369.namprd12.prod.outlook.com (10.168.234.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.19; Wed, 4 Dec 2019 00:38:48 +0000 Received: from DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3]) by DM5PR12MB2471.namprd12.prod.outlook.com ([fe80::d0f5:b875:7b5c:46c3%6]) with mapi id 15.20.2495.014; Wed, 4 Dec 2019 00:38:48 +0000 Subject: [PATCH v3 16/18] hw/i386: Introduce EPYC mode function handlers From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:46 -0600 Message-ID: <157541992659.46157.18191224973398213624.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN4PR0501CA0002.namprd05.prod.outlook.com (2603:10b6:803:40::15) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 9accf511-0ec6-4d89-1f82-08d778525387 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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Signed-off-by: Babu Moger --- hw/i386/pc.c | 12 ++++++++++++ include/hw/i386/topology.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e6c8a458e7..64e3658873 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2819,6 +2819,17 @@ static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) return true; } +static void pc_init_apicid_fn(MachineState *ms) +{ + PCMachineState *pcms = PC_MACHINE(ms); + + if (!strncmp(ms->cpu_type, "EPYC", 4)) { + pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc; + pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc; + pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc; + } +} + static void pc_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -2847,6 +2858,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->cpu_index_to_instance_props = pc_cpu_index_to_props; mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; + mc->init_apicid_fn = pc_init_apicid_fn; mc->auto_enable_numa_with_memhp = true; mc->has_hotpluggable_cpus = true; mc->default_boot_order = "cad"; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index b2b9e93a06..f028d2332a 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -140,7 +140,7 @@ static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info) * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info, +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) | @@ -200,7 +200,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info, { X86CPUTopoIDs topo_ids; x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids); - return apicid_from_topo_ids_epyc(topo_info, &topo_ids); + return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids); } /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * From patchwork Wed Dec 4 00:38:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272009 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E29613A4 for ; Wed, 4 Dec 2019 01:01:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 424BF20656 for ; Wed, 4 Dec 2019 01:01:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="cOJiM2Sw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 424BF20656 Authentication-Results: mail.kernel.org; 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Wed, 4 Dec 2019 00:38:55 +0000 Subject: [PATCH v3 17/18] i386: Fix pkg_id offset for epyc mode From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:38:53 -0600 Message-ID: <157541993357.46157.16412514558085238325.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: ec901109-70c5-4bfb-c3cf-08d7785257a2 X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:534; 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CPUState *cs = env_cpu(env); - uint32_t die_offset; + uint32_t die_offset, pkg_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -4466,6 +4466,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, topo_info.cores_per_die = cs->nr_cores; topo_info.threads_per_core = cs->nr_threads; + if (env->family_type == CPUX86FAMILY_EPYC) + pkg_offset = apicid_pkg_offset_epyc(&topo_info); + else + pkg_offset = apicid_pkg_offset(&topo_info); + /* Calculate & apply limits for different index ranges */ if (index >= 0xC0000000) { limit = env->cpuid_xlevel2; @@ -4647,7 +4652,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax = apicid_pkg_offset(&topo_info); + *eax = pkg_offset; *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -4681,7 +4686,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax = apicid_pkg_offset(&topo_info); + *eax = pkg_offset; *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; break; From patchwork Wed Dec 4 00:39:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Babu Moger X-Patchwork-Id: 11272035 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BB4F109A for ; Wed, 4 Dec 2019 01:16:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5EBCE206E4 for ; Wed, 4 Dec 2019 01:16:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amdcloud.onmicrosoft.com header.i=@amdcloud.onmicrosoft.com header.b="ES0zCT4Y" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5EBCE206E4 Authentication-Results: mail.kernel.org; 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Wed, 4 Dec 2019 00:39:01 +0000 Subject: [PATCH v3 18/18] tests: Update the Unit tests From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, mst@redhat.com, pbonzini@redhat.com, rth@twiddle.net, eblake@redhat.com, armbru@redhat.com, imammedo@redhat.com Date: Tue, 03 Dec 2019 18:39:00 -0600 Message-ID: <157541994039.46157.2036450511065834532.stgit@naples-babu.amd.com> In-Reply-To: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> References: <157541968844.46157.17994918142533791313.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version X-ClientProxiedBy: SN6PR05CA0024.namprd05.prod.outlook.com (2603:10b6:805:de::37) To DM5PR12MB2471.namprd12.prod.outlook.com (2603:10b6:4:b5::10) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: e1c8fbe2-bb6f-4253-efc0-08d778525bad X-MS-TrafficTypeDiagnostic: DM5PR12MB1369:|DM5PR12MB1369: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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Signed-off-by: Babu Moger --- tests/test-x86-cpuid.c | 115 ++++++++++++++++++++++++++++-------------------- 1 file changed, 68 insertions(+), 47 deletions(-) diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c index 1942287f33..00553c1d77 100644 --- a/tests/test-x86-cpuid.c +++ b/tests/test-x86-cpuid.c @@ -28,79 +28,100 @@ static void test_topo_bits(void) { + X86CPUTopoInfo topo_info = {0}; + /* simple tests for 1 thread per core, 1 core per die, 1 die per package */ - g_assert_cmpuint(apicid_smt_width(1, 1, 1), ==, 0); - g_assert_cmpuint(apicid_core_width(1, 1, 1), ==, 0); - g_assert_cmpuint(apicid_die_width(1, 1, 1), ==, 0); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 1}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 0); + g_assert_cmpuint(apicid_core_width(&topo_info), ==, 0); + g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), ==, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), ==, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), ==, 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), ==, 3); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), ==, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), ==, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), ==, 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 3), ==, 3); /* Test field width calculation for multiple values */ - g_assert_cmpuint(apicid_smt_width(1, 1, 2), ==, 1); - g_assert_cmpuint(apicid_smt_width(1, 1, 3), ==, 2); - g_assert_cmpuint(apicid_smt_width(1, 1, 4), ==, 2); - - g_assert_cmpuint(apicid_smt_width(1, 1, 14), ==, 4); - g_assert_cmpuint(apicid_smt_width(1, 1, 15), ==, 4); - g_assert_cmpuint(apicid_smt_width(1, 1, 16), ==, 4); - g_assert_cmpuint(apicid_smt_width(1, 1, 17), ==, 5); - - - g_assert_cmpuint(apicid_core_width(1, 30, 2), ==, 5); - g_assert_cmpuint(apicid_core_width(1, 31, 2), ==, 5); - g_assert_cmpuint(apicid_core_width(1, 32, 2), ==, 5); - g_assert_cmpuint(apicid_core_width(1, 33, 2), ==, 6); - - g_assert_cmpuint(apicid_die_width(1, 30, 2), ==, 0); - g_assert_cmpuint(apicid_die_width(2, 30, 2), ==, 1); - g_assert_cmpuint(apicid_die_width(3, 30, 2), ==, 2); - g_assert_cmpuint(apicid_die_width(4, 30, 2), ==, 2); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 2}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 1); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 3}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 4}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2); + + topo_info = (X86CPUTopoInfo) {0, 1, 1, 14}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 4); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 15}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 4); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 16}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 4); + topo_info = (X86CPUTopoInfo) {0, 1, 1, 17}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 5); + + + topo_info = (X86CPUTopoInfo) {0, 1, 30, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5); + topo_info = (X86CPUTopoInfo) {0, 1, 31, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5); + topo_info = (X86CPUTopoInfo) {0, 1, 32, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), ==, 5); + topo_info = (X86CPUTopoInfo) {0, 1, 33, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), ==, 6); + + topo_info = (X86CPUTopoInfo) {0, 1, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0); + topo_info = (X86CPUTopoInfo) {0, 2, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), ==, 1); + topo_info = (X86CPUTopoInfo) {0, 3, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2); + topo_info = (X86CPUTopoInfo) {0, 4, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2); /* build a weird topology and see if IDs are calculated correctly */ /* This will use 2 bits for thread ID and 3 bits for core ID */ - g_assert_cmpuint(apicid_smt_width(1, 6, 3), ==, 2); - g_assert_cmpuint(apicid_core_offset(1, 6, 3), ==, 2); - g_assert_cmpuint(apicid_die_offset(1, 6, 3), ==, 5); - g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), ==, 5); - - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), ==, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), ==, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), ==, 2); - - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), ==, + topo_info = (X86CPUTopoInfo) {0, 1, 6, 3}; + g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2); + g_assert_cmpuint(apicid_core_offset(&topo_info), ==, 2); + g_assert_cmpuint(apicid_die_offset(&topo_info), ==, 5); + g_assert_cmpuint(apicid_pkg_offset(&topo_info), ==, 5); + + topo_info = (X86CPUTopoInfo) {0, 1, 6, 3}; + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), ==, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), ==, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), ==, 2); + + topo_info = (X86CPUTopoInfo) {0, 1, 6, 3}; + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), ==, (1 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), ==, (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 2), ==, (1 << 2) | 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 0), ==, (2 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 1), ==, (2 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 2), ==, (2 << 2) | 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 0), ==, (5 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 1), ==, (5 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), ==, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 2), ==, (5 << 2) | 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 6 * 3 + 0 * 3 + 0), ==, (1 << 5)); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 6 * 3 + 1 * 3 + 1), ==, (1 << 5) | (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 3 * 6 * 3 + 5 * 3 + 2), ==, (3 << 5) | (5 << 2) | 2); }