From patchwork Wed Dec 4 23:20:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11273745 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 75C27159A for ; Wed, 4 Dec 2019 23:22:32 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52007206DF for ; Wed, 4 Dec 2019 23:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="NkJEU/yt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52007206DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxB-00014o-Kq; Wed, 04 Dec 2019 23:21:05 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxA-00014j-CN for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 23:21:04 +0000 X-Inumbo-ID: bd766d10-16ec-11ea-aea8-bc764e2007e4 Received: from mail-qv1-xf43.google.com (unknown [2607:f8b0:4864:20::f43]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id bd766d10-16ec-11ea-aea8-bc764e2007e4; Wed, 04 Dec 2019 23:21:03 +0000 (UTC) Received: by mail-qv1-xf43.google.com with SMTP id p2so563205qvo.10 for ; Wed, 04 Dec 2019 15:21:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eby1Z/q7U+7Sxm/O/Jl7zP2rKdfik8y03EjcrV9rvuY=; b=NkJEU/yt/blJhAPAwm0//b+ZWq1n7s4JlJ6JP+qdBGuTQCQuHFZ8PMWe00iEhl9sXR D5h+fsIE0OGIVs9vXL4gpNLeOVHliEVsqZGstR3wOREMlUTyHMBjBqiiJN9XSmUHGnl9 E029DgxCUKX3rVs0qGMWaVjtplCdTxiZQYRP12zEURRSXHIzCN4n9ZW6ehybuzzr5UNJ Zl0SICIsfPNpjp6MCNV3XJOhgzPiqFDsK+MaqCJejfrOaTmcJDz3S6PSEcE5G1+/Jk4t F2m0xoYu1kjAU9N6m6iUSEwzBQ39xf3hLWime1T3P66/AhdOKcdyJZrg+K7Z5WCheUkf kIJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eby1Z/q7U+7Sxm/O/Jl7zP2rKdfik8y03EjcrV9rvuY=; b=KieLTo+P+EgPtEmQ3AQuVs//fgnxji4fBO6v9/HjGKrP0u1Jpw19emas77KRKyUzTH Xw8LY4ElICE/u8ruKh2oGBNZcGfDT4+w1rmUSV94buv9fAMGvi5CC+jYS2/9OoQjZXsx oMztXXtyDtzklHmlWhp+WbxlTbwen6uapND8T7V6qFfN9shHLEDCasnvtZYhHm/re8J1 QESidRmQq7ixE5PuvaiTetfBqLyZRckmwcBqN8vquaK1Uvb9yQxDvVCNGxZ09mIOlIIx TaJ+CcgYWE0BqXANwiZLfl9u0jB8gRTmfo9RJur/MJXTTQc9i4E3iIwW5S9ahh96SqUl tqiQ== X-Gm-Message-State: APjAAAVkwq7IqIpQ/YC4zaLwv6KgyV4WZohMz1NZ0MJbibkyv0fDoR5I n7IFnh8/97W/9TiU15Q7WA0seg== X-Google-Smtp-Source: APXvYqwCGhoOs0wEUWkqNpwRHUAKwjbY4ROZeLY1H9ddt2HeC0y/qK9F5ZFbRQ+FLH5XluAaaaKK8A== X-Received: by 2002:a0c:ef91:: with SMTP id w17mr5033755qvr.202.1575501663211; Wed, 04 Dec 2019 15:21:03 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:02 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:53 -0500 Message-Id: <20191204232058.2500117-2-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 1/6] arm/arm64/xen: hypercall.h add includes guards X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The arm and arm64 versions of hypercall.h are missing the include guards. This is needed because C inlines for privcmd_call are going to be added to the files. Also fix a comment. Signed-off-by: Pavel Tatashin --- arch/arm/include/asm/assembler.h | 2 +- arch/arm/include/asm/xen/hypercall.h | 4 ++++ arch/arm64/include/asm/xen/hypercall.h | 4 ++++ include/xen/arm/hypercall.h | 6 +++--- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 99929122dad7..8e9262a0f016 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -480,7 +480,7 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .macro uaccess_disable, tmp, isb=1 #ifdef CONFIG_CPU_SW_DOMAIN_PAN /* - * Whenever we re-enter userspace, the domains should always be + * Whenever we re-enter kernel, the domains should always be * set appropriately. */ mov \tmp, #DACR_UACCESS_DISABLE diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h index 3522cbaed316..c6882bba5284 100644 --- a/arch/arm/include/asm/xen/hypercall.h +++ b/arch/arm/include/asm/xen/hypercall.h @@ -1 +1,5 @@ +#ifndef _ASM_ARM_XEN_HYPERCALL_H +#define _ASM_ARM_XEN_HYPERCALL_H #include + +#endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/arch/arm64/include/asm/xen/hypercall.h b/arch/arm64/include/asm/xen/hypercall.h index 3522cbaed316..c3198f9ccd2e 100644 --- a/arch/arm64/include/asm/xen/hypercall.h +++ b/arch/arm64/include/asm/xen/hypercall.h @@ -1 +1,5 @@ +#ifndef _ASM_ARM64_XEN_HYPERCALL_H +#define _ASM_ARM64_XEN_HYPERCALL_H #include + +#endif /* _ASM_ARM64_XEN_HYPERCALL_H */ diff --git a/include/xen/arm/hypercall.h b/include/xen/arm/hypercall.h index b40485e54d80..babcc08af965 100644 --- a/include/xen/arm/hypercall.h +++ b/include/xen/arm/hypercall.h @@ -30,8 +30,8 @@ * IN THE SOFTWARE. */ -#ifndef _ASM_ARM_XEN_HYPERCALL_H -#define _ASM_ARM_XEN_HYPERCALL_H +#ifndef _ARM_XEN_HYPERCALL_H +#define _ARM_XEN_HYPERCALL_H #include @@ -88,4 +88,4 @@ MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req, BUG(); } -#endif /* _ASM_ARM_XEN_HYPERCALL_H */ +#endif /* _ARM_XEN_HYPERCALL_H */ From patchwork Wed Dec 4 23:20:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11273747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9689138D for ; Wed, 4 Dec 2019 23:22:32 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 961F8206DF for ; Wed, 4 Dec 2019 23:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="N4nfr8PE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 961F8206DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxL-00016A-Aq; Wed, 04 Dec 2019 23:21:15 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxK-000160-Bk for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 23:21:14 +0000 X-Inumbo-ID: be8aeed8-16ec-11ea-aea8-bc764e2007e4 Received: from mail-qk1-x742.google.com (unknown [2607:f8b0:4864:20::742]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id be8aeed8-16ec-11ea-aea8-bc764e2007e4; Wed, 04 Dec 2019 23:21:05 +0000 (UTC) Received: by mail-qk1-x742.google.com with SMTP id c124so1713919qkg.0 for ; Wed, 04 Dec 2019 15:21:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=smj6n8EMZwJiO9OcqZKdj+gFypq1fwZIXw8AeaUdZHE=; b=N4nfr8PE7rjna1sy2un2T8I/QbS/FDLXdrJdb0wzVkKCQ0Nj4dVx7WmOcfoTbe5Err pCFB4uRN8dThnvHaL9+mll+NSkYsl6VZv2Yd50MyOh3YqGpl02gUx8B4ygniHLmcS6pV WwaVWKjUa5ffxJzDu0ELYDn5CgGrFItaaLreOkNgU/KSp+i9Suyx3HVGq7XY4Ej0TjWJ Ef1KpevZtJDkH9/dlSJgvPDOft/cByij6ONlj8yl/Cwgbln3gj9DTaq7uPAXOC0aWu+O iJaLlmbn717MW1qDNHGc+DEKhEaHFO9VZhUoOdnlsN+wP70BOG79UXsp6UJt4CRy/Zd9 yz9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=smj6n8EMZwJiO9OcqZKdj+gFypq1fwZIXw8AeaUdZHE=; b=ioB0My81ai55L0vmmlibGeggMWgsuj4ZYpiJpjlgAzh2oQquw7h0yhtN8z6uLJQMgT EVfcs+G76baIHnizV3BycpygfVOf5UFJnK/8/LmQKPTjZMUreTgMP+ZOKjS8r0nAeNiu ZrYksRTMwy1sqfM5zAkCCXcSsf+j4MMWT/7xOxS/hkligpL9wR4tLUmXFgn3PVDBn/zO jiw+rzSBMViNkWT6GJPj5KvIjB3oZP70jhwwhZagRY8auqxRw6P7ZnzB0mWcIvj5UiMB rN+622s7tfeuG3mHl8PuI7TeoIxx986VUUUWdGO3h4yRFSz/vTmkviEU+L9gdJsDWd7u KuVA== X-Gm-Message-State: APjAAAUS0yhN6tp5oqG+4/ExdhlOTRvMUBIENLDRW+yfvJrjhXxHXkLs B3JcyHbHbNYFUTa8Eon+xXwNqg== X-Google-Smtp-Source: APXvYqxwjlWsEl+Nl33Swhk+ma+381+gPtq7UHPUaqWh/EAaKEnwlcNsIHolGzi5TlRApATztOnEyg== X-Received: by 2002:a37:a744:: with SMTP id q65mr5771564qke.228.1575501664918; Wed, 04 Dec 2019 15:21:04 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:04 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:54 -0500 Message-Id: <20191204232058.2500117-3-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 2/6] arm/arm64/xen: use C inlines for privcmd_call X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" privcmd_call requires to enable access to userspace for the duration of the hypercall. Currently, this is done via assembly macros. Change it to C inlines instead. Signed-off-by: Pavel Tatashin Acked-by: Stefano Stabellini Reviewed-by: Julien Grall --- arch/arm/include/asm/xen/hypercall.h | 6 ++++++ arch/arm/xen/enlighten.c | 2 +- arch/arm/xen/hypercall.S | 4 ++-- arch/arm64/include/asm/xen/hypercall.h | 24 ++++++++++++++++++++++++ arch/arm64/xen/hypercall.S | 19 ++----------------- include/xen/arm/hypercall.h | 6 +++--- 6 files changed, 38 insertions(+), 23 deletions(-) diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h index c6882bba5284..cac5bd9ef519 100644 --- a/arch/arm/include/asm/xen/hypercall.h +++ b/arch/arm/include/asm/xen/hypercall.h @@ -2,4 +2,10 @@ #define _ASM_ARM_XEN_HYPERCALL_H #include +static inline long privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5) +{ + return arch_privcmd_call(call, a1, a2, a3, a4, a5); +} #endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index dd6804a64f1a..e87280c6d25d 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -440,4 +440,4 @@ EXPORT_SYMBOL_GPL(HYPERVISOR_platform_op_raw); EXPORT_SYMBOL_GPL(HYPERVISOR_multicall); EXPORT_SYMBOL_GPL(HYPERVISOR_vm_assist); EXPORT_SYMBOL_GPL(HYPERVISOR_dm_op); -EXPORT_SYMBOL_GPL(privcmd_call); +EXPORT_SYMBOL_GPL(arch_privcmd_call); diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S index b11bba542fac..277078c7da49 100644 --- a/arch/arm/xen/hypercall.S +++ b/arch/arm/xen/hypercall.S @@ -94,7 +94,7 @@ HYPERCALL2(multicall); HYPERCALL2(vm_assist); HYPERCALL3(dm_op); -ENTRY(privcmd_call) +ENTRY(arch_privcmd_call) stmdb sp!, {r4} mov r12, r0 mov r0, r1 @@ -119,4 +119,4 @@ ENTRY(privcmd_call) ldm sp!, {r4} ret lr -ENDPROC(privcmd_call); +ENDPROC(arch_privcmd_call); diff --git a/arch/arm64/include/asm/xen/hypercall.h b/arch/arm64/include/asm/xen/hypercall.h index c3198f9ccd2e..1a74fb28607f 100644 --- a/arch/arm64/include/asm/xen/hypercall.h +++ b/arch/arm64/include/asm/xen/hypercall.h @@ -1,5 +1,29 @@ #ifndef _ASM_ARM64_XEN_HYPERCALL_H #define _ASM_ARM64_XEN_HYPERCALL_H #include +#include +static inline long privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5) +{ + long rv; + + /* + * Privcmd calls are issued by the userspace. The kernel needs to + * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 + * translations to user memory via AT instructions. Since AT + * instructions are not affected by the PAN bit (ARMv8.1), we only + * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation + * is enabled (it implies that hardware UAO and PAN disabled). + */ + uaccess_ttbr0_enable(); + rv = arch_privcmd_call(call, a1, a2, a3, a4, a5); + /* + * Disable userspace access from kernel once the hyp call completed. + */ + uaccess_ttbr0_disable(); + + return rv; +} #endif /* _ASM_ARM64_XEN_HYPERCALL_H */ diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index c5f05c4a4d00..921611778d2a 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -49,7 +49,6 @@ #include #include -#include #include @@ -86,27 +85,13 @@ HYPERCALL2(multicall); HYPERCALL2(vm_assist); HYPERCALL3(dm_op); -ENTRY(privcmd_call) +ENTRY(arch_privcmd_call) mov x16, x0 mov x0, x1 mov x1, x2 mov x2, x3 mov x3, x4 mov x4, x5 - /* - * Privcmd calls are issued by the userspace. The kernel needs to - * enable access to TTBR0_EL1 as the hypervisor would issue stage 1 - * translations to user memory via AT instructions. Since AT - * instructions are not affected by the PAN bit (ARMv8.1), we only - * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation - * is enabled (it implies that hardware UAO and PAN disabled). - */ - uaccess_ttbr0_enable x6, x7, x8 hvc XEN_IMM - - /* - * Disable userspace access from kernel once the hyp call completed. - */ - uaccess_ttbr0_disable x6, x7 ret -ENDPROC(privcmd_call); +ENDPROC(arch_privcmd_call); diff --git a/include/xen/arm/hypercall.h b/include/xen/arm/hypercall.h index babcc08af965..624c8ad7e42a 100644 --- a/include/xen/arm/hypercall.h +++ b/include/xen/arm/hypercall.h @@ -41,9 +41,9 @@ struct xen_dm_op_buf; -long privcmd_call(unsigned call, unsigned long a1, - unsigned long a2, unsigned long a3, - unsigned long a4, unsigned long a5); +long arch_privcmd_call(unsigned int call, unsigned long a1, + unsigned long a2, unsigned long a3, + unsigned long a4, unsigned long a5); int HYPERVISOR_xen_version(int cmd, void *arg); int HYPERVISOR_console_io(int cmd, int count, char *str); int HYPERVISOR_grant_table_op(unsigned int cmd, void *uop, unsigned int count); From patchwork Wed Dec 4 23:20:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11273751 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74ACA138D for ; Wed, 4 Dec 2019 23:22:33 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 50EB8206DF for ; Wed, 4 Dec 2019 23:22:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="fKNAmmzI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 50EB8206DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxQ-00017G-KD; Wed, 04 Dec 2019 23:21:20 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxP-00016y-BI for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 23:21:19 +0000 X-Inumbo-ID: bf9c20da-16ec-11ea-aea8-bc764e2007e4 Received: from mail-qt1-x844.google.com (unknown [2607:f8b0:4864:20::844]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id bf9c20da-16ec-11ea-aea8-bc764e2007e4; Wed, 04 Dec 2019 23:21:07 +0000 (UTC) Received: by mail-qt1-x844.google.com with SMTP id q8so1559162qtr.10 for ; Wed, 04 Dec 2019 15:21:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0RbtzKmo7zfuXDWfdHWu8S+RDp64jOvNIHTxCP2zpR0=; b=fKNAmmzITxBQfPXz7RiuSqDCTIOORLjqiebWygrTmb5GDTbu93eab5NdPlECyOpMU1 bQycVBBiTsagRqQDAGCHalnDsreTbhq9OWqSwczPtC0iabVeXCIWyNwd0zY5A6fpBGtw BKN9bogl0ZI2CpWCScOwSItvhV47o5YyeNqB95okJJ/07WqsxwdFQnmqfF0aEoQmNRGW G9oIP64Vb03Kc2uzWTDE43+VAdjamyPxWnLdmYP2P3SJ7BpquFgkFhH7kjELqP6DG1Ul Wta7gGcIqNYLhwCSGgM42gICune/wyBO6yMOLDUu6z+3PLXyyW4zCU2Z0Qz1OZkITWeg 6Y6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0RbtzKmo7zfuXDWfdHWu8S+RDp64jOvNIHTxCP2zpR0=; b=Ll6ns7pHk1FEAfFoQC1Il9AdO+xYzqQijzGf1AzulOiVd306pNiqVF66Vb+9T7fW8h VFcYjE0LQYm4Gp1IWov4cbZFWHJPQYy1tx2tmkdugTlTOfCo3vnL/FIZk5uAJeg1Ns1f YsQHbKFenvLcfjEm+V4ai4wPa5rcYTUyusPns3vfUQvRVrtp+D5CsO42o0UM+J5YJZfO 9tft7GzfpKEajYPXm5AwP4waRw7iDxBejhnN2rJiwnhue/jxPKfAJkT4GxNnPfTj/jnm obcJwA46zC6oq4x2Xjh2XW6Y3e662trtnfTW8qLhQ8rRT4ltxkrOmWlgfv8svr7Cm4iV X8ZQ== X-Gm-Message-State: APjAAAVl5YqBU37Un48YbORTmiUi5Scbt/urpatIoJgEG0Sa4K47hBam JZFeJ7HzYRdFCgIHcd+ZtmWK8Q== X-Google-Smtp-Source: APXvYqwGVxtioWa6fg8PFhgdMLvrQWhtfXdKPWJtuq4IqRERiBvIOMKkvDiPshqepZ26wP88iuia0w== X-Received: by 2002:aed:31a2:: with SMTP id 31mr4461846qth.196.1575501666754; Wed, 04 Dec 2019 15:21:06 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:06 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:55 -0500 Message-Id: <20191204232058.2500117-4-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" We currently duplicate the logic to enable/disable uaccess via TTBR0, with C functions and assembly macros. This is a maintenenace burden and is liable to lead to subtle bugs, so let's get rid of the assembly macros, and always use the C functions. This requires refactoring some assembly functions to have a C wrapper. Signed-off-by: Pavel Tatashin Reported-by: kbuild test robot --- arch/arm64/include/asm/asm-uaccess.h | 22 ----------------- arch/arm64/include/asm/cacheflush.h | 35 ++++++++++++++++++++++++--- arch/arm64/mm/cache.S | 36 ++++++++++------------------ arch/arm64/mm/flush.c | 2 +- 4 files changed, 46 insertions(+), 49 deletions(-) diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h index f68a0e64482a..fba2a69f7fef 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -34,28 +34,6 @@ msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 isb .endm - - .macro uaccess_ttbr0_disable, tmp1, tmp2 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp2 // avoid preemption - __uaccess_ttbr0_disable \tmp1 - restore_irq \tmp2 -alternative_else_nop_endif - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 -alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp3 // avoid preemption - __uaccess_ttbr0_enable \tmp1, \tmp2 - restore_irq \tmp3 -alternative_else_nop_endif - .endm -#else - .macro uaccess_ttbr0_disable, tmp1, tmp2 - .endm - - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 - .endm #endif #endif diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 665c78e0665a..431f8da2dd02 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,16 +61,45 @@ * - kaddr - page address * - size - region size */ -extern void __flush_icache_range(unsigned long start, unsigned long end); -extern int invalidate_icache_range(unsigned long start, unsigned long end); +extern void __asm_flush_icache_range(unsigned long start, unsigned long end); +extern long __asm_flush_cache_user_range(unsigned long start, + unsigned long end); +extern int __asm_invalidate_icache_range(unsigned long start, + unsigned long end); extern void __flush_dcache_area(void *addr, size_t len); extern void __inval_dcache_area(void *addr, size_t len); extern void __clean_dcache_area_poc(void *addr, size_t len); extern void __clean_dcache_area_pop(void *addr, size_t len); extern void __clean_dcache_area_pou(void *addr, size_t len); -extern long __flush_cache_user_range(unsigned long start, unsigned long end); extern void sync_icache_aliases(void *kaddr, unsigned long len); +static inline void __flush_cache_user_range(unsigned long start, + unsigned long end) +{ + uaccess_ttbr0_enable(); + __asm_flush_cache_user_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline void __flush_icache_range(unsigned long start, unsigned long end) +{ + uaccess_ttbr0_enable(); + __asm_flush_icache_range(start, end); + uaccess_ttbr0_disable(); +} + +static inline int invalidate_icache_range(unsigned long start, + unsigned long end) +{ + int ret; + + uaccess_ttbr0_enable(); + ret = __asm_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); + + return ret; +} + static inline void flush_icache_range(unsigned long start, unsigned long end) { __flush_icache_range(start, end); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index db767b072601..602b9aa8603a 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -15,7 +15,7 @@ #include /* - * flush_icache_range(start,end) + * __asm_flush_icache_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -24,11 +24,11 @@ * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_icache_range) +ENTRY(__asm_flush_icache_range) /* FALLTHROUGH */ /* - * __flush_cache_user_range(start,end) + * __asm_flush_cache_user_range(start,end) * * Ensure that the I and D caches are coherent within specified region. * This is typically used when code has been written to a memory region, @@ -37,8 +37,7 @@ ENTRY(__flush_icache_range) * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(__flush_cache_user_range) - uaccess_ttbr0_enable x2, x3, x4 +ENTRY(__asm_flush_cache_user_range) alternative_if ARM64_HAS_CACHE_IDC dsb ishst b 7f @@ -60,41 +59,32 @@ alternative_if ARM64_HAS_CACHE_DIC alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 9f 8: mov x0, #0 -1: - uaccess_ttbr0_disable x1, x2 - ret -9: - mov x0, #-EFAULT +1: ret +9: mov x0, #-EFAULT b 1b -ENDPROC(__flush_icache_range) -ENDPROC(__flush_cache_user_range) +ENDPROC(__asm_flush_icache_range) +ENDPROC(__asm_flush_cache_user_range) /* - * invalidate_icache_range(start,end) + * __asm_invalidate_icache_range(start,end) * * Ensure that the I cache is invalid within specified region. * * - start - virtual start address of region * - end - virtual end address of region */ -ENTRY(invalidate_icache_range) +ENTRY(__asm_invalidate_icache_range) alternative_if ARM64_HAS_CACHE_DIC mov x0, xzr isb ret alternative_else_nop_endif - - uaccess_ttbr0_enable x2, x3, x4 - invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr -1: - uaccess_ttbr0_disable x1, x2 - ret -2: - mov x0, #-EFAULT +1: ret +2: mov x0, #-EFAULT b 1b -ENDPROC(invalidate_icache_range) +ENDPROC(__asm_invalidate_icache_range) /* * __flush_dcache_area(kaddr, size) diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index ac485163a4a7..b23f34d23f31 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__flush_icache_range); +EXPORT_SYMBOL(__asm_flush_icache_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) From patchwork Wed Dec 4 23:20:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11273741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED24E138D for ; Wed, 4 Dec 2019 23:22:30 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C83AA2073C for ; Wed, 4 Dec 2019 23:22:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="Cqr2IaSk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C83AA2073C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxV-00018u-Ty; Wed, 04 Dec 2019 23:21:25 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxU-00018O-Bf for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 23:21:24 +0000 X-Inumbo-ID: c0956e24-16ec-11ea-9c09-bc764e2007e4 Received: from mail-qk1-x742.google.com (unknown [2607:f8b0:4864:20::742]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id c0956e24-16ec-11ea-9c09-bc764e2007e4; Wed, 04 Dec 2019 23:21:08 +0000 (UTC) Received: by mail-qk1-x742.google.com with SMTP id d124so1665286qke.6 for ; Wed, 04 Dec 2019 15:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cJGBuyv8MEIEHzLn/Uzof9JuYF+NT8m3hWWPuvSYlYo=; b=Cqr2IaSkSM3+ylTz/1+aa0wyv0GTLmyzuvfeKqJdPU6Ym61dE8ilpQ/o6O3zLo76yG yWs4zxmVduoS9thvdX42Qhy/yXxpxLqmowjGfyNWNr2CrS0btzvUZX1xjS5/NQKuKc9m 09+5SGckvzu6mOOsgNPtOpMxLWPdDl8+PqcmsBcfflKtmm4meriKJKjLOG29yS1QWciV 0Wcks1MLbJb1W3cxbNWfbO8w7CCl3rfq/IVgDaUT9y3uk+unlYn3uMSIPYga04jFVfkX ZrVptH6pK0eqeK+rnhBPLi9SvwE1cFLa6IaeQSpSBwJircBHJEjEs6Y3XEWblHYg0XxR IQmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cJGBuyv8MEIEHzLn/Uzof9JuYF+NT8m3hWWPuvSYlYo=; b=gVHRdP689vA8B/2+RNm3EgiNvGovxB2ik0PJ3ks78n2Rb4wRxNBb/KWWG7UOcrwMzv KZGSLRmNv6C6HVTIHf0RG2IqMyAJch1N+dMw/7LFiAaEeEiC6Z1DiUfwggSmxKnXiFnS J/h7OsUhxVXifoJXLgm8KmYlhJ5T5C5/AC6cvsa2cpy62jaKZuH090a9YdWCN5+wqbSl ZwEqHCeabuMkQsj9AmRNMJgdCjRSr9m4EupfBnGWE/HHhSqMqMuxLZZll/SG2s78u2ZR MEZsfvMsyeIdhdPU83HS3Ff9l4xhNLgDZieS58l9GuwbNKxWWeUCd1zoOnjO12ooD1SF M6Jw== X-Gm-Message-State: APjAAAXQMewsQOnat4TBt40Hn5pnVxIxxj4eCN4xvgUB2cP7LVXa9yoX 0574yei03vX15eZaSDhoPHChrg== X-Google-Smtp-Source: APXvYqyIMm2ogNBIfOvl3Mqg4T1YApxStKZp5KMJvJR//w2WVxMty/nhPiOLBe4oOlxwY24OIF3FHA== X-Received: by 2002:ae9:e115:: with SMTP id g21mr53454qkm.187.1575501668421; Wed, 04 Dec 2019 15:21:08 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:07 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:56 -0500 Message-Id: <20191204232058.2500117-5-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 4/6] arm64: remove __asm_flush_icache_range X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" __asm_flush_icache_range is an alias to __asm_flush_cache_user_range, but now that these functions are called from C wrappers the fall through can instead be done at a higher level. Remove the __asm_flush_icache_range alias in assembly, and instead call __flush_cache_user_range() from __flush_icache_range(). Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/cacheflush.h | 5 +---- arch/arm64/mm/cache.S | 14 -------------- arch/arm64/mm/flush.c | 2 +- 3 files changed, 2 insertions(+), 19 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 431f8da2dd02..ea563344b4ad 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -61,7 +61,6 @@ * - kaddr - page address * - size - region size */ -extern void __asm_flush_icache_range(unsigned long start, unsigned long end); extern long __asm_flush_cache_user_range(unsigned long start, unsigned long end); extern int __asm_invalidate_icache_range(unsigned long start, @@ -83,9 +82,7 @@ static inline void __flush_cache_user_range(unsigned long start, static inline void __flush_icache_range(unsigned long start, unsigned long end) { - uaccess_ttbr0_enable(); - __asm_flush_icache_range(start, end); - uaccess_ttbr0_disable(); + __flush_cache_user_range(start, end); } static inline int invalidate_icache_range(unsigned long start, diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 602b9aa8603a..1981cbaf5d92 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -14,19 +14,6 @@ #include #include -/* - * __asm_flush_icache_range(start,end) - * - * Ensure that the I and D caches are coherent within specified region. - * This is typically used when code has been written to a memory region, - * and will be executed. - * - * - start - virtual start address of region - * - end - virtual end address of region - */ -ENTRY(__asm_flush_icache_range) - /* FALLTHROUGH */ - /* * __asm_flush_cache_user_range(start,end) * @@ -62,7 +49,6 @@ alternative_else_nop_endif 1: ret 9: mov x0, #-EFAULT b 1b -ENDPROC(__asm_flush_icache_range) ENDPROC(__asm_flush_cache_user_range) /* diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index b23f34d23f31..61521285f27d 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -75,7 +75,7 @@ EXPORT_SYMBOL(flush_dcache_page); /* * Additional functions defined in assembly. */ -EXPORT_SYMBOL(__asm_flush_icache_range); +EXPORT_SYMBOL(__asm_flush_cache_user_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) From patchwork Wed Dec 4 23:20:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11273743 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD19F138D for ; Wed, 4 Dec 2019 23:22:31 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B98A6206DF for ; Wed, 4 Dec 2019 23:22:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="GnME/3GQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B98A6206DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxa-0001BW-AR; Wed, 04 Dec 2019 23:21:30 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxZ-0001B3-C2 for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 23:21:29 +0000 X-Inumbo-ID: c1a07d22-16ec-11ea-aea8-bc764e2007e4 Received: from mail-qk1-x743.google.com (unknown [2607:f8b0:4864:20::743]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id c1a07d22-16ec-11ea-aea8-bc764e2007e4; Wed, 04 Dec 2019 23:21:10 +0000 (UTC) Received: by mail-qk1-x743.google.com with SMTP id x1so1625405qkl.12 for ; Wed, 04 Dec 2019 15:21:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jgWMYHD023tAXPY9yBvY7HlxUi3NtG7yB+YFJsFM+4s=; b=GnME/3GQIkWEOnq+HnWtjzDW7KOeACVPsdHQBWSmyQiiOW1JrEqbNdO1yXHOHEGGLa uiDQATmlJ+LFhPgQXv8Zf0F4NJElVwhSGKvmCcAUMQv+wEkB+XJDpMyg6iSNtxNh7VMy 4YRsLqt/0+myzBWoF8xlK6sHJAEmEPWcOsskDtof8qDxEGxli6obH0/ql8HXvOYyNOx0 E4CqVF/g/r8Y9BXPjdTCfVR8SCXfFoQnrtKWfB6fqzn7mEoF7LZSIahhhG8TlbwvWdi0 eV1TWGsF+FoGohnl0fwH163lctm1VQfxvAxKHjBKsqfJP8bqMssseBKgpDoDEsAqYzvT ACgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jgWMYHD023tAXPY9yBvY7HlxUi3NtG7yB+YFJsFM+4s=; b=OyIfgJYauUL2HigduwTsnkA7ATKr/Ta+CcZSp/L481yu/w2doFEviF+zzzzgUCiVWg hqWM9M6PEqtXYAVaBpoxIyuSqy1/Xkh5pmmv3cv7IGOQissOZqhMMqUdIHWmBGZXyc5I IZodEJ7H4UAgLCI4WwjuAQPxua+MrEs9tsBI1GUz+7YwLd0Cd7dCSs648rJQCzjaBb8z j6LnWLo3b4+IPmFXrCaWqmjsnhIu3aeP2NXf/stTHhCJB2M9F6M6HWTmjG5Bh7uLJ4mC XIxyIplgp2KBN5lwtWoE2Vsj7QDyGpr9rsSQdXz1tUPj4ZgzyAph9E7o3WhbxOEl2J0X Slmw== X-Gm-Message-State: APjAAAVMrE5UR+QgTWpvEQvpj3agGk58MshIk5YPeV8s2bqMTEyLMdoc ztBc529Xpd6v3XjklxUvCU6SvA== X-Google-Smtp-Source: APXvYqxYW3lHiAaEktvIv9R2Rs4Q7wh7u41fkOvqH028QUBhjHchCrv3OL1EskvJ6xR8p1wI4qmnmw== X-Received: by 2002:a05:620a:102e:: with SMTP id a14mr5398925qkk.159.1575501670158; Wed, 04 Dec 2019 15:21:10 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:09 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:57 -0500 Message-Id: <20191204232058.2500117-6-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The assmbly functions __asm_flush_cache_user_range and __asm_invalidate_icache_range have alternatives: alternative_if ARM64_HAS_CACHE_DIC ... alternative_if ARM64_HAS_CACHE_IDC ... But, the implementation of those alternatives is trivial and therefore can be done in the C inline wrappers. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/cacheflush.h | 19 +++++++++++++++++++ arch/arm64/mm/cache.S | 27 +++++---------------------- arch/arm64/mm/flush.c | 1 + 3 files changed, 25 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index ea563344b4ad..4eb244ee7154 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -75,8 +75,22 @@ extern void sync_icache_aliases(void *kaddr, unsigned long len); static inline void __flush_cache_user_range(unsigned long start, unsigned long end) { + if (cpus_have_const_cap(ARM64_HAS_CACHE_IDC)) { + dsb(ishst); + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { + isb(); + return; + } + } + uaccess_ttbr0_enable(); __asm_flush_cache_user_range(start, end); + + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) + isb(); + else + __asm_invalidate_icache_range(start, end); + uaccess_ttbr0_disable(); } @@ -90,6 +104,11 @@ static inline int invalidate_icache_range(unsigned long start, { int ret; + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { + isb(); + return 0; + } + uaccess_ttbr0_enable(); ret = __asm_invalidate_icache_range(start, end); uaccess_ttbr0_disable(); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 1981cbaf5d92..0093bb9fcd12 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -25,30 +25,18 @@ * - end - virtual end address of region */ ENTRY(__asm_flush_cache_user_range) -alternative_if ARM64_HAS_CACHE_IDC - dsb ishst - b 7f -alternative_else_nop_endif dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 -1: -user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE +1: user_alt 3f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE add x4, x4, x2 cmp x4, x1 b.lo 1b dsb ish - -7: -alternative_if ARM64_HAS_CACHE_DIC - isb - b 8f -alternative_else_nop_endif - invalidate_icache_by_line x0, x1, x2, x3, 9f -8: mov x0, #0 -1: ret -9: mov x0, #-EFAULT - b 1b + mov x0, #0 +2: ret +3: mov x0, #-EFAULT + b 2b ENDPROC(__asm_flush_cache_user_range) /* @@ -60,11 +48,6 @@ ENDPROC(__asm_flush_cache_user_range) * - end - virtual end address of region */ ENTRY(__asm_invalidate_icache_range) -alternative_if ARM64_HAS_CACHE_DIC - mov x0, xzr - isb - ret -alternative_else_nop_endif invalidate_icache_by_line x0, x1, x2, x3, 2f mov x0, xzr 1: ret diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index 61521285f27d..adfdacb163ad 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -76,6 +76,7 @@ EXPORT_SYMBOL(flush_dcache_page); * Additional functions defined in assembly. */ EXPORT_SYMBOL(__asm_flush_cache_user_range); +EXPORT_SYMBOL(__asm_invalidate_icache_range); #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size) From patchwork Wed Dec 4 23:20:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pasha Tatashin X-Patchwork-Id: 11273749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 080FF186D for ; Wed, 4 Dec 2019 23:22:33 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D8DFA206DF for ; Wed, 4 Dec 2019 23:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=soleen.com header.i=@soleen.com header.b="i1g8jJxL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D8DFA206DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=soleen.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxf-0001EO-Kk; Wed, 04 Dec 2019 23:21:35 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1icdxe-0001Dj-Cp for xen-devel@lists.xenproject.org; Wed, 04 Dec 2019 23:21:34 +0000 X-Inumbo-ID: c2b2074e-16ec-11ea-a0d2-bc764e2007e4 Received: from mail-qk1-x743.google.com (unknown [2607:f8b0:4864:20::743]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id c2b2074e-16ec-11ea-a0d2-bc764e2007e4; Wed, 04 Dec 2019 23:21:12 +0000 (UTC) Received: by mail-qk1-x743.google.com with SMTP id a10so1643975qko.9 for ; Wed, 04 Dec 2019 15:21:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=soleen.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZHIYboDwl4EWd97Tklkdkm+url9a5Lp8rxT6bERrC+M=; b=i1g8jJxL0yaISsSkQcVG1T+YRVLPQorkORTVckOF1ul4UmdgjxetevbONnxu7GHHR6 WXK96ycRVB4k6ym6P0dlJ6VstgCOx1UZBEAX/OKcv1s2MPsWxgrk5CYfyx4cV6pd9Bw5 jUsEz55BdSZdY6HhBAwTU4pjFn1ewPD8PlkxMk6lZhxQkCzDxJaV1DXZuXgeL6O172ce zJ2PNOb2JKEKgzLuvO8xUfDa7vPnEm7mX+/dOykrVC8c2EX4Wux0z26m27bI2YNOPLNh oAQa/+PV4LAQAqd/k1eK3LpIC4vlgv+RQN+BcKlhvKmUX7V+YJHfxJL87xtqtSABCsrW 1OWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZHIYboDwl4EWd97Tklkdkm+url9a5Lp8rxT6bERrC+M=; b=qFzC1XnrJH6yf/FNiIbEBHcNMB0duuqTP9+jdOylebQHL1DVVofTOCxZtwTOh+Fv/P bEN0Z7atkMfpCerNZ9oX26FpRziV+Yzq492Sd6noyOMnGUTFyp+BhnORWo4+DIRZTKsH ze3im3GuC9wPuor3XdalsFDMfn1ult9IDAuUxhPviz5Arg6B9NUozygRSD5Cnyqlp1GN 5AHk2hL24Omkeqr3NdKuMoFtEP5Tk90o4B2bGOCBf+bIc0p6uZFqabYkIYm579Tb43kA c5N6vX6hmizn8IHlxLgmoDeNsAIczFwWs0JX6gMHjxb3rmsrk7SPT6pf4aE1FD7v71c6 gWGQ== X-Gm-Message-State: APjAAAVBFM6lJrVTF69U/rVA16aXk98v25uVWfwrhmfjX0vy/m1TMBRo XBMzYAqtsqUixwLsY4hnGD6Z/g== X-Google-Smtp-Source: APXvYqyth5Vky9Sws+q1XOgIKaCf88qENA0eXdBaqBMhh1L+UlvBd0q1SnZjvczRgcyocJAH0Tk8+g== X-Received: by 2002:a37:6691:: with SMTP id a139mr5530912qkc.393.1575501671951; Wed, 04 Dec 2019 15:21:11 -0800 (PST) Received: from localhost.localdomain (c-73-69-118-222.hsd1.nh.comcast.net. [73.69.118.222]) by smtp.gmail.com with ESMTPSA id t38sm4667864qta.78.2019.12.04.15.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Dec 2019 15:21:11 -0800 (PST) From: Pavel Tatashin To: pasha.tatashin@soleen.com, jmorris@namei.org, sashal@kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, steve.capper@arm.com, linux-arm-kernel@lists.infradead.org, maz@kernel.org, james.morse@arm.com, vladimir.murzin@arm.com, mark.rutland@arm.com, tglx@linutronix.de, gregkh@linuxfoundation.org, allison@lohutok.net, info@metux.net, alexios.zavras@intel.com, sstabellini@kernel.org, boris.ostrovsky@oracle.com, jgross@suse.com, stefan@agner.ch, yamada.masahiro@socionext.com, xen-devel@lists.xenproject.org, linux@armlinux.org.uk, andrew.cooper3@citrix.com, julien@xen.org Date: Wed, 4 Dec 2019 18:20:58 -0500 Message-Id: <20191204232058.2500117-7-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191204232058.2500117-1-pasha.tatashin@soleen.com> References: <20191204232058.2500117-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 Subject: [Xen-devel] [PATCH v4 6/6] arm64: remove the rest of asm-uaccess.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The __uaccess_ttbr0_disable and __uaccess_ttbr0_enable, are the last two macros defined in asm-uaccess.h. For now move them to entry.S where they are used. Eventually, these macros should be replaced with C wrappers to reduce the maintenance burden. Also, once these macros are unified with the C counterparts, it is a good idea to check that PAN is in correct state on every enable/disable calls. Signed-off-by: Pavel Tatashin --- arch/arm64/include/asm/asm-uaccess.h | 39 ---------------------------- arch/arm64/kernel/entry.S | 27 ++++++++++++++++++- arch/arm64/lib/clear_user.S | 2 +- arch/arm64/lib/copy_from_user.S | 2 +- arch/arm64/lib/copy_in_user.S | 2 +- arch/arm64/lib/copy_to_user.S | 2 +- arch/arm64/mm/cache.S | 1 - 7 files changed, 30 insertions(+), 45 deletions(-) delete mode 100644 arch/arm64/include/asm/asm-uaccess.h diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h deleted file mode 100644 index fba2a69f7fef..000000000000 --- a/arch/arm64/include/asm/asm-uaccess.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ASM_UACCESS_H -#define __ASM_ASM_UACCESS_H - -#include -#include -#include -#include -#include - -/* - * User access enabling/disabling macros. - */ -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - .macro __uaccess_ttbr0_disable, tmp1 - mrs \tmp1, ttbr1_el1 // swapper_pg_dir - bic \tmp1, \tmp1, #TTBR_ASID_MASK - sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir - msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 - isb - add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE - msr ttbr1_el1, \tmp1 // set reserved ASID - isb - .endm - - .macro __uaccess_ttbr0_enable, tmp1, tmp2 - get_current_task \tmp1 - ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - mrs \tmp2, ttbr1_el1 - extr \tmp2, \tmp2, \tmp1, #48 - ror \tmp2, \tmp2, #16 - msr ttbr1_el1, \tmp2 // set the active ASID - isb - msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 - isb - .endm -#endif - -#endif diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 583f71abbe98..446d90ab31af 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -22,8 +22,8 @@ #include #include #include +#include #include -#include #include /* @@ -143,6 +143,31 @@ alternative_cb_end #endif .endm +#ifdef CONFIG_ARM64_SW_TTBR0_PAN + .macro __uaccess_ttbr0_disable, tmp1 + mrs \tmp1, ttbr1_el1 // swapper_pg_dir + bic \tmp1, \tmp1, #TTBR_ASID_MASK + sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir + msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 + isb + add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE + msr ttbr1_el1, \tmp1 // set reserved ASID + isb + .endm + + .macro __uaccess_ttbr0_enable, tmp1, tmp2 + get_current_task \tmp1 + ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 + mrs \tmp2, ttbr1_el1 + extr \tmp2, \tmp2, \tmp1, #48 + ror \tmp2, \tmp2, #16 + msr ttbr1_el1, \tmp2 // set the active ASID + isb + msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 + isb + .endm +#endif + .macro kernel_entry, el, regsize = 64 .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index aeafc03e961a..b0b4a86a09e2 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -6,7 +6,7 @@ */ #include -#include +#include #include .text diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index ebb3c06cbb5d..142bc7505518 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -5,7 +5,7 @@ #include -#include +#include #include #include diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 3d8153a1ebce..04dc48ca26f7 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -7,7 +7,7 @@ #include -#include +#include #include #include diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 357eae2c18eb..8f3218ae88ab 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -5,7 +5,7 @@ #include -#include +#include #include #include diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 0093bb9fcd12..627be857b8d0 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -12,7 +12,6 @@ #include #include #include -#include /* * __asm_flush_cache_user_range(start,end)