From patchwork Fri Dec 6 12:17:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qianggui Song X-Patchwork-Id: 11276051 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C998930 for ; Fri, 6 Dec 2019 12:17:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EBB2E24675 for ; Fri, 6 Dec 2019 12:17:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LtmjtbwU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EBB2E24675 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/eK/LWNdR3POXSf8PQRN4IZm53yjK8sYm/fGucf92JI=; b=LtmjtbwUNWlZbi sOyfu+gw7aoe6ZbDDvkYJfZb8l8zRoiZeY6cJb+kmzQqgjKV2fyE7UaVF0j6D/bdWE1HN+GuNgpj5 onTTjGAidxqqmpd87oo9av2HiEZ1cDASKB7CA0mtnRqHDwIx+5B2DxBcHoifgQQgw7dTM5b3Pm/4c hfcNp+3kMtPyd+jkA6GLbmLWojlI/mhy/Sl2OuItRf+Xlb320K8EtbyNApIbTh5EzIOHYT6lSCiYv I8yM8PTVr62trd5+gQUsVG1P9Tet3DMBcZ5PbNOGg8KEJshb3M1GeAzpn+z7ZyNVKWEJHlxDYcOmr YA2QW4twJ3c1ni31hvBQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1idCYG-0007wy-Az; Fri, 06 Dec 2019 12:17:40 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1idCY0-0007h2-V1; Fri, 06 Dec 2019 12:17:26 +0000 Received: from localhost.localdomain (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 6 Dec 2019 20:17:50 +0800 From: Qianggui Song To: Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 1/4] dt-bindings: interrupt-controller: New binding for Meson-A1 SoCs Date: Fri, 6 Dec 2019 20:17:10 +0800 Message-ID: <20191206121714.14579-2-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191206121714.14579-1-qianggui.song@amlogic.com> References: <20191206121714.14579-1-qianggui.song@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.19] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191206_041724_994892_6917307B X-CRM114-Status: UNSURE ( 6.79 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qianggui Song , devicetree@vger.kernel.org, Hanjie Lin , Jianxin Pan , Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Mark Rutland , Xingyu Chen , Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Update dt-binding document for GPIO interrupt controller of Meson-A1 SoCs Signed-off-by: Qianggui Song --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 684bb1cd75ec..23b18b92c558 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -17,6 +17,7 @@ Required properties: "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) + "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an From patchwork Fri Dec 6 12:17:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qianggui Song X-Patchwork-Id: 11276055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 028E6930 for ; Fri, 6 Dec 2019 12:17:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AEA1D24659 for ; Fri, 6 Dec 2019 12:17:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="d96YuI/5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AEA1D24659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; 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Fri, 06 Dec 2019 12:17:28 +0000 Received: from localhost.localdomain (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 6 Dec 2019 20:17:50 +0800 From: Qianggui Song To: Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 2/4] irqchip/meson-gpio: rework meson irqchip driver to support meson-A1 SoCs Date: Fri, 6 Dec 2019 20:17:11 +0800 Message-ID: <20191206121714.14579-3-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191206121714.14579-1-qianggui.song@amlogic.com> References: <20191206121714.14579-1-qianggui.song@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.19] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191206_041726_647580_DDB77855 X-CRM114-Status: GOOD ( 11.93 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qianggui Song , Hanjie Lin , Jianxin Pan , Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xingyu Chen , Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since Meson-A1 Socs register layout of gpio interrupt controller have difference with previous chips, registers to decide irq line and offset of trigger method are all changed, the current driver should be modified. Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 79 ++++++++++++++++++++++++-------- 1 file changed, 60 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index 829084b568fa..1824ffc30de2 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -30,44 +30,74 @@ * stuck at 0. Bits 8 to 15 are responsive and have the expected * effect. */ -#define REG_EDGE_POL_EDGE(x) BIT(x) -#define REG_EDGE_POL_LOW(x) BIT(16 + (x)) -#define REG_BOTH_EDGE(x) BIT(8 + (x)) -#define REG_EDGE_POL_MASK(x) ( \ - REG_EDGE_POL_EDGE(x) | \ - REG_EDGE_POL_LOW(x) | \ - REG_BOTH_EDGE(x)) +#define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x)) +#define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x)) +#define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x)) +#define REG_EDGE_POL_MASK(params, x) ( \ + REG_EDGE_POL_EDGE(params, x) | \ + REG_EDGE_POL_LOW(params, x) | \ + REG_BOTH_EDGE(params, x)) #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) +#define INIT_MESON8_COMMON_DATA \ + .edge_single_offset = 0, \ + .pol_low_offset = 16, \ + .pin_sel_mask = 0xff, \ + .ops = { \ + .gpio_irq_sel_pin = meson8_gpio_irq_sel_pin, \ + }, + +struct meson_gpio_irq_controller; +static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, + unsigned int channel, unsigned long hwirq); +struct irq_ctl_ops { + void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, + unsigned int channel, + unsigned long hwirq); + void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); +}; + struct meson_gpio_irq_params { unsigned int nr_hwirq; bool support_edge_both; + unsigned int edge_both_offset; + unsigned int edge_single_offset; + unsigned int pol_low_offset; + unsigned int pin_sel_mask; + struct irq_ctl_ops ops; }; static const struct meson_gpio_irq_params meson8_params = { .nr_hwirq = 134, + INIT_MESON8_COMMON_DATA }; static const struct meson_gpio_irq_params meson8b_params = { .nr_hwirq = 119, + INIT_MESON8_COMMON_DATA }; static const struct meson_gpio_irq_params gxbb_params = { .nr_hwirq = 133, + INIT_MESON8_COMMON_DATA }; static const struct meson_gpio_irq_params gxl_params = { .nr_hwirq = 110, + INIT_MESON8_COMMON_DATA }; static const struct meson_gpio_irq_params axg_params = { .nr_hwirq = 100, + INIT_MESON8_COMMON_DATA }; static const struct meson_gpio_irq_params sm1_params = { .nr_hwirq = 100, .support_edge_both = true, + .edge_both_offset = 8, + INIT_MESON8_COMMON_DATA }; static const struct of_device_id meson_irq_gpio_matches[] = { @@ -100,9 +130,18 @@ static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl, writel_relaxed(tmp, ctl->base + reg); } -static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel) +static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, + unsigned int channel, unsigned long hwirq) { - return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; + unsigned int reg_offset; + unsigned int bit_offset; + + reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; + bit_offset = REG_PIN_SEL_SHIFT(channel); + + meson_gpio_irq_update_bits(ctl, reg_offset, + ctl->params->pin_sel_mask << bit_offset, + hwirq << bit_offset); } static int @@ -110,7 +149,7 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, unsigned long hwirq, u32 **channel_hwirq) { - unsigned int reg, idx; + unsigned int idx; spin_lock(&ctl->lock); @@ -129,10 +168,7 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, * Setup the mux of the channel to route the signal of the pad * to the appropriate input of the GIC */ - reg = meson_gpio_irq_channel_to_reg(idx); - meson_gpio_irq_update_bits(ctl, reg, - 0xff << REG_PIN_SEL_SHIFT(idx), - hwirq << REG_PIN_SEL_SHIFT(idx)); + ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq); /* * Get the hwirq number assigned to this channel through @@ -173,7 +209,9 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, { u32 val = 0; unsigned int idx; + const struct meson_gpio_irq_params *params; + params = ctl->params; idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); /* @@ -190,22 +228,22 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, * precedence over the other edge/polarity settings */ if (type == IRQ_TYPE_EDGE_BOTH) { - if (!ctl->params->support_edge_both) + if (!params->support_edge_both) return -EINVAL; - val |= REG_BOTH_EDGE(idx); + val |= REG_BOTH_EDGE(params, idx); } else { if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - val |= REG_EDGE_POL_EDGE(idx); + val |= REG_EDGE_POL_EDGE(params, idx); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) - val |= REG_EDGE_POL_LOW(idx); + val |= REG_EDGE_POL_LOW(params, idx); } spin_lock(&ctl->lock); meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, - REG_EDGE_POL_MASK(idx), val); + REG_EDGE_POL_MASK(params, idx), val); spin_unlock(&ctl->lock); @@ -371,6 +409,9 @@ static int __init meson_gpio_irq_parse_dt(struct device_node *node, return ret; } + if (ctl->params->ops.gpio_irq_init) + ctl->params->ops.gpio_irq_init(ctl); + return 0; } From patchwork Fri Dec 6 12:17:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qianggui Song X-Patchwork-Id: 11276059 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDE5E930 for ; Fri, 6 Dec 2019 12:18:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9558624659 for ; Fri, 6 Dec 2019 12:18:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="kwKptgGH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9558624659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; 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Fri, 06 Dec 2019 12:18:13 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1idCY5-0007h2-1G; Fri, 06 Dec 2019 12:17:30 +0000 Received: from localhost.localdomain (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 6 Dec 2019 20:17:50 +0800 From: Qianggui Song To: Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 3/4] irqchip/meson-gpio: Add support for meson a1 SoCs Date: Fri, 6 Dec 2019 20:17:12 +0800 Message-ID: <20191206121714.14579-4-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191206121714.14579-1-qianggui.song@amlogic.com> References: <20191206121714.14579-1-qianggui.song@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.19] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191206_041729_127833_CFA08E29 X-CRM114-Status: GOOD ( 10.68 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qianggui Song , Hanjie Lin , Jianxin Pan , Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Xingyu Chen , Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The meson a1 Socs have some changes compared with previous chips. For A113L, it contains 62 pins and can be spied on: - 62:128 undefined - 61:50 12 pins on bank A - 49:37 13 pins on bank F - 36:20 17 pins on bank X - 19:13 7 pins on bank B - 12:0 13 pins on bank P There are five relative registers for gpio interrupt controller, details are as below: - PADCTRL_GPIO_IRQ_CTRL0 bit[31]: enable/disable the whole irq lines bit[16-23]: both edge trigger bit[8-15]: single edge trigger bit[0-7]: pol trigger - PADCTRL_GPIO_IRQ_CTRL[X] bit[0-6]: 7 bits to choose gpio source for irq line 2*[X] - 2 bit[16-22]: 7 bits to choose gpio source for irq line 2*[X] - 1 where X =1,2,3,4 Signed-off-by: Qianggui Song --- drivers/irqchip/irq-meson-gpio.c | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index 1824ffc30de2..8478100706a6 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -40,6 +40,9 @@ #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) +/* Below is used for Meson-A1 series like chips*/ +#define REG_PIN_A1_SEL 0x04 + #define INIT_MESON8_COMMON_DATA \ .edge_single_offset = 0, \ .pol_low_offset = 16, \ @@ -48,9 +51,26 @@ .gpio_irq_sel_pin = meson8_gpio_irq_sel_pin, \ }, +#define INIT_MESON_A1_COMMON_DATA \ + .support_edge_both = true, \ + .edge_both_offset = 16, \ + .edge_single_offset = 8, \ + .pol_low_offset = 0, \ + .pin_sel_mask = 0x7f, \ + .ops = { \ + .gpio_irq_sel_pin = meson_a1_gpio_irq_sel_pin, \ + .gpio_irq_init = meson_a1_gpio_irq_init, \ + }, + struct meson_gpio_irq_controller; static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, unsigned int channel, unsigned long hwirq); +static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, + unsigned int channel, + unsigned long hwirq); + +static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); + struct irq_ctl_ops { void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, unsigned int channel, @@ -100,6 +120,11 @@ static const struct meson_gpio_irq_params sm1_params = { INIT_MESON8_COMMON_DATA }; +static const struct meson_gpio_irq_params a1_params = { + .nr_hwirq = 62, + INIT_MESON_A1_COMMON_DATA +}; + static const struct of_device_id meson_irq_gpio_matches[] = { { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, @@ -108,6 +133,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = { { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params }, { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params }, { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params }, + { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params }, { } }; @@ -144,6 +170,21 @@ static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, hwirq << bit_offset); } +static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, + unsigned int channel, + unsigned long hwirq) +{ + unsigned int reg_offset; + unsigned int bit_offset; + + bit_offset = ((channel % 2) == 0) ? 0 : 16; + reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2); + + meson_gpio_irq_update_bits(ctl, reg_offset, + ctl->params->pin_sel_mask << bit_offset, + hwirq << bit_offset); +} + static int meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, unsigned long hwirq, @@ -250,6 +291,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, return 0; } +/* For a1 or later chips like a1 there is a switch to enable/disable irq */ +static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) +{ + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); +} + static unsigned int meson_gpio_irq_type_output(unsigned int type) { unsigned int sense = type & IRQ_TYPE_SENSE_MASK; From patchwork Fri Dec 6 12:17:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qianggui Song X-Patchwork-Id: 11276061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81EF7138C for ; Fri, 6 Dec 2019 12:18:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6037D24659 for ; Fri, 6 Dec 2019 12:18:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="t69ZxMc+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6037D24659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HSCOcVDH+gzj1KSVLMFG0Q3AMokCFuDFthR7wLSpfBs=; b=t69ZxMc+pnoJmA 5nyX+HOIEkNx567Q475tnS5Ve0nf8l9CGLSJ8MpRq+Gj2U26N/+EL537tkUNUkKeCq3s9m87qNDFx 5DfIFL+8u2VD8kg26063S5xu5cyJ9AQ05qzvrxVrUOsloclSYEo5paf4uzmr1/oV/aP04DOCVxUdp skfLHSiPL40rrXT7Nbsz7shR1fLPxh1SyRl0HzhLdczAoHgkK6ZODmN8L0Q6w3WLhw5rpiBp+Ihtn n6fXnT0v6b5//wtOUIKfwDVkm3Na7nBda1oQV4oF6qwJOmv3r2fxiSHs3KIWldgR3HTlzuVo7NP2r c7VRGVkZO4EpkfMiKrkQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1idCYy-0000FS-R6; Fri, 06 Dec 2019 12:18:24 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1idCY7-0007h2-7A; Fri, 06 Dec 2019 12:17:32 +0000 Received: from localhost.localdomain (10.28.8.19) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 6 Dec 2019 20:17:51 +0800 From: Qianggui Song To: Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH 4/4] arm64: dts: meson: a1: add gpio interrupt controller support Date: Fri, 6 Dec 2019 20:17:13 +0800 Message-ID: <20191206121714.14579-5-qianggui.song@amlogic.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191206121714.14579-1-qianggui.song@amlogic.com> References: <20191206121714.14579-1-qianggui.song@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.19] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191206_041731_277600_3FFFFA4A X-CRM114-Status: UNSURE ( 5.86 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Qianggui Song , devicetree@vger.kernel.org, Hanjie Lin , Jianxin Pan , Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, Mark Rutland , Xingyu Chen , Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org add gpio interrupt controller node to a1 SoC Signed-off-by: Qianggui Song --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 0965259af869..6d52350a5652 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -92,6 +92,15 @@ gpio: bank@0400 { }; + gpio_intc: interrupt-controller@0440 { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-a1-gpio-intc"; + reg = <0x0 0x0440 0x0 0x14>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <49 50 51 52 53 54 55 56>; + }; + uart_AO: serial@1c00 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";