From patchwork Fri Dec 6 23:13:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Davenport X-Patchwork-Id: 11277123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A607E139A for ; Fri, 6 Dec 2019 23:14:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 76B4D2464E for ; Fri, 6 Dec 2019 23:14:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="fkLpPdL6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726377AbfLFXOu (ORCPT ); Fri, 6 Dec 2019 18:14:50 -0500 Received: from mail-io1-f68.google.com ([209.85.166.68]:41220 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbfLFXOu (ORCPT ); Fri, 6 Dec 2019 18:14:50 -0500 Received: by mail-io1-f68.google.com with SMTP id z26so9016706iot.8 for ; Fri, 06 Dec 2019 15:14:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2tV+LQltIxtrwT9i6U9Zs1LuxslYBuD7ZjJ2pCIUfQo=; b=fkLpPdL6h40+44pP3LdTIKjR5KGwjlMFtmRar8gh1SfkE1OqhIxuNrlm3PXr894UmN 49SBwmZ9Jme9kuleURRwZ6bYCMueNQ2cpoKSpzm2T/YhfqJvEnU/eu1tjmjj4WHbNgjw pJBEC+lzwiSaxrQAjrdEk6z6NkVEyRskgp0KM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=2tV+LQltIxtrwT9i6U9Zs1LuxslYBuD7ZjJ2pCIUfQo=; b=Wr3c/ySYNZzYpZQ5PtnY7w+a38Ua78SjpzZytpjrcwpJNyv7MtZX4ZLciislg9+TkS +Vy5yhJG843nL1AnMPzOJcYhcpEXMC0DQxzcfKZxrsS5UlYQpkq34Z0YxLeUgGE63EJb qfv5yhUjNoEVKyEYBkfh9EIM4BUBdUFddtQ2uU5rUqInX5/CndWGcXBIfF4gcrHTJaEp Imr6b4MClBGUkZvwz5omhbJkawtRolN0aIr/Z+pCP2P8pbLm9VY+i8FS59YwQ0k/vtN9 /9UnBOqE5H8OXvk4jnrjG3NIysiWVsoxuAxcJkRbrourrte+Je5EfbVh21ELjvlBJUPk IbPQ== X-Gm-Message-State: APjAAAWoD/n6AeBfuFILA/KZvvgit+DxZ4KRIxBeVJu3I9M1LC/uQ1zf y9R9ajJUszf3uVDVmuxMzJ6xqA== X-Google-Smtp-Source: APXvYqxBN4bGzXyzVPfRdGmlPO8puYZX1U7xJR3GIbWwdz3Q1onKIW9w5WnD5t+2ZdImhlkciCGF2Q== X-Received: by 2002:a6b:9204:: with SMTP id u4mr11566798iod.99.1575674089530; Fri, 06 Dec 2019 15:14:49 -0800 (PST) Received: from ddavenport4.bld.corp.google.com ([2620:15c:183:0:92f:a80a:519d:f777]) by smtp.gmail.com with ESMTPSA id b15sm4317946ilo.37.2019.12.06.15.14.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Dec 2019 15:14:49 -0800 (PST) From: Drew Davenport To: dri-devel@lists.freedesktop.org Cc: Drew Davenport , David Airlie , Sean Paul , zhengbin , Bruce Wang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Alexios Zavras , Jeykumar Sankaran , Fritz Koenig , Jordan Crouse , Rob Clark , Thomas Gleixner , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH 1/6] drm/msm/dpu: Remove unnecessary NULL checks Date: Fri, 6 Dec 2019 16:13:43 -0700 Message-Id: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org dpu_hw_ctl* is checked for NULL when passed as an argument to several functions. It will never be NULL, so remove the checks. Signed-off-by: Drew Davenport --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 +++----- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f96e142c4361..45a87757e766 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1419,7 +1419,7 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, } ctl = phys->hw_ctl; - if (!ctl || !ctl->ops.trigger_flush) { + if (!ctl->ops.trigger_flush) { DPU_ERROR("missing trigger cb\n"); return; } @@ -1469,7 +1469,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) } ctl = phys_enc->hw_ctl; - if (ctl && ctl->ops.trigger_start) { + if (ctl->ops.trigger_start) { ctl->ops.trigger_start(ctl); trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); } @@ -1513,7 +1513,7 @@ static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) dpu_enc = to_dpu_encoder_virt(phys_enc->parent); ctl = phys_enc->hw_ctl; - if (!ctl || !ctl->ops.reset) + if (!ctl->ops.reset) return; DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), @@ -1554,8 +1554,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) continue; ctl = phys->hw_ctl; - if (!ctl) - continue; /* * This is cleared in frame_done worker, which isn't invoked @@ -1603,7 +1601,7 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) for (i = 0; i < dpu_enc->num_phys_encs; i++) { phys = dpu_enc->phys_encs[i]; - if (phys && phys->hw_ctl) { + if (phys) { ctl = phys->hw_ctl; if (ctl->ops.clear_pending_flush) ctl->ops.clear_pending_flush(ctl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 047960949fbb..cfd01b0ac7f1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -62,7 +62,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( return; ctl = phys_enc->hw_ctl; - if (!ctl || !ctl->ops.setup_intf_cfg) + if (!ctl->ops.setup_intf_cfg) return; intf_cfg.intf = phys_enc->intf_idx; @@ -125,7 +125,7 @@ static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx) { struct dpu_encoder_phys *phys_enc = arg; - if (!phys_enc || !phys_enc->hw_ctl) + if (!phys_enc) return; DPU_ATRACE_BEGIN("ctl_start_irq"); @@ -198,7 +198,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR; bool do_log = false; - if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl) + if (!phys_enc || !phys_enc->hw_pp) return -EINVAL; cmd_enc->pp_timeout_report_cnt++; @@ -428,7 +428,7 @@ static void _dpu_encoder_phys_cmd_pingpong_config( struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp + if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0); return; @@ -458,7 +458,7 @@ static void dpu_encoder_phys_cmd_enable_helper( struct dpu_hw_ctl *ctl; u32 flush_mask = 0; - if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) { + if (!phys_enc || !phys_enc->hw_pp) { DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); return; } @@ -614,7 +614,7 @@ static int _dpu_encoder_phys_cmd_wait_for_ctl_start( struct dpu_encoder_wait_info wait_info; int ret; - if (!phys_enc || !phys_enc->hw_ctl) { + if (!phys_enc) { DPU_ERROR("invalid argument(s)\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 3123ef873cdf..2252475dd8dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -297,8 +297,6 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) return; hw_ctl = phys_enc->hw_ctl; - if (!hw_ctl) - return; DPU_ATRACE_BEGIN("vblank_irq"); @@ -314,7 +312,7 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) * so we need to double-check with hw that it accepted the flush bits */ spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - if (hw_ctl && hw_ctl->ops.get_flush_register) + if (hw_ctl->ops.get_flush_register) flush_register = hw_ctl->ops.get_flush_register(hw_ctl); if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) @@ -549,7 +547,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( } ctl = phys_enc->hw_ctl; - if (!ctl || !ctl->ops.wait_reset_status) + if (!ctl->ops.wait_reset_status) return; /* @@ -574,7 +572,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) return; } - if (!phys_enc->hw_intf || !phys_enc->hw_ctl) { + if (!phys_enc->hw_intf) { DPU_ERROR("invalid hw_intf %d hw_ctl %d\n", phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0); return; From patchwork Fri Dec 6 23:13:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Davenport X-Patchwork-Id: 11277127 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B959F13B6 for ; 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Fri, 06 Dec 2019 15:14:56 -0800 (PST) Received: from ddavenport4.bld.corp.google.com ([2620:15c:183:0:92f:a80a:519d:f777]) by smtp.gmail.com with ESMTPSA id b15sm4317946ilo.37.2019.12.06.15.14.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Dec 2019 15:14:56 -0800 (PST) From: Drew Davenport To: dri-devel@lists.freedesktop.org Cc: Drew Davenport , Sean Paul , Bruce Wang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Jeykumar Sankaran , Jordan Crouse , Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH 2/6] drm/msm/dpu: Remove unnecessary NULL checks Date: Fri, 6 Dec 2019 16:13:44 -0700 Message-Id: <20191206161137.2.I3e20091f213b47dfa888bc2f528509d84d19c743@changeid> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> References: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org dpu_crtc_mixer.lm_ctl will never be NULL, so don't bother checking Signed-off-by: Drew Davenport --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index f197dce54576..b9ed8285ab39 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -197,8 +197,8 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) DPU_DEBUG("%s\n", dpu_crtc->name); for (i = 0; i < cstate->num_mixers; i++) { - if (!mixer[i].hw_lm || !mixer[i].lm_ctl) { - DPU_ERROR("invalid lm or ctl assigned to mixer\n"); + if (!mixer[i].hw_lm) { + DPU_ERROR("invalid lm assigned to mixer\n"); return; } mixer[i].mixer_op_mode = 0; @@ -1115,8 +1115,6 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) m = &cstate->mixers[i]; if (!m->hw_lm) seq_printf(s, "\tmixer[%d] has no lm\n", i); - else if (!m->lm_ctl) - seq_printf(s, "\tmixer[%d] has no ctl\n", i); else seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, From patchwork Fri Dec 6 23:13:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Davenport X-Patchwork-Id: 11277145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A3D1E930 for ; Fri, 6 Dec 2019 23:15:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8154424670 for ; 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Fri, 06 Dec 2019 15:14:56 -0800 (PST) From: Drew Davenport To: dri-devel@lists.freedesktop.org Cc: Drew Davenport , Sean Paul , Bruce Wang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Jeykumar Sankaran , Jordan Crouse , Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH 3/6] drm/msm/dpu: Remove unnecessary NULL checks Date: Fri, 6 Dec 2019 16:13:45 -0700 Message-Id: <20191206161137.3.I55d53dbb7c64256e4231a6b99c6e6d1c336f624b@changeid> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> References: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org dpu_crtc_mixer.hw_lm will never be NULL, so don't check. Signed-off-by: Drew Davenport --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b9ed8285ab39..bf513411b243 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -197,10 +197,6 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) DPU_DEBUG("%s\n", dpu_crtc->name); for (i = 0; i < cstate->num_mixers; i++) { - if (!mixer[i].hw_lm) { - DPU_ERROR("invalid lm assigned to mixer\n"); - return; - } mixer[i].mixer_op_mode = 0; mixer[i].flush_mask = 0; if (mixer[i].lm_ctl->ops.clear_all_blendstages) @@ -1113,12 +1109,9 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) for (i = 0; i < cstate->num_mixers; ++i) { m = &cstate->mixers[i]; - if (!m->hw_lm) - seq_printf(s, "\tmixer[%d] has no lm\n", i); - else - seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", - m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, - out_width, mode->vdisplay); + seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", + m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, + out_width, mode->vdisplay); } seq_puts(s, "\n"); From patchwork Fri Dec 6 23:13:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Davenport X-Patchwork-Id: 11277129 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97089139A for ; Fri, 6 Dec 2019 23:15:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 529272464E for ; Fri, 6 Dec 2019 23:15:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="JIy+azGN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726551AbfLFXO7 (ORCPT ); Fri, 6 Dec 2019 18:14:59 -0500 Received: from mail-il1-f196.google.com ([209.85.166.196]:38601 "EHLO mail-il1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726506AbfLFXO7 (ORCPT ); Fri, 6 Dec 2019 18:14:59 -0500 Received: by mail-il1-f196.google.com with SMTP id u17so7715131ilq.5 for ; Fri, 06 Dec 2019 15:14:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1nbRHvdkP0hLRgTfexh8/WK4VLoG7LzO+ZWO18GgBGY=; b=JIy+azGNeXNIeGZcbTheNvvLUgrGldNjpNaGaM3ALED7rlJRkUN2qhFOvmNdMlsQTL lpvjcHM4QxiM6FHMBfEm5CyLXT1NK/GEAYuxqLv3Z9uuQOjzdTGwRc6Y/BVFuIjYXOvX vQpbQPLtmbLp9bNGtDTuz77/akfCiEUHyZlSY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1nbRHvdkP0hLRgTfexh8/WK4VLoG7LzO+ZWO18GgBGY=; b=rgQCL+qXRTkJKC/dgPjWz5KrZtCGhahs6uYLY9VZ71slTVWUfo/DB0zu8SXX8QDY49 18zI+M7YLIRktOn7qdjIHt2F4c9FLFW31nu97qg0Y9WdXbbp77S8gtRT5BzV7953t3Vs Nrc7BAJ3wk6fDJO8wknwbdD8MPDc/6f7w41A4xIKahNiT/UdPDI9v5j37/4XvVeStWfK pYT8XMnbLyKJapSjm51W3XNfuVOo84JpvxEZMcpF7nBtJus2W+sFHtLlqk84iFll3xV7 n5RJ70BIOPO31xlfwbZ9pX2gejTnuR2zWhF3D4jLldiSegFQBrm8NapZsWHXKZRE1xQ7 4RDw== X-Gm-Message-State: APjAAAXDVjn3Ao22rqGjpB/KixYpB0Ug4PiIg4/OW82ClFzIf96E6hGi Q5cxBF/AK/6kf/93E4FbnnL2kg== X-Google-Smtp-Source: APXvYqyDf/uqUpunrIdThbIZ4cH4pyFIFN3uzZeKRVVjjgeaa0B/Fvs16WgmKVIpv6TQIIpIckuNjw== X-Received: by 2002:a92:c851:: with SMTP id b17mr15412044ilq.160.1575674097972; Fri, 06 Dec 2019 15:14:57 -0800 (PST) Received: from ddavenport4.bld.corp.google.com ([2620:15c:183:0:92f:a80a:519d:f777]) by smtp.gmail.com with ESMTPSA id b15sm4317946ilo.37.2019.12.06.15.14.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Dec 2019 15:14:57 -0800 (PST) From: Drew Davenport To: dri-devel@lists.freedesktop.org Cc: Drew Davenport , Sean Paul , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Jeykumar Sankaran , Fritz Koenig , Jordan Crouse , Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH 4/6] drm/msm/dpu: Remove unnecessary NULL check Date: Fri, 6 Dec 2019 16:13:46 -0700 Message-Id: <20191206161137.4.Ia99f646171bd2099e8710c4dc2f3825850d38737@changeid> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> References: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org dpu_encoder_virt.phys_encs[0:num_phys_encs-1] will not be NULL so don't check. Also fix multiline strings that caused checkpatch warning. Signed-off-by: Drew Davenport --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 162 ++++++++------------ 1 file changed, 61 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 45a87757e766..e9f8fe66af7b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -233,7 +233,7 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, u32 irq_status; int ret; - if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) { + if (!wait_info || intr_idx >= INTR_IDX_MAX) { DPU_ERROR("invalid params\n"); return -EINVAL; } @@ -308,7 +308,7 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, struct dpu_encoder_irq *irq; int ret = 0; - if (!phys_enc || intr_idx >= INTR_IDX_MAX) { + if (intr_idx >= INTR_IDX_MAX) { DPU_ERROR("invalid params\n"); return -EINVAL; } @@ -363,10 +363,6 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, struct dpu_encoder_irq *irq; int ret; - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return -EINVAL; - } irq = &phys_enc->irq[intr_idx]; /* silently skip irqs that weren't registered */ @@ -415,7 +411,7 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.get_hw_resources) + if (phys->ops.get_hw_resources) phys->ops.get_hw_resources(phys, hw_res); } } @@ -438,7 +434,7 @@ static void dpu_encoder_destroy(struct drm_encoder *drm_enc) for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.destroy) { + if (phys->ops.destroy) { phys->ops.destroy(phys); --dpu_enc->num_phys_encs; dpu_enc->phys_encs[i] = NULL; @@ -464,7 +460,7 @@ void dpu_encoder_helper_split_config( struct dpu_hw_mdp *hw_mdptop; struct msm_display_info *disp_info; - if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) { + if (!phys_enc->hw_mdptop || !phys_enc->parent) { DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); return; } @@ -528,16 +524,11 @@ static struct msm_display_topology dpu_encoder_get_topology( struct drm_display_mode *mode) { struct msm_display_topology topology; - int i, intf_count = 0; - - for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) - if (dpu_enc->phys_encs[i]) - intf_count++; /* User split topology for width > 1080 */ topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1; topology.num_enc = 0; - topology.num_intf = intf_count; + topology.num_intf = dpu_enc->num_phys_encs; return topology; } @@ -583,10 +574,10 @@ static int dpu_encoder_virt_atomic_check( for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.atomic_check) + if (phys->ops.atomic_check) ret = phys->ops.atomic_check(phys, crtc_state, conn_state); - else if (phys && phys->ops.mode_fixup) + else if (phys->ops.mode_fixup) if (!phys->ops.mode_fixup(phys, mode, adj_mode)) ret = -EINVAL; @@ -682,7 +673,7 @@ static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.irq_control) + if (phys->ops.irq_control) phys->ops.irq_control(phys, enable); } @@ -1032,46 +1023,43 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys) { - if (!dpu_enc->hw_pp[i]) { - DPU_ERROR_ENC(dpu_enc, "no pp block assigned" - "at idx: %d\n", i); - goto error; - } + if (!dpu_enc->hw_pp[i]) { + DPU_ERROR_ENC(dpu_enc, + "no pp block assigned at idx: %d\n", i); + goto error; + } - if (!hw_ctl[i]) { - DPU_ERROR_ENC(dpu_enc, "no ctl block assigned" - "at idx: %d\n", i); - goto error; - } + if (!hw_ctl[i]) { + DPU_ERROR_ENC(dpu_enc, + "no ctl block assigned at idx: %d\n", i); + goto error; + } - phys->hw_pp = dpu_enc->hw_pp[i]; - phys->hw_ctl = hw_ctl[i]; + phys->hw_pp = dpu_enc->hw_pp[i]; + phys->hw_ctl = hw_ctl[i]; - dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, - DPU_HW_BLK_INTF); - for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) { - struct dpu_hw_intf *hw_intf; + dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id, + DPU_HW_BLK_INTF); + for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) { + struct dpu_hw_intf *hw_intf; - if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter)) - break; + if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter)) + break; - hw_intf = (struct dpu_hw_intf *)hw_iter.hw; - if (hw_intf->idx == phys->intf_idx) - phys->hw_intf = hw_intf; - } + hw_intf = (struct dpu_hw_intf *)hw_iter.hw; + if (hw_intf->idx == phys->intf_idx) + phys->hw_intf = hw_intf; + } - if (!phys->hw_intf) { - DPU_ERROR_ENC(dpu_enc, - "no intf block assigned at idx: %d\n", - i); + if (!phys->hw_intf) { + DPU_ERROR_ENC(dpu_enc, + "no intf block assigned at idx: %d\n", i); goto error; - } - - phys->connector = conn->state->connector; - if (phys->ops.mode_set) - phys->ops.mode_set(phys, mode, adj_mode); } + + phys->connector = conn->state->connector; + if (phys->ops.mode_set) + phys->ops.mode_set(phys, mode, adj_mode); } dpu_enc->mode_set_complete = true; @@ -1203,7 +1191,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.disable) + if (phys->ops.disable) phys->ops.disable(phys); } @@ -1216,8 +1204,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); for (i = 0; i < dpu_enc->num_phys_encs; i++) { - if (dpu_enc->phys_encs[i]) - dpu_enc->phys_encs[i]->connector = NULL; + dpu_enc->phys_encs[i]->connector = NULL; } DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); @@ -1307,7 +1294,7 @@ void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.control_vblank_irq) + if (phys->ops.control_vblank_irq) phys->ops.control_vblank_irq(phys, enable); } } @@ -1463,11 +1450,6 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) { struct dpu_hw_ctl *ctl; - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } - ctl = phys_enc->hw_ctl; if (ctl->ops.trigger_start) { ctl->ops.trigger_start(ctl); @@ -1506,10 +1488,6 @@ static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) struct dpu_hw_ctl *ctl; int rc; - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } dpu_enc = to_dpu_encoder_virt(phys_enc->parent); ctl = phys_enc->hw_ctl; @@ -1550,7 +1528,7 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (!phys || phys->enable_state == DPU_ENC_DISABLED) + if (phys->enable_state == DPU_ENC_DISABLED) continue; ctl = phys->hw_ctl; @@ -1601,17 +1579,15 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) for (i = 0; i < dpu_enc->num_phys_encs; i++) { phys = dpu_enc->phys_encs[i]; - if (phys) { - ctl = phys->hw_ctl; - if (ctl->ops.clear_pending_flush) - ctl->ops.clear_pending_flush(ctl); + ctl = phys->hw_ctl; + if (ctl->ops.clear_pending_flush) + ctl->ops.clear_pending_flush(ctl); - /* update only for command mode primary ctl */ - if ((phys == dpu_enc->cur_master) && - (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) - && ctl->ops.trigger_pending) - ctl->ops.trigger_pending(ctl); - } + /* update only for command mode primary ctl */ + if ((phys == dpu_enc->cur_master) && + (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) + && ctl->ops.trigger_pending) + ctl->ops.trigger_pending(ctl); } } @@ -1771,12 +1747,10 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); for (i = 0; i < dpu_enc->num_phys_encs; i++) { phys = dpu_enc->phys_encs[i]; - if (phys) { - if (phys->ops.prepare_for_kickoff) - phys->ops.prepare_for_kickoff(phys); - if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) - needs_hw_reset = true; - } + if (phys->ops.prepare_for_kickoff) + phys->ops.prepare_for_kickoff(phys); + if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) + needs_hw_reset = true; } DPU_ATRACE_END("enc_prepare_for_kickoff"); @@ -1817,7 +1791,7 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc) /* allow phys encs to handle any post-kickoff business */ for (i = 0; i < dpu_enc->num_phys_encs; i++) { phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.handle_post_kickoff) + if (phys->ops.handle_post_kickoff) phys->ops.handle_post_kickoff(phys); } @@ -1846,7 +1820,7 @@ void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) for (i = 0; i < dpu_enc->num_phys_encs; i++) { phys = dpu_enc->phys_encs[i]; - if (phys && phys->ops.prepare_commit) + if (phys->ops.prepare_commit) phys->ops.prepare_commit(phys); } } @@ -1861,9 +1835,6 @@ static int _dpu_encoder_status_show(struct seq_file *s, void *data) for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (!phys) - continue; - seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", phys->intf_idx - INTF_0, atomic_read(&phys->vsync_cnt), @@ -1922,8 +1893,7 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); for (i = 0; i < dpu_enc->num_phys_encs; i++) - if (dpu_enc->phys_encs[i] && - dpu_enc->phys_encs[i]->ops.late_register) + if (dpu_enc->phys_encs[i]->ops.late_register) dpu_enc->phys_encs[i]->ops.late_register( dpu_enc->phys_encs[i], dpu_enc->debugfs_root); @@ -2092,11 +2062,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - - if (phys) { - atomic_set(&phys->vsync_cnt, 0); - atomic_set(&phys->underrun_cnt, 0); - } + atomic_set(&phys->vsync_cnt, 0); + atomic_set(&phys->underrun_cnt, 0); } mutex_unlock(&dpu_enc->enc_lock); @@ -2238,8 +2205,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (!phys) - continue; switch (event) { case MSM_ENC_COMMIT_DONE: @@ -2272,7 +2237,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) { struct dpu_encoder_virt *dpu_enc = NULL; - int i; if (!encoder) { DPU_ERROR("invalid encoder\n"); @@ -2283,12 +2247,8 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) if (dpu_enc->cur_master) return dpu_enc->cur_master->intf_mode; - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - - if (phys) - return phys->intf_mode; - } + if (dpu_enc->num_phys_encs) + return dpu_enc->phys_encs[0]->intf_mode; return INTF_MODE_NONE; } From patchwork Fri Dec 6 23:13:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Davenport X-Patchwork-Id: 11277133 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC67F13B6 for ; Fri, 6 Dec 2019 23:15:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 89F1B20707 for ; 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Fri, 06 Dec 2019 15:14:58 -0800 (PST) From: Drew Davenport To: dri-devel@lists.freedesktop.org Cc: Drew Davenport , David Airlie , Sean Paul , zhengbin , Bruce Wang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Jeykumar Sankaran , Jordan Crouse , Rob Clark , Thomas Gleixner , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH 5/6] drm/msm/dpu: Remove unreachable code Date: Fri, 6 Dec 2019 16:13:47 -0700 Message-Id: <20191206161137.5.I3259a95a1b16978f6b38c23597a9bbba4521cf67@changeid> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> References: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The return statement follows another return statement, so will never be reached. Signed-off-by: Drew Davenport --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index cfd01b0ac7f1..cc2ecf327582 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -816,6 +816,4 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( DPU_DEBUG_CMDENC(cmd_enc, "created\n"); return phys_enc; - - return ERR_PTR(ret); } From patchwork Fri Dec 6 23:13:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Davenport X-Patchwork-Id: 11277143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C902139A for ; Fri, 6 Dec 2019 23:15:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C9DE72464E for ; Fri, 6 Dec 2019 23:15:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="XoRfNjir" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726388AbfLFXPL (ORCPT ); Fri, 6 Dec 2019 18:15:11 -0500 Received: from mail-il1-f196.google.com ([209.85.166.196]:38943 "EHLO mail-il1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726553AbfLFXPB (ORCPT ); Fri, 6 Dec 2019 18:15:01 -0500 Received: by mail-il1-f196.google.com with SMTP id a7so7696198ild.6 for ; Fri, 06 Dec 2019 15:15:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XW/MrhXAVDyeCMiJcKC4crfk3pG/2/JBLuHke3ueDF0=; b=XoRfNjirtDbrYP3OT2Z5rNxteEyUfaMub2288xDttHO0RhBmtJvscXN/AzINgN+xmb u45yo7vI2ekiHAaX5BOnJS6L2IotUS/QzsXKYZzg0qW/rneuXQBbQJ3dib0UNOWOUxDN j9kxsuaq5GhKyK2Zfp9o08W2IjveK0F60fzFo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XW/MrhXAVDyeCMiJcKC4crfk3pG/2/JBLuHke3ueDF0=; b=Gx85ZBlG4fGI1qXuiD9OfnWuevX2bMJlrejy5OicGfuok8COOQ094QrfMYlEsmHycc pLRu4k34YcyyWzDa5bBRCYZsIIl1adVnSVoO/5qbMCnpF3Yw+/iOaWqKGpos1XpTBSml mpqyba4lUNkykX47Gy9dsHh4UVMp+TR+YNcU+o7BMdfR2joJrhlwIQdUVdTIWUlktuUs xv7TqGU0JIWKRTW0kCyJLPJjP8G9uYeC7XfLUwspsNlwnT/WPdvNp/JGoy3xQc2HNIyY n3MkVvBR8CvKYSpxEYbvGSIM7gNCrR+1icZegv0MN+esdCqTl1EkeeNj4vH9M8T5T7Rb da2A== X-Gm-Message-State: APjAAAXhjd9d7zKFrHNUk2hY2Lrwu+O/kNfJ4hY7UqWByzpjAH2SAS3r FJrIxOfZOvlEeNUhVF9zOCxqTw== X-Google-Smtp-Source: APXvYqxeyKh9xU1zUa8Wogw4dKJjWO9bUFq+RdVvi8CMl73qOfllHRjokhKv+ARs4bfVv5DKNEddVQ== X-Received: by 2002:a92:cc4e:: with SMTP id t14mr17535353ilq.13.1575674099951; Fri, 06 Dec 2019 15:14:59 -0800 (PST) Received: from ddavenport4.bld.corp.google.com ([2620:15c:183:0:92f:a80a:519d:f777]) by smtp.gmail.com with ESMTPSA id b15sm4317946ilo.37.2019.12.06.15.14.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Dec 2019 15:14:59 -0800 (PST) From: Drew Davenport To: dri-devel@lists.freedesktop.org Cc: Drew Davenport , David Airlie , Sean Paul , zhengbin , Bruce Wang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Jeykumar Sankaran , Jordan Crouse , Rob Clark , Thomas Gleixner , freedreno@lists.freedesktop.org, Daniel Vetter Subject: [PATCH 6/6] drm/msm/dpu: Remove unnecessary NULL checks Date: Fri, 6 Dec 2019 16:13:48 -0700 Message-Id: <20191206161137.6.I505289c0ad2bbcbbb8831c2f209f2f4ebee59f28@changeid> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> References: <20191206161137.1.Ibb7612c1ebcebe3f560b3269150c0e0363f01e44@changeid> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The dpu_encoder_phys * argument passed to these functions will never be NULL so don't check. Signed-off-by: Drew Davenport --- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 69 ++++--------------- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 44 +----------- 2 files changed, 17 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index cc2ecf327582..39e1e280ba44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -45,8 +45,7 @@ static bool dpu_encoder_phys_cmd_mode_fixup( const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { - if (phys_enc) - DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n"); + DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n"); return true; } @@ -58,9 +57,6 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( struct dpu_hw_ctl *ctl; struct dpu_hw_intf_cfg intf_cfg = { 0 }; - if (!phys_enc) - return; - ctl = phys_enc->hw_ctl; if (!ctl->ops.setup_intf_cfg) return; @@ -79,7 +75,7 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) int new_cnt; u32 event = DPU_ENCODER_FRAME_EVENT_DONE; - if (!phys_enc || !phys_enc->hw_pp) + if (!phys_enc->hw_pp) return; DPU_ATRACE_BEGIN("pp_done_irq"); @@ -106,7 +102,7 @@ static void dpu_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx) struct dpu_encoder_phys *phys_enc = arg; struct dpu_encoder_phys_cmd *cmd_enc; - if (!phys_enc || !phys_enc->hw_pp) + if (!phys_enc->hw_pp) return; DPU_ATRACE_BEGIN("rd_ptr_irq"); @@ -125,9 +121,6 @@ static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx) { struct dpu_encoder_phys *phys_enc = arg; - if (!phys_enc) - return; - DPU_ATRACE_BEGIN("ctl_start_irq"); atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0); @@ -141,9 +134,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) { struct dpu_encoder_phys *phys_enc = arg; - if (!phys_enc) - return; - if (phys_enc->parent_ops->handle_underrun_virt) phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, phys_enc); @@ -179,7 +169,7 @@ static void dpu_encoder_phys_cmd_mode_set( struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc || !mode || !adj_mode) { + if (!mode || !adj_mode) { DPU_ERROR("invalid args\n"); return; } @@ -198,7 +188,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR; bool do_log = false; - if (!phys_enc || !phys_enc->hw_pp) + if (!phys_enc->hw_pp) return -EINVAL; cmd_enc->pp_timeout_report_cnt++; @@ -247,11 +237,6 @@ static int _dpu_encoder_phys_cmd_wait_for_idle( struct dpu_encoder_wait_info wait_info; int ret; - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return -EINVAL; - } - wait_info.wq = &phys_enc->pending_kickoff_wq; wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; @@ -273,7 +258,7 @@ static int dpu_encoder_phys_cmd_control_vblank_irq( int ret = 0; int refcount; - if (!phys_enc || !phys_enc->hw_pp) { + if (!phys_enc->hw_pp) { DPU_ERROR("invalid encoder\n"); return -EINVAL; } @@ -314,9 +299,6 @@ static int dpu_encoder_phys_cmd_control_vblank_irq( static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, bool enable) { - if (!phys_enc) - return; - trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, enable, atomic_read(&phys_enc->vblank_refcount)); @@ -351,7 +333,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config( u32 vsync_hz; struct dpu_kms *dpu_kms; - if (!phys_enc || !phys_enc->hw_pp) { + if (!phys_enc->hw_pp) { DPU_ERROR("invalid encoder\n"); return; } @@ -428,8 +410,7 @@ static void _dpu_encoder_phys_cmd_pingpong_config( struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc || !phys_enc->hw_pp - || !phys_enc->hw_ctl->ops.setup_intf_cfg) { + if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) { DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0); return; } @@ -458,7 +439,7 @@ static void dpu_encoder_phys_cmd_enable_helper( struct dpu_hw_ctl *ctl; u32 flush_mask = 0; - if (!phys_enc || !phys_enc->hw_pp) { + if (!phys_enc->hw_pp) { DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); return; } @@ -480,7 +461,7 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc || !phys_enc->hw_pp) { + if (!phys_enc->hw_pp) { DPU_ERROR("invalid phys encoder\n"); return; } @@ -499,8 +480,7 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) static void _dpu_encoder_phys_cmd_connect_te( struct dpu_encoder_phys *phys_enc, bool enable) { - if (!phys_enc || !phys_enc->hw_pp || - !phys_enc->hw_pp->ops.connect_external_te) + if (!phys_enc->hw_pp || !phys_enc->hw_pp->ops.connect_external_te) return; trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable); @@ -518,7 +498,7 @@ static int dpu_encoder_phys_cmd_get_line_count( { struct dpu_hw_pingpong *hw_pp; - if (!phys_enc || !phys_enc->hw_pp) + if (!phys_enc->hw_pp) return -EINVAL; if (!dpu_encoder_phys_cmd_is_master(phys_enc)) @@ -536,7 +516,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc || !phys_enc->hw_pp) { + if (!phys_enc->hw_pp) { DPU_ERROR("invalid encoder\n"); return; } @@ -559,10 +539,6 @@ static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } kfree(cmd_enc); } @@ -580,7 +556,7 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( to_dpu_encoder_phys_cmd(phys_enc); int ret; - if (!phys_enc || !phys_enc->hw_pp) { + if (!phys_enc->hw_pp) { DPU_ERROR("invalid encoder\n"); return; } @@ -614,11 +590,6 @@ static int _dpu_encoder_phys_cmd_wait_for_ctl_start( struct dpu_encoder_wait_info wait_info; int ret; - if (!phys_enc) { - DPU_ERROR("invalid argument(s)\n"); - return -EINVAL; - } - wait_info.wq = &phys_enc->pending_kickoff_wq; wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt; wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; @@ -639,9 +610,6 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( { int rc; - if (!phys_enc) - return -EINVAL; - rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc); if (rc) { DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n", @@ -658,9 +626,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( int rc = 0; struct dpu_encoder_phys_cmd *cmd_enc; - if (!phys_enc) - return -EINVAL; - cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); /* only required for master controller */ @@ -681,9 +646,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank( struct dpu_encoder_phys_cmd *cmd_enc; struct dpu_encoder_wait_info wait_info; - if (!phys_enc) - return -EINVAL; - cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); /* only required for master controller */ @@ -715,9 +677,6 @@ static void dpu_encoder_phys_cmd_handle_post_kickoff( static void dpu_encoder_phys_cmd_trigger_start( struct dpu_encoder_phys *phys_enc) { - if (!phys_enc) - return; - dpu_encoder_helper_trigger_start(phys_enc); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 2252475dd8dc..114a3e8f6b0c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -220,8 +220,7 @@ static bool dpu_encoder_phys_vid_mode_fixup( const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { - if (phys_enc) - DPU_DEBUG_VIDENC(phys_enc, "\n"); + DPU_DEBUG_VIDENC(phys_enc, "\n"); /* * Modifying mode has consequences when the mode comes back to us @@ -239,7 +238,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( unsigned long lock_flags; struct dpu_hw_intf_cfg intf_cfg = { 0 }; - if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) { + if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { DPU_ERROR("invalid encoder %d\n", phys_enc != 0); return; } @@ -293,9 +292,6 @@ static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) u32 flush_register = 0; int new_cnt = -1, old_cnt = -1; - if (!phys_enc) - return; - hw_ctl = phys_enc->hw_ctl; DPU_ATRACE_BEGIN("vblank_irq"); @@ -333,9 +329,6 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) { struct dpu_encoder_phys *phys_enc = arg; - if (!phys_enc) - return; - if (phys_enc->parent_ops->handle_underrun_virt) phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, phys_enc); @@ -372,11 +365,6 @@ static void dpu_encoder_phys_vid_mode_set( struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { - if (!phys_enc) { - DPU_ERROR("invalid encoder/kms\n"); - return; - } - if (adj_mode) { phys_enc->cached_mode = *adj_mode; drm_mode_debug_printmodeline(adj_mode); @@ -393,11 +381,6 @@ static int dpu_encoder_phys_vid_control_vblank_irq( int ret = 0; int refcount; - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return -EINVAL; - } - refcount = atomic_read(&phys_enc->vblank_refcount); /* Slave encoders don't report vblank */ @@ -469,11 +452,6 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) { - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } - DPU_DEBUG_VIDENC(phys_enc, "\n"); kfree(phys_enc); } @@ -491,11 +469,6 @@ static int dpu_encoder_phys_vid_wait_for_vblank( struct dpu_encoder_wait_info wait_info; int ret; - if (!phys_enc) { - pr_err("invalid encoder\n"); - return -EINVAL; - } - wait_info.wq = &phys_enc->pending_kickoff_wq; wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; @@ -541,11 +514,6 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( struct dpu_hw_ctl *ctl; int rc; - if (!phys_enc) { - DPU_ERROR("invalid encoder/parameters\n"); - return; - } - ctl = phys_enc->hw_ctl; if (!ctl->ops.wait_reset_status) return; @@ -567,7 +535,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) unsigned long lock_flags; int ret; - if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev) { + if (!phys_enc->parent || !phys_enc->parent->dev) { DPU_ERROR("invalid encoder/device\n"); return; } @@ -637,9 +605,6 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, { int ret; - if (!phys_enc) - return; - trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0, enable, @@ -660,9 +625,6 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, static int dpu_encoder_phys_vid_get_line_count( struct dpu_encoder_phys *phys_enc) { - if (!phys_enc) - return -EINVAL; - if (!dpu_encoder_phys_vid_is_master(phys_enc)) return -EINVAL;