From patchwork Fri Sep 21 04:07:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 10609047 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 968275A4 for ; Fri, 21 Sep 2018 04:18:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 820952DB6B for ; Fri, 21 Sep 2018 04:18:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 73EC52DBD5; Fri, 21 Sep 2018 04:18:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.4 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE,SUSPICIOUS_RECIPS, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EEDE92DB6B for ; Fri, 21 Sep 2018 04:18:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=1UHtDUGknjemrK+691eB0K0Rk1pXoyFvdAhS/QuaaJc=; b=lE8juwi1KjYQsH C61BdpQPJPzi0qXagrv49NWWDU6m8wusMsW6En4W7ZEKxOCjnnR4LtlkmTbsS6AIM10kPhRaZP3yu o5v3v1op5Iaf1nL8Of6xiOQJKc22x1i6JS8uWM5r3XWri4VBmgCw1HREEdB866o79UJy+DRq2CQ3H gBnId6E0Qolkr1NJT4NEeGE9O2Kc6o+Yc2c0XPfqoJOlhqHX0AXb/XfLtS7cK2GuAnN3Lqp/N+YFt fCBwluRix4noApep0SYCUzqVJarH1VMa4WAymEtMPSNiTKr3RDkvzjgW1h2m0+lkr8KfaY8Euhnp3 SDEQKu8jGFBer0ObnK/Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g3CtX-00045P-Uc; Fri, 21 Sep 2018 04:18:19 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g3CjV-0007wq-VX; Fri, 21 Sep 2018 04:08:17 +0000 X-UUID: 807b2057b45f46bdb50ce0650a1643d0-20180921 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 839456864; Fri, 21 Sep 2018 12:07:42 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Sep 2018 12:07:40 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Sep 2018 12:07:40 +0800 From: To: , Subject: [PATCH 1/4] pinctrl: mediatek: fix static checker warning caused by EINT_NA Date: Fri, 21 Sep 2018 12:07:35 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-TM-SNTS-SMTP: 65AFECEC4204B721142E7DCE6902DEBE4EBEB91D766CB7AB5D6C60707F7371862000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_210758_174352_1311F06A X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, Sean Wang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean Wang EINT_NA is an u16 number, so it should be U16_MAX instead of -1 to fix up drivers/pinctrl/mediatek/pinctrl-paris.c:732 mtk_gpio_to_irq() warn: impossible condition (desc->eint.eint_n == -1) => (0-u16max == (-1)) Also happens in drivers/pinctrl/mediatek/pinctrl-paris.c:749 mtk_gpio_set_config() warn: impossible condition (desc->eint.eint_n == -1) => (0-u16max == (-1)) drivers/pinctrl/mediatek/pinctrl-moore.c:479 mtk_gpio_to_irq() warn: impossible condition (desc->eint.eint_n == -1) => (0-u16max == (-1)) drivers/pinctrl/mediatek/pinctrl-moore.c:496 mtk_gpio_set_config() warn: impossible condition '(desc->eint.eint_n == -1) => (0-u16max == (-1)) Fixes: 6561859b067f ("pinctrl: mediatek: add eint support to MT8183 pinctrl driver") Reported-by: Dan Carpenter Signed-off-by: Sean Wang --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index 10d33ec..b618042 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -18,7 +18,7 @@ #define MTK_PULLDOWN 0 #define MTK_PULLUP 1 -#define EINT_NA -1 +#define EINT_NA U16_MAX #define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ _s_bit, _x_bits, _sz_reg, _fixed) { \ From patchwork Fri Sep 21 04:07:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 10609033 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AC455A4 for ; Fri, 21 Sep 2018 04:08:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 630402DD59 for ; Fri, 21 Sep 2018 04:08:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 54ADA2DE31; Fri, 21 Sep 2018 04:08:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2C78E2DD59 for ; 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Fri, 21 Sep 2018 04:08:42 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g3CjV-0007wQ-Dh; Fri, 21 Sep 2018 04:08:04 +0000 X-UUID: 1793ccdb406248d493b3c8de302151fd-20180921 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 293481097; Fri, 21 Sep 2018 12:07:41 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Sep 2018 12:07:40 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Sep 2018 12:07:40 +0800 From: To: , Subject: [PATCH 2/4] pinctrl: mediatek: add no eint function for pin define Date: Fri, 21 Sep 2018 12:07:36 +0800 Message-ID: <554196e837f622eea62d11602b7c88721d6a776d.1537502494.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_210757_649238_4BF92996 X-CRM114-Status: UNSURE ( 8.42 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, Sean Wang , Mars Cheng , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mars Cheng Add NO_EINT_SUPPORT back to pinctrl-mtk-common-v2.h as the alias of EINT_NA to indicate that some pin not capable of being controlled as eint and that is required by pinctrl-paris based driver as old pinctrl-mtk-common.h already had. Signed-off-by: Mars Cheng Signed-off-by: Sean Wang --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index b618042..991c1c5 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -19,6 +19,7 @@ #define MTK_PULLUP 1 #define EINT_NA U16_MAX +#define NO_EINT_SUPPORT EINT_NA #define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ _s_bit, _x_bits, _sz_reg, _fixed) { \ From patchwork Fri Sep 21 04:07:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 10609049 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 013DB5A4 for ; Fri, 21 Sep 2018 04:18:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E004B2DB6B for ; Fri, 21 Sep 2018 04:18:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CE89F2DBD1; Fri, 21 Sep 2018 04:18:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE,UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 29E652DBC8 for ; Fri, 21 Sep 2018 04:18:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5EYqpjado7QhzO5eb41gOQR/Nk0uOkWV1LbRyC3gIoA=; b=r0KaP3aP5FJrV6 tI3HreW4UdIj3fZGi7JeqomAjXrpT/jeNyc/1k9mVbpZmYpCfRvodqZYVozWrE6KM9doPPEDLf5DZ kRRMAdZMy9FnXfJJpl9Pxo7dhPkzQ8CHgiTnfqOcCVgWN0aYaVKFqnp3ePAkb0VW/shJa4UsMNaLC 1ubntz8vNRLq1Jd2Fn2zaTIotPnFo1rF06Y8SA0YZFCh/jAboDAnSfNRtDEibvwG+N1mFHcoUMRaI Bk/YF28IBujEFdPVfZYufw+JCKSILPCuhwp368DF9rMPry0vymE839ogNqcNSAVwMOCi7Mbl8we95 Q1mnuBxUDUqnIYHtc+aw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g3CtY-00045V-3x; Fri, 21 Sep 2018 04:18:20 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1g3CjV-0007wr-VY; Fri, 21 Sep 2018 04:09:59 +0000 X-UUID: e0ebc3c410c3454dad727ae8fbb016ae-20180921 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1435398441; Fri, 21 Sep 2018 12:07:42 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Sep 2018 12:07:40 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Sep 2018 12:07:40 +0800 From: To: , Subject: [PATCH 3/4] pinctrl: mediatek: add MT6765 pinctrl driver Date: Fri, 21 Sep 2018 12:07:37 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-TM-SNTS-SMTP: B9D2446918B86835470F89BEDB1C5A278A2998B02C4F0DD86271C9FA55162B272000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_210758_729398_D78985BD X-CRM114-Status: GOOD ( 11.74 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ZH Chen , Sean Wang , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mars Cheng , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: ZH Chen Add MT6765 pinctrl driver based on MediaTek pinctrl-paris core. Signed-off-by: Mars Cheng Signed-off-by: ZH Chen Signed-off-by: Sean Wang --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt6765.c | 1100 ++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h | 1754 +++++++++++++++++++++++++ 4 files changed, 2862 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6765.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 1cd5502..05be5dd 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -69,6 +69,13 @@ config PINCTRL_MT2712 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK +config PINCTRL_MT6765 + bool "Mediatek MT6765 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT7622 bool "MediaTek MT7622 pin control" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 871e0e2..70d8000 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c new file mode 100644 index 0000000..1cae634 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -0,0 +1,1100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen + * + */ + +#include "pinctrl-mtk-mt6765.h" +#include "pinctrl-paris.h" + +/* MT6765 have multiple bases to program pin configuration listed as the below: + * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800, + * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200, + * iocfg[6]:0x10002500, iocfg[7]:0x10002600. + * _i_base could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt6765_pin_mode_range[] = { + PIN_FIELD(0, 202, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6765_pin_dir_range[] = { + PIN_FIELD(0, 202, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_di_range[] = { + PIN_FIELD(0, 202, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_do_range[] = { + PIN_FIELD(0, 202, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_smt_range[] = { + PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1), + PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, 3, 0x0080, 0x10, 3, 1), + PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 9, 1), + PINS_FIELD_BASE(13, 16, 6, 0x00b0, 0x10, 10, 1), + PINS_FIELD_BASE(17, 20, 6, 0x00b0, 0x10, 8, 1), + PINS_FIELD_BASE(21, 24, 6, 0x00b0, 0x10, 9, 1), + PINS_FIELD_BASE(25, 28, 6, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 1, 1), + PINS_FIELD_BASE(31, 34, 6, 0x00b0, 0x10, 2, 1), + PINS_FIELD_BASE(35, 36, 6, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(37, 37, 6, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, 6, 0x00b0, 0x10, 4, 1), + PINS_FIELD_BASE(39, 40, 6, 0x00b0, 0x10, 3, 1), + PINS_FIELD_BASE(41, 42, 7, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(43, 43, 7, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 8, 1), + PINS_FIELD_BASE(46, 47, 7, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(48, 48, 7, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(49, 49, 7, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 7, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(51, 51, 7, 0x00c0, 0x10, 16, 1), + PINS_FIELD_BASE(52, 57, 7, 0x00c0, 0x10, 0, 1), + PINS_FIELD_BASE(58, 60, 7, 0x00c0, 0x10, 12, 1), + PINS_FIELD_BASE(61, 62, 3, 0x0080, 0x10, 5, 1), + PINS_FIELD_BASE(63, 64, 3, 0x0080, 0x10, 4, 1), + PINS_FIELD_BASE(65, 66, 3, 0x0080, 0x10, 7, 1), + PINS_FIELD_BASE(67, 68, 3, 0x0080, 0x10, 6, 1), + PINS_FIELD_BASE(69, 73, 3, 0x0080, 0x10, 1, 1), + PINS_FIELD_BASE(74, 78, 3, 0x0080, 0x10, 2, 1), + PINS_FIELD_BASE(79, 80, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(85, 85, 7, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(86, 86, 7, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(87, 87, 7, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(89, 89, 2, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 8, 1), + PINS_FIELD_BASE(91, 92, 2, 0x00b0, 0x10, 8, 1), + PINS_FIELD_BASE(93, 94, 2, 0x00b0, 0x10, 7, 1), + PINS_FIELD_BASE(95, 96, 2, 0x00b0, 0x10, 14, 1), + PINS_FIELD_BASE(97, 98, 2, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 2, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 2, 0x00b0, 0x10, 1, 1), + PINS_FIELD_BASE(101, 102, 2, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(107, 107, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(108, 108, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(110, 110, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(111, 111, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(112, 112, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(114, 114, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(115, 115, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, 5, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(135, 135, 5, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(136, 136, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(137, 137, 5, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(138, 138, 5, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(139, 139, 5, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(141, 141, 5, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(142, 142, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(143, 143, 5, 0x0060, 0x10, 3, 1), + PINS_FIELD_BASE(144, 147, 5, 0x0060, 0x10, 10, 1), + PINS_FIELD_BASE(148, 149, 5, 0x0060, 0x10, 12, 1), + PINS_FIELD_BASE(150, 151, 7, 0x00c0, 0x10, 9, 1), + PINS_FIELD_BASE(152, 153, 7, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 11, 1), + PINS_FIELD_BASE(155, 158, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(159, 159, 7, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(161, 161, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(162, 162, 1, 0x0080, 0x10, 16, 1), + PINS_FIELD_BASE(163, 170, 4, 0x0080, 0x10, 0, 1), + PINS_FIELD_BASE(171, 179, 7, 0x00c0, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 2, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(1, 1, 2, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(2, 2, 2, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(3, 3, 2, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 2, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(5, 5, 2, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(6, 6, 2, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(7, 7, 2, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(8, 8, 3, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, 2, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 2, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 2, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(21, 21, 6, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, 6, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(23, 23, 6, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, 6, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 6, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 6, 0x0040, 0x10, 3, 1), + PINS_FIELD_BASE(28, 40, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 7, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(42, 42, 7, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(45, 45, 7, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, 7, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(47, 47, 7, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(50, 50, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(52, 52, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(54, 54, 7, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(56, 56, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(57, 57, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(59, 59, 7, 0x0060, 0x10, 31, 1), + PIN_FIELD_BASE(60, 60, 7, 0x0060, 0x10, 30, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 7, 0x0060, 0x10, 29, 1), + PIN_FIELD_BASE(87, 87, 7, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(88, 88, 7, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 21, 1), + PINS_FIELD_BASE(90, 94, 3, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, 1, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(108, 108, 1, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 1, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(110, 110, 1, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(111, 111, 1, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(112, 112, 1, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 1, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(114, 114, 1, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(115, 115, 1, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 1, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 1, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 1, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(119, 119, 1, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(120, 120, 1, 0x0040, 0x10, 11, 1), + PINS_FIELD_BASE(121, 133, 1, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(134, 134, 5, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 5, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 5, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(137, 137, 5, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(138, 138, 5, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(139, 139, 5, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 5, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(141, 141, 5, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(142, 142, 5, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(147, 147, 5, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(148, 148, 5, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 7, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(151, 151, 7, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(155, 155, 3, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(156, 156, 3, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(157, 157, 3, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(158, 158, 3, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(160, 160, 5, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(161, 161, 1, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(162, 162, 1, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(164, 164, 4, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0060, 0x10, 15, 1), + PINS_FIELD_BASE(178, 179, 7, 0x0060, 0x10, 16, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 2, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(1, 1, 2, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(2, 2, 2, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(3, 3, 2, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 2, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(5, 5, 2, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(6, 6, 2, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(7, 7, 2, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(8, 8, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, 2, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 2, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 2, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(21, 21, 6, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, 6, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(23, 23, 6, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, 6, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 6, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(26, 26, 6, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(27, 27, 6, 0x0060, 0x10, 3, 1), + PINS_FIELD_BASE(28, 40, 6, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 7, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(42, 42, 7, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(45, 45, 7, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, 7, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(47, 47, 7, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(50, 50, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(52, 52, 7, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(54, 54, 7, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 7, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(56, 56, 7, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(57, 57, 7, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(59, 59, 7, 0x0080, 0x10, 31, 1), + PIN_FIELD_BASE(60, 60, 7, 0x0080, 0x10, 30, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(85, 85, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(88, 88, 7, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0060, 0x10, 21, 1), + PINS_FIELD_BASE(90, 94, 3, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(108, 108, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(110, 110, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(111, 111, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(112, 112, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(114, 114, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(115, 115, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 11, 1), + PINS_FIELD_BASE(121, 133, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(134, 134, 5, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 5, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(136, 136, 5, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(137, 137, 5, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(138, 138, 5, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(139, 139, 5, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 5, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(141, 141, 5, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(142, 142, 5, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(147, 147, 5, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(148, 148, 5, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 7, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(151, 151, 7, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(156, 156, 3, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(157, 157, 3, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(158, 158, 3, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(160, 160, 5, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(161, 161, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(162, 162, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(164, 164, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0080, 0x10, 15, 1), + PINS_FIELD_BASE(178, 179, 7, 0x0080, 0x10, 16, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_tdsel_range[] = { + PINS_FIELD_BASE(0, 3, 2, 0x00c0, 0x10, 16, 4), + PINS_FIELD_BASE(4, 7, 2, 0x00c0, 0x10, 20, 4), + PIN_FIELD_BASE(8, 8, 3, 0x0090, 0x10, 12, 4), + PINS_FIELD_BASE(9, 11, 2, 0x00c0, 0x10, 24, 4), + PIN_FIELD_BASE(12, 12, 5, 0x0080, 0x10, 4, 4), + PINS_FIELD_BASE(13, 16, 6, 0x00e0, 0x10, 8, 4), + PINS_FIELD_BASE(17, 20, 6, 0x00e0, 0x10, 0, 4), + PINS_FIELD_BASE(21, 24, 6, 0x00e0, 0x10, 4, 4), + PINS_FIELD_BASE(25, 28, 6, 0x00d0, 0x10, 28, 4), + PIN_FIELD_BASE(29, 29, 6, 0x00d0, 0x10, 0, 4), + PIN_FIELD_BASE(30, 30, 6, 0x00d0, 0x10, 4, 4), + PINS_FIELD_BASE(31, 34, 6, 0x00d0, 0x10, 8, 4), + PINS_FIELD_BASE(35, 36, 6, 0x00d0, 0x10, 20, 4), + PIN_FIELD_BASE(37, 37, 6, 0x00d0, 0x10, 24, 4), + PIN_FIELD_BASE(38, 38, 6, 0x00d0, 0x10, 16, 4), + PINS_FIELD_BASE(39, 40, 6, 0x00d0, 0x10, 12, 4), + PINS_FIELD_BASE(41, 42, 7, 0x00d0, 0x10, 24, 4), + PIN_FIELD_BASE(43, 43, 7, 0x00d0, 0x10, 12, 4), + PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 16, 4), + PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 0, 4), + PINS_FIELD_BASE(46, 47, 7, 0x00d0, 0x10, 28, 4), + PINS_FIELD_BASE(48, 49, 7, 0x00e0, 0x10, 28, 4), + PINS_FIELD_BASE(50, 51, 7, 0x00e0, 0x10, 24, 4), + PINS_FIELD_BASE(52, 57, 7, 0x00d0, 0x10, 0, 4), + PINS_FIELD_BASE(58, 60, 7, 0x00e0, 0x10, 16, 4), + PINS_FIELD_BASE(61, 62, 3, 0x0090, 0x10, 20, 4), + PINS_FIELD_BASE(63, 64, 3, 0x0090, 0x10, 16, 4), + PINS_FIELD_BASE(65, 66, 3, 0x0090, 0x10, 28, 4), + PINS_FIELD_BASE(67, 68, 3, 0x0090, 0x10, 24, 4), + PINS_FIELD_BASE(69, 73, 3, 0x0090, 0x10, 4, 4), + PINS_FIELD_BASE(74, 78, 3, 0x0090, 0x10, 8, 4), + PINS_FIELD_BASE(79, 80, 3, 0x0090, 0x10, 0, 4), + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 8, 4), + PINS_FIELD_BASE(82, 83, 3, 0x00a0, 0x10, 4, 4), + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 8, 4), + PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 16, 4), + PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 20, 4), + PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 8, 4), + PIN_FIELD_BASE(88, 88, 7, 0x00d0, 0x10, 4, 4), + PIN_FIELD_BASE(89, 89, 2, 0x00d0, 0x10, 12, 4), + PIN_FIELD_BASE(90, 90, 3, 0x00a0, 0x10, 0, 4), + PINS_FIELD_BASE(91, 92, 2, 0x00d0, 0x10, 0, 4), + PINS_FIELD_BASE(93, 94, 2, 0x00c0, 0x10, 28, 4), + PINS_FIELD_BASE(95, 96, 2, 0x00d0, 0x10, 16, 4), + PINS_FIELD_BASE(97, 98, 2, 0x00c0, 0x10, 8, 4), + PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 0, 4), + PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 4, 4), + PINS_FIELD_BASE(101, 102, 2, 0x00c0, 0x10, 12, 4), + PINS_FIELD_BASE(103, 104, 2, 0x00d0, 0x10, 4, 4), + PINS_FIELD_BASE(105, 106, 2, 0x00d0, 0x10, 8, 4), + PIN_FIELD_BASE(107, 107, 1, 0x0090, 0x10, 16, 4), + PIN_FIELD_BASE(108, 108, 1, 0x0090, 0x10, 12, 4), + PIN_FIELD_BASE(109, 109, 1, 0x0090, 0x10, 20, 4), + PIN_FIELD_BASE(110, 110, 1, 0x0090, 0x10, 0, 4), + PIN_FIELD_BASE(111, 111, 1, 0x0090, 0x10, 4, 4), + PIN_FIELD_BASE(112, 112, 1, 0x0090, 0x10, 8, 4), + PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 4, 4), + PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 8, 4), + PIN_FIELD_BASE(115, 115, 1, 0x0090, 0x10, 24, 4), + PIN_FIELD_BASE(116, 116, 1, 0x0090, 0x10, 28, 4), + PIN_FIELD_BASE(117, 117, 1, 0x00a0, 0x10, 16, 4), + PIN_FIELD_BASE(118, 118, 1, 0x00a0, 0x10, 20, 4), + PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 24, 4), + PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 12, 4), + PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 0, 4), + PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 8, 4), + PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 12, 4), + PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 4, 4), + PINS_FIELD_BASE(125, 130, 4, 0x0090, 0x10, 12, 4), + PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 16, 4), + PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 12, 4), + PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 20, 4), + PIN_FIELD_BASE(134, 134, 5, 0x0080, 0x10, 12, 4), + PIN_FIELD_BASE(135, 135, 5, 0x0080, 0x10, 20, 4), + PIN_FIELD_BASE(136, 136, 5, 0x0070, 0x10, 4, 4), + PIN_FIELD_BASE(137, 137, 5, 0x0070, 0x10, 28, 4), + PIN_FIELD_BASE(138, 138, 5, 0x0070, 0x10, 16, 4), + PIN_FIELD_BASE(139, 139, 5, 0x0070, 0x10, 20, 4), + PIN_FIELD_BASE(140, 140, 5, 0x0070, 0x10, 0, 4), + PIN_FIELD_BASE(141, 141, 5, 0x0070, 0x10, 24, 4), + PIN_FIELD_BASE(142, 142, 5, 0x0070, 0x10, 8, 4), + PIN_FIELD_BASE(143, 143, 5, 0x0070, 0x10, 12, 4), + PINS_FIELD_BASE(144, 147, 5, 0x0080, 0x10, 8, 4), + PINS_FIELD_BASE(148, 149, 5, 0x0080, 0x10, 16, 4), + PINS_FIELD_BASE(150, 151, 7, 0x00e0, 0x10, 4, 4), + PINS_FIELD_BASE(152, 153, 7, 0x00e0, 0x10, 8, 4), + PIN_FIELD_BASE(154, 154, 7, 0x00e0, 0x10, 12, 4), + PINS_FIELD_BASE(155, 158, 3, 0x00a0, 0x10, 12, 4), + PIN_FIELD_BASE(159, 159, 7, 0x00e0, 0x10, 12, 4), + PIN_FIELD_BASE(160, 160, 5, 0x0080, 0x10, 0, 4), + PINS_FIELD_BASE(161, 162, 1, 0x00a0, 0x10, 28, 4), + PINS_FIELD_BASE(163, 170, 4, 0x0090, 0x10, 0, 4), + PINS_FIELD_BASE(171, 179, 7, 0x00d0, 0x10, 20, 4), +}; + +static const struct mtk_pin_field_calc mt6765_pin_rdsel_range[] = { + PINS_FIELD_BASE(0, 3, 2, 0x0090, 0x10, 8, 2), + PINS_FIELD_BASE(4, 7, 2, 0x0090, 0x10, 10, 2), + PIN_FIELD_BASE(8, 8, 3, 0x0060, 0x10, 6, 2), + PINS_FIELD_BASE(9, 11, 2, 0x0090, 0x10, 12, 2), + PIN_FIELD_BASE(12, 12, 5, 0x0050, 0x10, 18, 2), + PINS_FIELD_BASE(13, 16, 6, 0x00a0, 0x10, 18, 2), + PINS_FIELD_BASE(17, 20, 6, 0x00a0, 0x10, 14, 2), + PINS_FIELD_BASE(21, 24, 6, 0x00a0, 0x10, 16, 2), + PINS_FIELD_BASE(25, 28, 6, 0x00a0, 0x10, 12, 2), + PIN_FIELD_BASE(29, 29, 6, 0x0090, 0x10, 0, 6), + PIN_FIELD_BASE(30, 30, 6, 0x0090, 0x10, 6, 6), + PINS_FIELD_BASE(31, 34, 6, 0x0090, 0x10, 12, 6), + PINS_FIELD_BASE(35, 36, 6, 0x00a0, 0x10, 0, 6), + PIN_FIELD_BASE(37, 37, 6, 0x00a0, 0x10, 6, 6), + PIN_FIELD_BASE(38, 38, 6, 0x0090, 0x10, 24, 6), + PINS_FIELD_BASE(39, 40, 6, 0x0090, 0x10, 18, 6), + PINS_FIELD_BASE(41, 42, 7, 0x00a0, 0x10, 12, 2), + PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 6, 2), + PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 8, 2), + PIN_FIELD_BASE(45, 45, 7, 0x00a0, 0x10, 16, 2), + PINS_FIELD_BASE(46, 47, 7, 0x00a0, 0x10, 14, 2), + PINS_FIELD_BASE(48, 49, 7, 0x00a0, 0x10, 30, 2), + PINS_FIELD_BASE(50, 51, 7, 0x00a0, 0x10, 28, 2), + PINS_FIELD_BASE(52, 57, 7, 0x00a0, 0x10, 0, 2), + PINS_FIELD_BASE(58, 60, 7, 0x00a0, 0x10, 24, 2), + PINS_FIELD_BASE(61, 62, 3, 0x0060, 0x10, 10, 2), + PINS_FIELD_BASE(63, 64, 3, 0x0060, 0x10, 8, 2), + PINS_FIELD_BASE(65, 66, 3, 0x0060, 0x10, 14, 2), + PINS_FIELD_BASE(67, 68, 3, 0x0060, 0x10, 12, 2), + PINS_FIELD_BASE(69, 73, 3, 0x0060, 0x10, 2, 2), + PINS_FIELD_BASE(74, 78, 3, 0x0060, 0x10, 4, 2), + PINS_FIELD_BASE(79, 80, 3, 0x0060, 0x10, 0, 2), + PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 20, 2), + PINS_FIELD_BASE(82, 83, 3, 0x0060, 0x10, 18, 2), + PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 20, 2), + PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 24, 2), + PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 26, 2), + PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 4, 2), + PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 2, 2), + PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 22, 2), + PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 16, 2), + PINS_FIELD_BASE(91, 92, 2, 0x0090, 0x10, 16, 2), + PINS_FIELD_BASE(93, 94, 2, 0x0090, 0x10, 14, 2), + PINS_FIELD_BASE(95, 96, 2, 0x0090, 0x10, 24, 2), + PINS_FIELD_BASE(97, 98, 2, 0x0090, 0x10, 4, 2), + PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 0, 2), + PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 2, 2), + PINS_FIELD_BASE(101, 102, 2, 0x0090, 0x10, 6, 2), + PINS_FIELD_BASE(103, 104, 2, 0x0090, 0x10, 18, 2), + PINS_FIELD_BASE(105, 106, 2, 0x0090, 0x10, 20, 2), + PIN_FIELD_BASE(107, 107, 1, 0x0060, 0x10, 8, 2), + PIN_FIELD_BASE(108, 108, 1, 0x0060, 0x10, 6, 2), + PIN_FIELD_BASE(109, 109, 1, 0x0060, 0x10, 10, 2), + PIN_FIELD_BASE(110, 110, 1, 0x0060, 0x10, 0, 2), + PIN_FIELD_BASE(111, 111, 1, 0x0060, 0x10, 2, 2), + PIN_FIELD_BASE(112, 112, 1, 0x0060, 0x10, 4, 2), + PIN_FIELD_BASE(113, 113, 1, 0x0060, 0x10, 18, 2), + PIN_FIELD_BASE(114, 114, 1, 0x0060, 0x10, 20, 2), + PIN_FIELD_BASE(115, 115, 1, 0x0060, 0x10, 12, 2), + PIN_FIELD_BASE(116, 116, 1, 0x0060, 0x10, 14, 2), + PIN_FIELD_BASE(117, 117, 1, 0x0060, 0x10, 24, 2), + PIN_FIELD_BASE(118, 118, 1, 0x0060, 0x10, 26, 2), + PIN_FIELD_BASE(119, 119, 1, 0x0060, 0x10, 28, 2), + PIN_FIELD_BASE(120, 120, 1, 0x0060, 0x10, 22, 2), + PIN_FIELD_BASE(121, 121, 1, 0x0060, 0x10, 16, 2), + PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 8, 6), + PIN_FIELD_BASE(123, 123, 4, 0x0070, 0x10, 14, 6), + PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 2, 6), + PINS_FIELD_BASE(125, 130, 4, 0x0070, 0x10, 14, 6), + PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 20, 6), + PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 14, 6), + PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 26, 6), + PIN_FIELD_BASE(134, 134, 5, 0x0050, 0x10, 22, 2), + PIN_FIELD_BASE(135, 135, 5, 0x0050, 0x10, 30, 2), + PIN_FIELD_BASE(136, 136, 5, 0x0050, 0x10, 2, 2), + PIN_FIELD_BASE(137, 137, 5, 0x0050, 0x10, 14, 2), + PIN_FIELD_BASE(138, 138, 5, 0x0050, 0x10, 8, 2), + PIN_FIELD_BASE(139, 139, 5, 0x0050, 0x10, 10, 2), + PIN_FIELD_BASE(140, 140, 5, 0x0050, 0x10, 0, 2), + PIN_FIELD_BASE(141, 141, 5, 0x0050, 0x10, 12, 2), + PIN_FIELD_BASE(142, 142, 5, 0x0050, 0x10, 4, 2), + PIN_FIELD_BASE(143, 143, 5, 0x0050, 0x10, 6, 2), + PINS_FIELD_BASE(144, 147, 5, 0x0050, 0x10, 20, 2), + PINS_FIELD_BASE(148, 149, 5, 0x0050, 0x10, 24, 2), + PINS_FIELD_BASE(150, 151, 7, 0x00a0, 0x10, 18, 2), + PINS_FIELD_BASE(152, 153, 7, 0x00a0, 0x10, 20, 2), + PIN_FIELD_BASE(154, 154, 7, 0x00a0, 0x10, 22, 2), + PINS_FIELD_BASE(155, 158, 3, 0x0060, 0x10, 22, 2), + PIN_FIELD_BASE(159, 159, 7, 0x00a0, 0x10, 22, 2), + PIN_FIELD_BASE(160, 160, 5, 0x0050, 0x10, 16, 2), + PINS_FIELD_BASE(161, 162, 1, 0x0060, 0x10, 30, 2), + PINS_FIELD_BASE(163, 170, 4, 0x0070, 0x10, 0, 2), + PINS_FIELD_BASE(171, 179, 7, 0x00a0, 0x10, 10, 2), +}; + +static const struct mtk_pin_field_calc mt6765_pin_drv_range[] = { + PINS_FIELD_BASE(0, 2, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(3, 3, 2, 0x0000, 0x10, 15, 3), + PINS_FIELD_BASE(4, 6, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(7, 7, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(8, 8, 3, 0x0000, 0x10, 9, 3), + PINS_FIELD_BASE(9, 11, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, 5, 0x0000, 0x10, 27, 3), + PINS_FIELD_BASE(13, 15, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 23, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 26, 3), + PINS_FIELD_BASE(19, 20, 6, 0x0000, 0x10, 23, 3), + PINS_FIELD_BASE(21, 23, 6, 0x0000, 0x10, 29, 3), + PIN_FIELD_BASE(24, 24, 6, 0x0010, 0x10, 0, 3), + PINS_FIELD_BASE(25, 27, 6, 0x0000, 0x10, 17, 3), + PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 20, 3), + PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, 6, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(31, 34, 6, 0x0000, 0x10, 6, 3), + PINS_FIELD_BASE(35, 36, 6, 0x0000, 0x10, 13, 2), + PIN_FIELD_BASE(37, 37, 6, 0x0000, 0x10, 15, 2), + PIN_FIELD_BASE(38, 38, 6, 0x0000, 0x10, 11, 2), + PINS_FIELD_BASE(39, 40, 6, 0x0000, 0x10, 9, 2), + PINS_FIELD_BASE(41, 42, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(43, 43, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(44, 44, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(45, 45, 7, 0x0000, 0x10, 27, 3), + PINS_FIELD_BASE(46, 47, 7, 0x0000, 0x10, 24, 3), + PINS_FIELD_BASE(48, 49, 7, 0x0010, 0x10, 18, 3), + PINS_FIELD_BASE(50, 51, 7, 0x0010, 0x10, 15, 3), + PINS_FIELD_BASE(52, 57, 7, 0x0000, 0x10, 0, 3), + PINS_FIELD_BASE(58, 60, 7, 0x0010, 0x10, 9, 3), + PINS_FIELD_BASE(61, 62, 3, 0x0000, 0x10, 15, 3), + PINS_FIELD_BASE(63, 64, 3, 0x0000, 0x10, 12, 3), + PINS_FIELD_BASE(65, 66, 3, 0x0000, 0x10, 21, 3), + PINS_FIELD_BASE(67, 68, 3, 0x0000, 0x10, 18, 3), + PINS_FIELD_BASE(69, 73, 3, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(74, 78, 3, 0x0000, 0x10, 6, 3), + PINS_FIELD_BASE(79, 80, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 0, 3), + PINS_FIELD_BASE(82, 83, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(87, 87, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(88, 88, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(89, 89, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(93, 93, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 0, 3), + PINS_FIELD_BASE(95, 96, 2, 0x0010, 0x10, 18, 3), + PINS_FIELD_BASE(97, 98, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(99, 99, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 2, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(101, 102, 2, 0x0000, 0x10, 9, 3), + PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 9, 3), + PINS_FIELD_BASE(105, 106, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(107, 107, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(108, 108, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(114, 114, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(119, 119, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(120, 120, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0000, 0x10, 6, 3), + PINS_FIELD_BASE(125, 130, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(133, 133, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(134, 134, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(135, 135, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(136, 136, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(137, 137, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(138, 138, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(139, 139, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(140, 140, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(141, 141, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(143, 143, 5, 0x0000, 0x10, 9, 3), + PINS_FIELD_BASE(144, 146, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(147, 147, 5, 0x0010, 0x10, 3, 3), + PINS_FIELD_BASE(148, 149, 5, 0x0010, 0x10, 9, 3), + PINS_FIELD_BASE(150, 151, 7, 0x0010, 0x10, 0, 3), + PINS_FIELD_BASE(152, 153, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 6, 3), + PINS_FIELD_BASE(155, 157, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(158, 158, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(159, 159, 7, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 24, 3), + PINS_FIELD_BASE(161, 162, 1, 0x0010, 0x10, 15, 3), + PINS_FIELD_BASE(163, 166, 4, 0x0000, 0x10, 0, 3), + PINS_FIELD_BASE(167, 170, 4, 0x0000, 0x10, 3, 3), + PINS_FIELD_BASE(171, 174, 7, 0x0000, 0x10, 18, 3), + PINS_FIELD_BASE(175, 179, 7, 0x0000, 0x10, 15, 3), +}; + +static const struct mtk_pin_field_calc mt6765_pin_pupd_range[] = { + PINS_FIELD_BASE(0, 28, 0, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(36, 36, 6, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(37, 37, 6, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(38, 38, 6, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(39, 39, 6, 0x0050, 0x10, 8, 1), + PINS_FIELD_BASE(40, 90, 6, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0050, 0x10, 0, 1), + PINS_FIELD_BASE(94, 121, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0030, 0x10, 5, 1), + PINS_FIELD_BASE(133, 179, 4, 0x0030, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_r0_range[] = { + PINS_FIELD_BASE(0, 28, 4, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(36, 36, 6, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(37, 37, 6, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(38, 38, 6, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(39, 39, 6, 0x0070, 0x10, 8, 1), + PINS_FIELD_BASE(40, 90, 6, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 0, 1), + PINS_FIELD_BASE(94, 121, 2, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0050, 0x10, 5, 1), + PINS_FIELD_BASE(133, 179, 4, 0x0050, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_r1_range[] = { + PINS_FIELD_BASE(0, 28, 4, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(38, 38, 6, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(39, 39, 6, 0x0080, 0x10, 8, 1), + PINS_FIELD_BASE(40, 90, 6, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 0, 1), + PINS_FIELD_BASE(94, 121, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 5, 1), + PINS_FIELD_BASE(133, 179, 4, 0x0060, 0x10, 11, 1), +}; + +static const struct mtk_pin_field_calc mt6765_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 2, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(1, 1, 2, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(2, 2, 2, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(3, 3, 2, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 2, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(5, 5, 2, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(6, 6, 2, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(7, 7, 2, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(8, 8, 3, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, 5, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 26, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 25, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 27, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0020, 0x10, 24, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0020, 0x10, 19, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 16, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 18, 1), + PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 17, 1), + PIN_FIELD_BASE(21, 21, 6, 0x0020, 0x10, 22, 1), + PIN_FIELD_BASE(22, 22, 6, 0x0020, 0x10, 21, 1), + PIN_FIELD_BASE(23, 23, 6, 0x0020, 0x10, 23, 1), + PIN_FIELD_BASE(24, 24, 6, 0x0020, 0x10, 20, 1), + PIN_FIELD_BASE(25, 25, 6, 0x0020, 0x10, 14, 1), + PIN_FIELD_BASE(26, 26, 6, 0x0020, 0x10, 13, 1), + PIN_FIELD_BASE(27, 27, 6, 0x0020, 0x10, 15, 1), + PIN_FIELD_BASE(28, 28, 6, 0x0020, 0x10, 12, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, 6, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 6, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, 6, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(35, 35, 6, 0x0020, 0x10, 10, 1), + PIN_FIELD_BASE(36, 36, 6, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(37, 37, 6, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(38, 38, 6, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(39, 39, 6, 0x0020, 0x10, 8, 1), + PIN_FIELD_BASE(40, 40, 6, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(41, 41, 7, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(42, 42, 7, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(45, 45, 7, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, 7, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(47, 47, 7, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(48, 48, 7, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 7, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(50, 50, 7, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(51, 51, 7, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(52, 52, 7, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 7, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(54, 54, 7, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(55, 55, 7, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(56, 56, 7, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(57, 57, 7, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(58, 58, 7, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(59, 59, 7, 0x0040, 0x10, 31, 1), + PIN_FIELD_BASE(60, 60, 7, 0x0040, 0x10, 30, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 24, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 22, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 7, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(87, 87, 7, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(88, 88, 7, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0030, 0x10, 27, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0030, 0x10, 22, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0030, 0x10, 24, 1), + PIN_FIELD_BASE(107, 107, 1, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(108, 108, 1, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 1, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(110, 110, 1, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(111, 111, 1, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(112, 112, 1, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, 1, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(114, 114, 1, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(115, 115, 1, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(116, 116, 1, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 1, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 1, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(119, 119, 1, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(120, 120, 1, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 1, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 10, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 8, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 12, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 14, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 16, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 15, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 17, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 18, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0010, 0x10, 19, 1), + PIN_FIELD_BASE(134, 134, 5, 0x0020, 0x10, 14, 1), + PIN_FIELD_BASE(135, 135, 5, 0x0020, 0x10, 17, 1), + PIN_FIELD_BASE(136, 136, 5, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(137, 137, 5, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(138, 138, 5, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(139, 139, 5, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 5, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(141, 141, 5, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(142, 142, 5, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 12, 1), + PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 13, 1), + PIN_FIELD_BASE(147, 147, 5, 0x0020, 0x10, 10, 1), + PIN_FIELD_BASE(148, 148, 5, 0x0020, 0x10, 15, 1), + PIN_FIELD_BASE(149, 149, 5, 0x0020, 0x10, 16, 1), + PIN_FIELD_BASE(150, 150, 7, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(151, 151, 7, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(155, 155, 3, 0x0030, 0x10, 28, 1), + PIN_FIELD_BASE(156, 156, 3, 0x0030, 0x10, 27, 1), + PIN_FIELD_BASE(157, 157, 3, 0x0030, 0x10, 29, 1), + PIN_FIELD_BASE(158, 158, 3, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 8, 1), + PIN_FIELD_BASE(161, 161, 1, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(162, 162, 1, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 1, 1), + PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 2, 1), + PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 1), + PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 4, 1), + PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 5, 1), + PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 6, 1), + PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 7, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 15, 1), + PINS_FIELD_BASE(178, 179, 7, 0x0040, 0x10, 16, 1), +}; + +static const struct mtk_pin_reg_calc mt6765_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6765_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6765_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6765_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6765_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6765_pin_smt_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6765_pin_pd_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6765_pin_pu_range), + [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6765_pin_tdsel_range), + [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6765_pin_rdsel_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6765_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6765_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6765_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6765_pin_r1_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6765_pin_ies_range), +}; + +static const char * const mt6765_pinctrl_register_base_names[] = { + "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", +}; + +static const struct mtk_pin_soc mt6765_data = { + .reg_cal = mt6765_reg_cals, + .pins = mtk_pins_mt6765, + .npins = ARRAY_SIZE(mtk_pins_mt6765), + .ngrps = ARRAY_SIZE(mtk_pins_mt6765), + .gpio_m = 0, + .ies_present = true, + .base_names = mt6765_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt6765_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6765-pinctrl", }, + { } +}; + +static int mt6765_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_paris_pinctrl_probe(pdev, &mt6765_data); +} + +static struct platform_driver mt6765_pinctrl_driver = { + .driver = { + .name = "mt6765-pinctrl", + .of_match_table = mt6765_pinctrl_of_match, + }, + .probe = mt6765_pinctrl_probe, +}; + +static int __init mt6765_pinctrl_init(void) +{ + return platform_driver_register(&mt6765_pinctrl_driver); +} +arch_initcall(mt6765_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h new file mode 100644 index 0000000..7725637 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h @@ -0,0 +1,1754 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen + * + */ + +#ifndef __PINCTRL_MTK_MT6765_H +#define __PINCTRL_MTK_MT6765_H + +#include "pinctrl-paris.h" + +static struct mtk_pin_desc mtk_pins_mt6765[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "I2S0_MCK"), + MTK_FUNCTION(5, "MD_UTXD1"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(4, "I2S0_BCK"), + MTK_FUNCTION(5, "MD_URXD1"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "UCTS0"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "I2S0_LRCK"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "URTS0"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "SPI1_B_MI"), + MTK_FUNCTION(2, "SCP_SPI1_MI"), + MTK_FUNCTION(3, "UCTS0"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "SSPM_URXD_AO"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI1_B_CSB"), + MTK_FUNCTION(2, "SCP_SPI1_CS"), + MTK_FUNCTION(3, "URTS0"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "SSPM_UTXD_AO"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI1_B_MO"), + MTK_FUNCTION(2, "SCP_SPI1_MO"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "MD_UTXD0"), + MTK_FUNCTION(6, "TP_GPIO6_AO") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI1_B_CLK"), + MTK_FUNCTION(2, "SCP_SPI1_CK"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "MD_URXD0"), + MTK_FUNCTION(6, "TP_GPIO7_AO") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "SRCLKENAI0"), + MTK_FUNCTION(3, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "MFG_JTAG_TRSTN"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "JTRSTN_SEL1") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "MD_INT0"), + MTK_FUNCTION(2, "CMMCLK2"), + MTK_FUNCTION(3, "CONN_MCU_TRST_B"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "SDA_6306"), + MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "EXT_FRAME_SYNC"), + MTK_FUNCTION(6, "CMVREF1"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "ANT_SEL6"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "EXT_FRAME_SYNC"), + MTK_FUNCTION(6, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "PWM0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "MD_INT0"), + MTK_FUNCTION(5, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(6, "URTS1") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "SPI4_MI"), + MTK_FUNCTION(3, "SCP_SPI0_MI"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(6, "I2S0_MCK"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "SPI4_CSB"), + MTK_FUNCTION(3, "SCP_SPI0_CS"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "I2S0_BCK"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "SPI4_MO"), + MTK_FUNCTION(3, "SCP_SPI0_MO"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(6, "I2S0_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "SPI4_CLK"), + MTK_FUNCTION(3, "SCP_SPI0_CK"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "SPI2_MO"), + MTK_FUNCTION(3, "SCP_SPI0_MO"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "I2S0_DI"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "SPI2_CLK"), + MTK_FUNCTION(3, "SCP_SPI0_CK"), + MTK_FUNCTION(4, "MD_INT0"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "I2S3_BCK"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "SPI2_MI"), + MTK_FUNCTION(3, "SCP_SPI0_MI"), + MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(6, "I2S3_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "ANT_SEL7"), + MTK_FUNCTION(2, "SPI2_CSB"), + MTK_FUNCTION(3, "SCP_SPI0_CS"), + MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(5, "CMMCLK3"), + MTK_FUNCTION(6, "I2S3_DO"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "SPI3_MI"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "DAP_MD32_SWD"), + MTK_FUNCTION(4, "CMVREF0"), + MTK_FUNCTION(5, "SCP_SPI0_MI"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "SPI3_CSB"), + MTK_FUNCTION(2, "SRCLKENAI0"), + MTK_FUNCTION(3, "DAP_MD32_SWCK"), + MTK_FUNCTION(4, "CMVREF1"), + MTK_FUNCTION(5, "SCP_SPI0_CS"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "SPI3_MO"), + MTK_FUNCTION(2, "PWM0"), + MTK_FUNCTION(3, "KPROW7"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "SCP_SPI0_MO"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "SPI3_CLK"), + MTK_FUNCTION(2, "UDI_TCK"), + MTK_FUNCTION(3, "IO_JTAG_TCK"), + MTK_FUNCTION(4, "SSPM_JTAG_TCK"), + MTK_FUNCTION(5, "SCP_SPI0_CK"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "SPI1_A_MI"), + MTK_FUNCTION(2, "UDI_TMS"), + MTK_FUNCTION(3, "IO_JTAG_TMS"), + MTK_FUNCTION(4, "SSPM_JTAG_TMS"), + MTK_FUNCTION(5, "KPROW3"), + MTK_FUNCTION(6, "I2S1_MCK"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "SPI1_A_CSB"), + MTK_FUNCTION(2, "UDI_TDI"), + MTK_FUNCTION(3, "IO_JTAG_TDI"), + MTK_FUNCTION(4, "SSPM_JTAG_TDI"), + MTK_FUNCTION(5, "KPROW4"), + MTK_FUNCTION(6, "I2S1_BCK"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "SPI1_A_MO"), + MTK_FUNCTION(2, "UDI_TDO"), + MTK_FUNCTION(3, "IO_JTAG_TDO"), + MTK_FUNCTION(4, "SSPM_JTAG_TDO"), + MTK_FUNCTION(5, "KPROW5"), + MTK_FUNCTION(6, "I2S1_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "SPI1_A_CLK"), + MTK_FUNCTION(2, "UDI_NTRST"), + MTK_FUNCTION(3, "IO_JTAG_TRSTN"), + MTK_FUNCTION(4, "SSPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "KPROW6"), + MTK_FUNCTION(6, "I2S1_DO"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "IO_JTAG_TCK"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(4, "CONN_DSP_JCK"), + MTK_FUNCTION(5, "SSPM_JTAG_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "IO_JTAG_TMS"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "CONN_DSP_JMS"), + MTK_FUNCTION(5, "SSPM_JTAG_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "MSDC1_DAT3") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "IO_JTAG_TDI"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "CONN_DSP_JDI"), + MTK_FUNCTION(5, "SSPM_JTAG_TDI") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "IO_JTAG_TRSTN"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "CONN_DSP_JINTP"), + MTK_FUNCTION(5, "SSPM_JTAG_TRSTN") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "IO_JTAG_TDO"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "CONN_DSP_JDO"), + MTK_FUNCTION(5, "SSPM_JTAG_TDO") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "CCU_JTAG_TDO"), + MTK_FUNCTION(3, "MD1_SIM1_SIO"), + MTK_FUNCTION(5, "SCP_JTAG_TDO"), + MTK_FUNCTION(6, "CONN_DSP_JDO"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "CCU_JTAG_TMS"), + MTK_FUNCTION(3, "MD1_SIM1_SRST"), + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(5, "SCP_JTAG_TMS"), + MTK_FUNCTION(6, "CONN_DSP_JMS"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "CCU_JTAG_TDI"), + MTK_FUNCTION(3, "MD1_SIM1_SCLK"), + MTK_FUNCTION(5, "SCP_JTAG_TDI"), + MTK_FUNCTION(6, "CONN_DSP_JDI"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "MD1_SIM2_SCLK"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "CCU_JTAG_TCK"), + MTK_FUNCTION(3, "MD1_SIM2_SRST"), + MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(5, "SCP_JTAG_TCK"), + MTK_FUNCTION(6, "CONN_DSP_JCK"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "CCU_JTAG_TRST"), + MTK_FUNCTION(3, "MD1_SIM2_SIO"), + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(6, "CONN_DSP_JINTP"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "UCTS0"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "SSPM_UTXD_AO"), + MTK_FUNCTION(6, "MD_INT0"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "USB_DRVVBUS"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "URTS0"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(5, "SSPM_URXD_AO"), + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "SCL_6306"), + MTK_FUNCTION(6, "TP_UCTS1_AO"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "SDA_6306"), + MTK_FUNCTION(6, "TP_URTS1_AO"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "TP_URXD1_AO"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "TP_UTXD1_AO"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "BPI_BUS15") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "BPI_BUS13") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "BPI_BUS12") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "BPI_BUS8") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "SCL_6306") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "SDA_6306") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "RFIC0_BSI_D2") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "RFIC0_BSI_D1") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "RFIC0_BSI_D0") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MIPI1_SDATA") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "MIPI1_SCLK") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "MIPI0_SDATA") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "MIPI0_SCLK") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "MIPI3_SDATA"), + MTK_FUNCTION(2, "BPI_BUS16") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "MIPI3_SCLK"), + MTK_FUNCTION(2, "BPI_BUS17") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "MIPI2_SDATA") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "MIPI2_SCLK") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "BPI_BUS7") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "BPI_BUS6") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "BPI_BUS5") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "BPI_BUS4") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "BPI_BUS3") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "BPI_BUS2") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "BPI_BUS1") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "BPI_BUS0") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "BPI_BUS14") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "BPI_BUS11") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "BPI_PA_VM1"), + MTK_FUNCTION(2, "MIPI4_SDATA") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "BPI_PA_VM0"), + MTK_FUNCTION(2, "MIPI4_SCLK") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "RFIC0_BSI_EN") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "RFIC0_BSI_CK") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "CMVREF0"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "EXT_FRAME_SYNC") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "CMVREF1"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "SCL_6306"), + MTK_FUNCTION(6, "TP_GPIO4_AO"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "PWM0"), + MTK_FUNCTION(3, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(4, "ANT_SEL4"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "MD_INT0"), + MTK_FUNCTION(4, "ANT_SEL5"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(5, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(5, "CMFLASH"), + MTK_FUNCTION(6, "CMVREF0"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "SSPM_URXD_AO"), + MTK_FUNCTION(6, "WIFI_RXD") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "SSPM_UTXD_AO"), + MTK_FUNCTION(6, "WIFI_TXD") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "UCTS0"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "CONN_MCU_TDO"), + MTK_FUNCTION(4, "SPI5_MI"), + MTK_FUNCTION(5, "SCL_6306"), + MTK_FUNCTION(6, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "URTS0"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "CONN_MCU_TMS"), + MTK_FUNCTION(4, "SPI5_CSB"), + MTK_FUNCTION(6, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(4, "AUXIF_CLK"), + MTK_FUNCTION(5, "PTA_RXD"), + MTK_FUNCTION(6, "CONN_UART0_RXD"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(4, "AUXIF_ST"), + MTK_FUNCTION(5, "PTA_TXD"), + MTK_FUNCTION(6, "CONN_UART0_TXD"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "CMFLASH"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "CONN_MCU_TCK"), + MTK_FUNCTION(4, "SPI5_MO"), + MTK_FUNCTION(6, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "CONN_MCU_TDI"), + MTK_FUNCTION(4, "SPI5_CLK"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "TP_URTS2_AO"), + MTK_FUNCTION(6, "WIFI_TXD"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "TP_UCTS2_AO"), + MTK_FUNCTION(6, "WIFI_RXD"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(5, "TP_UTXD2_AO"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(5, "TP_URXD2_AO"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "SDA_6306"), + MTK_FUNCTION(4, "KPCOL3"), + MTK_FUNCTION(5, "CMVREF0"), + MTK_FUNCTION(6, "URTS0"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "MD_INT0"), + MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(4, "KPCOL4"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "ANT_SEL7"), + MTK_FUNCTION(4, "KPCOL5"), + MTK_FUNCTION(5, "CMVREF1"), + MTK_FUNCTION(6, "UCTS0"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "PWM3"), + MTK_FUNCTION(4, "MD_INT0"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "I2S3_BCK"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "PWM4"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "CMVREF0"), + MTK_FUNCTION(6, "I2S3_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "PWM5"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "CMVREF1"), + MTK_FUNCTION(6, "I2S3_DO") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "CONN_TOP_CLK") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "CONN_TOP_DATA") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "CONN_BT_CLK") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "CONN_BT_DATA") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "CONN_WF_CTRL0") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "CONN_WF_CTRL1") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "CONN_WF_CTRL2") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "CONN_WB_PTA") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "CONN_HRST_B") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(2, "MSDC0_CMD") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(2, "MSDC0_DAT4") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(2, "MSDC0_CLK") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(2, "MSDC0_DAT5") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(2, "MSDC0_DAT2") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(2, "MSDC0_DAT1") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(2, "MSDC0_DAT6") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(2, "MSDC0_DAT0") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(2, "MSDC0_DAT7") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC0_DSL"), + MTK_FUNCTION(2, "MSDC0_DSL") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(2, "MSDC0_DAT3") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(2, "MSDC0_RSTB") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S1_MCK") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S1_BCK") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "AUD_DAT_MISO0"), + MTK_FUNCTION(3, "I2S1_LRCK") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "AUD_DAT_MISO1"), + MTK_FUNCTION(3, "I2S1_DO") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "AUD_CLK_MISO"), + MTK_FUNCTION(2, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S2_MCK") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "AUD_SYNC_MISO"), + MTK_FUNCTION(2, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S2_BCK") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S2_LRCK") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S2_DI") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "PWM0"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "ANT_SEL3"), + MTK_FUNCTION(5, "MD_URXD0"), + MTK_FUNCTION(6, "TP_URXD2_AO") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(3, "ANT_SEL4"), + MTK_FUNCTION(5, "MD_UTXD0"), + MTK_FUNCTION(6, "TP_UTXD2_AO") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "ANT_SEL5"), + MTK_FUNCTION(5, "MD_URXD1"), + MTK_FUNCTION(6, "TP_UCTS1_AO") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "ANT_SEL6"), + MTK_FUNCTION(5, "MD_UTXD1"), + MTK_FUNCTION(6, "TP_URTS1_AO") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "PWM5"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(5, "PTA_TXD"), + MTK_FUNCTION(6, "CONN_UART0_TXD") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "SPI0_MI"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "AGPS_SYNC"), + MTK_FUNCTION(4, "TP_GPIO0_AO"), + MTK_FUNCTION(5, "MFG_JTAG_TDO"), + MTK_FUNCTION(6, "DFD_TDO"), + MTK_FUNCTION(7, "JTDO_SEL1") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SPI0_CSB"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(4, "TP_GPIO1_AO"), + MTK_FUNCTION(5, "MFG_JTAG_TMS"), + MTK_FUNCTION(6, "DFD_TMS"), + MTK_FUNCTION(7, "JTMS_SEL1") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SPI0_MO"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "TP_GPIO2_AO"), + MTK_FUNCTION(5, "MFG_JTAG_TDI"), + MTK_FUNCTION(6, "DFD_TDI"), + MTK_FUNCTION(7, "JTDI_SEL1") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SPI0_CLK"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "TP_GPIO3_AO"), + MTK_FUNCTION(5, "MFG_JTAG_TCK"), + MTK_FUNCTION(6, "DFD_TCK_XI"), + MTK_FUNCTION(7, "JTCK_SEL1") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "PWM4"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "ANT_SEL7"), + MTK_FUNCTION(5, "PTA_RXD"), + MTK_FUNCTION(6, "CONN_UART0_RXD") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "TP_GPIO5_AO"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SCL_6306"), + MTK_FUNCTION(3, "TP_GPIO6_AO"), + MTK_FUNCTION(4, "KPCOL6"), + MTK_FUNCTION(5, "PTA_RXD"), + MTK_FUNCTION(6, "CONN_UART0_RXD") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SDA_6306"), + MTK_FUNCTION(3, "TP_GPIO7_AO"), + MTK_FUNCTION(4, "KPCOL7"), + MTK_FUNCTION(5, "PTA_TXD"), + MTK_FUNCTION(6, "CONN_UART0_TXD") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179") + ), +}; + +#endif /* __PINCTRL_MTK_MT6765_H */ From patchwork Fri Sep 21 04:07:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 10609035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 614885A4 for ; Fri, 21 Sep 2018 04:08:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 596282DD59 for ; Fri, 21 Sep 2018 04:08:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D40D2DE31; Fri, 21 Sep 2018 04:08:54 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Fri, 21 Sep 2018 12:07:41 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 21 Sep 2018 12:07:40 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 21 Sep 2018 12:07:40 +0800 From: To: , Subject: [PATCH 4/4] pinctrl: mediatek: add eint support to MT6765 pinctrl driver Date: Fri, 21 Sep 2018 12:07:38 +0800 Message-ID: <82d47055aec8e40422eb72568e96bfbaf199d9d2.1537502494.git.sean.wang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180920_210757_657626_2B7B18B1 X-CRM114-Status: UNSURE ( 9.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, Sean Wang , Mars Cheng , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mars Cheng Just add eint support to MT6765 pinctrl driver as usual as happens on the other SoCs. Signed-off-by: Mars Cheng Signed-off-by: Sean Wang --- drivers/pinctrl/mediatek/pinctrl-mt6765.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 1cae634..32451e8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -1056,11 +1056,19 @@ static const char * const mt6765_pinctrl_register_base_names[] = { "iocfg6", "iocfg7", }; +static const struct mtk_eint_hw mt6765_eint_hw = { + .port_mask = 7, + .ports = 6, + .ap_num = 160, + .db_cnt = 13, +}; + static const struct mtk_pin_soc mt6765_data = { .reg_cal = mt6765_reg_cals, .pins = mtk_pins_mt6765, .npins = ARRAY_SIZE(mtk_pins_mt6765), .ngrps = ARRAY_SIZE(mtk_pins_mt6765), + .eint_hw = &mt6765_eint_hw, .gpio_m = 0, .ies_present = true, .base_names = mt6765_pinctrl_register_base_names,