From patchwork Wed Dec 11 13:23:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jian Hu X-Patchwork-Id: 11284917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7275314B7 for ; Wed, 11 Dec 2019 13:24:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5AFED2464B for ; Wed, 11 Dec 2019 13:24:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729132AbfLKNYF (ORCPT ); Wed, 11 Dec 2019 08:24:05 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:17383 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727477AbfLKNYF (ORCPT ); Wed, 11 Dec 2019 08:24:05 -0500 Received: from droid15-sz.amlogic.com (10.28.8.25) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Wed, 11 Dec 2019 21:24:35 +0800 From: Jian Hu To: Jerome Brunet , Neil Armstrong CC: Jian Hu , Kevin Hilman , Rob Herring , Martin Blumenstingl , Michael Turquette , Stephen Boyd , Qiufang Dai , Jianxin Pan , Victor Wan , Chandle Zou , , , , , Subject: [PATCH v2] arm64: dts: meson: add A1 periphs and PLL clock nodes Date: Wed, 11 Dec 2019 21:23:59 +0800 Message-ID: <20191211132359.53647-1-jian.hu@amlogic.com> X-Mailer: git-send-email 2.24.0 MIME-Version: 1.0 X-Originating-IP: [10.28.8.25] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add A1 periphs and PLL clock controller nodes, Some clocks in periphs controller are the parents of PLL clocks, Meanwhile some clocks in PLL controller are those of periphs clocks. They rely on each other. Signed-off-by: Jian Hu --- Compared with the previous series, the register region is only for the clock. So syscon is not used in A1. This patch depends on A1 clock patchset at [0] Changes since v1 at [1]: -remove the compared message in commit description, And put it after the '---' -reorder order the includes -reorder the clock node -change the clock node name [0] https://lkml.kernel.org/r/20191206074052.15557-1-jian.hu@amlogic.com [1] https://lkml.kernel.org/r/20191211070835.83489-1-jian.hu@amlogic.com --- --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 7210ad049d1d..48ba3eba547d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ +#include +#include #include #include @@ -74,6 +76,21 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + clkc_periphs: clock-controller@800 { + compatible = "amlogic,a1-periphs-clkc"; + #clock-cells = <1>; + reg = <0 0x800 0 0x104>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", + "fclk_div5", "fclk_div7", + "hifi_pll", "xtal"; + }; + uart_AO: serial@1c00 { compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; @@ -93,6 +110,15 @@ clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + clkc_pll: clock-controller@7c80 { + compatible = "amlogic,a1-pll-clkc"; + #clock-cells = <1>; + reg = <0 0x7c80 0 0x21c>; + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>, + <&clkc_periphs CLKID_XTAL_HIFIPLL>; + clock-names = "xtal_fixpll", "xtal_hifipll"; + }; }; gic: interrupt-controller@ff901000 {