From patchwork Fri Sep 21 09:13:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kedar J. Karanje" X-Patchwork-Id: 10609551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDEAF112B for ; Fri, 21 Sep 2018 09:55:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BDC352DD07 for ; Fri, 21 Sep 2018 09:55:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B0E872DD0B; Fri, 21 Sep 2018 09:55:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5294A2DD07 for ; Fri, 21 Sep 2018 09:55:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0ECD6E73F; Fri, 21 Sep 2018 09:55:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5AC86E73F for ; Fri, 21 Sep 2018 09:55:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 02:55:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="82212552" Received: from kedar-linux-box.iind.intel.com ([10.66.254.48]) by FMSMGA003.fm.intel.com with ESMTP; 21 Sep 2018 02:55:37 -0700 From: kedar.j.karanje@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Sep 2018 14:43:47 +0530 Message-Id: <1537521230-22904-2-git-send-email-kedar.j.karanje@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> References: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Get active pending request for given context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Praveen Diwakar , Yogesh Marathe , Ankit Navik , Aravindan Muthukumar MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar This patch gives us the active pending request count which is yet to be submitted to the GPU Change-Id: I10c2828ad0f1a0b7af147835737134e07a2d5b6d Signed-off-by: Praveen Diwakar Signed-off-by: Yogesh Marathe Signed-off-by: Aravindan Muthukumar Signed-off-by: Kedar J Karanje Signed-off-by: Ankit Navik --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 5 +++++ drivers/gpu/drm/i915/i915_gem_context.c | 1 + drivers/gpu/drm/i915/i915_gem_context.h | 6 ++++++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +++++ drivers/gpu/drm/i915/intel_lrc.c | 6 ++++++ 6 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f8cfd16..d37c46e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -903,6 +903,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, mutex_init(&dev_priv->av_mutex); mutex_init(&dev_priv->wm.wm_mutex); mutex_init(&dev_priv->pps_mutex); + mutex_init(&dev_priv->pred_mutex); i915_memcpy_init_early(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4aca534..137ec33 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1609,6 +1609,11 @@ struct drm_i915_private { * controller on different i2c buses. */ struct mutex gmbus_mutex; + /** pred_mutex protects against councurrent usage of pending + * request counter for multiple contexts + */ + struct mutex pred_mutex; + /** * Base address of the gmbus and gpio block. */ diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b10770c..30932d9 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -387,6 +387,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, } trace_i915_context_create(ctx); + ctx->req_cnt = 0; return ctx; } diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index b116e49..243ea22 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -194,6 +194,12 @@ struct i915_gem_context { * context close. */ struct list_head handles_list; + + /** req_cnt: tracks the pending commands, based on which we decide to + * go for low/medium/high load configuration of the GPU, this is + * controlled via a mutex + */ + u64 req_cnt; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 3f0c612..f799ff9 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -2178,6 +2178,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, struct drm_syncobj **fences) { struct i915_execbuffer eb; + struct drm_i915_private *dev_priv = to_i915(dev); struct dma_fence *in_fence = NULL; struct sync_file *out_fence = NULL; int out_fence_fd = -1; @@ -2390,6 +2391,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, */ eb.request->batch = eb.batch; + mutex_lock(&dev_priv->pred_mutex); + eb.ctx->req_cnt++; + mutex_unlock(&dev_priv->pred_mutex); + trace_i915_request_queue(eb.request, eb.batch_flags); err = eb_submit(&eb); err_request: diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 1744792..039fbdb 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -728,6 +728,12 @@ static void execlists_dequeue(struct intel_engine_cs *engine) trace_i915_request_in(rq, port_index(port, execlists)); last = rq; submit = true; + + mutex_lock(&rq->i915->pred_mutex); + if (rq->gem_context->req_cnt > 0) { + rq->gem_context->req_cnt--; + } + mutex_unlock(&rq->i915->pred_mutex); } rb_erase_cached(&p->node, &execlists->queue); From patchwork Fri Sep 21 09:13:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kedar J. Karanje" X-Patchwork-Id: 10609553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3300D15E8 for ; Fri, 21 Sep 2018 09:55:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 228952DCF5 for ; Fri, 21 Sep 2018 09:55:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 163E32DD07; Fri, 21 Sep 2018 09:55:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A39DA2DCF5 for ; Fri, 21 Sep 2018 09:55:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F68E6E74C; Fri, 21 Sep 2018 09:55:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 067166E73B for ; Fri, 21 Sep 2018 09:55:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 02:55:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="82212558" Received: from kedar-linux-box.iind.intel.com ([10.66.254.48]) by FMSMGA003.fm.intel.com with ESMTP; 21 Sep 2018 02:55:40 -0700 From: kedar.j.karanje@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Sep 2018 14:43:48 +0530 Message-Id: <1537521230-22904-3-git-send-email-kedar.j.karanje@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> References: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> Subject: [Intel-gfx] [PATCH 2/4] drm/i915: Update render power clock state configuration for given context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Praveen Diwakar , Yogesh Marathe , Ankit Navik , Aravindan Muthukumar MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar This patch will update power clock state register at runtime base on the flag update_render_config which can set by any governor which computes load and want to update rpcs register. subsequent patches will have a timer based governor which computes pending load/request. Change-Id: I4e7d2f484b957d5bd496e1decc59a69e3bc6d186 Signed-off-by: Praveen Diwakar Signed-off-by: Yogesh Marathe Signed-off-by: Aravindan Muthukumar Signed-off-by: Kedar J Karanje Signed-off-by: Ankit Navik --- drivers/gpu/drm/i915/i915_gem_context.c | 5 ++++ drivers/gpu/drm/i915/i915_gem_context.h | 14 +++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 41 +++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 30932d9..2838c1d 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -388,6 +388,11 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, trace_i915_context_create(ctx); ctx->req_cnt = 0; + ctx->update_render_config = 0; + ctx->slice_cnt = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask); + ctx->subslice_cnt = hweight8( + INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); + ctx->eu_cnt = INTEL_INFO(dev_priv)->sseu.eu_per_subslice; return ctx; } diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 243ea22..52e341c 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -200,6 +200,20 @@ struct i915_gem_context { * controlled via a mutex */ u64 req_cnt; + + /** slice_cnt: used to set the # of slices to be enabled. */ + u8 slice_cnt; + + /** subslice_cnt: used to set the # of subslices to be enabled. */ + u8 subslice_cnt; + + /** eu_cnt: used to set the # of eu to be enabled. */ + u8 eu_cnt; + + /** update_render_config: to track the updates to the render + * configuration (S/SS/EU Configuration on the GPU) + */ + bool update_render_config; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 039fbdb..d2d0e7d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -364,6 +364,36 @@ execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) spin_unlock_irqrestore(&engine->timeline.lock, flags); } +static u32 +get_context_rpcs_config(struct i915_gem_context *ctx) +{ + struct drm_i915_private *dev_priv = ctx->i915; + u32 rpcs = 0; + + if (INTEL_GEN(dev_priv) < 8) + return 0; + + if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { + rpcs |= GEN8_RPCS_S_CNT_ENABLE; + rpcs |= ctx->slice_cnt << GEN8_RPCS_S_CNT_SHIFT; + rpcs |= GEN8_RPCS_ENABLE; + } + + if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { + rpcs |= GEN8_RPCS_SS_CNT_ENABLE; + rpcs |= ctx->subslice_cnt << GEN8_RPCS_SS_CNT_SHIFT; + rpcs |= GEN8_RPCS_ENABLE; + } + + if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { + rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MIN_SHIFT; + rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MAX_SHIFT; + rpcs |= GEN8_RPCS_ENABLE; + } + + return rpcs; +} + static inline void execlists_context_status_change(struct i915_request *rq, unsigned long status) { @@ -418,11 +448,22 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) static u64 execlists_update_context(struct i915_request *rq) { struct intel_context *ce = rq->hw_context; + struct i915_gem_context *ctx = rq->gem_context; + struct intel_engine_cs *engine = rq->engine; struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt; u32 *reg_state = ce->lrc_reg_state; + u32 rpcs_config = 0; reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); + if (ctx->pid && ctx->name && (rq->engine->id == RCS) && + ctx->update_render_config) { + rpcs_config = get_context_rpcs_config(ctx); + reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); + CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, + rpcs_config); + ctx->update_render_config = 0; + } /* True 32b PPGTT with dynamic page allocation: update PDP * registers and point the unallocated PDPs to scratch page. From patchwork Fri Sep 21 09:13:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kedar J. Karanje" X-Patchwork-Id: 10609559 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 502A915E8 for ; Fri, 21 Sep 2018 09:55:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 40B3D2DCF5 for ; Fri, 21 Sep 2018 09:55:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34E9F2DD07; Fri, 21 Sep 2018 09:55:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BBB142DCF5 for ; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EFAF36E750; Fri, 21 Sep 2018 09:55:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C50E6E73F for ; Fri, 21 Sep 2018 09:55:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 02:55:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="82212562" Received: from kedar-linux-box.iind.intel.com ([10.66.254.48]) by FMSMGA003.fm.intel.com with ESMTP; 21 Sep 2018 02:55:43 -0700 From: kedar.j.karanje@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Sep 2018 14:43:49 +0530 Message-Id: <1537521230-22904-4-git-send-email-kedar.j.karanje@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> References: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> Subject: [Intel-gfx] [PATCH 3/4] drm/i915: set optimum eu/slice/sub-slice configuration based on load type X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Praveen Diwakar , Yogesh Marathe , Ankit Navik , Aravindan Muthukumar MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_set_optimum_config will select optimum configuration from pre-defined optimum configuration table(opt_config). Change-Id: I3a6a2a6bdddd01b3d3c97995f5403aef3c6fa989 Signed-off-by: Praveen Diwakar Signed-off-by: Yogesh Marathe Signed-off-by: Aravindan Muthukumar Signed-off-by: Kedar J Karanje Signed-off-by: Ankit Navik --- drivers/gpu/drm/i915/i915_gem_context.c | 46 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_context.h | 32 +++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 2838c1d..1b76410 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -94,6 +94,32 @@ #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 +static struct optimum_config opt_config[TIER_VERSION_MAX][LOAD_TYPE_MAX] = { + { + /* Cherry trail low */ + { 1, 1, 4}, + /* Cherry trail medium */ + { 1, 1, 6}, + /* Cherry trail high */ + { 1, 2, 6} + }, + { + /* kbl gt2 low */ + { 2, 3, 4}, + /* kbl gt2 medium */ + { 2, 3, 6}, + /* kbl gt2 high */ + { 2, 3, 8} + }, + { + /* kbl gt3 low */ + { 2, 3, 4}, + /* kbl gt3 medium */ + { 2, 3, 6}, + /* kbl gt3 high */ + { 2, 3, 8} + } +}; static void lut_close(struct i915_gem_context *ctx) { struct i915_lut_handle *lut, *ln; @@ -393,10 +419,30 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, ctx->subslice_cnt = hweight8( INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); ctx->eu_cnt = INTEL_INFO(dev_priv)->sseu.eu_per_subslice; + ctx->load_type = 0; + ctx->prev_load_type = 0; return ctx; } + +void i915_set_optimum_config(int type, struct i915_gem_context *ctx, + enum gem_tier_versions version) +{ + struct intel_context *ce = &ctx->__engine[RCS]; + u32 *reg_state = ce->lrc_reg_state; + u32 rpcs_config = 0; + /* Call opt_config to get correct configuration for eu,slice,subslice */ + ctx->slice_cnt = (u8)opt_config[version][type].slice; + ctx->subslice_cnt = (u8)opt_config[version][type].subslice; + ctx->eu_cnt = (u8)opt_config[version][type].eu; + + /* Enabling this to update the rpcs */ + if (ctx->prev_load_type != type) + ctx->update_render_config = 1; + + ctx->prev_load_type = type; +} /** * i915_gem_context_create_gvt - create a GVT GEM context * @dev: drm device * diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 52e341c..50183e6 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -53,6 +53,26 @@ struct intel_context_ops { void (*destroy)(struct intel_context *ce); }; +enum gem_load_type { + LOAD_TYPE_LOW, + LOAD_TYPE_MEDIUM, + LOAD_TYPE_HIGH, + LOAD_TYPE_MAX +}; + +enum gem_tier_versions { + CHERRYVIEW = 0, + KABYLAKE_GT2, + KABYLAKE_GT3, + TIER_VERSION_MAX +}; + +struct optimum_config { + int slice; + int subslice; + int eu; +}; + /** * struct i915_gem_context - client state * @@ -210,6 +230,16 @@ struct i915_gem_context { /** eu_cnt: used to set the # of eu to be enabled. */ u8 eu_cnt; + /** load_type: The designated load_type (high/medium/low) for a given + * number of pending commands in the command queue. + */ + u8 load_type; + + /** prev_load_type: The earlier load type that the GPU was configured + * for (high/medium/low). + */ + u8 prev_load_type; + /** update_render_config: to track the updates to the render * configuration (S/SS/EU Configuration on the GPU) */ @@ -342,6 +372,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +void i915_set_optimum_config(int type, struct i915_gem_context *ctx, + enum gem_tier_versions version); struct i915_gem_context * i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio); From patchwork Fri Sep 21 09:13:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kedar J. Karanje" X-Patchwork-Id: 10609557 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5268A112B for ; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 412152DCF5 for ; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 35B922DD07; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D01D22DCF5 for ; Fri, 21 Sep 2018 09:55:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F4EB6E753; Fri, 21 Sep 2018 09:55:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4AC6E6E73B for ; Fri, 21 Sep 2018 09:55:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 02:55:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="82212568" Received: from kedar-linux-box.iind.intel.com ([10.66.254.48]) by FMSMGA003.fm.intel.com with ESMTP; 21 Sep 2018 02:55:46 -0700 From: kedar.j.karanje@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Sep 2018 14:43:50 +0530 Message-Id: <1537521230-22904-5-git-send-email-kedar.j.karanje@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> References: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Predictive governor to control eu/slice/subslice based on workload X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Praveen Diwakar , Yogesh Marathe , Ankit Navik , Aravindan Muthukumar MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar High resoluton timer is used for this purpose. Debugfs is provided to enable/disable/update timer configuration Change-Id: I35d692c5afe962fcad4573185bc6f744487711d0 Signed-off-by: Praveen Diwakar Signed-off-by: Yogesh Marathe Signed-off-by: Aravindan Muthukumar Signed-off-by: Kedar J Karanje Signed-off-by: Ankit Navik --- drivers/gpu/drm/i915/i915_debugfs.c | 94 ++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f9ce35d..81ba509 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4740,6 +4740,97 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_drrs_status", i915_drrs_status, 0}, {"i915_rps_boost_info", i915_rps_boost_info, 0}, }; + +#define POLL_PERIOD_MS (1000 * 1000) +#define PENDING_REQ_0 0 /* No active request pending*/ +#define PENDING_REQ_3 3 /* Threshold value of 3 active request pending*/ + /* Anything above this is considered as HIGH load + * context + */ + /* And less is considered as LOW load*/ + /* And equal is considered as mediaum load */ + +static int predictive_load_enable; +static int predictive_load_timer_init; + +static enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer) +{ + struct drm_i915_private *dev_priv = + container_of(hrtimer, typeof(*dev_priv), + pred_timer); + enum intel_engine_id id; + struct intel_engine_cs *engine; + struct i915_gem_context *ctx; + u64 req_pending; + + list_for_each_entry(ctx, &dev_priv->contexts.list, link) { + + if (!ctx->name) + continue; + + mutex_lock(&dev_priv->pred_mutex); + req_pending = ctx->req_cnt; + mutex_unlock(&dev_priv->pred_mutex); + + if (req_pending == PENDING_REQ_0) + continue; + + if (req_pending > PENDING_REQ_3) + ctx->load_type = LOAD_TYPE_HIGH; + else if (req_pending == PENDING_REQ_3) + ctx->load_type = LOAD_TYPE_MEDIUM; + else if (req_pending < PENDING_REQ_3) + ctx->load_type = LOAD_TYPE_LOW; + + i915_set_optimum_config(ctx->load_type, ctx, KABYLAKE_GT3); + } + + hrtimer_forward_now(hrtimer, + ns_to_ktime(predictive_load_enable*POLL_PERIOD_MS)); + + return HRTIMER_RESTART; +} + +static int +i915_predictive_load_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = predictive_load_enable; + return 0; +} + +static int +i915_predictive_load_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + struct intel_device_info *info; + + info = mkwrite_device_info(dev_priv); + + predictive_load_enable = val; + + if (predictive_load_enable) { + if (!predictive_load_timer_init) { + hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + dev_priv->pred_timer.function = predictive_load_cb; + predictive_load_timer_init = 1; + } + hrtimer_start(&dev_priv->pred_timer, + ns_to_ktime(predictive_load_enable*POLL_PERIOD_MS), + HRTIMER_MODE_REL_PINNED); + } else { + hrtimer_cancel(&dev_priv->pred_timer); + } + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_predictive_load_ctl, + i915_predictive_load_get, i915_predictive_load_set, + "%llu\n"); + #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) static const struct i915_debugfs_files { @@ -4769,7 +4860,8 @@ static const struct i915_debugfs_files { {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, {"i915_ipc_status", &i915_ipc_status_fops}, {"i915_drrs_ctl", &i915_drrs_ctl_fops}, - {"i915_edp_psr_debug", &i915_edp_psr_debug_fops} + {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, + {"i915_predictive_load_ctl", &i915_predictive_load_ctl} }; int i915_debugfs_register(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 137ec33..0505c47 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1552,6 +1552,7 @@ struct intel_cdclk_state { }; struct drm_i915_private { + struct hrtimer pred_timer; struct drm_device drm; struct kmem_cache *objects;