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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:05:51 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 1/7] soc: imx: gpcv2: Rename imx8mq-power.h to imx8m-power.h Date: Fri, 13 Dec 2019 10:05:36 -0600 Message-Id: <20191213160542.15757-2-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080553_903031_E7B0BBAD X-CRM114-Status: GOOD ( 12.93 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:b41 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In preparation to add support for i.MX8M Mini, this renames the existing file to be more generic, so it doesn't become necessary to include multiple files to accomplish the same task in the future. Signed-off-by: Adam Ford --- V2: No Change arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- drivers/soc/imx/gpcv2.c | 2 +- include/dt-bindings/power/{imx8mq-power.h => imx8m-power.h} | 0 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 55a3d1c4bdf0..f73045539fb1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include #include "dt-bindings/input/input.h" diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index b0dffb06c05d..250f740d2314 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #define GPC_LPCR_A_CORE_BSC 0x000 diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8m-power.h similarity index 100% rename from include/dt-bindings/power/imx8mq-power.h rename to include/dt-bindings/power/imx8m-power.h From patchwork Fri Dec 13 16:05:37 2019 Content-Type: text/plain; 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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:05:53 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 2/7] soc: imx: gpcv2: Update imx8m-power.h to include iMX8M Mini Date: Fri, 13 Dec 2019 10:05:37 -0600 Message-Id: <20191213160542.15757-3-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080556_257925_0B2D50AB X-CRM114-Status: GOOD ( 10.09 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:b43 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In preparation for i.MX8M Mini support in the GPC driver, the include file used by both the device tree and the source needs to have the appropriate references for it. Signed-off-by: Adam Ford --- V2: No Change include/dt-bindings/power/imx8m-power.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/dt-bindings/power/imx8m-power.h b/include/dt-bindings/power/imx8m-power.h index 8a513bd9166e..0054bba744b8 100644 --- a/include/dt-bindings/power/imx8m-power.h +++ b/include/dt-bindings/power/imx8m-power.h @@ -18,4 +18,18 @@ #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 #define IMX8M_POWER_DOMAIN_PCIE2 10 +#define IMX8MM_POWER_DOMAIN_MIPI 0 +#define IMX8MM_POWER_DOMAIN_PCIE 1 +#define IMX8MM_POWER_DOMAIN_USB_OTG1 2 +#define IMX8MM_POWER_DOMAIN_USB_OTG2 3 +#define IMX8MM_POWER_DOMAIN_DDR1 4 +#define IMX8MM_POWER_DOMAIN_GPU2D 5 +#define IMX8MM_POWER_DOMAIN_GPU 6 +#define IMX8MM_POWER_DOMAIN_VPU 7 +#define IMX8MM_POWER_DOMAIN_GPU3D 8 +#define IMX8MM_POWER_DOMAIN_DISP 9 +#define IMX8MM_POWER_VPU_G1 10 +#define IMX8MM_POWER_VPU_G2 11 +#define IMX8MM_POWER_VPU_H1 12 + #endif From patchwork Fri Dec 13 16:05:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 11291661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50D5B14BD for ; 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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:05:56 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 3/7] soc: imx: gpcv2: add support for i.MX8M Mini SoC Date: Fri, 13 Dec 2019 10:05:38 -0600 Message-Id: <20191213160542.15757-4-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080558_376607_EB7A8E5B X-CRM114-Status: GOOD ( 13.57 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:b43 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The GPCv2 on the Freescale i.MX8M Mini SoC works in the same way as the GPCv2 on the i.MX8MQ, but with slightly different power domains and mapping. This patch adds the necessary tables so the GPC can operate on the i.MX8M Mini. Signed-off-by: Adam Ford --- V2: No Change drivers/soc/imx/gpcv2.c | 244 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 250f740d2314..52668e985e8e 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -41,6 +41,20 @@ #define IMX8M_PCIE1_A53_DOMAIN BIT(3) #define IMX8M_MIPI_A53_DOMAIN BIT(2) +#define IMX8MM_VPU_H1_A53_DOMAIN BIT(15) +#define IMX8MM_VPU_G2_A53_DOMAIN BIT(14) +#define IMX8MM_VPU_G1_A53_DOMAIN BIT(13) +#define IMX8MM_DISP_MIX_A53_DOMAIN BIT(12) +#define IMX8MM_GPU_3D_A53_DOMAIN BIT(11) +#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10) +#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9) +#define IMX8MM_GPU_2D_A53_DOMAIN BIT(8) +#define IMX8MM_DDR1_A53_DOMAIN BIT(7) +#define IMX8MM_OTG2_A53_DOMAIN BIT(5) +#define IMX8MM_OTG1_A53_DOMAIN BIT(4) +#define IMX8MM_PCIE_A53_DOMAIN BIT(3) +#define IMX8MM_MIPI_A53_DOMAIN BIT(2) + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -64,6 +78,20 @@ #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) #define IMX8M_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MM_VPU_H1_SW_Pxx_REQ BIT(13) +#define IMX8MM_VPU_G2_SW_Pxx_REQ BIT(12) +#define IMX8MM_VPU_G1_SW_Pxx_REQ BIT(11) +#define IMX8MM_DISP_SW_Pxx_REQ BIT(10) +#define IMX8MM_GPU_3D_SW_Pxx_REQ BIT(9) +#define IMX8MM_VPU_SW_Pxx_REQ BIT(8) +#define IMX8MM_GPU_SW_Pxx_REQ BIT(7) +#define IMX8MM_GPU_2D_SW_PXX_REQ BIT(6) +#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5) +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1) +#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc #define GPC_PU_PWRHSK 0x1fc @@ -72,6 +100,10 @@ #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) +#define IMX8MM_GPU_HSK_PWRDNREQN BIT(9) +#define IMX8MM_VPU_HSK_PWRDNREQN BIT(8) +#define IMX8MM_DISP_HSK_PWRDNREQN BIT(7) + /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -94,6 +126,24 @@ #define IMX8M_PGC_MIPI_CSI2 28 #define IMX8M_PGC_PCIE2 29 +/* + * Taken from i.MX8M Mini values from Reference + * Manual, Rev. 2, 08/2019 + */ +#define IMX8MM_PGC_MIPI 16 +#define IMX8MM_PGC_PCIE 17 +#define IMX8MM_PGC_OTG1 18 +#define IMX8MM_PGC_OTG2 19 +#define IMX8MM_PGC_DDR1 21 +#define IMX8MM_PGC_GPU2D 22 +#define IMX8MM_PGC_GPU 23 +#define IMX8MM_PGC_VPU 24 +#define IMX8MM_PGC_GPU3D 25 +#define IMX8MM_PGC_DISP 26 +#define IMX8MM_PGC_VPU_G1 27 +#define IMX8MM_PGC_VPU_G2 28 +#define IMX8MM_PGC_VPU_H1 29 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -278,6 +328,7 @@ static const struct imx_pgc_domain_data imx7_pgc_domain_data = { .reg_access_table = &imx7_access_table, }; +/* i.MX8M dual/QuadLite/Quad */ static const struct imx_pgc_domain imx8m_pgc_domains[] = { [IMX8M_POWER_DOMAIN_MIPI] = { .genpd = { @@ -442,6 +493,198 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { .reg_access_table = &imx8m_access_table, }; +/* i.MX8M Mini */ +static const struct imx_pgc_domain imx8mm_pgc_domains[] = { + [IMX8MM_POWER_DOMAIN_MIPI] = { + .genpd = { + .name = "mipi", + }, + .bits = { + .pxx = IMX8MM_MIPI_SW_Pxx_REQ, + .map = IMX8MM_MIPI_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_MIPI, + }, + + [IMX8MM_POWER_DOMAIN_PCIE] = { + .genpd = { + .name = "pcie1", + }, + .bits = { + .pxx = IMX8MM_PCIE_SW_Pxx_REQ, + .map = IMX8MM_PCIE_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_PCIE, + }, + + [IMX8MM_POWER_DOMAIN_USB_OTG1] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8MM_OTG1_SW_Pxx_REQ, + .map = IMX8MM_OTG1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_OTG1, + }, + + [IMX8MM_POWER_DOMAIN_USB_OTG2] = { + .genpd = { + .name = "usb-otg2", + }, + .bits = { + .pxx = IMX8MM_OTG2_SW_Pxx_REQ, + .map = IMX8MM_OTG2_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_OTG2, + }, + + [IMX8MM_POWER_DOMAIN_DDR1] = { + .genpd = { + .name = "ddr1", + }, + .bits = { + .pxx = IMX8MM_DDR1_SW_Pxx_REQ, + .map = IMX8MM_DDR1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_DDR1, + }, + + [IMX8MM_POWER_DOMAIN_GPU2D] = { + .genpd = { + .name = "gpu2d", + }, + .bits = { + .pxx = IMX8MM_GPU_2D_SW_PXX_REQ, + .map = IMX8MM_GPU_2D_A53_DOMAIN, + .hsk = IMX8MM_GPU_HSK_PWRDNREQN, + }, + .pgc = IMX8MM_PGC_GPU2D, + }, + + + [IMX8MM_POWER_DOMAIN_GPU] = { + .genpd = { + .name = "gpu", + }, + .bits = { + .pxx = IMX8MM_GPU_SW_Pxx_REQ, + .map = IMX8MM_GPUMIX_A53_DOMAIN, + .hsk = IMX8MM_GPU_HSK_PWRDNREQN, + }, + .pgc = IMX8M_PGC_GPU, + }, + + [IMX8MM_POWER_DOMAIN_VPU] = { + .genpd = { + .name = "vpu", + }, + .bits = { + .pxx = IMX8MM_VPU_SW_Pxx_REQ, + .map = IMX8MM_VPUMIX_A53_DOMAIN, + .hsk = IMX8MM_VPU_HSK_PWRDNREQN, + }, + .pgc = IMX8M_PGC_VPU, + }, + + [IMX8MM_POWER_DOMAIN_GPU3D] = { + .genpd = { + .name = "gpu3d", + }, + .bits = { + .pxx = IMX8MM_GPU_3D_SW_Pxx_REQ, + .map = IMX8MM_GPU_3D_A53_DOMAIN, + .hsk = IMX8MM_GPU_HSK_PWRDNREQN, + }, + .pgc = IMX8MM_PGC_GPU2D, + }, + + [IMX8MM_POWER_DOMAIN_DISP] = { + .genpd = { + .name = "disp", + }, + .bits = { + .pxx = IMX8MM_DISP_SW_Pxx_REQ, + .map = IMX8MM_DISP_MIX_A53_DOMAIN, + .hsk = IMX8MM_DISP_HSK_PWRDNREQN, + }, + .pgc = IMX8M_PGC_DISP, + }, + + [IMX8MM_POWER_VPU_G1] = { + .genpd = { + .name = "vpu_g1", + }, + .bits = { + .pxx = IMX8MM_VPU_G1_SW_Pxx_REQ, + .map = IMX8MM_VPU_G1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_MIPI_CSI1, + }, + + [IMX8MM_POWER_VPU_G2] = { + .genpd = { + .name = "vpu_g2", + }, + .bits = { + .pxx = IMX8MM_VPU_G2_SW_Pxx_REQ, + .map = IMX8MM_VPU_G2_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_MIPI_CSI2, + }, + + [IMX8MM_POWER_VPU_H1] = { + .genpd = { + .name = "vpu_h1", + }, + .bits = { + .pxx = IMX8MM_VPU_H1_SW_Pxx_REQ, + .map = IMX8MM_VPU_H1_A53_DOMAIN, + }, + .pgc = IMX8M_PGC_PCIE2, + }, +}; + +static const struct regmap_range imx8mm_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + GPC_PU_PWRHSK), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI), + GPC_PGC_SR(IMX8MM_PGC_MIPI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE), + GPC_PGC_SR(IMX8MM_PGC_PCIE)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1), + GPC_PGC_SR(IMX8MM_PGC_OTG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2), + GPC_PGC_SR(IMX8MM_PGC_OTG2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1), + GPC_PGC_SR(IMX8MM_PGC_DDR1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D), + GPC_PGC_SR(IMX8MM_PGC_GPU2D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU), + GPC_PGC_SR(IMX8MM_PGC_GPU)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU), + GPC_PGC_SR(IMX8MM_PGC_VPU)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISP), + GPC_PGC_SR(IMX8MM_PGC_DISP)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G1), + GPC_PGC_SR(IMX8MM_PGC_VPU_G1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G2), + GPC_PGC_SR(IMX8MM_PGC_VPU_G2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_H1), + GPC_PGC_SR(IMX8MM_PGC_VPU_H1)), +}; + +static const struct regmap_access_table imx8mm_access_table = { + .yes_ranges = imx8mm_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges), +}; + +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { + .domains = imx8mm_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), + .reg_access_table = &imx8mm_access_table, +}; + static int imx_pgc_get_clocks(struct imx_pgc_domain *domain) { int i, ret; @@ -641,6 +884,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, + { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, { } }; From patchwork Fri Dec 13 16:05:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 11291803 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 550F514E3 for ; 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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:05:58 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 4/7] dt-bindings: imx-gpcv2: Update bindings to support i.MX8M Mini Date: Fri, 13 Dec 2019 10:05:39 -0600 Message-Id: <20191213160542.15757-5-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080600_403709_DF1CADF2 X-CRM114-Status: GOOD ( 14.01 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:c43 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The with the recent additions to the driver, the GPCv2 driver can support the i.MX8M Mini, but it needs updated 'compatible' entry to use the proper table. This patch adds the i.MX8MM to the compatible list of devices. Signed-off-by: Adam Ford Acked-by: Rob Herring --- V2: No Change Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt index 7c7e972aaa42..576a79097a4c 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt @@ -9,6 +9,7 @@ Required properties: - compatible: Should be one of: - "fsl,imx7d-gpc" - "fsl,imx8mq-gpc" + - "fsl,imx8mm-gpc" - reg: should be register base and length as documented in the datasheet @@ -24,8 +25,9 @@ which, in turn, is expected to contain the following: Required properties: - reg: Power domain index. Valid values are defined in - include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and - include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc + include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc, + include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc, and + include/dt-bindings/power/imx8m-power.h for fsl,imx8mm-gpc - #power-domain-cells: Should be 0 From patchwork Fri Dec 13 16:05:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 11291741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0235175D for ; Fri, 13 Dec 2019 22:26:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 946CD2077B for ; Fri, 13 Dec 2019 22:26:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WGVlUGNf"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jplSiqf4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 946CD2077B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WywL+U36Wez1gLzv7Cp51sy1uJ1LKTamIJKrH1j87Dw=; b=WGVlUGNf+i32C2 rmcJoZuBM8wVFnEK+9vBCXQyJdzjZcAmWAcRULQN3I8tFx3iXm2L5moLr95Q1Yie+uNsVlFVEnMd2 NYa87hRB2D5tFHxq+tkUFXGTp1HIzde15EH2bdGteV8g2JgPhfjrVe9z6B9sYPjiXUjUuWpX0D+RU n0buDAMkhEgNeMCaVpWjC59NxCGbpXtS+BD7xWMobxYvD5/AOYGxvMHoUPAWhibvzyWU+BakUtQn6 UuIk5LB8EuHVMY2S/Uuq841i7EyudinDwzTqRl7ttfTczqWYWZgMenERpE5RmG/+OkjkHPye6P0cS zWHXz8bhvmB1NWlX4iAQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1ifnTx-0005dp-N2; Fri, 13 Dec 2019 16:07:57 +0000 Received: from mail-yw1-xc43.google.com ([2607:f8b0:4864:20::c43]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1ifnS6-0003pC-Ke for linux-arm-kernel@lists.infradead.org; Fri, 13 Dec 2019 16:06:04 +0000 Received: by mail-yw1-xc43.google.com with SMTP id t141so19036ywc.11 for ; Fri, 13 Dec 2019 08:06:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TUBn4hPQtTP6/1UnracKB+PKuO3QMFkkquLizrjA/XM=; b=jplSiqf47y6ZYGeFyNC9sZb3biXn2gVEJv+PNanVJiJfXKyGzSYXXYRfL7jBHBCM4n 2Aqo6V6mUEzEMOcUjxb0pk24ulPgKMf5pdFFfE33y2TtBqr0kM4nGeY4zTvSUSoDfmMD J70Deq811qD/hht1L21MoaE5Q8SLoPsULIueKFkEh3jOpz1mPB+ezRVkdNymmWeI4bif 5wCpDZO0aFl0eVcGNVignY7201cs3i3SsddVZNdZNugBdC9+b/5pJoVjKTbWwPszg0oe sT2qDSAfMwE9kGXBLhDfwSHGj+ZtMk3QT4BSpakH0JQUlZmPdH3tJWAhk1oo5Ab6zMaj Qujg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TUBn4hPQtTP6/1UnracKB+PKuO3QMFkkquLizrjA/XM=; b=HrNwGCLSL4T4Zka4cnbJpd0k0aqyBXhzOTBmb8hSbEDK3f0Wo+kYUR+d1BNCSRcE5M dMPMltTkFob+i769+33jzeExfmfOc/mtKfeoa6D5ff6+dofmhbFk7uPi/T/v61SWf1+6 6tWi0MKilZE4oe2+rLft1GoxpxuxxGXziXpWgKQyC0bwtZK2a8JlTB+b8Bpx0tq/gj6o wG5Xde0MplapZwC0OT0ol+K81X1+AafAN6ARIy3UD1w2BBmKCPBkFRNbLoWyxMEzxU1w uentMpAWzNFGkI9HjdBIeqkkopiS/+2vyGTG/XhKezAjJaQHtHm9u1UKsfmhHPZFb5oV qRPQ== X-Gm-Message-State: APjAAAWHcalT80cEXJCDi5GPiddz60PFqDphRPmIRhs04uLG4hIUVm/3 XWkwcSj3/syNjc3eEmz/y636GqZH X-Google-Smtp-Source: APXvYqzObFt2i3P9CQgT7UV8LybxmIu+0nBxBacvga9qhhrksInhZa+8qHAwAJAlCO1naM/6MDEqMQ== X-Received: by 2002:a81:b548:: with SMTP id c8mr8655777ywk.465.1576253161238; Fri, 13 Dec 2019 08:06:01 -0800 (PST) Received: from localhost.localdomain (c-73-37-219-234.hsd1.mn.comcast.net. [73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:06:00 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 5/7] arm64: dts: imx8mm: add GPC power domains Date: Fri, 13 Dec 2019 10:05:40 -0600 Message-Id: <20191213160542.15757-6-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080602_842201_6F1E8301 X-CRM114-Status: GOOD ( 11.27 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:c43 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There is a power domain controller on the i.XM8M Mini used for handling interrupts and controlling certain peripherals like USB OTG and PCIe, which are currently unavailable. This patch enables support the controller itself to the help facilitate enabling additional peripherals. Signed-off-by: Adam Ford --- V2: Removed references making GPC an interrupt controller. arch/arm64/boot/dts/freescale/imx8mm.dtsi | 78 +++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 23c8fad7932b..f38bed94bce2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -495,6 +496,83 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_mipi: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_ddr1: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_gpu2d: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_gpu: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_gpu3d: power-domain@8 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_disp: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_g1: power-domain@a { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_g2: power-domain@b { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_h1: power-domain@c { + #power-domain-cells = <0>; + reg = ; + }; + }; + }; }; aips2: bus@30400000 { From patchwork Fri Dec 13 16:05:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 11291773 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82793930 for ; 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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:06:03 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 6/7] ARM64: dts: imx8mm: Fix clocks and power domain for USB OTG Date: Fri, 13 Dec 2019 10:05:41 -0600 Message-Id: <20191213160542.15757-7-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080605_874408_1D9247F7 X-CRM114-Status: GOOD ( 11.83 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:c42 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There are two USB OTG controllers on the i.MX8M Mini, but currently neither are functional. According to the device tree entries published on the NXP kernel for the imx8m mini, these both need to be assigned to the proper clocks and power domain in order to function. This patch configures both USB OTG controllers to enable a missing clock and define the power domain so boards wishing to enable the USB OTG can do so. Signed-off-by: Adam Ford --- V2: No Change arch/arm64/boot/dts/freescale/imx8mm.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f38bed94bce2..dbeee4059c55 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -865,8 +865,11 @@ interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + power-domains = <&pgc_otg1>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; status = "disabled"; @@ -884,8 +887,11 @@ interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + power-domains = <&pgc_otg2>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; status = "disabled"; From patchwork Fri Dec 13 16:05:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 11291857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D0DDD14B7 for ; Fri, 13 Dec 2019 22:30:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B47C420706 for ; Fri, 13 Dec 2019 22:30:35 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:06:05 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V2 7/7] arm64: dts: imx8mm: Add PCIe support Date: Fri, 13 Dec 2019 10:05:42 -0600 Message-Id: <20191213160542.15757-8-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_080607_334157_F0CA1C7B X-CRM114-Status: GOOD ( 14.93 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:c41 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (aford173[at]gmail.com) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (aford173[at]gmail.com) -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, peng.fan@nxp.com, Fabio Estevam , ping.bai@nxp.com, Adam Ford , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The PCIE controller on the i.MX8M Mini appears to be the same as the i.MX8MQ but it is absent. This patch uses the bindings from the i.MX8MQ and the clock information from the NXP Linux release and marks it as disabled so it can be configured and enabled on boards where needed. Signed-off-by: Adam Ford --- V2: No Change arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index dbeee4059c55..33fa760a3f2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -934,6 +935,40 @@ status = "disabled"; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */