From patchwork Fri Dec 13 23:45:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291955 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10CA014DB for ; Fri, 13 Dec 2019 23:46:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E43182465E for ; Fri, 13 Dec 2019 23:46:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="SnfBwtRp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726767AbfLMXqI (ORCPT ); Fri, 13 Dec 2019 18:46:08 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:38392 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726345AbfLMXqF (ORCPT ); Fri, 13 Dec 2019 18:46:05 -0500 Received: by mail-pg1-f195.google.com with SMTP id a33so245687pgm.5 for ; Fri, 13 Dec 2019 15:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LCB1KIVahlXQKWBS7hxxSbVh5ZcN9u97BqK9nO2uQ04=; b=SnfBwtRpMms+XqhrvoTDfK3B9tOlEd29DDYcdfTbv1yQlasgMa3ncrTzHEbvqmeAXR uCP98TANejscAqyK9+hOQA4UQUXHllXs9HJksbv5JDXC9xL6AnYWt4hjU7a7zAOk07UH TvpiY2+9LBqOgJe74n3uu9mqTNHlxbVWy6S98= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LCB1KIVahlXQKWBS7hxxSbVh5ZcN9u97BqK9nO2uQ04=; b=R3gQqvNfoYlsjmyEJAGLQ+wH24ytXcAhBkR0QiVSp+6iYOB9AwH4/Or50/YF4ZAQKb 39StinQfcHnO24A6xmwoY6uV+9tYr9QywTw8vZIikRY89/TOyFgsGjftd3LfBLoME68O qJQgJ2W+ZF6Xmx40lI79lDLOww9YPJ8mfzC6jxvCQUg9AcNBNv3mRNQ2WqfWMpZTuXSx mMaF6dRSgRTGSzMNzT2p5RTQHzNxDJ60ZFBWCxl2h9YJ0oxJmlOo4c+cQWCHXkRYNzt3 MniX01v2WUx0fkEBEpMYsjiEbWGQ+xi+ZfMJeQxEshkxB8CCiW0WsUzc6b2qTxSRTcWc Bg5Q== X-Gm-Message-State: APjAAAUNO0e1u2uHSKZzoBlX7LwYO6u9YmCHAX/Y1byLAMvL9KCPACRe o+AiFqUxZYTa/3iu4aimMrne5Q== X-Google-Smtp-Source: APXvYqwWU0kzoE96+aLrGB9T1QDrKSljpD+TwHPMs33XMNH5KyYsirHxBbrw+ZdaseYw0W0rize4cQ== X-Received: by 2002:a63:106:: with SMTP id 6mr2447435pgb.190.1576280765132; Fri, 13 Dec 2019 15:46:05 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:04 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Date: Fri, 13 Dec 2019 15:45:22 -0800 Message-Id: <20191213154448.1.Icb765d5799e9651e5249c0c27627ba33a9e411cf@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These two things were in one function. Split into two. This looks like it's duplicating some code, but don't worry. This is is just in preparation for future changes. This is intended to have zero functional change and will just make future patches easier to understand. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 33 +++++++++++++++++++-------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 43abf01ebd4c..2fb9370a76e6 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -417,6 +417,24 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata) REFCLK_FREQ(i)); } +static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata) +{ + unsigned int bit_rate_mhz, clk_freq_mhz; + unsigned int val; + struct drm_display_mode *mode = + &pdata->bridge.encoder->crtc->state->adjusted_mode; + + /* set DSIA clk frequency */ + bit_rate_mhz = (mode->clock / 1000) * + mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); + + /* for each increment in val, frequency increases by 5MHz */ + val = (MIN_DSI_CLK_FREQ_MHZ / 5) + + (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); + regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); +} + /** * LUT index corresponds to register value and * LUT values corresponds to dp data rate supported @@ -426,22 +444,16 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata) +static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) { - unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz; - unsigned int val, i; + unsigned int bit_rate_mhz, dp_rate_mhz; + unsigned int i; struct drm_display_mode *mode = &pdata->bridge.encoder->crtc->state->adjusted_mode; /* set DSIA clk frequency */ bit_rate_mhz = (mode->clock / 1000) * mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); - clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); - - /* for each increment in val, frequency increases by 5MHz */ - val = (MIN_DSI_CLK_FREQ_MHZ / 5) + - (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); - regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); /* set DP data rate */ dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) / @@ -510,7 +522,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) val); /* set dsi/dp clk frequency value */ - ti_sn_bridge_set_dsi_dp_rate(pdata); + ti_sn_bridge_set_dsi_rate(pdata); + ti_sn_bridge_set_dp_rate(pdata); /* enable DP PLL */ regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); From patchwork Fri Dec 13 23:45:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291959 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 665F714DB for ; Fri, 13 Dec 2019 23:46:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 469AE24676 for ; Fri, 13 Dec 2019 23:46:40 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 13 Dec 2019 15:46:05 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Date: Fri, 13 Dec 2019 15:45:23 -0800 Message-Id: <20191213154448.2.Id445d0057bedcb0a190009e0706e9254c2fd48eb@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When we iterate over ti_sn_bridge_dp_rate_lut, there's no reason to start at index 0 which always contains the value 0. 0 is not a valid link rate. This change should have no real effect but is a small cleanup. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 2fb9370a76e6..7b596af265e4 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -458,7 +458,7 @@ static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) /* set DP data rate */ dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) / DP_CLK_FUDGE_DEN; - for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) + for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz) break; From patchwork Fri Dec 13 23:45:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291957 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63DC1930 for ; Fri, 13 Dec 2019 23:46:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 43C1224679 for ; Fri, 13 Dec 2019 23:46:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="RRbRwgBi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726786AbfLMXqI (ORCPT ); Fri, 13 Dec 2019 18:46:08 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:45269 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726767AbfLMXqI (ORCPT ); Fri, 13 Dec 2019 18:46:08 -0500 Received: by mail-pg1-f194.google.com with SMTP id b9so229892pgk.12 for ; Fri, 13 Dec 2019 15:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Ve4LMGBgan+F8VZipmKjjix5j1MoppRCjBAaqc2gpE=; b=RRbRwgBiDBHRW2GR/MOwzVGUgQELNYjduuux7ac+ai8K079MsvEkqbNHZ+XhO4+zUS Z2jnz7vhwVep544DeCJyd6nNMPL3X87C94ruUuVUYEcDVliAlRLly1tgJGUX1+/IPheI u1xgFGC7DtCX6ChZeaggPTX3cY47hqaNzs9XQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Ve4LMGBgan+F8VZipmKjjix5j1MoppRCjBAaqc2gpE=; b=q5uIII9keOg36oMl6stt8L1ur7uQ5xjW7w+ASl0/sapR/Njq1KZqu5uKwVuOJrpxq/ op2qlHznpdyhHvWZOwH6suSX8/ErdJ9y7NrcmsaP48ABoya6avYH8Ye7qhoQIXwOoM8w DdoUw2uxhPsUQvGGI4Z/P/mOL47gNggzTu7HAtzJ5PdAAkvLQLZs8dNZd0jtpySq5VBF PB+es3sbWLro04tfkSASa48NaUvyn6FhHoX+Jnfk/H+UKzRi9WR53Q8LQkqk8vhu4Oo+ u8LWl7YnYyjCfiPnUu/5hiJYLmflzMAm8HFoSdFpJi+K8PSP0T9KxPiZpQtk9bVKlRa3 dgSA== X-Gm-Message-State: APjAAAUrzg2uVzgk8oAU3C7giDzQE54Y8OMMUy+nxaoR0fVTmrTfetIK 3mbS5pNXFj4dGTESRzlqm9gTFQ== X-Google-Smtp-Source: APXvYqxO0d9p2M8qFnt6mqa6LtLZ5HJZK6HH0joHpvkGPX0B+IxH8OZBSzCB+ugzc3JO9EngFiHocQ== X-Received: by 2002:aa7:9839:: with SMTP id q25mr2409112pfl.161.1576280767575; Fri, 13 Dec 2019 15:46:07 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:07 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Date: Fri, 13 Dec 2019 15:45:24 -0800 Message-Id: <20191213154448.3.Ia6e05f4961adb0d4a0d32ba769dd7781ee8db431@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The ti-sn65dsi86 is a bridge from MIPI to DP and thus has two links: the MIPI link and the DP link. The two links do not need to have the same format or number of lanes. Stop using MIPI variables when talking about the DP link. This has zero functional change because: * currently we are hardcoding the MIPI link as unpacked RGB888 which requires 24 bits and currently we are not changing the DP link rate from the bridge's default of 8 bits per pixel. * currently we are hardcoding both the MIPI and DP as being 4 lanes. This is all in prep for fixing some of the above. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 7b596af265e4..ab644baaf90c 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -100,6 +100,7 @@ struct ti_sn_bridge { struct drm_panel *panel; struct gpio_desc *enable_gpio; struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; + int dp_lanes; }; static const struct regmap_range ti_sn_bridge_volatile_ranges[] = { @@ -313,6 +314,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) } /* TODO: setting to 4 lanes always for now */ + pdata->dp_lanes = 4; dsi->lanes = 4; dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO; @@ -451,13 +453,17 @@ static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) struct drm_display_mode *mode = &pdata->bridge.encoder->crtc->state->adjusted_mode; - /* set DSIA clk frequency */ - bit_rate_mhz = (mode->clock / 1000) * - mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); + /* + * Calculate minimum bit rate based on our pixel clock. At + * the moment this driver never sets the DP_18BPP_EN bit in + * register 0x5b so we hardcode 24bpp. + */ + bit_rate_mhz = (mode->clock / 1000) * 24; - /* set DP data rate */ - dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) / + /* Calculate minimum DP data rate, taking 80% as per DP spec */ + dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) / DP_CLK_FUDGE_DEN; + for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz) break; @@ -517,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) CHA_DSI_LANES_MASK, val); /* DP lane config */ - val = DP_NUM_LANES(pdata->dsi->lanes - 1); + val = DP_NUM_LANES(pdata->dp_lanes - 1); regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val); From patchwork Fri Dec 13 23:45:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291925 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0282614DB for ; Fri, 13 Dec 2019 23:46:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D4188214AF for ; Fri, 13 Dec 2019 23:46:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Fz4y2Ke4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726817AbfLMXqK (ORCPT ); Fri, 13 Dec 2019 18:46:10 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:37650 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726771AbfLMXqJ (ORCPT ); Fri, 13 Dec 2019 18:46:09 -0500 Received: by mail-pf1-f195.google.com with SMTP id p14so532876pfn.4 for ; Fri, 13 Dec 2019 15:46:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hBWP2/QJL0y05bggOLUlEYkrP/w5ugSFmgOaMEwZL50=; b=Fz4y2Ke44kCSsjzp+a34ad3A68+TnKJKWD4UJoHpxQ3EPHdetc8nwEGtkef+RvhiQT /0RpPlwnBBSL4CMm358u9SBm7lHGQl+OPgpswKiTIrkQQO3ejRMFLLZCGR76bDdIHMq+ tXv1nyQTQ+fkJCAZYl2Ety2Fv61bHqb15i3aI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hBWP2/QJL0y05bggOLUlEYkrP/w5ugSFmgOaMEwZL50=; b=EXe19WS9VvKMumDqVFhNiXLASc+A2jQ8Px/pvgVbnzkc217r/Qu7TNkI0dJDfJ1eTO 6ez1lxXssPY/okCqFSI6XpJWRtNxOKLkUFReHRd3qd2ezCHiuEYLoUs0Ky74Bn2LQ8le 1FcW8hQBPKmgnlZMEiLUEYSVKSgvgp4Nh0BUWIK4Ze2a9cfvwadWjKl7KhyFi5InXj1J 5sdeqfraH0NvsRxFjjXQs8acwcLqxlpUbcTLDVeQ+4OgIkXER8SuNt60fKORnYS9O4VA eQrIz+b842712sj/cEOEInrhRXN8p42l95tvSqpE2T05qS15S0ndC2HWHNsL7xEP3mFH hlzA== X-Gm-Message-State: APjAAAUZEkq3vrBVF7jxgRWY8eY/87x1X8gRfTc7APSB/e9qaq9hfHcC PBtNBmOnPNEP9zfTBZMCALjppw== X-Google-Smtp-Source: APXvYqw1TNBWKyOrLHCw7vDkyzfBgewAvNgShojcv9sMhHxdOwVu4YowVmdOkduBPxrqAMLThPoXNQ== X-Received: by 2002:a63:9d85:: with SMTP id i127mr2328536pgd.186.1576280768713; Fri, 13 Dec 2019 15:46:08 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:08 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Date: Fri, 13 Dec 2019 15:45:25 -0800 Message-Id: <20191213154448.4.If3e2d0493e7b6e8b510ea90d8724ff760379b3ba@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The driver used to say that the value to program into bridge register 0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this is wrong. The data sheet says: * 1 = 1 lane * 2 = 2 lanes * 3 = 4 lanes A more proper way to express this encoding is min(dp_lanes, 3). At the moment this change has zero effect because we've hardcoded the number of DP lanes to 4. ...and (4 - 1) == min(4, 3). How fortunate! ...but soon we'll stop hardcoding the number of lanes. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index ab644baaf90c..d55d19759796 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) CHA_DSI_LANES_MASK, val); /* DP lane config */ - val = DP_NUM_LANES(pdata->dp_lanes - 1); + val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val); From patchwork Fri Dec 13 23:45:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291929 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 87A14930 for ; Fri, 13 Dec 2019 23:46:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6794924125 for ; Fri, 13 Dec 2019 23:46:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="ZsIZN4XD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726841AbfLMXqL (ORCPT ); Fri, 13 Dec 2019 18:46:11 -0500 Received: from mail-pj1-f65.google.com ([209.85.216.65]:37177 "EHLO mail-pj1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726825AbfLMXqK (ORCPT ); Fri, 13 Dec 2019 18:46:10 -0500 Received: by mail-pj1-f65.google.com with SMTP id ep17so383272pjb.4 for ; Fri, 13 Dec 2019 15:46:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UUJY8C2R1UDrN9sVA9Df9NEy0bvM49t/SSGj3bqxYIA=; b=ZsIZN4XD3zKnYDKUlFHgZN5qlLlZaKZvDA3IqUDEaZ1MKvXpxV2C0yQcyN0bwItqa9 Rq2DzcDdb79znuQ1AwruLYFwFlCJlG7ArsO/sbIKvRxKg0y7W5KwBVO2ICkZL7a2vr8M 0p4OgUdPIJ7z4DMmfblZ2UxMhHWhpRS36zwbw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UUJY8C2R1UDrN9sVA9Df9NEy0bvM49t/SSGj3bqxYIA=; b=JvfOE3efF2onikBCRqh2l1NRQQjFjJTeX1QKAEZZuF1v87HPIm3UGkG4aC3FGydwWg LZFjJWbuOIGHQcahZvSR131Nq/Yqh3hWYmDnqmVBHcgWy05TG2vSdQ7dNvBonlhRgAqv NT84XS+WZyvH+rVV/74WKAhrenMIo+6vMHV+YuCKwwj3wkXlk9OqtHEC6sfoyAogrfPm go2M7G9GFY8eNZdZ/S0Gr7feg5F0svb/Hl5QFi5knXPB2s96fr5OxuffeZR2Ip4FmCbp i92XW3OmsUG1UgAgOQQTZ97QJEnBkTsNf4Y+QnUH5eavFyffc9Xq3VjvfT16JOBTD5GA R7yw== X-Gm-Message-State: APjAAAVKI54O7mR6M73zBuDMVS2/6IfoDXojOyd7t+RQ9iiHOU04aAXU RgsdRUUNejxnnDsQfCCvo8meDQ== X-Google-Smtp-Source: APXvYqyclxT5JoQSvi7XSMZMqIl7nPTvJKywUFXfL73GfTko0ecOAss5ATHTnj7+cNjZej2o7vrvgw== X-Received: by 2002:a17:90a:c790:: with SMTP id gn16mr2482321pjb.76.1576280769888; Fri, 13 Dec 2019 15:46:09 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:09 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Date: Fri, 13 Dec 2019 15:45:26 -0800 Message-Id: <20191213154448.5.Idbd0051d0de53f7e9d18a291ea33011c0854fcc6@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org At least one panel hooked up to the bridge (AUO B116XAK01) only supports 1 lane of DP. Let's read this information and stop hardcoding 4 DP lanes. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 32 +++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d55d19759796..0fc9e97b2d98 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -313,8 +313,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) goto err_dsi_host; } - /* TODO: setting to 4 lanes always for now */ - pdata->dp_lanes = 4; + /* TODO: setting to 4 MIPI lanes always for now */ dsi->lanes = 4; dsi->format = MIPI_DSI_FMT_RGB888; dsi->mode_flags = MIPI_DSI_MODE_VIDEO; @@ -511,12 +510,41 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) usleep_range(10000, 10500); /* 10ms delay recommended by spec */ } +static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) +{ + u8 data; + int ret; + + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); + if (ret != 1) { + DRM_DEV_ERROR(pdata->dev, + "Can't read lane count (%d); assuming 4\n", ret); + return 4; + } + + return data & DP_LANE_COUNT_MASK; +} + static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); unsigned int val; int ret; + /* + * Run with the maximum number of lanes that the DP sink supports. + * + * Depending use cases, we might want to revisit this later because: + * - It's plausible that someone may have run fewer lines to the + * sink than the sink actually supports, assuming that the lines + * will just be driven at a higher rate. + * - The DP spec seems to indicate that it's more important to minimize + * the number of lanes than the link rate. + * + * If we do revisit, it would be important to measure the power impact. + */ + pdata->dp_lanes = ti_sn_get_max_lanes(pdata); + /* DSI_A lane config */ val = CHA_DSI_LANES(4 - pdata->dsi->lanes); regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, From patchwork Fri Dec 13 23:45:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7929414DB for ; Fri, 13 Dec 2019 23:46:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F6CC24658 for ; Fri, 13 Dec 2019 23:46:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Lp92qpj8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726928AbfLMXq2 (ORCPT ); Fri, 13 Dec 2019 18:46:28 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:41369 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726840AbfLMXqL (ORCPT ); Fri, 13 Dec 2019 18:46:11 -0500 Received: by mail-pl1-f196.google.com with SMTP id bd4so1876651plb.8 for ; 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Fri, 13 Dec 2019 15:46:10 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:10 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Date: Fri, 13 Dec 2019 15:45:27 -0800 Message-Id: <20191213154448.6.Iaf8d698f4e5253d658ae283d2fd07268076a7c27@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The current bridge driver always forced us to use 24 bits per pixel over the DP link. This is a waste if you are hooked up to a panel that only supports 6 bits per color or fewer, since in that case you ran run at 18 bits per pixel and thus end up at a lower DP clock rate. Let's support this. While at it, let's clean up the math in the function to avoid rounding errors (and round in the correct direction when we have to round). Numbers are sufficiently small (because mode->clock is in kHz) that we don't need to worry about integer overflow. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 0fc9e97b2d98..d5990a0947b9 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -51,6 +51,7 @@ #define SN_ENH_FRAME_REG 0x5A #define VSTREAM_ENABLE BIT(3) #define SN_DATA_FORMAT_REG 0x5B +#define BPP_18_RGB BIT(0) #define SN_HPD_DISABLE_REG 0x5C #define HPD_DISABLE BIT(0) #define SN_AUX_WDATA_REG(x) (0x64 + (x)) @@ -436,6 +437,14 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata) regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); } +static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata) +{ + if (pdata->connector.display_info.bpc <= 6) + return 18; + else + return 24; +} + /** * LUT index corresponds to register value and * LUT values corresponds to dp data rate supported @@ -447,21 +456,17 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) { - unsigned int bit_rate_mhz, dp_rate_mhz; + unsigned int bit_rate_khz, dp_rate_mhz; unsigned int i; struct drm_display_mode *mode = &pdata->bridge.encoder->crtc->state->adjusted_mode; - /* - * Calculate minimum bit rate based on our pixel clock. At - * the moment this driver never sets the DP_18BPP_EN bit in - * register 0x5b so we hardcode 24bpp. - */ - bit_rate_mhz = (mode->clock / 1000) * 24; + /* Calculate minimum bit rate based on our pixel clock. */ + bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata); /* Calculate minimum DP data rate, taking 80% as per DP spec */ - dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) / - DP_CLK_FUDGE_DEN; + dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, + 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz) @@ -550,6 +555,10 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, CHA_DSI_LANES_MASK, val); + /* Set the DP output format (18 bpp or 24 bpp) */ + val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; + regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); + /* DP lane config */ val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, From patchwork Fri Dec 13 23:45:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67A3E930 for ; Fri, 13 Dec 2019 23:46:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C95A24656 for ; Fri, 13 Dec 2019 23:46:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="F6arw4C7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726869AbfLMXqN (ORCPT ); Fri, 13 Dec 2019 18:46:13 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:44890 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726856AbfLMXqN (ORCPT ); Fri, 13 Dec 2019 18:46:13 -0500 Received: by mail-pg1-f195.google.com with SMTP id x7so231966pgl.11 for ; Fri, 13 Dec 2019 15:46:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cA4UDUHuCTqvlIh454k1CuQ9LBQaRg6FJ8cZd003K1c=; b=F6arw4C77gsnO3MMZuHtdQgaIV/tPDc/9xs0Znpn4zcamJF2EiYYwM5SXXX2RsSfuE e9ArJWGHwqypnETr+1RR9JJD+hpKmoraaTH7+w7y7h9RaBPlrMwoSUhLrOWJq43A75T1 YxoGhGHLaC29Halx1mNtG/A8Ea3eSPKLP/0CI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cA4UDUHuCTqvlIh454k1CuQ9LBQaRg6FJ8cZd003K1c=; b=LmbjZ4+x1fVWpXS+L4cmVdV+mckvgwkQg/lf3w9tZwV1aQY57qrpQTC+0ETfU/fAAc NyOAq5ITws1lsXDuacrX9TJ+s1MUp/CHvt8PufCPhOO3vq4gowagRP8XU80tn6vh43wb 74o8p6W1DAfkkSRgpLkpS6qabXLCHJojs/fipN1D/Da3+3LWsxyltQp20gvI20EoEfRl nN1MAy+MNZff/Cg24EfCpEtxQzVDRxCmg9+QJSeuKbR4LBRLHev6krCjr1cNF1Nvp/p3 uCQ/76I+sPNiOORXPF8ipAzCmgn6VxoKavtmbo9eYntggH+f/o+FaeU098C/b0n1VhM3 HNNw== X-Gm-Message-State: APjAAAWeESNuYdabwnm1S0l5ihq9Njb4ndPFIaCMDz9h6vgqRKIxAJRu vKwwlyOmax+4+HZSKBTPS8a6CQ== X-Google-Smtp-Source: APXvYqyWbcMVX6RrILQqSb7dvBaskEzzs7sYm+xMlYD7IHgX8YdOLFiBpC076Ti6YOU5glF8ziBxIQ== X-Received: by 2002:a63:5407:: with SMTP id i7mr2453004pgb.330.1576280772173; Fri, 13 Dec 2019 15:46:12 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:11 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Date: Fri, 13 Dec 2019 15:45:28 -0800 Message-Id: <20191213154448.7.I1fc75ad11db9048ef08cfe1ab7322753d9a219c7@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We'll re-organize the ti_sn_bridge_enable() function a bit to group together all the parts relating to link training and split them into a sub-function. This is not intended to have any functional change and is in preparation for trying link training several times at different rates. One small side effect here is that if link training fails we'll now leave the DP PLL disabled, but that seems like a sane thing to do. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 86 ++++++++++++++++----------- 1 file changed, 52 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index d5990a0947b9..48fb4dc72e1c 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -530,6 +530,46 @@ static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) return data & DP_LANE_COUNT_MASK; } +static int ti_sn_link_training(struct ti_sn_bridge *pdata) +{ + unsigned int val; + int ret; + + /* set dp clk frequency value */ + ti_sn_bridge_set_dp_rate(pdata); + + /* enable DP PLL */ + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); + + ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, + val & DPPLL_SRC_DP_PLL_LOCK, 1000, + 50 * 1000); + if (ret) { + DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); + goto exit; + } + + /* Semi auto link training mode */ + regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); + ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, + val == ML_TX_MAIN_LINK_OFF || + val == ML_TX_NORMAL_MODE, 1000, + 500 * 1000); + if (ret) { + DRM_ERROR("Training complete polling failed (%d)\n", ret); + } else if (val == ML_TX_MAIN_LINK_OFF) { + DRM_ERROR("Link training failed, link is off\n"); + ret = -EIO; + } + +exit: + /* Disable the PLL if we failed */ + if (ret) + regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); + + return ret; +} + static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); @@ -555,29 +595,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, CHA_DSI_LANES_MASK, val); - /* Set the DP output format (18 bpp or 24 bpp) */ - val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; - regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); - - /* DP lane config */ - val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); - regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, - val); - - /* set dsi/dp clk frequency value */ + /* set dsi clk frequency value */ ti_sn_bridge_set_dsi_rate(pdata); - ti_sn_bridge_set_dp_rate(pdata); - - /* enable DP PLL */ - regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); - - ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, - val & DPPLL_SRC_DP_PLL_LOCK, 1000, - 50 * 1000); - if (ret) { - DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); - return; - } /** * The SN65DSI86 only supports ASSR Display Authentication method and @@ -588,19 +607,18 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); - /* Semi auto link training mode */ - regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); - ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, - val == ML_TX_MAIN_LINK_OFF || - val == ML_TX_NORMAL_MODE, 1000, - 500 * 1000); - if (ret) { - DRM_ERROR("Training complete polling failed (%d)\n", ret); - return; - } else if (val == ML_TX_MAIN_LINK_OFF) { - DRM_ERROR("Link training failed, link is off\n"); + /* Set the DP output format (18 bpp or 24 bpp) */ + val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0; + regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); + + /* DP lane config */ + val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); + regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, + val); + + ret = ti_sn_link_training(pdata); + if (ret) return; - } /* config video parameters */ ti_sn_bridge_set_video_timings(pdata); From patchwork Fri Dec 13 23:45:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291945 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 24B88930 for ; Fri, 13 Dec 2019 23:46:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EE06C24658 for ; Fri, 13 Dec 2019 23:46:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="dcKFlE9X" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726881AbfLMXqW (ORCPT ); Fri, 13 Dec 2019 18:46:22 -0500 Received: from mail-pl1-f196.google.com ([209.85.214.196]:45633 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726856AbfLMXqO (ORCPT ); Fri, 13 Dec 2019 18:46:14 -0500 Received: by mail-pl1-f196.google.com with SMTP id w18so72412plq.12 for ; Fri, 13 Dec 2019 15:46:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+EeHRETkxu0picdlIzKsYQGsspaxhuZcBp2HnJGPsVI=; b=dcKFlE9XwzZl4mRXm1/nubZ9pM/vI36bs0JeNK8OmJeHbYVsGHdZYepNRVJ27sqRc8 hBJ40LIojZR/TpIta9y7LrW5GFl/dpxEH1+dISE61RwY2XZdnLh1/ZIv6XoYsVSE5+b2 5ynaQAh0YciRpY3C3TrKMakmgW3Wn/NaJtiGM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+EeHRETkxu0picdlIzKsYQGsspaxhuZcBp2HnJGPsVI=; b=DqYM3MT2bLI8eu8NHsLlWiRFN+oTsTFMCR+vqaDj6CbTZOc49+kHwmv2akebjfChoX Q5nJyxKu1oWKhBXQygquUDEGPH0OuYdbohB0o9gE+UtZ4oIdFoU75hLbkLm5rNquZLo9 PgjaGy9MNPrsaL2pIfCSQiuughfvUvAp3c0O/cfWQP/mUN1hHVK2Z4+xasH6NwsiEUVW Qm9OGjciNAW9HhRisN/ljyCKsJVslVv5LhnZWVrnhdOG1ZGJIfcf4wZajlYJIRNpEXP2 Q0eT479j2Ymbpo1abm0XX+YXJBCRcNuif1rnNBQRueLo6sCX4MuVIbwC8keS5eCyKUgG xq5Q== X-Gm-Message-State: APjAAAU3qcqyhnT8f57vj7nh9VhI8oVmQ+O3YJ8ApgmxIEaoYn+iZyfx gU5c+eRiCnbKBV6AvkAisdsD8B/RiL8BFA== X-Google-Smtp-Source: APXvYqzwmXELCKHrbQ5y46SHZ0WNh/wWcubb9wd3jDnndYX/iS4e3gFT+K2H5pXNZA1dmILWpcEWAg== X-Received: by 2002:a17:90a:2569:: with SMTP id j96mr2373833pje.79.1576280773362; Fri, 13 Dec 2019 15:46:13 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id z19sm12282905pfn.49.2019.12.13.15.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 15:46:12 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Date: Fri, 13 Dec 2019 15:45:29 -0800 Message-Id: <20191213154448.8.I251add713bc5c97225200894ab110ea9183434fd@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If we fail training at a lower DP link rate let's now keep trying until we run out of rates to try. Basically the algorithm here is to start at the link rate that is the theoretical minimum and then slowly bump up until we run out of rates or hit the max rate of the sink. We query the sink using a DPCD read. This is, in fact, important in practice. Specifically at least one panel hooked up to the bridge (AUO B116XAK01) had a theoretical min rate more than 1.62 GHz (if run at 24 bpp) and fails to train at the next rate (2.16 GHz). It would train at 2.7 GHz, though. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 69 +++++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index 48fb4dc72e1c..cc8bef172f69 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -454,7 +454,7 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; -static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) +static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) { unsigned int bit_rate_khz, dp_rate_mhz; unsigned int i; @@ -472,8 +472,42 @@ static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata) if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz) break; - regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, - DP_DATARATE_MASK, DP_DATARATE(i)); + return i; +} + +static int ti_sn_bridge_get_max_dp_rate_idx(struct ti_sn_bridge *pdata) +{ + u8 data; + int ret; + + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &data); + if (ret != 1) { + DRM_DEV_ERROR(pdata->dev, + "Can't read max rate (%d); assuming 5.4 GHz\n", + ret); + return ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; + } + + /* + * Return an index into ti_sn_bridge_dp_rate_lut. Just hardcode + * these indicies since it's not like the register spec is ever going + * to change and a loop would just be more complicated. Apparently + * the DP sink can only return these few rates as supported even + * though the bridge allows some rates in between. + */ + switch (data) { + case DP_LINK_BW_1_62: + return 1; + case DP_LINK_BW_2_7: + return 4; + case DP_LINK_BW_5_4: + return 7; + } + + DRM_DEV_ERROR(pdata->dev, + "Unexpected max data rate (%#x); assuming 5.4 GHz\n", + (int)data); + return ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; } static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) @@ -530,13 +564,15 @@ static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) return data & DP_LANE_COUNT_MASK; } -static int ti_sn_link_training(struct ti_sn_bridge *pdata) +static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx, + const char **last_err_str) { unsigned int val; int ret; /* set dp clk frequency value */ - ti_sn_bridge_set_dp_rate(pdata); + regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, + DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); /* enable DP PLL */ regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); @@ -545,7 +581,7 @@ static int ti_sn_link_training(struct ti_sn_bridge *pdata) val & DPPLL_SRC_DP_PLL_LOCK, 1000, 50 * 1000); if (ret) { - DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret); + *last_err_str = "DP_PLL_LOCK polling failed"; goto exit; } @@ -556,9 +592,9 @@ static int ti_sn_link_training(struct ti_sn_bridge *pdata) val == ML_TX_NORMAL_MODE, 1000, 500 * 1000); if (ret) { - DRM_ERROR("Training complete polling failed (%d)\n", ret); + *last_err_str = "Training complete polling failed"; } else if (val == ML_TX_MAIN_LINK_OFF) { - DRM_ERROR("Link training failed, link is off\n"); + *last_err_str = "Link training failed, link is off"; ret = -EIO; } @@ -573,6 +609,9 @@ static int ti_sn_link_training(struct ti_sn_bridge *pdata) static void ti_sn_bridge_enable(struct drm_bridge *bridge) { struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); + const char *last_err_str; + int dp_rate_idx; + int max_dp_rate_idx; unsigned int val; int ret; @@ -616,9 +655,19 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val); - ret = ti_sn_link_training(pdata); - if (ret) + /* Train until we run out of rates */ + max_dp_rate_idx = ti_sn_bridge_get_max_dp_rate_idx(pdata); + for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); + dp_rate_idx <= max_dp_rate_idx; + dp_rate_idx++) { + ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); + if (!ret) + break; + } + if (ret) { + DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); return; + } /* config video parameters */ ti_sn_bridge_set_video_timings(pdata); From patchwork Fri Dec 13 23:45:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11291941 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D95171593 for ; Fri, 13 Dec 2019 23:46:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B89A62467B for ; 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Fri, 13 Dec 2019 15:46:14 -0800 (PST) From: Douglas Anderson To: Andrzej Hajda , Neil Armstrong Cc: robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, bjorn.andersson@linaro.org, Douglas Anderson , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart , Daniel Vetter Subject: [PATCH 9/9] drm/bridge: ti-sn65dsi86: Skip non-standard DP rates Date: Fri, 13 Dec 2019 15:45:30 -0800 Message-Id: <20191213154448.9.I1791f91dd22894da04f86699a7507d101d4385bc@changeid> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20191213234530.145963-1-dianders@chromium.org> References: <20191213234530.145963-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The bridge chip supports these DP rates according to TI's spec: * 1.62 Gbps (RBR) * 2.16 Gbps * 2.43 Gbps * 2.7 Gbps (HBR) * 3.24 Gbps * 4.32 Gbps * 5.4 Gbps (HBR2) As far as I can tell, only RBR, HBR, and HBR2 are part of the DP spec. If other rates work then I believe it's because the sink has allowed bending the spec a little bit. I hoped that we could tell which rates would work and which rates didn't work based on whether link training passed or not. Unfortunately this wasn't so good on at least one panel hooked up to the bridge (AUO B116XAK01). On that panel with 24 bpp configured: * 1.62: too small for 69500 kHz at 24 bpp * 2.16: link training failed * 2.43: link training passed, but garbage on screen * 2.7: joy and happiness Let's bypass all non-standard rates, which makes this panel happy working. I'll still keep the code organized in such a way where it _could_ try the other rates, though, on the assumption that eventually someone will find a way to make use of them. Signed-off-by: Douglas Anderson --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index cc8bef172f69..cb774ee536cd 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -454,6 +454,15 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 }; +/** + * A table indicating which of the rates in ti_sn_bridge_dp_rate_lut + * is as per the DP spec (AKA a standard) as opposed to an intermediate + * rate. + */ +static const bool ti_sn_bridge_dp_rate_standard[] = { + false, true, false, false, true, false, false, true +}; + static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata) { unsigned int bit_rate_khz, dp_rate_mhz; @@ -660,6 +669,18 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata); dp_rate_idx <= max_dp_rate_idx; dp_rate_idx++) { + /* + * To be on the safe side, we'll skip all non-standard + * rates and move up to the next standard one. This is + * because some panels will pass link training with a non- + * standard rate but just show garbage. If the non-standard + * rates are useful we should figure out how to enable them + * through querying the panel, having a per-panel whitelist, + * or adding a DT property. + */ + if (!ti_sn_bridge_dp_rate_standard[dp_rate_idx]) + continue; + ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); if (!ret) break;