From patchwork Mon Dec 16 15:01:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Greg Kurz X-Patchwork-Id: 11294365 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11815930 for ; Mon, 16 Dec 2019 15:02:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B5327206E0 for ; Mon, 16 Dec 2019 15:02:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B5327206E0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:55114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igrtL-0003nx-Lu for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 10:02:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49675) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igrsH-0002h5-Kr for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:01:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igrsG-0006GF-4P for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:01:29 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:46120 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igrsF-0006E8-VQ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:01:28 -0500 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBGEunge098194 for ; Mon, 16 Dec 2019 10:01:20 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2wwdt9ev8s-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 16 Dec 2019 10:01:20 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 16 Dec 2019 15:01:14 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBGF1D0930146730 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 16 Dec 2019 15:01:13 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 29FABA405F; Mon, 16 Dec 2019 15:01:13 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B8D77A405B; Mon, 16 Dec 2019 15:01:12 +0000 (GMT) Received: from bahia.lan (unknown [9.145.39.6]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 16 Dec 2019 15:01:12 +0000 (GMT) Subject: [PATCH v3 1/2] cpu: Introduce cpu_class_set_parent_reset() From: Greg Kurz To: Eduardo Habkost Date: Mon, 16 Dec 2019 16:01:12 +0100 In-Reply-To: <157650846660.354886.16810288202617432561.stgit@bahia.lan> References: <157650846660.354886.16810288202617432561.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19121615-0020-0000-0000-00000398C334 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121615-0021-0000-0000-000021EFDA96 Message-Id: <157650847239.354886.2782881118916307978.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-16_05:2019-12-16,2019-12-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 mlxscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxlogscore=992 malwarescore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912160132 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , David Hildenbrand , Cornelia Huck , qemu-devel@nongnu.org, Alistair Francis , Paolo Bonzini , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Similarly to what we already do with qdev, use a helper to overload the reset QOM methods of the parent in children classes, for clarity. Signed-off-by: Greg Kurz Reviewed-by: David Gibson Reviewed-by: Alistair Francis Reviewed-by: Cornelia Huck Acked-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé --- hw/core/cpu.c | 8 ++++++++ include/hw/core/cpu.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index db1a03c6bbb3..fde5fd395b10 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -239,6 +239,14 @@ void cpu_dump_statistics(CPUState *cpu, int flags) } } +void cpu_class_set_parent_reset(CPUClass *cc, + void (*child_reset)(CPUState *cpu), + void (**parent_reset)(CPUState *cpu)) +{ + *parent_reset = cc->reset; + cc->reset = child_reset; +} + void cpu_reset(CPUState *cpu) { CPUClass *klass = CPU_GET_CLASS(cpu); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77c6f0529903..73e9a869a41c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1135,6 +1135,10 @@ void cpu_exec_unrealizefn(CPUState *cpu); */ bool target_words_bigendian(void); +void cpu_class_set_parent_reset(CPUClass *cc, + void (*child_reset)(CPUState *cpu), + void (**parent_reset)(CPUState *cpu)); + #ifdef NEED_CPU_H #ifdef CONFIG_SOFTMMU From patchwork Mon Dec 16 15:01:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kurz X-Patchwork-Id: 11294369 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C11FC109A for ; Mon, 16 Dec 2019 15:04:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8FE49206E0 for ; Mon, 16 Dec 2019 15:04:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8FE49206E0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:55124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igruk-0005H2-P8 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 10:04:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49708) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igrsM-0002q9-Tz for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:01:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igrsG-0006GX-Od for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:01:34 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:4370 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1igrsG-0006GK-IU for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:01:28 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBGEuoeg013773 for ; Mon, 16 Dec 2019 10:01:26 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wwe8ae6ur-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 16 Dec 2019 10:01:26 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 16 Dec 2019 15:01:19 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBGF1Ike22609976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 16 Dec 2019 15:01:19 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D374F5205A; Mon, 16 Dec 2019 15:01:18 +0000 (GMT) Received: from bahia.lan (unknown [9.145.39.6]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 799A252057; Mon, 16 Dec 2019 15:01:18 +0000 (GMT) Subject: [PATCH v3 2/2] cpu: Use cpu_class_set_parent_reset() From: Greg Kurz To: Eduardo Habkost Date: Mon, 16 Dec 2019 16:01:18 +0100 In-Reply-To: <157650846660.354886.16810288202617432561.stgit@bahia.lan> References: <157650846660.354886.16810288202617432561.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19121615-0028-0000-0000-000003C926A8 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121615-0029-0000-0000-0000248C6B56 Message-Id: <157650847817.354886.7047137349018460524.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-16_05:2019-12-16,2019-12-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 adultscore=0 mlxscore=0 clxscore=1034 mlxlogscore=999 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912160132 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , David Hildenbrand , Cornelia Huck , qemu-devel@nongnu.org, Alistair Francis , Paolo Bonzini , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Convert all targets to use cpu_class_set_parent_reset() with the following coccinelle script: @@ type CPUParentClass; CPUParentClass *pcc; CPUClass *cc; identifier parent_fn; identifier child_fn; @@ +cpu_class_set_parent_reset(cc, child_fn, &pcc->parent_fn); -pcc->parent_fn = cc->reset; ... -cc->reset = child_fn; Signed-off-by: Greg Kurz Acked-by: David Gibson Reviewed-by: Alistair Francis Reviewed-by: Cornelia Huck Acked-by: David Hildenbrand --- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 3 +-- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 3 +-- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 3 +-- target/tricore/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 18 files changed, 18 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7a4ac9339bf9..712a9425fdf5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2625,8 +2625,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); dc->props = arm_cpu_properties; - acc->parent_reset = cc->reset; - cc->reset = arm_cpu_reset; + cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 7adfd6caf4ed..486675e3822f 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -256,8 +256,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); - ccc->parent_reset = cc->reset; - cc->reset = cris_cpu_reset; + cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69f518a21a9b..57d36931725d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7049,8 +7049,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) &xcc->parent_unrealize); dc->props = x86_cpu_properties; - xcc->parent_reset = cc->reset; - cc->reset = x86_cpu_reset; + cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; cc->class_by_name = x86_cpu_class_by_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b35537de6285..687bf35e6588 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -218,8 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, lm32_cpu_realizefn, &lcc->parent_realize); - lcc->parent_reset = cc->reset; - cc->reset = lm32_cpu_reset; + cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); cc->class_by_name = lm32_cpu_class_by_name; cc->has_work = lm32_cpu_has_work; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index e6596de29c2c..176d95e6fcfb 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -257,8 +257,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, m68k_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = m68k_cpu_reset; + cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); cc->class_by_name = m68k_cpu_class_by_name; cc->has_work = m68k_cpu_has_work; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9cfd7445e7da..71d88f603b2e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -292,8 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, mb_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = mb_cpu_reset; + cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbcf7ca4635c..6cd6b9650baa 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -189,8 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = mips_cpu_reset; + cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 48996d0554f2..cf47bc709b54 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -101,8 +101,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, moxie_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = moxie_cpu_reset; + cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); cc->class_by_name = moxie_cpu_class_by_name; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ca9c7a6df5d1..bbdbc0c6fbf0 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -188,8 +188,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, nios2_cpu_realizefn, &ncc->parent_realize); dc->props = nios2_properties; - ncc->parent_reset = cc->reset; - cc->reset = nios2_cpu_reset; + cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; cc->has_work = nios2_cpu_has_work; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 506aec6bfba5..5cd04dafab69 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -150,8 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - occ->parent_reset = cc->reset; - cc->reset = openrisc_cpu_reset; + cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ba726dec4d00..e5773a99fffd 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10614,8 +10614,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; dc->props = ppc_cpu_properties; - pcc->parent_reset = cc->reset; - cc->reset = ppc_cpu_reset; + cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); cc->class_by_name = ppc_cpu_class_by_name; pcc->parent_parse_features = cc->parse_features; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d37861a4305b..d6f187272859 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -462,8 +462,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = riscv_cpu_reset; + cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 99ea09085a30..80b93435a74b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -448,12 +448,11 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) dc->props = s390x_cpu_properties; dc->user_creatable = true; - scc->parent_reset = cc->reset; + cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset); #if !defined(CONFIG_USER_ONLY) scc->load_normal = s390_cpu_load_normal; #endif scc->reset = s390_cpu_reset; - cc->reset = s390_cpu_reset_full; cc->class_by_name = s390_cpu_class_by_name, cc->has_work = s390_cpu_has_work; #ifdef CONFIG_TCG diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index d0a7707991fe..70c8d8170ff3 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -214,8 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, superh_cpu_realizefn, &scc->parent_realize); - scc->parent_reset = cc->reset; - cc->reset = superh_cpu_reset; + cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); cc->class_by_name = superh_cpu_class_by_name; cc->has_work = superh_cpu_has_work; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bc659295520f..9c306e52717e 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -859,8 +859,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) &scc->parent_realize); dc->props = sparc_cpu_properties; - scc->parent_reset = cc->reset; - cc->reset = sparc_cpu_reset; + cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 2b2a7ccc313f..cd422a0467a0 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -142,8 +142,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, tilegx_cpu_realizefn, &tcc->parent_realize); - tcc->parent_reset = cc->reset; - cc->reset = tilegx_cpu_reset; + cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); cc->class_by_name = tilegx_cpu_class_by_name; cc->has_work = tilegx_cpu_has_work; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index df807c1d7437..85bc9f03a1ee 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -153,8 +153,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, tricore_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = tricore_cpu_reset; + cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name = tricore_cpu_class_by_name; cc->has_work = tricore_cpu_has_work; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c65dcf9dd782..4856aee8eca6 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -184,8 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, xtensa_cpu_realizefn, &xcc->parent_realize); - xcc->parent_reset = cc->reset; - cc->reset = xtensa_cpu_reset; + cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); cc->class_by_name = xtensa_cpu_class_by_name; cc->has_work = xtensa_cpu_has_work;