From patchwork Tue Dec 17 04:41:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296553 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59FC9921 for ; Tue, 17 Dec 2019 04:48:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F8BE206B7 for ; Tue, 17 Dec 2019 04:48:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="R808v/mB" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2F8BE206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4mO-0005YM-NP for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:48:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33155) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hr-0007ug-1d for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hp-0005Bc-Er for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:34 -0500 Received: from ozlabs.org ([203.11.71.1]:47621) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ho-00059L-Fj; Mon, 16 Dec 2019 23:43:33 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWN0bg8z9sRc; Tue, 17 Dec 2019 15:43:27 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557808; bh=G3RlUE4GGV7WFPkmzMdVQo+5DIerYIqTacCbW7UfBhU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R808v/mBqidFhYvVtDY4uRannnAPpP0G345pDGEVhZhKrP85+i9FQAspsef/7zp8/ 4H23Bk8hFS85C/6FWmJSmpmJu2ZjtRqdCznsARYqbuaB6WPm7ZsDHi5cHiAGzkguwC 2oM/HVI972Mf1sbx+BHBO1nHjw64LUavbC/zMgP0= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 01/88] ppc/pnv: Add a PNOR model Date: Tue, 17 Dec 2019 15:41:55 +1100 Message-Id: <20191217044322.351838-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater On a POWERPC PowerNV system, the host firmware is stored in a PNOR flash chip which contents is mapped on the LPC bus. This model adds a simple dummy device to map the contents of a block device in the host address space. Signed-off-by: Cédric Le Goater Message-Id: <20191021131215.3693-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/Makefile.objs | 4 +- hw/ppc/pnv.c | 14 ++++ hw/ppc/pnv_pnor.c | 135 ++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv.h | 3 + include/hw/ppc/pnv_pnor.h | 25 +++++++ 5 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 hw/ppc/pnv_pnor.c create mode 100644 include/hw/ppc/pnv_pnor.h diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index 580bb4f0dd..101e9fc591 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -9,7 +9,9 @@ obj-$(CONFIG_PSERIES) += spapr_tpm_proxy.o obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o # IBM PowerNV obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o -obj-$(CONFIG_POWERNV) += pnv_homer.o +obj-$(CONFIG_POWERNV) += pnv_homer.o pnv_pnor.o + + ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) obj-y += spapr_pci_vfio.o spapr_pci_nvlink2.o endif diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 627c08e5b9..d0c1d42277 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -44,6 +44,7 @@ #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_pnor.h" #include "hw/isa/isa.h" #include "hw/boards.h" @@ -633,6 +634,8 @@ static void pnv_init(MachineState *machine) long fw_size; int i; char *chip_typename; + DriveInfo *pnor = drive_get(IF_MTD, 0, 0); + DeviceState *dev; /* allocate RAM */ if (machine->ram_size < (1 * GiB)) { @@ -644,6 +647,17 @@ static void pnv_init(MachineState *machine) machine->ram_size); memory_region_add_subregion(get_system_memory(), 0, ram); + /* + * Create our simple PNOR device + */ + dev = qdev_create(NULL, TYPE_PNV_PNOR); + if (pnor) { + qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), + &error_abort); + } + qdev_init_nofail(dev); + pnv->pnor = PNV_PNOR(dev); + /* load skiboot firmware */ if (bios_name == NULL) { bios_name = FW_FILE_NAME; diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c new file mode 100644 index 0000000000..bfb1e92b03 --- /dev/null +++ b/hw/ppc/pnv_pnor.c @@ -0,0 +1,135 @@ +/* + * QEMU PowerNV PNOR simple model + * + * Copyright (c) 2015-2019, IBM Corporation. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "sysemu/block-backend.h" +#include "sysemu/blockdev.h" +#include "hw/loader.h" +#include "hw/ppc/pnv_pnor.h" +#include "hw/qdev-properties.h" + +static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size) +{ + PnvPnor *s = PNV_PNOR(opaque); + uint64_t ret = 0; + int i; + + for (i = 0; i < size; i++) { + ret |= (uint64_t) s->storage[addr + i] << (8 * (size - i - 1)); + } + + return ret; +} + +static void pnv_pnor_update(PnvPnor *s, int offset, int size) +{ + int offset_end; + + if (s->blk) { + return; + } + + offset_end = offset + size; + offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); + offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); + + blk_pwrite(s->blk, offset, s->storage + offset, + offset_end - offset, 0); +} + +static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + PnvPnor *s = PNV_PNOR(opaque); + int i; + + for (i = 0; i < size; i++) { + s->storage[addr + i] = (data >> (8 * (size - i - 1))) & 0xFF; + } + pnv_pnor_update(s, addr, size); +} + +/* + * TODO: Check endianness: skiboot is BIG, Aspeed AHB is LITTLE, flash + * is BIG. + */ +static const MemoryRegionOps pnv_pnor_ops = { + .read = pnv_pnor_read, + .write = pnv_pnor_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static void pnv_pnor_realize(DeviceState *dev, Error **errp) +{ + PnvPnor *s = PNV_PNOR(dev); + int ret; + + if (s->blk) { + uint64_t perm = BLK_PERM_CONSISTENT_READ | + (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); + ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); + if (ret < 0) { + return; + } + + s->size = blk_getlength(s->blk); + if (s->size <= 0) { + error_setg(errp, "failed to get flash size"); + return; + } + + s->storage = blk_blockalign(s->blk, s->size); + + if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { + error_setg(errp, "failed to read the initial flash content"); + return; + } + } else { + s->storage = blk_blockalign(NULL, s->size); + memset(s->storage, 0xFF, s->size); + } + + memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s, + TYPE_PNV_PNOR, s->size); +} + +static Property pnv_pnor_properties[] = { + DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20), + DEFINE_PROP_DRIVE("drive", PnvPnor, blk), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_pnor_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = pnv_pnor_realize; + dc->props = pnv_pnor_properties; +} + +static const TypeInfo pnv_pnor_info = { + .name = TYPE_PNV_PNOR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PnvPnor), + .class_init = pnv_pnor_class_init, +}; + +static void pnv_pnor_register_types(void) +{ + type_register_static(&pnv_pnor_info); +} + +type_init(pnv_pnor_register_types) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 0b4c722e6b..5ecd3ba6ed 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -24,6 +24,7 @@ #include "hw/sysbus.h" #include "hw/ipmi/ipmi.h" #include "hw/ppc/pnv_lpc.h" +#include "hw/ppc/pnv_pnor.h" #include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_homer.h" @@ -175,6 +176,8 @@ typedef struct PnvMachineState { IPMIBmc *bmc; Notifier powerdown_notifier; + + PnvPnor *pnor; } PnvMachineState; static inline bool pnv_chip_is_power9(const PnvChip *chip) diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h new file mode 100644 index 0000000000..dec811695c --- /dev/null +++ b/include/hw/ppc/pnv_pnor.h @@ -0,0 +1,25 @@ +/* + * QEMU PowerNV PNOR simple model + * + * Copyright (c) 2019, IBM Corporation. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ +#ifndef _PPC_PNV_PNOR_H +#define _PPC_PNV_PNOR_H + +#define TYPE_PNV_PNOR "pnv-pnor" +#define PNV_PNOR(obj) OBJECT_CHECK(PnvPnor, (obj), TYPE_PNV_PNOR) + +typedef struct PnvPnor { + SysBusDevice parent_obj; + + BlockBackend *blk; + + uint8_t *storage; + uint32_t size; + MemoryRegion mmio; +} PnvPnor; + +#endif /* _PPC_PNV_PNOR_H */ From patchwork Tue Dec 17 04:41:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296545 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 136D0921 for ; Tue, 17 Dec 2019 04:45:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D42F1206B7 for ; Tue, 17 Dec 2019 04:45:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="pIudIm2E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D42F1206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jM-0001aR-UK for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:45:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33131) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hq-0007uc-IN for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hp-0005BR-AA for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:34 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:46007 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ho-00059G-BO; Mon, 16 Dec 2019 23:43:33 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWN1j2Vz9sRl; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557808; bh=QvZsbPbPTXJgbugyS+JXPXYYFX2UHblPzgJxd95tWIQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pIudIm2EW9b2PY9LE9wj407nP1c29ArCaz371V9KT3NSmlLQC4OXkKUEcUNiS4IVn CgSnd143JXXrUHpxPet9NkFM/qOinxGPb/HC9+ArEvwa1YLGzQCfY0DhHN6mN9SL43 7y+Z15WxlQ2Q4k7T8FJn0DW6uKue41m4o0Q20l/c= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 02/88] ppc/pnv: Add a "/qemu" device tree node Date: Tue, 17 Dec 2019 15:41:56 +1100 Message-Id: <20191217044322.351838-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater It helps skiboot identifying that is running on a QEMU platform. The compatible string will define the POWERPC processor version. Signed-off-by: Cédric Le Goater Message-Id: <20191106142129.4908-1-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d0c1d42277..416caab6f6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -480,6 +480,9 @@ static void *pnv_dt_create(MachineState *machine) fdt = g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); + /* /qemu node */ + _FDT((fdt_add_subnode(fdt, 0, "qemu"))); + /* Root node */ _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); From patchwork Tue Dec 17 04:41:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296543 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A941C921 for ; Tue, 17 Dec 2019 04:45:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB445206B7 for ; Tue, 17 Dec 2019 04:45:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Cg6ETgnh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB445206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jJ-0001Wp-Qw for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:45:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33148) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hq-0007ue-Oh for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hp-0005CI-S9 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:34 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:36051 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hp-00059E-IJ; Mon, 16 Dec 2019 23:43:33 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWN2rnTz9sRm; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557808; bh=7WtGCoSP4LSJ5xm86Y5S5hA1ZYwNk3CokkO9wz5Tx4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cg6ETgnhI5UCaIXjNxWuuJXXX+oBvZ6WxTm3a6AeceP5TdoUcRozAywauDBJSMFxf +iHG1gXJfm1cFH8OGyxvP61Fx7+rJO9+AkQvjZ936EByh40eyO+YK30nh/YJhJHXc9 lziEipqhe6R0NPWatfEDr4A1dEUiNLWxgWTHqC24= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 03/88] ppc/pnv: Drop "chip" link from POWER9 PSI object Date: Tue, 17 Dec 2019 15:41:57 +1100 Message-Id: <20191217044322.351838-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz It has no apparent user. Signed-off-by: Greg Kurz Message-Id: <157383383118.166856.2588933416368211047.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 416caab6f6..4e9ddc05ad 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1096,8 +1096,6 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), TYPE_PNV9_PSI, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, - &error_abort); object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), TYPE_PNV9_LPC, &error_abort, NULL); From patchwork Tue Dec 17 04:41:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296559 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06D03921 for ; Tue, 17 Dec 2019 04:49:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ADDB8206EC for ; Tue, 17 Dec 2019 04:49:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="PAeF7c4+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADDB8206EC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4nt-0007X0-Lx for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:49:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33243) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hu-0007xh-1E for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hs-0005Hj-QK for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:37 -0500 Received: from ozlabs.org ([203.11.71.1]:48911) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hs-0005C9-Er; Mon, 16 Dec 2019 23:43:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWN6Sbzz9sSK; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557808; bh=3OB/+PigK7cKnLJGlLXLbBDqK/mIpgH/LS3KK12fuxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PAeF7c4+d9nDESaL37rmN2tFtoBquzv9Q+lUAIN/EmM3QGd/G/+oI+xSTPS7MzL5M Szx2e5vM/SZwwRH1Km9vSKSp8bzGo8TQhqJNWmOuKvGOkNTbYpoAUpjmCuVogsb90I QKm4bWAi0QyvwbHYrV+dBcAXPlnctzoChaRfaLg8= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 05/88] xive: Link "xive" property to XiveSource::xive pointer Date: Tue, 17 Dec 2019 15:41:59 +1100 Message-Id: <20191217044322.351838-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The source object has both a pointer and a "xive" property pointing to the notifier object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz Message-Id: <157383333227.165747.12901571295951957951.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 4 ++-- hw/intc/spapr_xive.c | 4 ++-- hw/intc/xive.c | 13 +++---------- hw/ppc/pnv_psi.c | 3 +-- 4 files changed, 8 insertions(+), 16 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 348f2fdd26..9e23dc705d 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1695,8 +1695,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) */ object_property_set_int(OBJECT(xsrc), PNV_XIVE_NR_IRQS, "nr-irqs", &error_fatal); - object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), - &error_fatal); + object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", + &error_abort); object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 9cb8d38a3b..10890aeeeb 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -276,8 +276,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp) */ object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", &error_fatal); - object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(xive), - &error_fatal); + object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", + &error_abort); object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 9376e84aff..2eac15efa6 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1060,17 +1060,8 @@ static void xive_source_reset(void *dev) static void xive_source_realize(DeviceState *dev, Error **errp) { XiveSource *xsrc = XIVE_SOURCE(dev); - Object *obj; - Error *local_err = NULL; - - obj = object_property_get_link(OBJECT(dev), "xive", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'xive' not found: "); - return; - } - xsrc->xive = XIVE_NOTIFIER(obj); + assert(xsrc->xive); if (!xsrc->nr_irqs) { error_setg(errp, "Number of interrupt needs to be greater than 0"); @@ -1116,6 +1107,8 @@ static Property xive_source_properties[] = { DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), + DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, + XiveNotifier *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 68d0dfacfe..a360515a86 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -851,8 +851,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) &error_fatal); object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs", &error_fatal); - object_property_add_const_link(OBJECT(xsrc), "xive", OBJECT(psi), - &error_fatal); + object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort); object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); From patchwork Tue Dec 17 04:42:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DABAC14B7 for ; Tue, 17 Dec 2019 04:48:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B16B5206B7 for ; Tue, 17 Dec 2019 04:48:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="J5JVpA4V" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B16B5206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4me-0005rq-4n for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:48:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33268) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hu-0007y1-Hz for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hs-0005I0-Ui for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:38 -0500 Received: from ozlabs.org ([203.11.71.1]:50079) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hs-0005CB-IV; Mon, 16 Dec 2019 23:43:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWP0gYRz9sS9; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557809; bh=kTPVeY0vCORU7ueoqjo8nwZLHGxRXqP2NzL13CPE7ns=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J5JVpA4V4LjkTSEk/4grQ+tcnmQyaFZH/yU8cO83cIWPmDu9As4IXhTqN8+R03WOG Y6JRi0okZekzJ8+hn3YxHRgt2/1kaoT9eV67Y0o7BxRiHFXw524Y1uOeMkifCVYwuW AaYgPYLQutx6S2vJp5IJi1vyq5U5I0VRa0aLoD+M= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer Date: Tue, 17 Dec 2019 15:42:00 +1100 Message-Id: <20191217044322.351838-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The END source object has both a pointer and a "xive" property pointing to the router object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz Message-Id: <157383333784.165747.5298512574054268786.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 4 ++-- hw/intc/spapr_xive.c | 4 ++-- hw/intc/xive.c | 13 +++---------- 3 files changed, 7 insertions(+), 14 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9e23dc705d..6aa7aeed6f 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1705,8 +1705,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(end_xsrc), PNV_XIVE_NR_ENDS, "nr-ends", &error_fatal); - object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), - &error_fatal); + object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", + &error_abort); object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 10890aeeeb..729246e906 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -290,8 +290,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp) */ object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", &error_fatal); - object_property_add_const_link(OBJECT(end_xsrc), "xive", OBJECT(xive), - &error_fatal); + object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", + &error_abort); object_property_set_bool(OBJECT(end_xsrc), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 2eac15efa6..3d472e29c8 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1814,17 +1814,8 @@ static const MemoryRegionOps xive_end_source_ops = { static void xive_end_source_realize(DeviceState *dev, Error **errp) { XiveENDSource *xsrc = XIVE_END_SOURCE(dev); - Object *obj; - Error *local_err = NULL; - - obj = object_property_get_link(OBJECT(dev), "xive", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'xive' not found: "); - return; - } - xsrc->xrtr = XIVE_ROUTER(obj); + assert(xsrc->xrtr); if (!xsrc->nr_ends) { error_setg(errp, "Number of interrupt needs to be greater than 0"); @@ -1850,6 +1841,8 @@ static Property xive_end_source_properties[] = { DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), + DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, + XiveRouter *), DEFINE_PROP_END_OF_LIST(), }; From patchwork Tue Dec 17 04:42:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296549 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F3D15921 for ; Tue, 17 Dec 2019 04:45:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9F85206B7 for ; Tue, 17 Dec 2019 04:45:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="hY0GgRnb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C9F85206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jU-0001kv-Ta for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:45:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33251) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hu-0007xq-5O for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hs-0005Hb-Lt for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:38 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:51499 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hs-0005C0-Aj; Mon, 16 Dec 2019 23:43:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWN5LtLz9sS6; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557808; bh=cIWbSV2hKfff9gsmveOl7Eih/ky92vv9vdYrVaFyE9s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hY0GgRnblNFayn8s02HEx8IabSoGlVzTNXrXtxxr3NE6EhzL1nTTxPLB5NaCKYHt8 VHezLzmxYgiB0PvgSH9Vk3OR+YFDQmlrnsaEjYkfp+Yar9yyMWxiUEYHDUyE2mN+yY nMvMtZ0zBlEf92ocfAQAJ1mjjUZWyrpb7YD6FXdQ= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer Date: Tue, 17 Dec 2019 15:42:01 +1100 Message-Id: <20191217044322.351838-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The LPC object has both a pointer and a "psi" property pointing to the PSI object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383334342.165747.3159314903077305653.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 8 ++++---- hw/ppc/pnv_lpc.c | 19 ++++++++----------- 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 4e9ddc05ad..201facc701 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -901,8 +901,6 @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), TYPE_PNV8_LPC, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip8->lpc), "psi", - OBJECT(&chip8->psi), &error_abort); object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), TYPE_PNV8_OCC, &error_abort, NULL); @@ -981,6 +979,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) &PNV_PSI(psi8)->xscom_regs); /* Create LPC controller */ + object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", + &error_abort); object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", &error_fatal); pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); @@ -1099,8 +1099,6 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), TYPE_PNV9_LPC, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip9->lpc), "psi", - OBJECT(&chip9->psi), &error_abort); object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), TYPE_PNV9_OCC, &error_abort, NULL); @@ -1199,6 +1197,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) &PNV_PSI(psi9)->xscom_regs); /* LPC */ + object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", + &error_abort); object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 9466d4a1be..fb9f930320 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -24,7 +24,7 @@ #include "qemu/module.h" #include "hw/irq.h" #include "hw/isa/isa.h" - +#include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_xscom.h" @@ -682,17 +682,8 @@ static const TypeInfo pnv_lpc_power9_info = { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc = PNV_LPC(dev); - Object *obj; - Error *local_err = NULL; - obj = object_property_get_link(OBJECT(dev), "psi", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'psi' not found: "); - return; - } - /* The LPC controller needs PSI to generate interrupts */ - lpc->psi = PNV_PSI(obj); + assert(lpc->psi); /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; @@ -734,12 +725,18 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) &lpc->lpc_hc_regs); } +static Property pnv_lpc_properties[] = { + DEFINE_PROP_LINK("psi", PnvLpcController, psi, TYPE_PNV_PSI, PnvPsi *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pnv_lpc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pnv_lpc_realize; dc->desc = "PowerNV LPC Controller"; + dc->props = pnv_lpc_properties; } static const TypeInfo pnv_lpc_info = { From patchwork Tue Dec 17 04:42:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296561 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD47C14B7 for ; Tue, 17 Dec 2019 04:51:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1FE22072B for ; Tue, 17 Dec 2019 04:51:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="O/ij+1BI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A1FE22072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35180 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4p3-0000xF-Be for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:51:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33283) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hv-0007yP-0w for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ht-0005J0-HD for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:38 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:46943 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ht-0005CX-6w; Mon, 16 Dec 2019 23:43:37 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWP2qhgz9sSV; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557809; bh=tSyoSdwyR3uKzR0o5jcXN4uMBZ9xtr5h1Z8KnS7ZHbA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O/ij+1BI0CsG3aTfJN6CiqkvR2CY3k+OPhCiLpatVm5B2FYPIss28whquCgyrYlqC Ed8CDoC5i+MPuPoGRY59zrFpiynbtvRFSb7aPtu5jiVOJvwkTLGNYiM2MRHyxvFIEO 0u1u6ePMHdFzvwSv97Hhn13rJFn0FYKuVPuEA3Fo= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer Date: Tue, 17 Dec 2019 15:42:02 +1100 Message-Id: <20191217044322.351838-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The OCC object has both a pointer and a "psi" property pointing to the PSI object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383334894.165747.7617090757862105199.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 8 ++++---- hw/ppc/pnv_occ.c | 20 +++++++++----------- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 201facc701..ce24a4ee99 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -904,8 +904,6 @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), TYPE_PNV8_OCC, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip8->occ), "psi", - OBJECT(&chip8->psi), &error_abort); object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), TYPE_PNV8_HOMER, &error_abort, NULL); @@ -1000,6 +998,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) } /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", + &error_abort); object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); @@ -1102,8 +1102,6 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), TYPE_PNV9_OCC, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip9->occ), "psi", - OBJECT(&chip9->psi), &error_abort); object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), TYPE_PNV9_HOMER, &error_abort, NULL); @@ -1211,6 +1209,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) (uint64_t) PNV9_LPCM_BASE(chip)); /* Create the simplified OCC model */ + object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", + &error_abort); object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 785653bb67..765c0a6ce5 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" - +#include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_occ.h" @@ -257,18 +257,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp) { PnvOCC *occ = PNV_OCC(dev); PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); - Object *obj; - Error *local_err = NULL; - occ->occmisc = 0; + assert(occ->psi); - obj = object_property_get_link(OBJECT(dev), "psi", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'psi' not found: "); - return; - } - occ->psi = PNV_PSI(obj); + occ->occmisc = 0; /* XScom region for OCC registers */ pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, @@ -279,12 +271,18 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp) occ, "occ-common-area", poc->sram_size); } +static Property pnv_occ_properties[] = { + DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pnv_occ_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pnv_occ_realize; dc->desc = "PowerNV OCC Controller"; + dc->props = pnv_occ_properties; } static const TypeInfo pnv_occ_type_info = { From patchwork Tue Dec 17 04:42:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296565 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EFAD5921 for ; Tue, 17 Dec 2019 04:51:21 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5FC020733 for ; Tue, 17 Dec 2019 04:51:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="F9mVrSJ/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5FC020733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4pM-0001PA-Di for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:51:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33324) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hw-00080Y-6F for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hu-0005KF-ID for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:40 -0500 Received: from ozlabs.org ([203.11.71.1]:58873) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hu-0005D7-5Y; Mon, 16 Dec 2019 23:43:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWP4ntgz9sST; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557809; bh=xdy4ml9PTOzwf29Yc3/mszIQeVuCWoBI17z72LVZWy4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F9mVrSJ/zschzBC4hr9/dboMEgtTG3CYagHIZ89ASSjg9CVJJqjnok+nrth3g+1jS G0lRh1DRAaE1Rukd98F3FLw7kYOFEd8JLsTA0+rjmPK5yzCMITkvLVivA2PapaiVap Lm92mVDaWb/eWoW08vFv4Yv7I13gzwlOD3KO/8Jo= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer Date: Tue, 17 Dec 2019 15:42:03 +1100 Message-Id: <20191217044322.351838-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The homer object has both a pointer and a "chip" property pointing to the chip object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383335451.165747.32301068645427993.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 8 ++++---- hw/ppc/pnv_homer.c | 20 ++++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ce24a4ee99..3fa24a2d60 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -907,8 +907,6 @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), TYPE_PNV8_HOMER, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip8->homer), "chip", obj, - &error_abort); } static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) @@ -1012,6 +1010,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) &chip8->occ.sram_regs); /* HOMER */ + object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", + &error_abort); object_property_set_bool(OBJECT(&chip8->homer), true, "realized", &local_err); if (local_err) { @@ -1105,8 +1105,6 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), TYPE_PNV9_HOMER, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip9->homer), "chip", obj, - &error_abort); } static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) @@ -1223,6 +1221,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) &chip9->occ.sram_regs); /* HOMER */ + object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", + &error_abort); object_property_set_bool(OBJECT(&chip9->homer), true, "realized", &local_err); if (local_err) { diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index cc881a3b32..994a378108 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -22,6 +22,7 @@ #include "exec/memory.h" #include "sysemu/cpus.h" #include "hw/qdev-core.h" +#include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_homer.h" @@ -229,28 +230,27 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp) { PnvHomer *homer = PNV_HOMER(dev); PnvHomerClass *hmrc = PNV_HOMER_GET_CLASS(homer); - Object *obj; - Error *local_err = NULL; - - obj = object_property_get_link(OBJECT(dev), "chip", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'chip' not found: "); - return; - } - homer->chip = PNV_CHIP(obj); + + assert(homer->chip); + /* homer region */ memory_region_init_io(&homer->regs, OBJECT(dev), hmrc->homer_ops, homer, "homer-main-memory", hmrc->homer_size); } +static Property pnv_homer_properties[] = { + DEFINE_PROP_LINK("chip", PnvHomer, chip, TYPE_PNV_CHIP, PnvChip *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pnv_homer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pnv_homer_realize; dc->desc = "PowerNV HOMER Memory"; + dc->props = pnv_homer_properties; } static const TypeInfo pnv_homer_type_info = { From patchwork Tue Dec 17 04:42:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296575 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF7A414B7 for ; Tue, 17 Dec 2019 04:54:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5F422146E for ; Tue, 17 Dec 2019 04:54:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="TNbGcFFp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5F422146E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4sh-0006CU-RA for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:54:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33295) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hv-0007yn-9j for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ht-0005JL-UT for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:39 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45905 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ht-0005D5-K9; Mon, 16 Dec 2019 23:43:37 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWP6L6zz9sSQ; Tue, 17 Dec 2019 15:43:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557809; bh=0Y4e9z7qnnI/ns1o/F7tXL36eNCsL0ItzSihF6vlJW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TNbGcFFpLxa5zPgG11H1BiE4UQ9HJmwxZI9C7HNJNwQtKjwP+SfXc8VtVpyT67ykz bDc/ncs6AnzLTWBstENEOB+oCoWvtlkxu3xOdBGfLnfbjOkysA6SvrJ9eJH9t1K+Au +ytVoTryJM2iWt1ScssVCn+O/3OR+dJwbiGfh1kc= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer Date: Tue, 17 Dec 2019 15:42:04 +1100 Message-Id: <20191217044322.351838-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The core object has both a pointer and a "chip" property pointing to the chip object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383336007.165747.1524120147081367440.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 4 ++-- hw/ppc/pnv_core.c | 10 ++-------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3fa24a2d60..2bf8a3b23b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1327,8 +1327,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) object_property_set_int(OBJECT(pnv_core), pcc->core_pir(chip, core_hwid), "pir", &error_fatal); - object_property_add_const_link(OBJECT(pnv_core), "chip", - OBJECT(chip), &error_fatal); + object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", + &error_abort); object_property_set_bool(OBJECT(pnv_core), true, "realized", &error_fatal); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 61b3d3ce22..5ab75bde6c 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -217,15 +217,8 @@ static void pnv_core_realize(DeviceState *dev, Error **errp) void *obj; int i, j; char name[32]; - Object *chip; - chip = object_property_get_link(OBJECT(dev), "chip", &local_err); - if (!chip) { - error_propagate_prepend(errp, local_err, - "required link 'chip' not found: "); - return; - } - pc->chip = PNV_CHIP(chip); + assert(pc->chip); pc->threads = g_new(PowerPCCPU *, cc->nr_threads); for (i = 0; i < cc->nr_threads; i++) { @@ -297,6 +290,7 @@ static void pnv_core_unrealize(DeviceState *dev, Error **errp) static Property pnv_core_properties[] = { DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), + DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; From patchwork Tue Dec 17 04:42:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296563 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2AC0D921 for ; Tue, 17 Dec 2019 04:51:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3C3E2072B for ; Tue, 17 Dec 2019 04:51:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Tgi+luE7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F3C3E2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4p8-00014A-PX for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:51:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33315) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hv-000808-V8 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hu-0005K5-Ej for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:39 -0500 Received: from ozlabs.org ([203.11.71.1]:53943) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hu-0005Cm-2b; Mon, 16 Dec 2019 23:43:38 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWP3rR1z9sSL; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557809; bh=o607y6vGbDPx2ydgklkHMMijSMIsRAC5+3Ij0tB2wRc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tgi+luE7yWf53Wf1kN5wg+yY6u+wLtXQNIDPyR43tU5/DSZMU1/FkDOt47+D5NOF4 2+fzV8q1B2cxpZ3Pn0kLmYlWrwqsSD7qm77f0Ez5tzDDDRJUQtyMvOoHGR2SJMxVI2 dVlBEJkw2mizaI78JDviUB5/wjamuufapQLhHMpk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer Date: Tue, 17 Dec 2019 15:42:05 +1100 Message-Id: <20191217044322.351838-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The XIVE object has both a pointer and a "chip" property pointing to the chip object. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. Signed-off-by: Greg Kurz Message-Id: <157383336564.165747.10250365296928442882.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 13 +++---------- hw/ppc/pnv.c | 4 ++-- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 6aa7aeed6f..4e56c2e468 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1675,17 +1675,8 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) XiveSource *xsrc = &xive->ipi_source; XiveENDSource *end_xsrc = &xive->end_source; Error *local_err = NULL; - Object *obj; - obj = object_property_get_link(OBJECT(dev), "chip", &local_err); - if (!obj) { - error_propagate(errp, local_err); - error_prepend(errp, "required link 'chip' not found: "); - return; - } - - /* The PnvChip id identifies the XIVE interrupt controller. */ - xive->chip = PNV_CHIP(obj); + assert(xive->chip); /* * The XiveSource and XiveENDSource objects are realized with the @@ -1800,6 +1791,8 @@ static Property pnv_xive_properties[] = { DEFINE_PROP_UINT64("vc-bar", PnvXive, vc_base, 0), DEFINE_PROP_UINT64("pc-bar", PnvXive, pc_base, 0), DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0), + /* The PnvChip id identifies the XIVE interrupt controller. */ + DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 2bf8a3b23b..a2a8b97330 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1091,8 +1091,6 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), TYPE_PNV_XIVE, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, - &error_abort); object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), TYPE_PNV9_PSI, &error_abort, NULL); @@ -1172,6 +1170,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) "pc-bar", &error_fatal); object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), "tm-bar", &error_fatal); + object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", + &error_abort); object_property_set_bool(OBJECT(&chip9->xive), true, "realized", &local_err); if (local_err) { From patchwork Tue Dec 17 04:42:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296567 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B27AD921 for ; Tue, 17 Dec 2019 04:52:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88B6120733 for ; Tue, 17 Dec 2019 04:52:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="P1vTwRBK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 88B6120733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4q5-0002f2-4j for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:52:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33263) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hu-0007y0-Cx for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hs-0005I5-WD for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:38 -0500 Received: from ozlabs.org ([203.11.71.1]:58479) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hs-0005CM-Jh; Mon, 16 Dec 2019 23:43:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWP1mSQz9sSF; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557809; bh=I3lX+zITKorz/QN+en/TanYk+EQ79cpoj7L5bElovIA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P1vTwRBKhY2EqmOjJ74BLJp8tgTSUaCJU77V5t2BRF+iNioKH+xIUMdUiVXOaNiSm f/WVH8xmiXFrHymQebTSo5/Gk+1NUNnMXBqJGeZDvaSxN2TrMlYmzobf8NB9XA+Csf lPzbcfKMJviPGU5LhhOIMXzEnb2MZmUQeIYWjY2k= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 12/88] xics: Link ICS_PROP_XICS property to ICSState::xics pointer Date: Tue, 17 Dec 2019 15:42:06 +1100 Message-Id: <20191217044322.351838-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The ICS object has both a pointer and an ICS_PROP_XICS property pointing to the XICS fabric. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitely sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz Message-Id: <157403283596.409804.17347207690271971987.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 13 +++---------- hw/ppc/pnv_psi.c | 3 +-- hw/ppc/spapr_irq.c | 9 ++------- 3 files changed, 6 insertions(+), 19 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index e7ac9ba618..f7a4548089 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -609,17 +609,8 @@ static void ics_reset_handler(void *dev) static void ics_realize(DeviceState *dev, Error **errp) { ICSState *ics = ICS(dev); - Error *local_err = NULL; - Object *obj; - obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err); - if (!obj) { - error_propagate_prepend(errp, local_err, - "required link '" ICS_PROP_XICS - "' not found: "); - return; - } - ics->xics = XICS_FABRIC(obj); + assert(ics->xics); if (!ics->nr_irqs) { error_setg(errp, "Number of interrupts needs to be greater 0"); @@ -699,6 +690,8 @@ static const VMStateDescription vmstate_ics = { static Property ics_properties[] = { DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), + DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC, + XICSFabric *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index a360515a86..7e725aaf2b 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -497,8 +497,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) } /* Create PSI interrupt control source */ - object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj, - &error_abort); + object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort); object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); if (err) { error_propagate(errp, err); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index d6bb7fd2d6..fbdda14372 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -319,13 +319,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) return; } - object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), - &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - + object_property_set_link(obj, OBJECT(spapr), ICS_PROP_XICS, + &error_abort); object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &local_err); if (local_err) { error_propagate(errp, local_err); From patchwork Tue Dec 17 04:42:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296569 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46EEC921 for ; Tue, 17 Dec 2019 04:53:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 190FF20733 for ; Tue, 17 Dec 2019 04:53:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="CkIFCxxS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 190FF20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4rl-0004lj-5I for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:53:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33485) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i0-00088F-4r for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hy-0005PY-Tp for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:44 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:34677 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005Ip-Il; Mon, 16 Dec 2019 23:43:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWQ5YMDz9sSZ; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557810; bh=pG34byp+FTDvxI9Olx4WbQLypc0hfrTikv9BQlYsOr8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CkIFCxxSJ4asBZRXXQ82IHNZKUR8ILRXCT0PIbs0n6b5oC2UgJG+EW2VrkKmiW9aJ XOQ3GTIEftefNbc2fVTjV7CXXVp3DPetrhBVpaUOqeDRm+UkUYqUhcEWtrIK8BfEVd elfS4k9ntMJ/VVVzr1PNP5OBL5+SvyXnD2TsvWFc= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer Date: Tue, 17 Dec 2019 15:42:07 +1100 Message-Id: <20191217044322.351838-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The ICP object has both a pointer and an ICP_PROP_XICS property pointing to the XICS fabric. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz Message-Id: <157403284152.409804.17114564311521923733.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index f7a4548089..35dddb8867 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -310,15 +310,7 @@ static void icp_realize(DeviceState *dev, Error **errp) Object *obj; Error *err = NULL; - obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err); - if (!obj) { - error_propagate_prepend(errp, err, - "required link '" ICP_PROP_XICS - "' not found: "); - return; - } - - icp->xics = XICS_FABRIC(obj); + assert(icp->xics); obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err); if (!obj) { @@ -368,12 +360,19 @@ static void icp_unrealize(DeviceState *dev, Error **errp) vmstate_unregister(NULL, &vmstate_icp_server, icp); } +static Property icp_properties[] = { + DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC, + XICSFabric *), + DEFINE_PROP_END_OF_LIST(), +}; + static void icp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = icp_realize; dc->unrealize = icp_unrealize; + dc->props = icp_properties; /* * Reason: part of XICS interrupt controller, needs to be wired up * by icp_create(). @@ -397,9 +396,7 @@ Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) obj = object_new(type); object_property_add_child(cpu, type, obj, &error_abort); object_unref(obj); - object_ref(OBJECT(xi)); - object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), - &error_abort); + object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort); object_ref(cpu); object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); object_property_set_bool(obj, true, "realized", &local_err); @@ -417,7 +414,6 @@ void icp_destroy(ICPState *icp) Object *obj = OBJECT(icp); object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort)); - object_unref(object_property_get_link(obj, ICP_PROP_XICS, &error_abort)); object_unparent(obj); } From patchwork Tue Dec 17 04:42:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296573 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6394C14B7 for ; Tue, 17 Dec 2019 04:54:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A1B020733 for ; Tue, 17 Dec 2019 04:54:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Pnashcfm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A1B020733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4sI-0005b5-Q3 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:54:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33616) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i7-0008EL-UI for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4i1-0005T4-E1 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:48 -0500 Received: from ozlabs.org ([203.11.71.1]:39847) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4i1-0005Kk-28; Mon, 16 Dec 2019 23:43:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWR3VHcz9sSd; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557811; bh=DkwFpJiNBFvJaIJBPjZaMoONoRs9YS2BWDzgU84Y6bA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PnashcfmSEHJD4E3gp+tRqqzF360/15aSBhso7G9J9uRrxiDdjepUjWYHVp5q2Z1W vIgtsByciFPSUUp1gt8rpxFp8v5waGI+H8pEVIeNXO/+K+AZNhjUHh6xN7OLYl/2kF 34GPYZCrOi4eMH95Ij+vkgSAPhypWmrwlCll1atY= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer Date: Tue, 17 Dec 2019 15:42:08 +1100 Message-Id: <20191217044322.351838-15-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The ICP object has both a pointer and an ICP_PROP_CPU property pointing to the cpu. Confusing bugs could arise if these ever go out of sync. Change the property definition so that it explicitly sets the pointer. The property isn't optional : not being able to set the link is a bug and QEMU should rather abort than exit in this case. Signed-off-by: Greg Kurz Message-Id: <157403284709.409804.16142099083325945141.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 35dddb8867..0b259a09c5 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -305,25 +305,13 @@ void icp_reset(ICPState *icp) static void icp_realize(DeviceState *dev, Error **errp) { ICPState *icp = ICP(dev); - PowerPCCPU *cpu; CPUPPCState *env; - Object *obj; Error *err = NULL; assert(icp->xics); + assert(icp->cs); - obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err); - if (!obj) { - error_propagate_prepend(errp, err, - "required link '" ICP_PROP_CPU - "' not found: "); - return; - } - - cpu = POWERPC_CPU(obj); - icp->cs = CPU(obj); - - env = &cpu->env; + env = &POWERPC_CPU(icp->cs)->env; switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_POWER7: icp->output = env->irq_inputs[POWER7_INPUT_INT]; @@ -363,6 +351,7 @@ static void icp_unrealize(DeviceState *dev, Error **errp) static Property icp_properties[] = { DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC, XICSFabric *), + DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *), DEFINE_PROP_END_OF_LIST(), }; @@ -397,8 +386,7 @@ Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) object_property_add_child(cpu, type, obj, &error_abort); object_unref(obj); object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort); - object_ref(cpu); - object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); + object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { object_unparent(obj); @@ -413,7 +401,6 @@ void icp_destroy(ICPState *icp) { Object *obj = OBJECT(icp); - object_unref(object_property_get_link(obj, ICP_PROP_CPU, &error_abort)); object_unparent(obj); } From patchwork Tue Dec 17 04:42:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296583 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 498296C1 for ; Tue, 17 Dec 2019 04:58:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1ECF120733 for ; Tue, 17 Dec 2019 04:58:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="fwQ2P6Nc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1ECF120733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4vt-0002cs-OC for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:58:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33474) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4hz-00087W-Tu for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hy-0005Oy-Mg for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:43 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:59887 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005JP-BC; Mon, 16 Dec 2019 23:43:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWR0Dtnz9sRX; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557811; bh=eIhwrx3OcXp3/wr/CB8zxrx4IUYT4c8un45IagMXKSk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fwQ2P6NclKPnCR9V852flQoYRWui02gKSN/Q5y0Nt/K6hIQ9/lHjcpPk000eEMLP8 GN9iG7yx5i9ffc21aE11dhZZla+nbrOKI9fpxy7rLNYcgilYt7Wb4Jc5y86HawdOTz JiKV8tsOxN73PxrkItO++Ef6gL/ibmOfaXLhQrFw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized Date: Tue, 17 Dec 2019 15:42:09 +1100 Message-Id: <20191217044322.351838-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Failing to set any of the ICS property should really never happen: - object_property_add_child() always succeed unless the child object already has a parent, which isn't the case here obviously since the ICS has just been created with object_new() - the ICS has an "nr-irqs" property than can be set as long as the ICS isn't realized In both cases, an error indicates there is a bug in QEMU. Propagating the error, ie. exiting QEMU since spapr_irq_init() is called with &error_fatal doesn't make much sense. Abort instead. This is consistent with what is done with XIVE : both qdev_create() and qdev_prop_set_uint32() abort QEMU on error. Signed-off-by: Greg Kurz Message-Id: <157403285265.409804.8683093665795248192.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/spapr_irq.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index fbdda14372..d4a54afc86 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -313,20 +313,11 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) Object *obj; obj = object_new(TYPE_ICS_SPAPR); - object_property_add_child(OBJECT(spapr), "ics", obj, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } + object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); object_property_set_link(obj, OBJECT(spapr), ICS_PROP_XICS, &error_abort); - object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - + object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); From patchwork Tue Dec 17 04:42:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296577 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77CCF14B7 for ; Tue, 17 Dec 2019 04:56:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CC9A20733 for ; Tue, 17 Dec 2019 04:56:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KSKF80Ca" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4CC9A20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4u0-0008KG-UH for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:56:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33491) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i0-00088S-9m for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hz-0005Q5-8y for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:44 -0500 Received: from ozlabs.org ([203.11.71.1]:44197) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005It-TO; Mon, 16 Dec 2019 23:43:43 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWQ3Mvlz9sSc; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557810; bh=XLlY5FBUcVMyrEFkz9vewlVb4cLY9FD8ynFlsFrhYL8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KSKF80CaXWmW06rRmci+xEwVB+LYvGxtsvh3hzelY8T+Dd9SIZYtXbAbThavsbihv ZK4xd0fHbPdra+NZVCXDxMYZ4lu0cqExqMecN3HM4ALgydCbNgPZUjZ/hIryxwHDrz EQcy7JaDgk7sngoCe0DNHkEHCMo2/cGH3V1YzyDQ= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 16/88] ppc/pnv: Add a LPC "ranges" property Date: Tue, 17 Dec 2019 15:42:10 +1100 Message-Id: <20191217044322.351838-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater And fix a typo in the MEM address space definition. Signed-off-by: Cédric Le Goater Message-Id: <20191118091908.15044-1-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv_lpc.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index fb9f930320..c5a85c38c7 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -86,7 +86,7 @@ enum { #define ISA_FW_SIZE 0x10000000 #define LPC_IO_OPB_ADDR 0xd0010000 #define LPC_IO_OPB_SIZE 0x00010000 -#define LPC_MEM_OPB_ADDR 0xe0010000 +#define LPC_MEM_OPB_ADDR 0xe0000000 #define LPC_MEM_OPB_SIZE 0x10000000 #define LPC_FW_OPB_ADDR 0xf0000000 #define LPC_FW_OPB_SIZE 0x10000000 @@ -143,6 +143,16 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset) cpu_to_be32(PNV9_LPCM_SIZE >> 32), cpu_to_be32((uint32_t)PNV9_LPCM_SIZE), }; + uint32_t lpc_ranges[12] = { 0, 0, + cpu_to_be32(LPC_MEM_OPB_ADDR), + cpu_to_be32(LPC_MEM_OPB_SIZE), + cpu_to_be32(1), 0, + cpu_to_be32(LPC_IO_OPB_ADDR), + cpu_to_be32(LPC_IO_OPB_SIZE), + cpu_to_be32(3), 0, + cpu_to_be32(LPC_FW_OPB_ADDR), + cpu_to_be32(LPC_FW_OPB_SIZE), + }; uint32_t reg[2]; /* @@ -211,6 +221,8 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset) _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat, sizeof(lpc_compat)))); + _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges, + sizeof(lpc_ranges)))); return 0; } From patchwork Tue Dec 17 04:42:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296591 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68DA6930 for ; Tue, 17 Dec 2019 05:00:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3ECFB20733 for ; Tue, 17 Dec 2019 05:00:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="X/TXAZPi" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3ECFB20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4y8-00066H-Tu for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:00:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33573) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i2-0008CH-G7 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4i1-0005SR-7V for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:46 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:51863 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4i0-0005Ko-T4; Mon, 16 Dec 2019 23:43:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWR547Yz9sSX; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557811; bh=z9QUoRpZ10vAUbFSnp5wy0y9JozdiioGdb647sP2Mqw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X/TXAZPik/kVDT/nyVLQgoYMExWlJ0CAAah+Yy667Bfd+p3H8OJMlXXQEgsctdsrA fhcxSvac5hQt3HYBdZgTLL4I6NI2xSyekxlYWy07GygdS6KmYCBYF00djaUKvokIFE aes7SdjxqYiL6PyGxEYOOuqKSuTru6Pht0n0d1Dc= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 17/88] ppc/xive: Record the IPB in the associated NVT Date: Tue, 17 Dec 2019 15:42:11 +1100 Message-Id: <20191217044322.351838-18-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When an interrupt can not be presented to a vCPU, because it is not running on any of the HW treads, the XIVE presenter updates the Interrupt Pending Buffer register of the associated XIVE NVT structure. This is only done if backlog is activated in the END but this is generally the case. The current code assumes that the fields of the NVT structure is architected with the same layout of the thread interrupt context registers. Fix this assumption and define an offset for the IPB register backup value in the NVT. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-2-clg@kaod.org> Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xive.c | 11 +++++++++-- include/hw/ppc/xive_regs.h | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 3d472e29c8..177663d2b4 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1607,14 +1607,21 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, * - logical server : forward request to IVPE (not supported) */ if (xive_end_is_backlog(&end)) { + uint8_t ipb; + if (format == 1) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x invalid config: F1 & backlog\n", end_blk, end_idx); return; } - /* Record the IPB in the associated NVT structure */ - ipb_update((uint8_t *) &nvt.w4, priority); + /* + * Record the IPB in the associated NVT structure for later + * use. The presenter will resend the interrupt when the vCPU + * is dispatched again on a HW thread. + */ + ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); + nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); /* diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 55307cd153..530f232b04 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -255,6 +255,7 @@ typedef struct XiveNVT { uint32_t w2; uint32_t w3; uint32_t w4; +#define NVT_W4_IPB PPC_BITMASK32(16, 23) uint32_t w5; uint32_t w6; uint32_t w7; From patchwork Tue Dec 17 04:42:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296585 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D548214B7 for ; Tue, 17 Dec 2019 04:58:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB40020733 for ; Tue, 17 Dec 2019 04:58:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="cM2m+FkK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB40020733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4wJ-0003LU-Bp for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:58:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33495) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i0-00088Z-FH for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hz-0005QE-AD for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:44 -0500 Received: from ozlabs.org ([203.11.71.1]:51113) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005Ij-Uw; Mon, 16 Dec 2019 23:43:43 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWQ1vdjz9sSf; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557810; bh=YLyu+TvN7QrUe5KSxjn+8t7hVOL9DOYECayzY0UoxQ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cM2m+FkKSmhv6a6eeLH7PuMRwGE16qJRzFbL486Gr6EKFK/kSj73KfyHvBQJJoWmU 9+PE7q7Fql3zqyGZO5VLtJCb91/R/8naMGS/I1D0AgMacD/NqQtWQ9tlPKlWXGTcK6 ZiVjs80xns3Wnan2xL+lDbCglW8OHy2WbJ4aflEg= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 18/88] ppc/xive: Introduce helpers for the NVT id Date: Tue, 17 Dec 2019 15:42:12 +1100 Message-Id: <20191217044322.351838-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Each vCPU in the system is identified with an NVT identifier which is pushed in the OS CAM line (QW1W2) of the HW thread interrupt context register when the vCPU is dispatched on a HW thread. This identifier is used by the presenter subengine to find a matching target to notify of an event. It is also used to fetch the associate NVT structure which may contain pending interrupts that need a resend. Add a couple of helpers for the NVT ids. The NVT space is 19 bits wide, giving a maximum of 512K per chip. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-3-clg@kaod.org> Signed-off-by: David Gibson --- include/hw/ppc/xive.h | 5 ----- include/hw/ppc/xive_regs.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 8fd439ec9b..fa7adf87fe 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -418,11 +418,6 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); -static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) -{ - return (nvt_blk << 19) | nvt_idx; -} - /* * KVM XIVE device helpers */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 530f232b04..1a5622f8de 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -272,4 +272,25 @@ typedef struct XiveNVT { #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) +/* + * The VP number space in a block is defined by the END_W6_NVT_INDEX + * field of the XIVE END + */ +#define XIVE_NVT_SHIFT 19 + +static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) +{ + return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; +} + +static inline uint32_t xive_nvt_idx(uint32_t cam_line) +{ + return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); +} + +static inline uint32_t xive_nvt_blk(uint32_t cam_line) +{ + return (cam_line >> XIVE_NVT_SHIFT) & 0xf; +} + #endif /* PPC_XIVE_REGS_H */ From patchwork Tue Dec 17 04:42:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1912930 for ; Tue, 17 Dec 2019 05:04:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B66E520733 for ; Tue, 17 Dec 2019 05:04:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Gi+HCqPI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B66E520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih51s-0002C6-Dr for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:04:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33499) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i0-00088b-H1 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hy-0005P7-Oq for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:44 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:59651 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005Jt-DG; Mon, 16 Dec 2019 23:43:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWR297tz9sSY; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557811; bh=QKA6fjaDYEUorHcTXfljK4SzeitthhfaucE1VVMPv2k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gi+HCqPIEXTEkG8guGaN47BL36Z3Z5EOVFuItHYu9vC8HAQz7qvXKAaY/mqhL4fus bLK/x596QSjlNVenRL1HAhjXavRrLnWi0q6O41VmlPLTFgWNycQt6Gb4qRWWMthWY6 U543iVzznNhHVeLduHE7akGnl3kMLnxKk0Y5OAkI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine Date: Tue, 17 Dec 2019 15:42:13 +1100 Message-Id: <20191217044322.351838-20-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater pnv_xive_vst_size() tries to compute the size of a VSD table from the information given by FW. The number of entries of the table are deduced from the result and the MMIO regions of the ESBs and the END ESBs are then resized accordingly with the computed value. This reduces the number of elements that can be addressed by the ESB pages. The maximum number of elements of a direct table can contain is simply: Table size / sizeof(XIVE structure) An indirect table is a one page array of VSDs pointing to subpages containing XIVE virtual structures and the maximum number of elements an indirect table can contain : (PAGE_SIZE / sizeof(vsd)) * (PAGE_SIZE / sizeof(XIVE structure)) which gives us 16M for XiveENDs, 8M for XiveNVTs. That's more than the associated VC and PC BARS can address. The result returned by pnv_xive_vst_size() for indirect tables is incorrect and can not be used to reduce the size of the MMIO region of a XIVE resource using an indirect table, such as ENDs in skiboot. Remove pnv_xive_vst_size() and use a simpler form for direct tables only. Keep the resizing of the MMIO region for direct tables only as this is still useful for the ESB MMIO window. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-4-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 112 +++++++++++++++++---------------------------- 1 file changed, 43 insertions(+), 69 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 4e56c2e468..a4d80fd5e7 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -123,36 +123,22 @@ static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift) page_shift == 21 || page_shift == 24; } -static uint64_t pnv_xive_vst_size(uint64_t vsd) -{ - uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); - - /* - * Read the first descriptor to get the page size of the indirect - * table. - */ - if (VSD_INDIRECT & vsd) { - uint32_t nr_pages = vst_tsize / XIVE_VSD_SIZE; - uint32_t page_shift; - - vsd = ldq_be_dma(&address_space_memory, vsd & VSD_ADDRESS_MASK); - page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; - - if (!pnv_xive_vst_page_size_allowed(page_shift)) { - return 0; - } - - return nr_pages * (1ull << page_shift); - } - - return vst_tsize; -} - static uint64_t pnv_xive_vst_addr_direct(PnvXive *xive, uint32_t type, uint64_t vsd, uint32_t idx) { const XiveVstInfo *info = &vst_infos[type]; uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; + uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); + uint32_t idx_max; + + idx_max = vst_tsize / info->size - 1; + if (idx > idx_max) { +#ifdef XIVE_DEBUG + xive_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", + info->name, idx, idx_max); +#endif + return 0; + } return vst_addr + idx * info->size; } @@ -215,7 +201,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, { const XiveVstInfo *info = &vst_infos[type]; uint64_t vsd; - uint32_t idx_max; if (blk >= info->max_blocks) { xive_error(xive, "VST: invalid block id %d for VST %s %d !?", @@ -232,15 +217,6 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } - idx_max = pnv_xive_vst_size(vsd) / info->size - 1; - if (idx > idx_max) { -#ifdef XIVE_DEBUG - xive_error(xive, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?", - info->name, blk, idx, idx_max); -#endif - return 0; - } - if (VSD_INDIRECT & vsd) { return pnv_xive_vst_addr_indirect(xive, type, vsd, idx); } @@ -453,19 +429,12 @@ static uint64_t pnv_xive_pc_size(PnvXive *xive) return (~xive->regs[CQ_PC_BARM >> 3] + 1) & CQ_PC_BARM_MASK; } -static uint32_t pnv_xive_nr_ipis(PnvXive *xive) +static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) { - uint8_t blk = xive->chip->chip_id; - - return pnv_xive_vst_size(xive->vsds[VST_TSEL_SBE][blk]) * SBE_PER_BYTE; -} - -static uint32_t pnv_xive_nr_ends(PnvXive *xive) -{ - uint8_t blk = xive->chip->chip_id; + uint64_t vsd = xive->vsds[VST_TSEL_SBE][blk]; + uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); - return pnv_xive_vst_size(xive->vsds[VST_TSEL_EQDT][blk]) - / vst_infos[VST_TSEL_EQDT].size; + return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; } /* @@ -598,6 +567,7 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type, XiveSource *xsrc = &xive->ipi_source; const XiveVstInfo *info = &vst_infos[type]; uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; + uint64_t vst_tsize = 1ull << page_shift; uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; /* Basic checks */ @@ -633,11 +603,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type, case VST_TSEL_EQDT: /* - * Backing store pages for the END. Compute the number of ENDs - * provisioned by FW and resize the END ESB window accordingly. + * Backing store pages for the END. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * END ESB window accordingly. */ - memory_region_set_size(&end_xsrc->esb_mmio, pnv_xive_nr_ends(xive) * - (1ull << (end_xsrc->esb_shift + 1))); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->end_edt_mmio, 0, &end_xsrc->esb_mmio); break; @@ -646,11 +621,16 @@ static void pnv_xive_vst_set_exclusive(PnvXive *xive, uint8_t type, /* * Backing store pages for the source PQ bits. The model does * not use these PQ bits backed in RAM because the XiveSource - * model has its own. Compute the number of IRQs provisioned - * by FW and resize the IPI ESB window accordingly. + * model has its own. + * + * If the table is direct, we can compute the number of PQ + * entries provisioned by FW (such as skiboot) and resize the + * ESB window accordingly. */ - memory_region_set_size(&xsrc->esb_mmio, pnv_xive_nr_ipis(xive) * - (1ull << xsrc->esb_shift)); + if (!(VSD_INDIRECT & vsd)) { + memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE + * (1ull << xsrc->esb_shift)); + } memory_region_add_subregion(&xive->ipi_edt_mmio, 0, &xsrc->esb_mmio); break; @@ -1579,8 +1559,7 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) XiveRouter *xrtr = XIVE_ROUTER(xive); uint8_t blk = xive->chip->chip_id; uint32_t srcno0 = XIVE_EAS(blk, 0); - uint32_t nr_ipis = pnv_xive_nr_ipis(xive); - uint32_t nr_ends = pnv_xive_nr_ends(xive); + uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; int i; @@ -1600,21 +1579,16 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) } } - monitor_printf(mon, "XIVE[%x] ENDT %08x .. %08x\n", blk, 0, nr_ends - 1); - for (i = 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + i = 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_pic_print_info(&end, i++, mon); } - monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0, - nr_ends - 1); - for (i = 0; i < nr_ends; i++) { - if (xive_router_get_end(xrtr, blk, i, &end)) { - break; - } - xive_end_eas_pic_print_info(&end, i, mon); + monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + i = 0; + while (!xive_router_get_end(xrtr, blk, i, &end)) { + xive_end_eas_pic_print_info(&end, i++, mon); } } From patchwork Tue Dec 17 04:42:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 37004930 for ; Tue, 17 Dec 2019 05:01:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C49B20733 for ; Tue, 17 Dec 2019 05:01:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="aDveKUjx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0C49B20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4z7-0006u6-FE for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:01:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33480) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i0-00087w-10 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hy-0005PO-S7 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:43 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:40345 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005IT-Gb; Mon, 16 Dec 2019 23:43:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWQ1BM3z9sSR; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557810; bh=/bVJz8FI8ZTVWwvUmPr/bk76ycZKdhdgCe/CQD3lNcU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aDveKUjxtBsezpxRKF71hef+xdIR8PlvVfdS2M9ociV5MIpK0605jwrGBVGY/zsTu 1WhOOToprven+U/F89xG3Zvbz1uhxyvbpnIw1EM5xgiYHGSfCft5fiPzIA/Z29opVH qB9hZNmKm5Rv4+LZeRx2w8tELuMih8ceWhT+Efik= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 20/88] xive/kvm: Trigger interrupts from userspace Date: Tue, 17 Dec 2019 15:42:14 +1100 Message-Id: <20191217044322.351838-21-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz When using the XIVE KVM device, the trigger page is directly accessible in QEMU. Unlike with XICS, no need to ask KVM to fire the interrupt. A simple store on the trigger page does the job. Just call xive_esb_trigger(). This may improve performance of emulated devices that go through qemu_set_irq(), eg. virtio devices created with ioeventfd=off or configured by the guest to use LSI interrupts, which aren't really recommended setups. Signed-off-by: Greg Kurz Message-Id: <157408992731.494439.3405812941731584740.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/spapr_xive_kvm.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 08012ac7cd..69e73552f1 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -354,32 +354,20 @@ static void kvmppc_xive_source_get_state(XiveSource *xsrc) void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val) { XiveSource *xsrc = opaque; - SpaprXive *xive = SPAPR_XIVE(xsrc->xive); - struct kvm_irq_level args; - int rc; - - /* The KVM XIVE device should be in use */ - assert(xive->fd != -1); - args.irq = srcno; if (!xive_source_irq_is_lsi(xsrc, srcno)) { if (!val) { return; } - args.level = KVM_INTERRUPT_SET; } else { if (val) { xsrc->status[srcno] |= XIVE_STATUS_ASSERTED; - args.level = KVM_INTERRUPT_SET_LEVEL; } else { xsrc->status[srcno] &= ~XIVE_STATUS_ASSERTED; - args.level = KVM_INTERRUPT_UNSET; } } - rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args); - if (rc < 0) { - error_report("XIVE: kvm_irq_line() failed : %s", strerror(errno)); - } + + xive_esb_trigger(xsrc, srcno); } /* From patchwork Tue Dec 17 04:42:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1DD2930 for ; Tue, 17 Dec 2019 05:10:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86D202072D for ; Tue, 17 Dec 2019 05:10:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="MF40L5ZU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 86D202072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih57V-0002cM-6v for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:10:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33859) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iS-00008m-Jt for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iR-0005n9-J0 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:12 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:52677 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iR-0005Q9-8L; Mon, 16 Dec 2019 23:44:11 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWS3GRlz9sSj; Tue, 17 Dec 2019 15:43:30 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557812; bh=Qr/f8LIMoTqVdF6BB8cAbzhbd2tEVe4IjlvUHANWBx8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MF40L5ZUudkHSZpryrBv9Ep/ltcxpiSVzF/0+3hudN8JjiGS2pSADeli6vQ3Ckszo oZgAxziaIeWaYGkTLf5VKBHO6oODvrIccviR45zC6Qhb75V6TuOIvjISPkQtB5ZgNd lDcS2eDLuZrlgZrPYKmcoNhxlpfFujpJ7rWVW5Ng= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 21/88] ppc/pnv: Quiesce some XIVE errors Date: Tue, 17 Dec 2019 15:42:15 +1100 Message-Id: <20191217044322.351838-22-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When dumping the END and NVT tables, the error logging is too noisy. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-6-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index a4d80fd5e7..9a771f6407 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -29,7 +29,7 @@ #include "pnv_xive_regs.h" -#define XIVE_DEBUG +#undef XIVE_DEBUG /* * Virtual structures table (VST) @@ -157,7 +157,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type, vsd = ldq_be_dma(&address_space_memory, vsd_addr); if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); +#endif return 0; } @@ -178,7 +180,9 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type, vsd = ldq_be_dma(&address_space_memory, vsd_addr); if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); +#endif return 0; } From patchwork Tue Dec 17 04:42:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296629 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 07E5C930 for ; Tue, 17 Dec 2019 05:12:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D19CB2072D for ; Tue, 17 Dec 2019 05:12:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="GLrd+IAl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D19CB2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih59v-0006IR-EL for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:12:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33883) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iT-0000BR-Uj for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iS-0005oo-S7 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:13 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45237 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iS-0005Pr-I7; Mon, 16 Dec 2019 23:44:12 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWS1cnDz9sSm; Tue, 17 Dec 2019 15:43:30 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557812; bh=pepwT/pUYDx/GUmEQo/uunQvZUzzeXQhKHZYA4EiAUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GLrd+IAlG/GsubjIeT8gx3BUy5KFq6n1O6umPxJCbz9ogKA6p29GXFXb5CET0bcbr NbCUMABpgtcc3I6XFubM2O1nKzew2IPwvQYHaYLyYMWBG85tspDqqp4Sl4XQNMHug4 i/NuKd+TTQmrqQsyluZM7pwCExv2qEu98ASkq4t4= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 22/88] ppc/xive: Introduce OS CAM line helpers Date: Tue, 17 Dec 2019 15:42:16 +1100 Message-Id: <20191217044322.351838-23-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The OS CAM line has a special encoding exploited by the HW. Provide helper routines to hide the details to the TIMA command handlers. This also clarifies the endianness of different variables : 'qw1w2' is big-endian and 'cam' is native. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-7-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 177663d2b4..42e9a11ef7 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -337,14 +337,49 @@ static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, xive_tctx_notify(tctx, TM_QW1_OS); } +static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, + uint32_t *nvt_idx, bool *vo) +{ + if (nvt_blk) { + *nvt_blk = xive_nvt_blk(cam); + } + if (nvt_idx) { + *nvt_idx = xive_nvt_idx(cam); + } + if (vo) { + *vo = !!(cam & TM_QW1W2_VO); + } +} + +static uint32_t xive_tctx_get_os_cam(XiveTCTX *tctx, uint8_t *nvt_blk, + uint32_t *nvt_idx, bool *vo) +{ + uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); + uint32_t cam = be32_to_cpu(qw1w2); + + xive_os_cam_decode(cam, nvt_blk, nvt_idx, vo); + return qw1w2; +} + +static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) +{ + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); +} + static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, unsigned size) { - uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); uint32_t qw1w2; + uint32_t qw1w2_new; + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vo; - qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); + + /* Invalidate CAM line */ + qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); + xive_tctx_set_os_cam(tctx, qw1w2_new); return qw1w2; } From patchwork Tue Dec 17 04:42:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296611 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53DD414B7 for ; Tue, 17 Dec 2019 05:07:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 262D12072D for ; Tue, 17 Dec 2019 05:07:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="B/VxeNQ2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 262D12072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih551-00077a-ND for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:07:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33708) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iG-0008JO-5S for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iB-0005ZB-C8 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:58 -0500 Received: from ozlabs.org ([203.11.71.1]:59995) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iA-0005Qt-3f; Mon, 16 Dec 2019 23:43:54 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWT4m6Kz9sSq; Tue, 17 Dec 2019 15:43:30 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557813; bh=rqWdDbUCcpNjWZZpcK2jNRyA4bZeefxs9gm4nLiAqUM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B/VxeNQ25Ptsu8PVHK1qRpKomuP7Z9uRb5/EpuD/ky6m5jTzA0VoS3XjljzR2kmIq lI8853r20DoThbJx7NSrepkK5BIjiVD1tVulKsazZvdGTD7ei83a/e2kubthKTQDwz D5r+QxAKRpX+VuUlZvL0rkqwgEz4dPvdBx6CeDrA= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX Date: Tue, 17 Dec 2019 15:42:17 +1100 Message-Id: <20191217044322.351838-24-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater A context should be 'valid' when pulled from the thread interrupt context registers. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-8-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 42e9a11ef7..511e1a9363 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -377,6 +377,11 @@ static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, qw1w2 = xive_tctx_get_os_cam(tctx, &nvt_blk, &nvt_idx, &vo); + if (!vo) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVT %x/%x !?\n", + nvt_blk, nvt_idx); + } + /* Invalidate CAM line */ qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0); xive_tctx_set_os_cam(tctx, qw1w2_new); From patchwork Tue Dec 17 04:42:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296595 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A0714B7 for ; Tue, 17 Dec 2019 05:02:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E75120733 for ; Tue, 17 Dec 2019 05:02:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="duOEa1Wp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4E75120733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih50A-0008IK-L7 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:02:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33908) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iV-0000Dl-9X for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iR-0005nb-T5 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:15 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:55305 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iR-0005UW-IQ; Mon, 16 Dec 2019 23:44:11 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWV17mhz9sSp; Tue, 17 Dec 2019 15:43:30 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557814; bh=0iPUaHnfHvwmQN/HVOaXeUDSVR/0Qc7oi4z2XkI4XvI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=duOEa1WpjVZZTvCXheJ6aFjf0DKjmsOq8UXjkePPCvPa0LkWTt2kulgSQlxCYbfhd NctQ1SNieFNecqm29TIzZc4dYBEp/F7T+NBhKtIVzZeUxpIWjrnS7UqSUnAGaRyNBZ Gnxx9A6m6eAsxFc38OND8XhFVcGlPApYO5PfHjcE= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 24/88] ipmi: Add support to customize OEM functions Date: Tue, 17 Dec 2019 15:42:18 +1100 Message-Id: <20191217044322.351838-25-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Corey Minyard , aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The routine ipmi_register_oem_netfn() lets external modules register command handlers for OEM functions. Required for the PowerNV machine. Cc: Corey Minyard Reviewed-by: Corey Minyard Signed-off-by: Cédric Le Goater Message-Id: <20191028070027.22752-2-clg@kaod.org> Acked-by: Corey Minyard Signed-off-by: David Gibson --- hw/ipmi/ipmi_bmc_sim.c | 50 +++++------------------------------------- include/hw/ipmi/ipmi.h | 42 +++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 44 deletions(-) diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c index 71e56f3b13..6670cf039d 100644 --- a/hw/ipmi/ipmi_bmc_sim.c +++ b/hw/ipmi/ipmi_bmc_sim.c @@ -167,32 +167,14 @@ typedef struct IPMISensor { #define MAX_SENSORS 20 #define IPMI_WATCHDOG_SENSOR 0 -typedef struct IPMIBmcSim IPMIBmcSim; -typedef struct RspBuffer RspBuffer; - #define MAX_NETFNS 64 -typedef struct IPMICmdHandler { - void (*cmd_handler)(IPMIBmcSim *s, - uint8_t *cmd, unsigned int cmd_len, - RspBuffer *rsp); - unsigned int cmd_len_min; -} IPMICmdHandler; - -typedef struct IPMINetfn { - unsigned int cmd_nums; - const IPMICmdHandler *cmd_handlers; -} IPMINetfn; - typedef struct IPMIRcvBufEntry { QTAILQ_ENTRY(IPMIRcvBufEntry) entry; uint8_t len; uint8_t buf[MAX_IPMI_MSG_SIZE]; } IPMIRcvBufEntry; -#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim" -#define IPMI_BMC_SIMULATOR(obj) OBJECT_CHECK(IPMIBmcSim, (obj), \ - TYPE_IPMI_BMC_SIMULATOR) struct IPMIBmcSim { IPMIBmc parent; @@ -279,28 +261,8 @@ struct IPMIBmcSim { #define IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN 2 #define IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE 3 -struct RspBuffer { - uint8_t buffer[MAX_IPMI_MSG_SIZE]; - unsigned int len; -}; - #define RSP_BUFFER_INITIALIZER { } -static inline void rsp_buffer_set_error(RspBuffer *rsp, uint8_t byte) -{ - rsp->buffer[2] = byte; -} - -/* Add a byte to the response. */ -static inline void rsp_buffer_push(RspBuffer *rsp, uint8_t byte) -{ - if (rsp->len >= sizeof(rsp->buffer)) { - rsp_buffer_set_error(rsp, IPMI_CC_REQUEST_DATA_TRUNCATED); - return; - } - rsp->buffer[rsp->len++] = byte; -} - static inline void rsp_buffer_pushmore(RspBuffer *rsp, uint8_t *bytes, unsigned int n) { @@ -630,8 +592,8 @@ static void ipmi_init_sensors_from_sdrs(IPMIBmcSim *s) } } -static int ipmi_register_netfn(IPMIBmcSim *s, unsigned int netfn, - const IPMINetfn *netfnd) +int ipmi_sim_register_netfn(IPMIBmcSim *s, unsigned int netfn, + const IPMINetfn *netfnd) { if ((netfn & 1) || (netfn >= MAX_NETFNS) || (s->netfns[netfn / 2])) { return -1; @@ -1860,10 +1822,10 @@ static const IPMINetfn storage_netfn = { static void register_cmds(IPMIBmcSim *s) { - ipmi_register_netfn(s, IPMI_NETFN_CHASSIS, &chassis_netfn); - ipmi_register_netfn(s, IPMI_NETFN_SENSOR_EVENT, &sensor_event_netfn); - ipmi_register_netfn(s, IPMI_NETFN_APP, &app_netfn); - ipmi_register_netfn(s, IPMI_NETFN_STORAGE, &storage_netfn); + ipmi_sim_register_netfn(s, IPMI_NETFN_CHASSIS, &chassis_netfn); + ipmi_sim_register_netfn(s, IPMI_NETFN_SENSOR_EVENT, &sensor_event_netfn); + ipmi_sim_register_netfn(s, IPMI_NETFN_APP, &app_netfn); + ipmi_sim_register_netfn(s, IPMI_NETFN_STORAGE, &storage_netfn); } static uint8_t init_sdrs[] = { diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h index 6f2413b39b..8a99d958bb 100644 --- a/include/hw/ipmi/ipmi.h +++ b/include/hw/ipmi/ipmi.h @@ -55,6 +55,7 @@ enum ipmi_op { #define IPMI_CC_COMMAND_NOT_SUPPORTED 0xd5 #define IPMI_NETFN_APP 0x06 +#define IPMI_NETFN_OEM 0x3a #define IPMI_DEBUG 1 @@ -265,4 +266,45 @@ int ipmi_bmc_sdr_find(IPMIBmc *b, uint16_t recid, const struct ipmi_sdr_compact **sdr, uint16_t *nextrec); void ipmi_bmc_gen_event(IPMIBmc *b, uint8_t *evt, bool log); +#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim" +#define IPMI_BMC_SIMULATOR(obj) OBJECT_CHECK(IPMIBmcSim, (obj), \ + TYPE_IPMI_BMC_SIMULATOR) + +typedef struct IPMIBmcSim IPMIBmcSim; + +typedef struct RspBuffer { + uint8_t buffer[MAX_IPMI_MSG_SIZE]; + unsigned int len; +} RspBuffer; + +static inline void rsp_buffer_set_error(RspBuffer *rsp, uint8_t byte) +{ + rsp->buffer[2] = byte; +} + +/* Add a byte to the response. */ +static inline void rsp_buffer_push(RspBuffer *rsp, uint8_t byte) +{ + if (rsp->len >= sizeof(rsp->buffer)) { + rsp_buffer_set_error(rsp, IPMI_CC_REQUEST_DATA_TRUNCATED); + return; + } + rsp->buffer[rsp->len++] = byte; +} + +typedef struct IPMICmdHandler { + void (*cmd_handler)(IPMIBmcSim *s, + uint8_t *cmd, unsigned int cmd_len, + RspBuffer *rsp); + unsigned int cmd_len_min; +} IPMICmdHandler; + +typedef struct IPMINetfn { + unsigned int cmd_nums; + const IPMICmdHandler *cmd_handlers; +} IPMINetfn; + +int ipmi_sim_register_netfn(IPMIBmcSim *s, unsigned int netfn, + const IPMINetfn *netfnd); + #endif From patchwork Tue Dec 17 04:42:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296647 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F3CC6C1 for ; Tue, 17 Dec 2019 05:17:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8E782072D for ; Tue, 17 Dec 2019 05:17:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="o0Edwegn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E8E782072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Ev-0005jw-Mf for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:17:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33963) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iY-0000Hu-B7 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iW-0005sw-MW for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:18 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:34589 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iW-0005Po-Bq; Mon, 16 Dec 2019 23:44:16 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWR6d7zz9sSb; Tue, 17 Dec 2019 15:43:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557811; bh=Td+HUQPIiW4jdSS03cW6WQtatFv45X48Sv9D83TYMSg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o0EdwegnbUdz5sfUfZLn3+rmbvYRcsXazoQXqTQBoJ9cJup3bnnNjT0CjHs1Zb3xr +OTcrd1ZSTRI3u+VkvhfDpaeJ62B3vD8FelaJuRXT9NIY13r1w3tVRlcreAD4hBmOl lhaZ+E0zDLLVKJkSju2krkNjcqKAL9VY04XaVxgw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 25/88] ppc/pnv: Add HIOMAP commands Date: Tue, 17 Dec 2019 15:42:19 +1100 Message-Id: <20191217044322.351838-26-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson , Joel Stanley Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater This activates HIOMAP support on the QEMU PowerNV machine. The PnvPnor model is used to access the flash contents. The model simply maps the contents at a fix offset and enables or disables the mapping. HIOMAP Protocol description : https://github.com/openbmc/hiomapd/blob/master/Documentation/protocol.md Reviewed-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-Id: <20191028070027.22752-3-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 1 + hw/ppc/pnv_bmc.c | 102 ++++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_lpc.c | 13 +++++ include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_pnor.h | 5 ++ 5 files changed, 122 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a2a8b97330..c3ac0d6d5b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -569,6 +569,7 @@ static void pnv_reset(MachineState *machine) obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); if (obj) { pnv->bmc = IPMI_BMC(obj); + pnv_bmc_hiomap(pnv->bmc); } fdt = pnv_dt_create(machine); diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index dc5e918cb7..aa5c89586c 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -114,3 +114,105 @@ void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt) sdr->sensor_type))); } } + +/* + * HIOMAP protocol handler + */ +#define HIOMAP_C_RESET 1 +#define HIOMAP_C_GET_INFO 2 +#define HIOMAP_C_GET_FLASH_INFO 3 +#define HIOMAP_C_CREATE_READ_WINDOW 4 +#define HIOMAP_C_CLOSE_WINDOW 5 +#define HIOMAP_C_CREATE_WRITE_WINDOW 6 +#define HIOMAP_C_MARK_DIRTY 7 +#define HIOMAP_C_FLUSH 8 +#define HIOMAP_C_ACK 9 +#define HIOMAP_C_ERASE 10 +#define HIOMAP_C_DEVICE_NAME 11 +#define HIOMAP_C_LOCK 12 + +#define BLOCK_SHIFT 12 /* 4K */ + +static uint16_t bytes_to_blocks(uint32_t bytes) +{ + return bytes >> BLOCK_SHIFT; +} + +static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len, + RspBuffer *rsp) +{ + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvPnor *pnor = pnv->pnor; + uint32_t pnor_size = pnor->size; + uint32_t pnor_addr = PNOR_SPI_OFFSET; + bool readonly = false; + + rsp_buffer_push(rsp, cmd[2]); + rsp_buffer_push(rsp, cmd[3]); + + switch (cmd[2]) { + case HIOMAP_C_MARK_DIRTY: + case HIOMAP_C_FLUSH: + case HIOMAP_C_ERASE: + case HIOMAP_C_ACK: + break; + + case HIOMAP_C_GET_INFO: + rsp_buffer_push(rsp, 2); /* Version 2 */ + rsp_buffer_push(rsp, BLOCK_SHIFT); /* block size */ + rsp_buffer_push(rsp, 0); /* Timeout */ + rsp_buffer_push(rsp, 0); /* Timeout */ + break; + + case HIOMAP_C_GET_FLASH_INFO: + rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF); + rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8); + rsp_buffer_push(rsp, 0x01); /* erase size */ + rsp_buffer_push(rsp, 0x00); /* erase size */ + break; + + case HIOMAP_C_CREATE_READ_WINDOW: + readonly = true; + /* Fall through */ + + case HIOMAP_C_CREATE_WRITE_WINDOW: + memory_region_set_readonly(&pnor->mmio, readonly); + memory_region_set_enabled(&pnor->mmio, true); + + rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) & 0xFF); + rsp_buffer_push(rsp, bytes_to_blocks(pnor_addr) >> 8); + rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) & 0xFF); + rsp_buffer_push(rsp, bytes_to_blocks(pnor_size) >> 8); + rsp_buffer_push(rsp, 0x00); /* offset */ + rsp_buffer_push(rsp, 0x00); /* offset */ + break; + + case HIOMAP_C_CLOSE_WINDOW: + memory_region_set_enabled(&pnor->mmio, false); + break; + + case HIOMAP_C_DEVICE_NAME: + case HIOMAP_C_RESET: + case HIOMAP_C_LOCK: + default: + qemu_log_mask(LOG_GUEST_ERROR, "HIOMAP: unknow command %02X\n", cmd[2]); + break; + } +} + +#define HIOMAP 0x5a + +static const IPMICmdHandler hiomap_cmds[] = { + [HIOMAP] = { hiomap_cmd, 3 }, +}; + +static const IPMINetfn hiomap_netfn = { + .cmd_nums = ARRAY_SIZE(hiomap_cmds), + .cmd_handlers = hiomap_cmds +}; + +int pnv_bmc_hiomap(IPMIBmc *bmc) +{ + return ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(bmc), + IPMI_NETFN_OEM, &hiomap_netfn); +} diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index c5a85c38c7..dd5374c838 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -810,6 +810,7 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp) ISABus *isa_bus; qemu_irq *irqs; qemu_irq_handler handler; + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); /* let isa_bus_new() create its own bridge on SysBus otherwise * devices speficied on the command line won't find the bus and @@ -834,5 +835,17 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp) irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS); isa_bus_irqs(isa_bus, irqs); + + /* + * TODO: Map PNOR on the LPC FW address space on demand ? + */ + memory_region_add_subregion(&lpc->isa_fw, PNOR_SPI_OFFSET, + &pnv->pnor->mmio); + /* + * Start disabled. The HIOMAP protocol will activate the mapping + * with HIOMAP_C_CREATE_WRITE_WINDOW + */ + memory_region_set_enabled(&pnv->pnor->mmio, false); + return isa_bus; } diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 5ecd3ba6ed..07c56c05ad 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -198,6 +198,7 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) */ void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); void pnv_bmc_powerdown(IPMIBmc *bmc); +int pnv_bmc_hiomap(IPMIBmc *bmc); /* * POWER8 MMIO base addresses diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h index dec811695c..c3dd28643c 100644 --- a/include/hw/ppc/pnv_pnor.h +++ b/include/hw/ppc/pnv_pnor.h @@ -9,6 +9,11 @@ #ifndef _PPC_PNV_PNOR_H #define _PPC_PNV_PNOR_H +/* + * PNOR offset on the LPC FW address space + */ +#define PNOR_SPI_OFFSET 0x0c000000UL + #define TYPE_PNV_PNOR "pnv-pnor" #define PNV_PNOR(obj) OBJECT_CHECK(PnvPnor, (obj), TYPE_PNV_PNOR) From patchwork Tue Dec 17 04:42:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296587 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 49D6214B7 for ; Tue, 17 Dec 2019 04:59:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D70720733 for ; Tue, 17 Dec 2019 04:59:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="B1zEpCub" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D70720733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4wu-0004GW-QP for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:59:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33707) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iG-0008JN-5H for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iB-0005ZZ-Q9 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:58 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:53459 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iA-0005QK-Db; Mon, 16 Dec 2019 23:43:55 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWS6T4rz9sSh; Tue, 17 Dec 2019 15:43:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557812; bh=yLXzg2VI1CzpHWdUBG1skoOw2fJbrqhcfdSr1eU4hcQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B1zEpCub7ulfeeT6pmVNmUaTmFkP8/2WSFJtMIQj6ALIwwwV2ZRwNmn960P9BFR/t gROm2KPA5E/JjgaW9bB6POqsIXTQOgdlc2mICVmbWnLfu+rGAXW1U4nEXM7vkGQ5+l 3jhNh1co4cIxHI915/JO8/AThoIU+PlM/nAM4lOA= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 26/88] ppc/pnv: Create BMC devices at machine init Date: Tue, 17 Dec 2019 15:42:20 +1100 Message-Id: <20191217044322.351838-27-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The BMC of the OpenPOWER systems monitors the machine state using sensors, controls the power and controls the access to the PNOR flash device containing the firmware image required to boot the host. QEMU models the power cycle process, access to the sensors and access to the PNOR device. But, for these features to be available, the QEMU PowerNV machine needs two extras devices on the command line, an IPMI BT device for communication and a BMC backend device: -device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10 The BMC properties are then defined accordingly in the device tree and OPAL self adapts. If a BMC device and an IPMI BT device are not available, OPAL does not try to communicate with the BMC in any manner. This is not how real systems behave. To be closer to the default behavior, create an IPMI BMC simulator device and an IPMI BT device at machine initialization time. We loose the ability to define an external BMC device but there are benefits: - a better match with real systems, - a better test coverage of the OPAL code, - system powerdown and reset commands that work, - a QEMU device tree compliant with the specifications (*). (*) Still needs a MBOX device. Signed-off-by: Cédric Le Goater Message-Id: <20191121162340.11049-1-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 33 ++++++++++++++++----------------- hw/ppc/pnv_bmc.c | 20 +++++++++++++++++--- include/hw/ppc/pnv.h | 2 +- 3 files changed, 34 insertions(+), 21 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c3ac0d6d5b..f0adb06c8d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -551,27 +551,10 @@ static void pnv_powerdown_notify(Notifier *n, void *opaque) static void pnv_reset(MachineState *machine) { - PnvMachineState *pnv = PNV_MACHINE(machine); void *fdt; - Object *obj; qemu_devices_reset(); - /* - * OpenPOWER systems have a BMC, which can be defined on the - * command line with: - * - * -device ipmi-bmc-sim,id=bmc0 - * - * This is the internal simulator but it could also be an external - * BMC. - */ - obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); - if (obj) { - pnv->bmc = IPMI_BMC(obj); - pnv_bmc_hiomap(pnv->bmc); - } - fdt = pnv_dt_create(machine); /* Pack resulting tree */ @@ -629,6 +612,16 @@ static bool pnv_match_cpu(const char *default_type, const char *cpu_type) return ppc_default->pvr_match(ppc_default, ppc->pvr); } +static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) +{ + Object *obj; + + obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); + object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); + object_property_set_int(obj, irq, "irq", &error_fatal); + object_property_set_bool(obj, true, "realized", &error_fatal); +} + static void pnv_init(MachineState *machine) { PnvMachineState *pnv = PNV_MACHINE(machine); @@ -751,6 +744,9 @@ static void pnv_init(MachineState *machine) } g_free(chip_typename); + /* Create the machine BMC simulator */ + pnv->bmc = pnv_bmc_create(); + /* Instantiate ISA bus on chip 0 */ pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); @@ -760,6 +756,9 @@ static void pnv_init(MachineState *machine) /* Create an RTC ISA device too */ mc146818_rtc_init(pnv->isa_bus, 2000, NULL); + /* Create the IPMI BT device for communication with the BMC */ + pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); + /* * OpenPOWER systems use a IPMI SEL Event message to notify the * host to powerdown diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index aa5c89586c..07fa1e1c7e 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -17,6 +17,8 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" +#include "qapi/error.h" #include "target/ppc/cpu.h" #include "qemu/log.h" #include "hw/ipmi/ipmi.h" @@ -211,8 +213,20 @@ static const IPMINetfn hiomap_netfn = { .cmd_handlers = hiomap_cmds }; -int pnv_bmc_hiomap(IPMIBmc *bmc) +/* + * Instantiate the machine BMC. PowerNV uses the QEMU internal + * simulator but it could also be external. + */ +IPMIBmc *pnv_bmc_create(void) { - return ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(bmc), - IPMI_NETFN_OEM, &hiomap_netfn); + Object *obj; + + obj = object_new(TYPE_IPMI_BMC_SIMULATOR); + object_property_set_bool(obj, true, "realized", &error_fatal); + + /* Install the HIOMAP protocol handlers to access the PNOR */ + ipmi_sim_register_netfn(IPMI_BMC_SIMULATOR(obj), IPMI_NETFN_OEM, + &hiomap_netfn); + + return IPMI_BMC(obj); } diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 07c56c05ad..90f1343ed0 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -198,7 +198,7 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) */ void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); void pnv_bmc_powerdown(IPMIBmc *bmc); -int pnv_bmc_hiomap(IPMIBmc *bmc); +IPMIBmc *pnv_bmc_create(void); /* * POWER8 MMIO base addresses From patchwork Tue Dec 17 04:42:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296579 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F165C1580 for ; Tue, 17 Dec 2019 04:56:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C627220733 for ; Tue, 17 Dec 2019 04:56:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="ejBv/UPj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C627220733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ue-0000mq-Gu for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:56:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33710) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iG-0008JP-5U for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iB-0005Zs-S7 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:58 -0500 Received: from ozlabs.org ([203.11.71.1]:34159) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iB-0005TW-BU; Mon, 16 Dec 2019 23:43:55 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWT6bt3z9sSk; Tue, 17 Dec 2019 15:43:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557813; bh=qLrrxGz/L7uIfowC5RKd93eD4t4+MzoytoM8oaYxtik=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ejBv/UPj41KRJgeI9Ed4GCrnoIiNVoycWAnLumAStDEtYXfK52hW40S2OwHD5dSqy 7UX2ZlppC6sb8Apjsh1oIwkjS4LGrJa+Jqpz+Q9JcIXuoja+/S3eyQ8oj5IZUH3ycy AoUOimvg8qtFgE1QhY/yL1XQ7FxCpSIGaBIgkX84= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 27/88] ppc/xive: Introduce a XivePresenter interface Date: Tue, 17 Dec 2019 15:42:21 +1100 Message-Id: <20191217044322.351838-28-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification Virtual Target (NVT) to notify, it broadcasts a message on the PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT dispatched on one of its HW threads, and then forwards the notification if any response was received. The current XIVE presenter model is sufficient for the pseries machine because it has a single interrupt controller device, but the PowerNV machine can have multiple chips each having its own interrupt controller. In this case, the XIVE presenter model is too simple and the CAM line matching should scan all chips of the system. To start fixing this issue, we first extend the XIVE Router model with a new XivePresenter QOM interface representing the XIVE IVPE sub-engine. This interface exposes a 'match_nvt' handler which the sPAPR and PowerNV XIVE Router models will need to implement to perform the CAM line matching. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 26 +++++++++++++++++--------- include/hw/ppc/xive.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 9 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 511e1a9363..344bb3f3bc 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1363,9 +1363,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) /* * The thread context register words are in big-endian format. */ -static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint32_t logic_serv) +int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint32_t logic_serv) { uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx); uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); @@ -1422,11 +1423,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format, return -1; } -typedef struct XiveTCTXMatch { - XiveTCTX *tctx; - uint8_t ring; -} XiveTCTXMatch; - static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -1460,7 +1456,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, * Check the thread context CAM lines and record matches. We * will handle CPU exception delivery later */ - ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx, + ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format, + nvt_blk, nvt_idx, cam_ignore, logic_serv); /* * Save the context and follow on to catch duplicates, that we @@ -1754,6 +1751,7 @@ static const TypeInfo xive_router_info = { .class_init = xive_router_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_XIVE_NOTIFIER }, + { TYPE_XIVE_PRESENTER }, { } } }; @@ -1923,10 +1921,20 @@ static const TypeInfo xive_notifier_info = { .class_size = sizeof(XiveNotifierClass), }; +/* + * XIVE Presenter + */ +static const TypeInfo xive_presenter_info = { + .name = TYPE_XIVE_PRESENTER, + .parent = TYPE_INTERFACE, + .class_size = sizeof(XivePresenterClass), +}; + static void xive_register_types(void) { type_register_static(&xive_source_info); type_register_static(&xive_notifier_info); + type_register_static(&xive_presenter_info); type_register_static(&xive_router_info); type_register_static(&xive_end_source_info); type_register_static(&xive_tctx_info); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index fa7adf87fe..f9aa0fa0da 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -367,6 +367,38 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); +/* + * XIVE Presenter + */ + +typedef struct XiveTCTXMatch { + XiveTCTX *tctx; + uint8_t ring; +} XiveTCTXMatch; + +typedef struct XivePresenter XivePresenter; + +#define TYPE_XIVE_PRESENTER "xive-presenter" +#define XIVE_PRESENTER(obj) \ + INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_CLASS(klass) \ + OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER) +#define XIVE_PRESENTER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER) + +typedef struct XivePresenterClass { + InterfaceClass parent; + int (*match_nvt)(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); +} XivePresenterClass; + +int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, + uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint32_t logic_serv); + /* * XIVE END ESBs */ From patchwork Tue Dec 17 04:42:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296571 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6601921 for ; Tue, 17 Dec 2019 04:54:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B410520733 for ; Tue, 17 Dec 2019 04:54:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="VmK3lUkz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B410520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35220 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4s6-0005Gm-Gn for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:54:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33746) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iI-0008KS-Jd for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iG-0005c0-49 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:02 -0500 Received: from ozlabs.org ([203.11.71.1]:58735) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iB-0005Qq-Po; Mon, 16 Dec 2019 23:43:58 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWT2RXYz9sSn; Tue, 17 Dec 2019 15:43:31 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557813; bh=KLAeVuzvCddEVuCYat0RW1q80cGghwTWyDDGVAH29qY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VmK3lUkza3DspA78aXn9Ta/ILd68fp+MyZiH0l1hPGgQnjIfRZUOS8B6V3U1FxDlU +jGzoy0KSwsY9s17pm0NZ80XMwVJgNUxImfWTKWTKR9Ovpb8wkZosFEyuRAvU+TbwW CWC2FCY0i4fIEnhsGbtMUXFWbtrOhPGt2sJesYjg= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 28/88] ppc/xive: Implement the XivePresenter interface Date: Tue, 17 Dec 2019 15:42:22 +1100 Message-Id: <20191217044322.351838-29-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt' handler of the XivePresenter QOM interface. This is simply moving code and taking into account the new API. To be noted that the xive_router_get_tctx() helper is not used anymore when doing CAM matching and will be removed later on after other changes. The XIVE presenter model is still too simple for the PowerNV machine and the CAM matching algo is not correct on multichip system. Subsequent patches will introduce more changes to scan all chips of the system. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-3-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 41 +++++++++++++++++++++++++++++++++++ hw/intc/spapr_xive.c | 49 ++++++++++++++++++++++++++++++++++++++++++ hw/intc/xive.c | 51 ++++++-------------------------------------- 3 files changed, 97 insertions(+), 44 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9a771f6407..8055de89cf 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -372,6 +372,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } +static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + CPUState *cs; + int count = 0; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); + int ring; + + /* + * Check the thread context CAM lines and record matches. + */ + ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, + cam_ignore, logic_serv); + /* + * Save the context and follow on to catch duplicates, that we + * don't support yet. + */ + if (ring != -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " + "thread context NVT %x/%x\n", + nvt_blk, nvt_idx); + return -1; + } + + match->ring = ring; + match->tctx = tctx; + count++; + } + } + + return count; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -1780,6 +1819,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); + XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); xdc->dt_xscom = pnv_xive_dt_xscom; @@ -1795,6 +1835,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) xrc->get_tctx = pnv_xive_get_tctx; xnc->notify = pnv_xive_notify; + xpc->match_nvt = pnv_xive_match_nvt; }; static const TypeInfo pnv_xive_info = { diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 729246e906..bb3b2dfdb7 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -405,6 +405,52 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) return spapr_cpu_state(cpu)->tctx; } +static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + CPUState *cs; + int count = 0; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx; + int ring; + + /* + * Skip partially initialized vCPUs. This can happen when + * vCPUs are hotplugged. + */ + if (!tctx) { + continue; + } + + /* + * Check the thread context CAM lines and record matches. + */ + ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, + cam_ignore, logic_serv); + /* + * Save the matching thread interrupt context and follow on to + * check for duplicates which are invalid. + */ + if (ring != -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " + "context NVT %x/%x\n", nvt_blk, nvt_idx); + return -1; + } + + match->ring = ring; + match->tctx = tctx; + count++; + } + } + + return count; +} + static const VMStateDescription vmstate_spapr_xive_end = { .name = TYPE_SPAPR_XIVE "/end", .version_id = 1, @@ -684,6 +730,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); + XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); dc->desc = "sPAPR XIVE Interrupt Controller"; dc->props = spapr_xive_properties; @@ -708,6 +755,8 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) sicc->print_info = spapr_xive_print_info; sicc->dt = spapr_xive_dt; sicc->post_load = spapr_xive_post_load; + + xpc->match_nvt = spapr_xive_match_nvt; } static const TypeInfo spapr_xive_info = { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 344bb3f3bc..da6196ca95 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1428,51 +1428,14 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { - CPUState *cs; + XivePresenter *xptr = XIVE_PRESENTER(xrtr); + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); + int count; - /* - * TODO (PowerNV): handle chip_id overwrite of block field for - * hardwired CAM compares - */ - - CPU_FOREACH(cs) { - XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs); - int ring; - - /* - * Skip partially initialized vCPUs. This can happen when - * vCPUs are hotplugged. - */ - if (!tctx) { - continue; - } - - /* - * HW checks that the CPU is enabled in the Physical Thread - * Enable Register (PTER). - */ - - /* - * Check the thread context CAM lines and record matches. We - * will handle CPU exception delivery later - */ - ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format, - nvt_blk, nvt_idx, - cam_ignore, logic_serv); - /* - * Save the context and follow on to catch duplicates, that we - * don't support yet. - */ - if (ring != -1) { - if (match->tctx) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread " - "context NVT %x/%x\n", nvt_blk, nvt_idx); - return false; - } - - match->ring = ring; - match->tctx = tctx; - } + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); + if (count < 0) { + return false; } if (!match->tctx) { From patchwork Tue Dec 17 04:42:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05360930 for ; Tue, 17 Dec 2019 05:10:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D01312072D for ; Tue, 17 Dec 2019 05:10:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="G+ehzKJr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D01312072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35482 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih57m-000334-7u for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:10:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34261) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iq-0000p0-8o for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4in-0006FU-Qv for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:35 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:33735 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4in-0005nf-G2; Mon, 16 Dec 2019 23:44:33 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWW2zbBz9sSw; Tue, 17 Dec 2019 15:43:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557815; bh=aHFtWdrb+8pmavyOXG6lJ9YUtDF+TfjGta6fhwbERI0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G+ehzKJr/jacEzz1apPYITGlMaQ3ZYh6IIbfqXXJdeVFPa/aszwAPQzL3FbdVwvU0 HXQKqpyYDI7EewCmGMsy+yOSEOvN7UWakwgowdXpuN0Fm+rKMIJVcXhmVd0gSSlbx9 6wrAaJMbUnFOikW7MmIDHvxslptdRkjAe+mvVKvg= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 29/88] ppc/pnv: Instantiate cores separately Date: Tue, 17 Dec 2019 15:42:23 +1100 Message-Id: <20191217044322.351838-30-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Allocating a big void * array to store multiple objects isn't a recommended practice for various reasons: - no compile time type checking - potential dangling pointers if a reference on an individual is taken and the array is freed later on - duplicate boiler plate everywhere the array is browsed through Allocate an array of pointers and populate it instead. Signed-off-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-4-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 30 ++++++++++++------------------ include/hw/ppc/pnv.h | 2 +- 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f0adb06c8d..d899c83e52 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -280,14 +280,12 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) { - const char *typename = pnv_chip_core_typename(chip); - size_t typesize = object_type_get_instance_size(typename); int i; pnv_dt_xscom(chip, fdt, 0); for (i = 0; i < chip->nr_cores; i++) { - PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); + PnvCore *pnv_core = chip->cores[i]; pnv_dt_core(chip, pnv_core, fdt); @@ -302,14 +300,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) { - const char *typename = pnv_chip_core_typename(chip); - size_t typesize = object_type_get_instance_size(typename); int i; pnv_dt_xscom(chip, fdt, 0); for (i = 0; i < chip->nr_cores; i++) { - PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); + PnvCore *pnv_core = chip->cores[i]; pnv_dt_core(chip, pnv_core, fdt); } @@ -913,8 +909,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) { PnvChip *chip = PNV_CHIP(chip8); PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); - const char *typename = pnv_chip_core_typename(chip); - size_t typesize = object_type_get_instance_size(typename); int i, j; char *name; XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); @@ -928,7 +922,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) /* Map the ICP registers for each thread */ for (i = 0; i < chip->nr_cores; i++) { - PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); + PnvCore *pnv_core = chip->cores[i]; int core_hwid = CPU_CORE(pnv_core)->core_id; for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { @@ -1108,8 +1102,6 @@ static void pnv_chip_power9_instance_init(Object *obj) static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) { PnvChip *chip = PNV_CHIP(chip9); - const char *typename = pnv_chip_core_typename(chip); - size_t typesize = object_type_get_instance_size(typename); int i; chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); @@ -1118,7 +1110,7 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) for (i = 0; i < chip9->nr_quads; i++) { char eq_name[32]; PnvQuad *eq = &chip9->quads[i]; - PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); + PnvCore *pnv_core = chip->cores[i * 4]; int core_id = CPU_CORE(pnv_core)->core_id; snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); @@ -1290,7 +1282,6 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) Error *error = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); const char *typename = pnv_chip_core_typename(chip); - size_t typesize = object_type_get_instance_size(typename); int i, core_hwid; if (!object_class_by_name(typename)) { @@ -1305,21 +1296,24 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) return; } - chip->cores = g_malloc0(typesize * chip->nr_cores); + chip->cores = g_new0(PnvCore *, chip->nr_cores); for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) && (i < chip->nr_cores); core_hwid++) { char core_name[32]; - void *pnv_core = chip->cores + i * typesize; + PnvCore *pnv_core; uint64_t xscom_core_base; if (!(chip->cores_mask & (1ull << core_hwid))) { continue; } + pnv_core = PNV_CORE(object_new(typename)); + snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); - object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, - typename, &error_fatal, NULL); + object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), + &error_abort); + chip->cores[i] = pnv_core; object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", &error_fatal); object_property_set_int(OBJECT(pnv_core), core_hwid, @@ -1340,7 +1334,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) } pnv_xscom_add_subregion(chip, xscom_core_base, - &PNV_CORE(pnv_core)->xscom_regs); + &pnv_core->xscom_regs); i++; } } diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 90f1343ed0..03cb429f21 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -56,7 +56,7 @@ typedef struct PnvChip { uint32_t nr_cores; uint64_t cores_mask; - void *cores; + PnvCore **cores; MemoryRegion xscom_mmio; MemoryRegion xscom; From patchwork Tue Dec 17 04:42:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B831930 for ; Tue, 17 Dec 2019 05:05:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 41DC020733 for ; Tue, 17 Dec 2019 05:05:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KhdT80b8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 41DC020733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih52a-00034q-Uc for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:05:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34013) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ia-0000LX-Fu for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iZ-0005vz-8B for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:20 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:36987 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iY-0005Zd-Tf; Mon, 16 Dec 2019 23:44:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWV3DSZz9sSl; Tue, 17 Dec 2019 15:43:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557814; bh=SF6fWedF+5KWjn9BhcYbOsSQqaIC10oX6/pQpr5822g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KhdT80b8J/NZIKjKnnWmeVf2v3Q4fjbt1LyhWBUUopSdAXiEMMXX5VxJOa//wkvtX 81g7wFGb9rrfN0868oz3lMe9dCzoVzmvyeRTffWEQ7sX1biomPfKh58njQBg/9xwyM 7JyhB0aRjcYzisV4lFbP+H6hIU3pEDAJ+zIDuP0Q= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT Date: Tue, 17 Dec 2019 15:42:24 +1100 Message-Id: <20191217044322.351838-31-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater CPU_FOREACH() loops on all the CPUs of the machine which is incorrect. Each XIVE Presenter should scan only the HW threads of the chip it belongs to. Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-5-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 61 ++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 8055de89cf..9798bd9e72 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -377,34 +377,43 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { - CPUState *cs; + PnvXive *xive = PNV_XIVE(xptr); + PnvChip *chip = xive->chip; int count = 0; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); - int ring; - - /* - * Check the thread context CAM lines and record matches. - */ - ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx, - cam_ignore, logic_serv); - /* - * Save the context and follow on to catch duplicates, that we - * don't support yet. - */ - if (ring != -1) { - if (match->tctx) { - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " - "thread context NVT %x/%x\n", - nvt_blk, nvt_idx); - return -1; + int i, j; + + for (i = 0; i < chip->nr_cores; i++) { + PnvCore *pc = chip->cores[i]; + CPUCore *cc = CPU_CORE(pc); + + for (j = 0; j < cc->nr_threads; j++) { + PowerPCCPU *cpu = pc->threads[j]; + XiveTCTX *tctx; + int ring; + + tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + /* + * Check the thread context CAM lines and record matches. + */ + ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, + nvt_idx, cam_ignore, logic_serv); + /* + * Save the context and follow on to catch duplicates, that we + * don't support yet. + */ + if (ring != -1) { + if (match->tctx) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " + "thread context NVT %x/%x\n", + nvt_blk, nvt_idx); + return -1; + } + + match->ring = ring; + match->tctx = tctx; + count++; } - - match->ring = ring; - match->tctx = tctx; - count++; } } From patchwork Tue Dec 17 04:42:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296665 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C3426C1 for ; Tue, 17 Dec 2019 05:23:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5259D2072B for ; Tue, 17 Dec 2019 05:23:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KNHRyfEP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5259D2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5K5-0004y9-2f for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:23:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34296) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ir-0000rk-SU for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iq-0006JT-Rp for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:37 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:46691 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iq-0005ql-Hw; Mon, 16 Dec 2019 23:44:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWX22l1z9sT1; Tue, 17 Dec 2019 15:43:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557816; bh=C8HKUXcfECjE3sXrMS4Qa0Rb0MODe28HXahNg2u1FYE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KNHRyfEPGlseVZsr985epRYy4vFfO2ioRwHUlmVeFXSj4zwZIihF2na44zjOdNGs6 b4z9OBuyKLxaV9DYtjmSkVns8T7hlL3kKlxgbA6nro0s+cIbgNEchSllmYdCjG0mfd xPdmgQrSfMTrO5cn4AvpBinzyVXKpeTd1Q2XtDz0= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper Date: Tue, 17 Dec 2019 15:42:25 +1100 Message-Id: <20191217044322.351838-32-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-6-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 9 +++++++-- include/hw/ppc/ppc.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 52a18eb7d7..8dd982fc1e 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1495,15 +1495,20 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) } } +int ppc_cpu_pir(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + return env->spr_cb[SPR_PIR].default_value; +} + PowerPCCPU *ppc_get_vcpu_by_pir(int pir) { CPUState *cs; CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - if (env->spr_cb[SPR_PIR].default_value == pir) { + if (ppc_cpu_pir(cpu) == pir) { return cpu; } } diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 4bdcb8bacd..585be6ab98 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -5,6 +5,7 @@ void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level); PowerPCCPU *ppc_get_vcpu_by_pir(int pir); +int ppc_cpu_pir(PowerPCCPU *cpu); /* PowerPC hardware exceptions management helpers */ typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); From patchwork Tue Dec 17 04:42:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296653 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 781E46C1 for ; Tue, 17 Dec 2019 05:20:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AD2B2072D for ; Tue, 17 Dec 2019 05:20:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="EnwRO3qQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3AD2B2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5HE-0000mt-Qu for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:20:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34008) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ia-0000LJ-8r for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iZ-0005vp-31 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:20 -0500 Received: from ozlabs.org ([203.11.71.1]:49689) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iY-0005aN-NY; Mon, 16 Dec 2019 23:44:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWV4SJlz9sSs; Tue, 17 Dec 2019 15:43:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557814; bh=DSSa+2JspH3S+BZddb51VgY8bu9p/D1QJFBo+rul0po=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EnwRO3qQoy/YU3F+usm43cfCb9ZV920WTksOoJBDGErVlEEcYnjPUL4bRPCyy4QUo lwpYDw21utzN6K5FdrijBG8MY/NkwQjQjBFmQs8PDuh6ok74LhwIbCm6DkQK6piiqv Uy+P4q8GKXJaSPQ78+KXMUlmSKB6Hax0LnRwYtbk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Date: Tue, 17 Dec 2019 15:42:26 +1100 Message-Id: <20191217044322.351838-33-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater and use this helper to exclude CPUs which are not enabled in the XIVE controller. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-7-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 19 +++++++++++++++++++ include/hw/ppc/pnv.h | 5 +++++ 2 files changed, 24 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9798bd9e72..ec8349ee4a 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } +/* + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The + * second register covers cores 16-23 (normal) or 8-11 (fused). + */ +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + uint32_t fc = PNV9_PIR2FUSEDCORE(pir); + uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; + uint32_t bit = pir & 0x3f; + + return xive->regs[reg >> 3] & PPC_BIT(bit); +} + static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, XiveTCTX *tctx; int ring; + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + continue; + } + tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); /* diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 03cb429f21..12b0169a40 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -99,6 +99,11 @@ typedef struct Pnv9Chip { PnvQuad *quads; } Pnv9Chip; +/* + * A SMT8 fused core is a pair of SMT4 cores. + */ +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) + typedef struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; From patchwork Tue Dec 17 04:42:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3482514B7 for ; Tue, 17 Dec 2019 05:05:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CCF1A20733 for ; Tue, 17 Dec 2019 05:05:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="ZEDBd/qP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CCF1A20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih53L-0004IC-Cj for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:05:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34135) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ie-0000Sz-GB for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4id-00060a-72 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:24 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:36595 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ic-0005cl-TD; Mon, 16 Dec 2019 23:44:23 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWW1C85z9sSy; Tue, 17 Dec 2019 15:43:33 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557815; bh=MNkuUrwEEOI6QJkCE3jk3dhRDtxbCW6eBnBkT4Cz3Ok=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZEDBd/qP++CLQlsPY7kBwe4JVsb24pl8VRlhnnNQyPZCjQ3pFUL6sk09jtRiSH0RB 53TXnpNiidqkvNEzo6EHlVQAl4YYuYNLKAA4FPDl4Ur+wTRsS54pyyKdkYT7xjDvIb 5qcts6GIwvvxZplmezHaj9lbviITZ3mWCxT+nZh8= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 33/88] ppc/pnv: Fix TIMA indirect access Date: Tue, 17 Dec 2019 15:42:27 +1100 Message-Id: <20191217044322.351838-34-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When the TIMA of a CPU needs to be accessed from the indirect page, the thread id of the target CPU is first stored in the PC_TCTXT_INDIR0 register. This thread id is relative to the chip and not to the system. Introduce a helper routine to look for a CPU of a given PIR and fix pnv_xive_get_indirect_tctx() to scan only the threads of the local chip and not the whole machine. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-8-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 13 +++++++------ hw/ppc/pnv.c | 17 +++++++++++++++++ include/hw/ppc/pnv.h | 2 ++ 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index ec8349ee4a..b2ab2ccc91 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1400,12 +1400,13 @@ static const MemoryRegionOps pnv_xive_ic_lsi_ops = { */ /* - * When the TIMA is accessed from the indirect page, the thread id - * (PIR) has to be configured in the IC registers before. This is used - * for resets and for debug purpose also. + * When the TIMA is accessed from the indirect page, the thread id of + * the target CPU is configured in the PC_TCTXT_INDIR0 register before + * use. This is used for resets and for debug purpose also. */ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) { + PnvChip *chip = xive->chip; uint64_t tctxt_indir = xive->regs[PC_TCTXT_INDIR0 >> 3]; PowerPCCPU *cpu = NULL; int pir; @@ -1415,15 +1416,15 @@ static XiveTCTX *pnv_xive_get_indirect_tctx(PnvXive *xive) return NULL; } - pir = GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir) & 0xff; - cpu = ppc_get_vcpu_by_pir(pir); + pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); + cpu = pnv_chip_find_cpu(chip, pir); if (!cpu) { xive_error(xive, "IC: invalid PIR %x for indirect access", pir); return NULL; } /* Check that HW thread is XIVE enabled */ - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { xive_error(xive, "IC: CPU %x is not enabled", pir); } diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d899c83e52..8f688f4efc 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1371,6 +1371,23 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV Chip"; } +PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) +{ + int i, j; + + for (i = 0; i < chip->nr_cores; i++) { + PnvCore *pc = chip->cores[i]; + CPUCore *cc = CPU_CORE(pc); + + for (j = 0; j < cc->nr_threads; j++) { + if (ppc_cpu_pir(pc->threads[j]) == pir) { + return pc->threads[j]; + } + } + } + return NULL; +} + static ICSState *pnv_ics_get(XICSFabric *xi, int irq) { PnvMachineState *pnv = PNV_MACHINE(xi); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 12b0169a40..a58cfea3f2 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -162,6 +162,8 @@ typedef struct PnvChipClass { #define PNV_CHIP_INDEX(chip) \ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) +PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); + #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") #define PNV_MACHINE(obj) \ OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) From patchwork Tue Dec 17 04:42:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296581 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 91E0A1580 for ; Tue, 17 Dec 2019 04:57:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6816620733 for ; Tue, 17 Dec 2019 04:57:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="BqKnVI2b" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6816620733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4vP-00020L-1Y for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:57:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34015) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ia-0000Li-KQ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iZ-0005w8-D1 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:20 -0500 Received: from ozlabs.org ([203.11.71.1]:54015) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iZ-0005tU-1C; Mon, 16 Dec 2019 23:44:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWX35gKz9sSt; Tue, 17 Dec 2019 15:43:33 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557816; bh=F/pFA7MC0rZHFbacZZRgPrkJ9ewpdL3GjV0RoZQA0C0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BqKnVI2b5Fn1Dp09/40N9Xt6TaYQLY4o5qGsue9fTTYSSr7WVEgGR93zmBlKHGgJT WRmAx5ofDYx3u8ck2a0pD/owR1kapApgBMs/v9T/0a7v/QyVNqWZmwin/oo0B/DauF b72kSy362ZmmX4szv6NUwoTC66+yy18t2hbYLzlY= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 34/88] ppc/xive: Introduce a XiveFabric interface Date: Tue, 17 Dec 2019 15:42:28 +1100 Message-Id: <20191217044322.351838-35-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The XiveFabric QOM interface acts as the PowerBUS interface between the interrupt controller and the system and should be implemented by the QEMU machine. On HW, the XIVE sub-engine is responsible for the communication with the other chip is the Common Queue (CQ) bridge unit. This interface offers a 'match_nvt' handler to perform the CAM line matching when looking for a XIVE Presenter with a dispatched NVT. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-9-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 10 ++++++++++ include/hw/ppc/xive.h | 22 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index da6196ca95..1c9e58f8de 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1893,8 +1893,18 @@ static const TypeInfo xive_presenter_info = { .class_size = sizeof(XivePresenterClass), }; +/* + * XIVE Fabric + */ +static const TypeInfo xive_fabric_info = { + .name = TYPE_XIVE_FABRIC, + .parent = TYPE_INTERFACE, + .class_size = sizeof(XiveFabricClass), +}; + static void xive_register_types(void) { + type_register_static(&xive_fabric_info); type_register_static(&xive_source_info); type_register_static(&xive_notifier_info); type_register_static(&xive_presenter_info); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index f9aa0fa0da..b00af98877 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -399,6 +399,28 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint32_t logic_serv); +/* + * XIVE Fabric (Interface between Interrupt Controller and Machine) + */ + +typedef struct XiveFabric XiveFabric; + +#define TYPE_XIVE_FABRIC "xive-fabric" +#define XIVE_FABRIC(obj) \ + INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC) +#define XIVE_FABRIC_CLASS(klass) \ + OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC) +#define XIVE_FABRIC_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC) + +typedef struct XiveFabricClass { + InterfaceClass parent; + int (*match_nvt)(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match); +} XiveFabricClass; + /* * XIVE END ESBs */ From patchwork Tue Dec 17 04:42:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296589 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8AF0E14B7 for ; Tue, 17 Dec 2019 05:00:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5EC1C20733 for ; Tue, 17 Dec 2019 05:00:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="PipfyywD" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5EC1C20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4xk-0005cN-Hl for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:00:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34045) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ib-0000NZ-Es for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ia-0005xE-CK for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:21 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:47239 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ia-0005aQ-1G; Mon, 16 Dec 2019 23:44:20 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWV6T2Mz9sSv; Tue, 17 Dec 2019 15:43:33 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557814; bh=ey4PkgIVy1Dh/wZ3ywzkhTE9eyeU/5i9x3xN5XfNKH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PipfyywDpH4HMBUg0w+fH764+JCgVoE5K1H6A3nCe8kPLTqLq7gj++jG7Z0mtnOMY yMy3gdryG169YyxW4TK3v2kPqgdFwrOoKSCmGPeR98amu9W0RY61BGmSHWAwRaLOL3 TaQaygHnnNfr1aIV2e2kOVxSuZ8v6ha74PTQvIqk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 35/88] ppc/pnv: Implement the XiveFabric interface Date: Tue, 17 Dec 2019 15:42:29 +1100 Message-Id: <20191217044322.351838-36-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The CAM line matching on the PowerNV machine now scans all chips of the system and all CPUs of a chip to find a dispatched NVT in the thread contexts. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-10-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 8f688f4efc..5b8b07f6ae 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1443,6 +1443,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, } } +static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, + XiveTCTXMatch *match) +{ + PnvMachineState *pnv = PNV_MACHINE(xfb); + int total_count = 0; + int i; + + for (i = 0; i < pnv->num_chips; i++) { + Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); + XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); + int count; + + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); + + if (count < 0) { + return count; + } + + total_count += count; + } + + return total_count; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1506,9 +1535,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); + xfc->match_nvt = pnv_match_nvt; mc->alias = "powernv"; } @@ -1555,6 +1586,10 @@ static const TypeInfo types[] = { .name = MACHINE_TYPE_NAME("powernv9"), .parent = TYPE_PNV_MACHINE, .class_init = pnv_machine_power9_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_XIVE_FABRIC }, + { }, + }, }, { .name = MACHINE_TYPE_NAME("powernv8"), From patchwork Tue Dec 17 04:42:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E1D16C1 for ; Tue, 17 Dec 2019 05:15:07 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3A0C2072D for ; Tue, 17 Dec 2019 05:15:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="UrEh27Af" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F3A0C2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5CL-0001kl-Nb for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:15:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33938) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iW-0000FG-RF for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iU-0005pz-Jt for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:16 -0500 Received: from ozlabs.org ([203.11.71.1]:40659) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iU-0005o2-89; Mon, 16 Dec 2019 23:44:14 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWW4sDKz9sSr; Tue, 17 Dec 2019 15:43:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557815; bh=b95cTm7gCSJ13xwayBFkUd+nNE6sdmf8MwHdEAUorT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UrEh27AfcyP91DC69Xnk+ezS8ntDS77RZ86wBreiobiwVE6s5G5xOKTZtcnKlV285 2CpRb8mgrpx7ItWxS+SAvRzdGTsu11jBevUWvAcOuYwG+d1KoD4dO/QbGTYmcJ6cEP hOg+fpW8qjtQCREbU9YU6q3qV2oyDb9+E+mT3myI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 36/88] ppc/spapr: Implement the XiveFabric interface Date: Tue, 17 Dec 2019 15:42:30 +1100 Message-Id: <20191217044322.351838-37-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The CAM line matching sequence in the pseries machine does not change much apart from the use of the new QOM interfaces. There is an extra indirection because of the sPAPR IRQ backend of the machine. Only the XIVE backend implements the new 'match_nvt' handler. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-11-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/spapr.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 3ae7db1563..d9c9a2bcee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4275,6 +4275,42 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj, kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } +static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + SpaprMachineState *spapr = SPAPR_MACHINE(xfb); + XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); + int count; + + /* This is a XIVE only operation */ + assert(spapr->active_intc == SPAPR_INTC(spapr->xive)); + + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); + if (count < 0) { + return count; + } + + /* + * When we implement the save and restore of the thread interrupt + * contexts in the enter/exit CPU handlers of the machine and the + * escalations in QEMU, we should be able to handle non dispatched + * vCPUs. + * + * Until this is done, the sPAPR machine should find at least one + * matching context always. + */ + if (count == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", + nvt_blk, nvt_idx); + } + + return count; +} + int spapr_get_vcpu_id(PowerPCCPU *cpu) { return cpu->vcpu_id; @@ -4371,6 +4407,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); mc->desc = "pSeries Logical Partition (PAPR compliant)"; mc->ignore_boot_device_suffixes = true; @@ -4447,6 +4484,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) smc->linux_pci_probe = true; smc->smp_threads_vsmt = true; smc->nr_xirqs = SPAPR_NR_XIRQS; + xfc->match_nvt = spapr_match_nvt; } static const TypeInfo spapr_machine_info = { @@ -4465,6 +4503,7 @@ static const TypeInfo spapr_machine_info = { { TYPE_PPC_VIRTUAL_HYPERVISOR }, { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, + { TYPE_XIVE_FABRIC }, { } }, }; From patchwork Tue Dec 17 04:42:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7B3614B7 for ; Tue, 17 Dec 2019 05:08:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8DD912072D for ; Tue, 17 Dec 2019 05:08:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="JJhjjU2Y" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8DD912072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih55U-0007wy-8s for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:08:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34263) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iq-0000p9-DI for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ip-0006HD-4O for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:36 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45673 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4io-0005pB-Pz; Mon, 16 Dec 2019 23:44:35 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWW6tTnz9sT0; Tue, 17 Dec 2019 15:43:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557815; bh=wPQbnCmTulcBaUJR53le06ApidmfEUZ/0yBK/Wsb83g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JJhjjU2YeKbZh4EgzcEZ+ex8I2rsii36PMc0oe07lzc1ryZcLKQ3JqD8boPz4ufjl X9jXJO7AX7nEX5Jauk6kLKLPMBm0LuZIw5OiR0kWIBJjYwrASOaIQezJ1Lro56RaPY 8GwmsiXoWA+UDFDCrwTOJy/NlZ6MApQHmfbYAOJ4= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces Date: Tue, 17 Dec 2019 15:42:31 +1100 Message-Id: <20191217044322.351838-38-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Now that the machines have handlers implementing the XiveFabric and XivePresenter interfaces, remove xive_presenter_match() and make use of the 'match_nvt' handler of the machine. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-12-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 48 +++++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 1c9e58f8de..8e683847bf 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1423,30 +1423,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, return -1; } -static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, - uint8_t nvt_blk, uint32_t nvt_idx, - bool cam_ignore, uint8_t priority, - uint32_t logic_serv, XiveTCTXMatch *match) -{ - XivePresenter *xptr = XIVE_PRESENTER(xrtr); - XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); - int count; - - count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, - priority, logic_serv, match); - if (count < 0) { - return false; - } - - if (!match->tctx) { - qemu_log_mask(LOG_UNIMP, "XIVE: NVT %x/%x is not dispatched\n", - nvt_blk, nvt_idx); - return false; - } - - return true; -} - /* * This is our simple Xive Presenter Engine model. It is merged in the * Router as it does not require an extra object. @@ -1462,22 +1438,32 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, * * The parameters represent what is sent on the PowerBus */ -static bool xive_presenter_notify(XiveRouter *xrtr, uint8_t format, +static bool xive_presenter_notify(uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) { + XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine()); + XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; - bool found; + int count; - found = xive_presenter_match(xrtr, format, nvt_blk, nvt_idx, cam_ignore, - priority, logic_serv, &match); - if (found) { + /* + * Ask the machine to scan the interrupt controllers for a match + */ + count = xfc->match_nvt(xfb, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, &match); + if (count < 0) { + return false; + } + + /* handle CPU exception delivery */ + if (count) { ipb_update(&match.tctx->regs[match.ring], priority); xive_tctx_notify(match.tctx, match.ring); } - return found; + return !!count; } /* @@ -1590,7 +1576,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, return; } - found = xive_presenter_notify(xrtr, format, nvt_blk, nvt_idx, + found = xive_presenter_notify(format, nvt_blk, nvt_idx, xive_get_field32(END_W7_F0_IGNORE, end.w7), priority, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); From patchwork Tue Dec 17 04:42:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296677 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E5936C1 for ; Tue, 17 Dec 2019 05:25:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53FAE2072B for ; Tue, 17 Dec 2019 05:25:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="aQeeuYGK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53FAE2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35797 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5MZ-0000Oe-Va for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:25:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34374) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ix-0000zE-4x for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iv-0006Po-CE for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:42 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:60959 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iv-0005wF-1e; Mon, 16 Dec 2019 23:44:41 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWX45rZz9sSx; Tue, 17 Dec 2019 15:43:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557816; bh=piLi9ZJMSTKCOcegDGaL5RCevw3ESsXiD4T/sAMW9X4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aQeeuYGKNcsrbPdldzFREf2B3gg6Qe23WVlIIDg+su9Xz7shOqD1sHlcEXfEqvzur GFcseJmfdGJw9Tmhay+zz2bbUc119pumnIzgWM6pevVHUHWW0/npbtDZsFWpqSwX4M Eat6cwH+EgFwH4+NJKjTp2KqqBc5PgvI9QDmj3S8= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Date: Tue, 17 Dec 2019 15:42:32 +1100 Message-Id: <20191217044322.351838-39-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The TIMA operations are performed on behalf of the XIVE IVPE sub-engine (Presenter) on the thread interrupt context registers. The current operations supported by the model are simple and do not require access to the controller but more complex operations will need access to the controller NVT table and to its configuration. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-13-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 4 +-- hw/intc/xive.c | 58 ++++++++++++++++++++++++------------------- include/hw/ppc/xive.h | 7 +++--- 3 files changed, 38 insertions(+), 31 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index b2ab2ccc91..95e9de312c 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1436,7 +1436,7 @@ static void xive_tm_indirect_write(void *opaque, hwaddr offset, { XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); - xive_tctx_tm_write(tctx, offset, value, size); + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); } static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, @@ -1444,7 +1444,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset, { XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque)); - return xive_tctx_tm_read(tctx, offset, size); + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); } static const MemoryRegionOps xive_tm_indirect_ops = { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 8e683847bf..9e7e5ea57c 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -144,19 +144,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring) * XIVE Thread Interrupt Management Area (TIMA) */ -static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) { xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); } -static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) +static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); } -static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, - unsigned size) +static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); uint32_t qw2w2; @@ -166,13 +167,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset, return qw2w2; } -static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset, +static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; } -static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size) +static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; } @@ -315,13 +317,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr offset, unsigned size) * state changes (side effects) in addition to setting/returning the * interrupt management area context of the processor thread. */ -static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned size) +static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { return xive_tctx_accept(tctx, TM_QW1_OS); } -static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) { xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); } @@ -330,8 +333,8 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset, * Adjust the IPB to allow a CPU to process event queues of other * priorities during one physical interrupt cycle. */ -static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset, - uint64_t value, unsigned size) +static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) { ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); xive_tctx_notify(tctx, TM_QW1_OS); @@ -366,8 +369,8 @@ static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t qw1w2) memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); } -static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset, - unsigned size) +static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, unsigned size) { uint32_t qw1w2; uint32_t qw1w2_new; @@ -396,9 +399,11 @@ typedef struct XiveTmOp { uint8_t page_offset; uint32_t op_offset; unsigned size; - void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size); - uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size); + void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, + uint64_t value, unsigned size); + uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + unsigned size); } XiveTmOp; static const XiveTmOp xive_tm_operations[] = { @@ -444,8 +449,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) /* * TIMA MMIO handlers */ -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size) +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size) { const XiveTmOp *xto; @@ -462,7 +467,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA " "@%"HWADDR_PRIx"\n", offset); } else { - xto->write_handler(tctx, offset, value, size); + xto->write_handler(xptr, tctx, offset, value, size); } return; } @@ -472,7 +477,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, */ xto = xive_tm_find_op(offset, size, true); if (xto) { - xto->write_handler(tctx, offset, value, size); + xto->write_handler(xptr, tctx, offset, value, size); return; } @@ -482,7 +487,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, xive_tm_raw_write(tctx, offset, value, size); } -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + unsigned size) { const XiveTmOp *xto; @@ -500,7 +506,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) "@%"HWADDR_PRIx"\n", offset); return -1; } - return xto->read_handler(tctx, offset, size); + return xto->read_handler(xptr, tctx, offset, size); } /* @@ -508,7 +514,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size) */ xto = xive_tm_find_op(offset, size, false); if (xto) { - return xto->read_handler(tctx, offset, size); + return xto->read_handler(xptr, tctx, offset, size); } /* @@ -522,14 +528,14 @@ static void xive_tm_write(void *opaque, hwaddr offset, { XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); - xive_tctx_tm_write(tctx, offset, value, size); + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); } static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); - return xive_tctx_tm_read(tctx, offset, size); + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); } const MemoryRegionOps xive_tm_ops = { diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index b00af98877..97bbcddb38 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -463,9 +463,10 @@ typedef struct XiveENDSource { #define XIVE_TM_USER_PAGE 0x3 extern const MemoryRegionOps xive_tm_ops; -void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value, - unsigned size); -uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size); +void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + uint64_t value, unsigned size); +uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, + unsigned size); void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); From patchwork Tue Dec 17 04:42:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296621 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46816930 for ; Tue, 17 Dec 2019 05:10:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3B182072D for ; Tue, 17 Dec 2019 05:10:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="hOFpnWQl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F3B182072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih57Q-0002VD-QE for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:10:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34493) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4j2-00018i-KC for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4j1-0006Zz-0a for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:48 -0500 Received: from ozlabs.org ([203.11.71.1]:56989) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4j0-00061k-D8; Mon, 16 Dec 2019 23:44:46 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWY5xcqz9sTC; Tue, 17 Dec 2019 15:43:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557817; bh=uUiqDKLLVTBBPiFHlPyXS5b1JgnGOzsSFBr2SRaf5go=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hOFpnWQlMFYLN0RdPJpRXybpptSxIj5G1JKBu3IAtaatvgV+Z+BYo4bGOAP6xuKF4 6iIkjjN36+1yg8xL6B/iIWc3j8PKBVUymDy6H5sZ01DXtRtPSClupFKqmPxdt4scjv Y2tFfn+NEYMttjp1FJunt9Bh69WbY7kzFlFNei/s= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 39/88] linux-headers: Update Date: Tue, 17 Dec 2019 15:42:33 +1100 Message-Id: <20191217044322.351838-40-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Update to mainline commit be2eca94d144 ("Merge tag 'for-linus-5.5-1'` of git://github.com/cminyard/linux-ipmi") Signed-off-by: Greg Kurz Message-Id: <157478677756.67101.11558821804418331832.stgit@bahia.tlslab.ibm.com> Signed-off-by: David Gibson --- include/standard-headers/linux/ethtool.h | 6 ++++++ include/standard-headers/linux/virtio_ring.h | 2 +- linux-headers/asm-arm/kvm.h | 3 ++- linux-headers/asm-arm64/kvm.h | 5 ++++- linux-headers/asm-mips/unistd_n32.h | 1 + linux-headers/asm-mips/unistd_n64.h | 1 + linux-headers/asm-mips/unistd_o32.h | 1 + linux-headers/asm-powerpc/kvm.h | 3 +++ linux-headers/linux/kvm.h | 11 +++++++++++ linux-headers/linux/psp-sev.h | 3 +++ 10 files changed, 33 insertions(+), 3 deletions(-) diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h index 4ff422b635..6e8a10ee10 100644 --- a/include/standard-headers/linux/ethtool.h +++ b/include/standard-headers/linux/ethtool.h @@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices { ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66, ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, + ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69, + ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70, + ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71, + ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72, + ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73, /* must be last entry */ __ETHTOOL_LINK_MODE_MASK_NBITS @@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices { #define SPEED_56000 56000 #define SPEED_100000 100000 #define SPEED_200000 200000 +#define SPEED_400000 400000 #define SPEED_UNKNOWN -1 diff --git a/include/standard-headers/linux/virtio_ring.h b/include/standard-headers/linux/virtio_ring.h index 306cd41147..f230fed479 100644 --- a/include/standard-headers/linux/virtio_ring.h +++ b/include/standard-headers/linux/virtio_ring.h @@ -167,7 +167,7 @@ static inline void vring_init(struct vring *vr, unsigned int num, void *p, { vr->num = num; vr->desc = p; - vr->avail = p + num*sizeof(struct vring_desc); + vr->avail = (struct vring_avail *)((char *)p + num * sizeof(struct vring_desc)); vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] + sizeof(__virtio16) + align-1) & ~(align - 1)); } diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h index 9d379d3372..0db5644e27 100644 --- a/linux-headers/asm-arm/kvm.h +++ b/linux-headers/asm-arm/kvm.h @@ -131,8 +131,9 @@ struct kvm_vcpu_events { struct { __u8 serror_pending; __u8 serror_has_esr; + __u8 ext_dabt_pending; /* Align it to 8 bytes */ - __u8 pad[6]; + __u8 pad[5]; __u64 serror_esr; } exception; __u32 reserved[12]; diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index 0ce6e49f3a..920af01c8b 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -164,8 +164,9 @@ struct kvm_vcpu_events { struct { __u8 serror_pending; __u8 serror_has_esr; + __u8 ext_dabt_pending; /* Align it to 8 bytes */ - __u8 pad[6]; + __u8 pad[5]; __u64 serror_esr; } exception; __u32 reserved[12]; @@ -323,6 +324,8 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_CTRL 1 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 +#define KVM_ARM_VCPU_PVTIME_CTRL 2 +#define KVM_ARM_VCPU_PVTIME_IPA 0 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h index 7dffe8e34e..659d5c9ade 100644 --- a/linux-headers/asm-mips/unistd_n32.h +++ b/linux-headers/asm-mips/unistd_n32.h @@ -364,6 +364,7 @@ #define __NR_fsmount (__NR_Linux + 432) #define __NR_fspick (__NR_Linux + 433) #define __NR_pidfd_open (__NR_Linux + 434) +#define __NR_clone3 (__NR_Linux + 435) #endif /* _ASM_MIPS_UNISTD_N32_H */ diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h index f4592d6fc5..4b6310a05c 100644 --- a/linux-headers/asm-mips/unistd_n64.h +++ b/linux-headers/asm-mips/unistd_n64.h @@ -340,6 +340,7 @@ #define __NR_fsmount (__NR_Linux + 432) #define __NR_fspick (__NR_Linux + 433) #define __NR_pidfd_open (__NR_Linux + 434) +#define __NR_clone3 (__NR_Linux + 435) #endif /* _ASM_MIPS_UNISTD_N64_H */ diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h index 04c6728352..4ce7b4e288 100644 --- a/linux-headers/asm-mips/unistd_o32.h +++ b/linux-headers/asm-mips/unistd_o32.h @@ -410,6 +410,7 @@ #define __NR_fsmount (__NR_Linux + 432) #define __NR_fspick (__NR_Linux + 433) #define __NR_pidfd_open (__NR_Linux + 434) +#define __NR_clone3 (__NR_Linux + 435) #endif /* _ASM_MIPS_UNISTD_O32_H */ diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h index b0f72dea8b..264e266a85 100644 --- a/linux-headers/asm-powerpc/kvm.h +++ b/linux-headers/asm-powerpc/kvm.h @@ -667,6 +667,8 @@ struct kvm_ppc_cpu_char { /* PPC64 eXternal Interrupt Controller Specification */ #define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */ +#define KVM_DEV_XICS_GRP_CTRL 2 +#define KVM_DEV_XICS_NR_SERVERS 1 /* Layout of 64-bit source attribute values */ #define KVM_XICS_DESTINATION_SHIFT 0 @@ -683,6 +685,7 @@ struct kvm_ppc_cpu_char { #define KVM_DEV_XIVE_GRP_CTRL 1 #define KVM_DEV_XIVE_RESET 1 #define KVM_DEV_XIVE_EQ_SYNC 2 +#define KVM_DEV_XIVE_NR_SERVERS 3 #define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */ #define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */ #define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */ diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 3d9b18f7f8..3b27a1ae85 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -235,6 +235,7 @@ struct kvm_hyperv_exit { #define KVM_EXIT_S390_STSI 25 #define KVM_EXIT_IOAPIC_EOI 26 #define KVM_EXIT_HYPERV 27 +#define KVM_EXIT_ARM_NISV 28 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -394,6 +395,11 @@ struct kvm_run { } eoi; /* KVM_EXIT_HYPERV */ struct kvm_hyperv_exit hyperv; + /* KVM_EXIT_ARM_NISV */ + struct { + __u64 esr_iss; + __u64 fault_ipa; + } arm_nisv; /* Fix the size of the union. */ char padding[256]; }; @@ -1000,6 +1006,9 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PMU_EVENT_FILTER 173 #define KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 174 #define KVM_CAP_HYPERV_DIRECT_TLBFLUSH 175 +#define KVM_CAP_PPC_GUEST_DEBUG_SSTEP 176 +#define KVM_CAP_ARM_NISV_TO_USER 177 +#define KVM_CAP_ARM_INJECT_EXT_DABT 178 #ifdef KVM_CAP_IRQ_ROUTING @@ -1227,6 +1236,8 @@ enum kvm_device_type { #define KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_XIVE, #define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE + KVM_DEV_TYPE_ARM_PV_TIME, +#define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_MAX, }; diff --git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h index 34c39690c0..31f971e896 100644 --- a/linux-headers/linux/psp-sev.h +++ b/linux-headers/linux/psp-sev.h @@ -58,6 +58,9 @@ typedef enum { SEV_RET_HWSEV_RET_PLATFORM, SEV_RET_HWSEV_RET_UNSAFE, SEV_RET_UNSUPPORTED, + SEV_RET_INVALID_PARAM, + SEV_RET_RESOURCE_LIMIT, + SEV_RET_SECURE_DATA_INVALID, SEV_RET_MAX, } sev_ret_code; From patchwork Tue Dec 17 04:42:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296639 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 207976C1 for ; Tue, 17 Dec 2019 05:15:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA2DF2072D for ; Tue, 17 Dec 2019 05:15:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="JwQiLSDK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EA2DF2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5CS-0001tX-Fd for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:15:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34397) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iy-00011S-FN for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iw-0006SM-Se for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:44 -0500 Received: from ozlabs.org ([203.11.71.1]:36259) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iw-0005xo-Gs; Mon, 16 Dec 2019 23:44:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWY231Mz9sT8; Tue, 17 Dec 2019 15:43:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557817; bh=nv2sfMu4exbWQFeK7G3IiZ7uOvCpR+2vpj7MWBUe+D4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JwQiLSDKsC3Uy0NpWG33BnYXxdOHij68wkos6zxswhGfd3WgsHlzPYRXsV3AzPN2K xNBEJvOrR6eA8nUf+uu7jhw8ddTdSpdtZSeTFKanP1sYMhyN2aN6qoMNwggQmgCfXH imgAKoJES6HCTe6TFZnN07Bt0VbTlB71fenOKzwo= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller Date: Tue, 17 Dec 2019 15:42:34 +1100 Message-Id: <20191217044322.351838-41-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The XIVE and XICS-on-XIVE KVM devices on POWER9 hosts can greatly reduce their consumption of some scarce HW resources, namely Virtual Presenter identifiers, if they know the maximum number of vCPUs that may run in the VM. Prepare ground for this by passing the value down to xics_kvm_connect() and kvmppc_xive_connect(). This is purely mechanical, no functional change. Signed-off-by: Greg Kurz Message-Id: <157478678301.67101.2717368060417156338.stgit@bahia.tlslab.ibm.com> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/spapr_xive.c | 6 ++++-- hw/intc/spapr_xive_kvm.c | 3 ++- hw/intc/xics_kvm.c | 3 ++- hw/intc/xics_spapr.c | 5 +++-- hw/ppc/spapr_irq.c | 8 +++++--- include/hw/ppc/spapr_irq.h | 10 ++++++++-- include/hw/ppc/spapr_xive.h | 3 ++- include/hw/ppc/xics_spapr.h | 3 ++- 8 files changed, 28 insertions(+), 13 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index bb3b2dfdb7..18a043a277 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -697,12 +697,14 @@ static void spapr_xive_dt(SpaprInterruptController *intc, uint32_t nr_servers, plat_res_int_priorities, sizeof(plat_res_int_priorities))); } -static int spapr_xive_activate(SpaprInterruptController *intc, Error **errp) +static int spapr_xive_activate(SpaprInterruptController *intc, + uint32_t nr_servers, Error **errp) { SpaprXive *xive = SPAPR_XIVE(intc); if (kvm_enabled()) { - int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); + int rc = spapr_irq_init_kvm(kvmppc_xive_connect, intc, nr_servers, + errp); if (rc < 0) { return rc; } diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 69e73552f1..46c7609bd8 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -728,7 +728,8 @@ static void *kvmppc_xive_mmap(SpaprXive *xive, int pgoff, size_t len, * All the XIVE memory regions are now backed by mappings from the KVM * XIVE device. */ -int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp) +int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers, + Error **errp) { SpaprXive *xive = SPAPR_XIVE(intc); XiveSource *xsrc = &xive->source; diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 954c424b36..a1f1b7b0d3 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -342,7 +342,8 @@ void ics_kvm_set_irq(ICSState *ics, int srcno, int val) } } -int xics_kvm_connect(SpaprInterruptController *intc, Error **errp) +int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers, + Error **errp) { ICSState *ics = ICS_SPAPR(intc); int rc; diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index b3705dab0e..8ae4f41459 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -422,10 +422,11 @@ static int xics_spapr_post_load(SpaprInterruptController *intc, int version_id) return 0; } -static int xics_spapr_activate(SpaprInterruptController *intc, Error **errp) +static int xics_spapr_activate(SpaprInterruptController *intc, + uint32_t nr_servers, Error **errp) { if (kvm_enabled()) { - return spapr_irq_init_kvm(xics_kvm_connect, intc, errp); + return spapr_irq_init_kvm(xics_kvm_connect, intc, nr_servers, errp); } return 0; } diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index d4a54afc86..07e08d6544 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -70,15 +70,16 @@ void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num) bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); } -int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), +int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn, SpaprInterruptController *intc, + uint32_t nr_servers, Error **errp) { MachineState *machine = MACHINE(qdev_get_machine()); Error *local_err = NULL; if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { - if (fn(intc, &local_err) < 0) { + if (fn(intc, nr_servers, &local_err) < 0) { if (machine_kernel_irqchip_required(machine)) { error_prepend(&local_err, "kernel_irqchip requested but unavailable: "); @@ -481,6 +482,7 @@ static void set_active_intc(SpaprMachineState *spapr, SpaprInterruptController *new_intc) { SpaprInterruptControllerClass *sicc; + uint32_t nr_servers = spapr_max_server_number(spapr); assert(new_intc); @@ -498,7 +500,7 @@ static void set_active_intc(SpaprMachineState *spapr, sicc = SPAPR_INTC_GET_CLASS(new_intc); if (sicc->activate) { - sicc->activate(new_intc, &error_fatal); + sicc->activate(new_intc, nr_servers, &error_fatal); } spapr->active_intc = new_intc; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index ff814d13de..ca8cb44213 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -43,7 +43,8 @@ typedef struct SpaprInterruptController SpaprInterruptController; typedef struct SpaprInterruptControllerClass { InterfaceClass parent; - int (*activate)(SpaprInterruptController *intc, Error **errp); + int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers, + Error **errp); void (*deactivate)(SpaprInterruptController *intc); /* @@ -98,8 +99,13 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq); int spapr_irq_post_load(SpaprMachineState *spapr, int version_id); void spapr_irq_reset(SpaprMachineState *spapr, Error **errp); int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp); -int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), + +typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *, + uint32_t, Error **); + +int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn, SpaprInterruptController *intc, + uint32_t nr_servers, Error **errp); /* diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 742b7e834f..3a103c224d 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -66,7 +66,8 @@ int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx, /* * KVM XIVE device helpers */ -int kvmppc_xive_connect(SpaprInterruptController *intc, Error **errp); +int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers, + Error **errp); void kvmppc_xive_disconnect(SpaprInterruptController *intc); void kvmppc_xive_reset(SpaprXive *xive, Error **errp); void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas, diff --git a/include/hw/ppc/xics_spapr.h b/include/hw/ppc/xics_spapr.h index 28b87038c8..1c65c96e3c 100644 --- a/include/hw/ppc/xics_spapr.h +++ b/include/hw/ppc/xics_spapr.h @@ -32,7 +32,8 @@ #define TYPE_ICS_SPAPR "ics-spapr" #define ICS_SPAPR(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SPAPR) -int xics_kvm_connect(SpaprInterruptController *intc, Error **errp); +int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers, + Error **errp); void xics_kvm_disconnect(SpaprInterruptController *intc); bool xics_kvm_has_broken_disconnect(SpaprMachineState *spapr); From patchwork Tue Dec 17 04:42:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38759930 for ; Tue, 17 Dec 2019 05:07:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0E1A52072D for ; Tue, 17 Dec 2019 05:07:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="IC/xXLhh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0E1A52072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih54m-0006h0-R9 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:07:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34092) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ic-0000QM-SQ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ib-0005yk-PE for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:22 -0500 Received: from ozlabs.org ([203.11.71.1]:44833) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ib-0005wL-Du; Mon, 16 Dec 2019 23:44:21 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWX5Dxkz9sT2; Tue, 17 Dec 2019 15:43:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557816; bh=eHt+im12o+kyfnKW0xo3miFJfZBW7JfBFQ7bKqjoviY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IC/xXLhhQENWfgyZGtUi4SpU1hg+F0WJpr/jg8RA3HqBsys3A/RA9/asRUaaXiecN ti6agTuYOfUSignAiIkgPyCm65H9bT6DnjXiY6GaY969y5Byi6lUP5tXO9cQk7I4u0 cOELX4BMGQgSl5ENs1UaR+iTFI6WQtGnKEgMpenw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 41/88] spapr/xics: Configure number of servers in KVM Date: Tue, 17 Dec 2019 15:42:35 +1100 Message-Id: <20191217044322.351838-42-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The XICS-on-XIVE KVM devices now has an attribute to configure the number of interrupt servers. This allows to greatly optimize the usage of the VP space in the XIVE HW, and thus to start a lot more VMs. Only set this attribute if available in order to support older POWER9 KVM and pre-POWER9 XICS KVM devices. The XICS-on-XIVE KVM device now reports the exhaustion of VPs upon the connection of the first VCPU. Check that in order to have a chance to provide a hint to the user. ` Signed-off-by: Greg Kurz Message-Id: <157478678846.67101.9660531022460517710.stgit@bahia.tlslab.ibm.com> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics_kvm.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index a1f1b7b0d3..8d6156578f 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -165,8 +165,15 @@ void icp_kvm_realize(DeviceState *dev, Error **errp) ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, kernel_xics_fd, vcpu_id); if (ret < 0) { - error_setg(errp, "Unable to connect CPU%ld to kernel XICS: %s", vcpu_id, - strerror(errno)); + Error *local_err = NULL; + + error_setg(&local_err, "Unable to connect CPU%ld to kernel XICS: %s", + vcpu_id, strerror(errno)); + if (errno == ENOSPC) { + error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n", + MACHINE(qdev_get_machine())->smp.max_cpus); + } + error_propagate(errp, local_err); return; } enabled_icp = g_malloc(sizeof(*enabled_icp)); @@ -399,6 +406,16 @@ int xics_kvm_connect(SpaprInterruptController *intc, uint32_t nr_servers, goto fail; } + /* Tell KVM about the # of VCPUs we may have (POWER9 and newer only) */ + if (kvm_device_check_attr(rc, KVM_DEV_XICS_GRP_CTRL, + KVM_DEV_XICS_NR_SERVERS)) { + if (kvm_device_access(rc, KVM_DEV_XICS_GRP_CTRL, + KVM_DEV_XICS_NR_SERVERS, &nr_servers, true, + &local_err)) { + goto fail; + } + } + kernel_xics_fd = rc; kvm_kernel_irqchip = true; kvm_msi_via_irqfd_allowed = true; From patchwork Tue Dec 17 04:42:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DAF68930 for ; Tue, 17 Dec 2019 05:04:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B12B520733 for ; Tue, 17 Dec 2019 05:04:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="hJ9N7d1E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B12B520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih52Y-0002zv-Dd for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:04:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34585) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jB-0001Nk-KN for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jA-0006o4-Eo for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:57 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:38365 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jA-0006G0-4I; Mon, 16 Dec 2019 23:44:56 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWZ0qFjz9sT3; Tue, 17 Dec 2019 15:43:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557818; bh=hd3b5kZWmqs5s5i8WFPHWqDD8/H2XVn5MIFF9ib4lpM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hJ9N7d1E8F4ddkP5mCdjTNaUgunRwvueDPtvCmQDq8xm7yMWzOCUFqdzfjU21y+fr +19YVLB7G72Ip3kB9b7dO5lFu5rOUNIa7hoFsoqdTMoJFNJaHN9QYXmIKiU065R/iZ Qh9IcZKZfGpuYMn81vV/zARI7lL2BuB/L725etvA= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 42/88] spapr/xive: Configure number of servers in KVM Date: Tue, 17 Dec 2019 15:42:36 +1100 Message-Id: <20191217044322.351838-43-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The XIVE KVM devices now has an attribute to configure the number of interrupt servers. This allows to greatly optimize the usage of the VP space in the XIVE HW, and thus to start a lot more VMs. Only set this attribute if available in order to support older POWER9 KVM. The XIVE KVM device now reports the exhaustion of VPs upon the connection of the first VCPU. Check that in order to have a chance to provide a hint to the user. Signed-off-by: Greg Kurz Message-Id: <157478679392.67101.7843580591407950866.stgit@bahia.tlslab.ibm.com> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/spapr_xive_kvm.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 46c7609bd8..32b2809210 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -152,7 +152,8 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp) void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) { - SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive; + MachineState *ms = MACHINE(qdev_get_machine()); + SpaprXive *xive = SPAPR_MACHINE(ms)->xive; unsigned long vcpu_id; int ret; @@ -171,8 +172,16 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) ret = kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->fd, vcpu_id, 0); if (ret < 0) { - error_setg(errp, "XIVE: unable to connect CPU%ld to KVM device: %s", + Error *local_err = NULL; + + error_setg(&local_err, + "XIVE: unable to connect CPU%ld to KVM device: %s", vcpu_id, strerror(errno)); + if (errno == ENOSPC) { + error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n", + ms->smp.max_cpus); + } + error_propagate(errp, local_err); return; } @@ -758,6 +767,16 @@ int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers, return -1; } + /* Tell KVM about the # of VCPUs we may have */ + if (kvm_device_check_attr(xive->fd, KVM_DEV_XIVE_GRP_CTRL, + KVM_DEV_XIVE_NR_SERVERS)) { + if (kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_CTRL, + KVM_DEV_XIVE_NR_SERVERS, &nr_servers, true, + &local_err)) { + goto fail; + } + } + /* * 1. Source ESB pages - KVM mapping */ From patchwork Tue Dec 17 04:42:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0090D6C1 for ; Tue, 17 Dec 2019 05:23:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB7EC2072B for ; Tue, 17 Dec 2019 05:23:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="m6i7wqdO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB7EC2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5KO-0005U8-Kq for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:23:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34756) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jK-0001c4-QC for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jJ-00070z-EE for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:06 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:45849 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jJ-0006Qf-2I; Mon, 16 Dec 2019 23:45:05 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWZ6LY5z9sTB; Tue, 17 Dec 2019 15:43:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557818; bh=X9t78hdpVHh941VAJHuK29vpxbHkZ/R4dADMSE3VC54=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m6i7wqdO4d4YBwzEhzwovnqyySwkfV6NhXCK81IqPjFW1L1mUmxKh1b8JHuJ/cz5R U91fUiLu+IoB0LEOEL95sIlVeIYS1ldTS0aIPIqgmii8wnuvwNjUKEgREckfj5dcn+ xkAS1eMJINs1qgya4oZs0pGxSGr1l4v2UQX8RnSI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Date: Tue, 17 Dec 2019 15:42:37 +1100 Message-Id: <20191217044322.351838-44-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The TIMA region gives access to the thread interrupt context registers of a CPU. It is mapped at the same address on all chips and can be accessed by any CPU of the system. To identify the chip from which the access is being done, the PowerBUS uses a 'chip' field in the load/store messages. QEMU does not model these messages, instead, we extract the chip id from the CPU PIR and do a lookup at the machine level to fetch the targeted interrupt controller. Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify this process in pnv_xive_get_tctx(). The latter will be removed in the subsequent patches but the same principle will be kept. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-14-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++----------------- hw/ppc/pnv.c | 14 ++++++++++++++ include/hw/ppc/pnv.h | 3 +++ 3 files changed, 40 insertions(+), 17 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 95e9de312c..db9d9c11a8 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +/* + * The TIMA MMIO space is shared among the chips and to identify the + * chip from which the access is being done, we extract the chip id + * from the PIR. + */ +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + PnvChip *chip; + PnvXive *xive; + + chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); + assert(chip); + xive = &PNV9_CHIP(chip)->xive; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + xive_error(xive, "IC: CPU %x is not enabled", pir); + } + return xive; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive = NULL; - CPUPPCState *env = &cpu->env; - int pir = env->spr_cb[SPR_PIR].default_value; + PnvXive *xive = pnv_xive_tm_get_xive(cpu); - /* - * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. - */ - xive = pnv_xive_get_ic((pir >> 8) & 0xf); if (!xive) { return NULL; } - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); - } - - return tctx; + return XIVE_TCTX(pnv_cpu_state(cpu)->intc); } /* diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5b8b07f6ae..fa656858b2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, return total_count; } +PnvChip *pnv_get_chip(uint32_t chip_id) +{ + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + int i; + + for (i = 0; i < pnv->num_chips; i++) { + PnvChip *chip = pnv->chips[i]; + if (chip->chip_id == chip_id) { + return chip; + } + } + return NULL; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index a58cfea3f2..3a7bc3c57e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -103,6 +103,7 @@ typedef struct Pnv9Chip { * A SMT8 fused core is a pair of SMT4 cores. */ #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) typedef struct PnvChipClass { /*< private >*/ @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } +PnvChip *pnv_get_chip(uint32_t chip_id); + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL From patchwork Tue Dec 17 04:42:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296631 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74E3F930 for ; Tue, 17 Dec 2019 05:12:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4AB6A2072D for ; Tue, 17 Dec 2019 05:12:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="lrb6Qnui" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4AB6A2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5AB-0006jC-VH for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:12:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34377) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ix-0000za-CD for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iv-0006Qi-Sc for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:43 -0500 Received: from ozlabs.org ([203.11.71.1]:54963) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iv-0005wV-HP; Mon, 16 Dec 2019 23:44:41 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWX70nMz9sT5; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557816; bh=ZHXb/8Y5KCzTAlhr35nTDdW8rY7WydhcNYlDpNpq9Fg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lrb6Qnui1lfZB0SpmkApQuiebAzDpQmZEqWqiFcbS/DOI0h5//cpaHymdskfvPlqq ZY9Gs24cpqQc+RgmZaIcffsY20jovjItklzGz+BAvlVhYOxlP9xxPdRZZqfr0Bju6I QGOT38qtlJlSppX5Du762rhkCtpLMMz+l5hDqNdM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model Date: Tue, 17 Dec 2019 15:42:38 +1100 Message-Id: <20191217044322.351838-45-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater On the P9 Processor, the thread interrupt context registers of a CPU can be accessed "directly" when by load/store from the CPU or "indirectly" by the IC through an indirect TIMA page. This requires to configure first the PC_TCTXT_INDIRx registers. Today, we rely on the get_tctx() handler to deduce from the CPU PIR the chip from which the TIMA access is being done. By handling the TIMA memory ops under the interrupt controller model of each machine, we can uniformize the TIMA direct and indirect ops under PowerNV. We can also check that the CPUs have been enabled in the XIVE controller. This prepares ground for the future versions of XIVE. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-15-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 35 ++++++++++++++++++++++++++++++++++- hw/intc/spapr_xive.c | 33 +++++++++++++++++++++++++++++++-- hw/intc/xive.c | 29 ----------------------------- include/hw/ppc/xive.h | 1 - 4 files changed, 65 insertions(+), 33 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index db9d9c11a8..c14a2d1869 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1467,6 +1467,39 @@ static const MemoryRegionOps xive_tm_indirect_ops = { }, }; +static void pnv_xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + PowerPCCPU *cpu = POWERPC_CPU(current_cpu); + PnvXive *xive = pnv_xive_tm_get_xive(cpu); + XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size); +} + +static uint64_t pnv_xive_tm_read(void *opaque, hwaddr offset, unsigned size) +{ + PowerPCCPU *cpu = POWERPC_CPU(current_cpu); + PnvXive *xive = pnv_xive_tm_get_xive(cpu); + XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); + + return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size); +} + +const MemoryRegionOps pnv_xive_tm_ops = { + .read = pnv_xive_tm_read, + .write = pnv_xive_tm_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; + /* * Interrupt controller XSCOM region. */ @@ -1809,7 +1842,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) "xive-pc", PNV9_XIVE_PC_SIZE); /* Thread Interrupt Management Area (Direct) */ - memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, + memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, xive, "xive-tima", PNV9_XIVE_TM_SIZE); qemu_register_reset(pnv_xive_reset, dev); diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 18a043a277..40891543e0 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -205,6 +205,35 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable) memory_region_set_enabled(&xive->end_source.esb_mmio, false); } +static void spapr_xive_tm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; + + xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); +} + +static uint64_t spapr_xive_tm_read(void *opaque, hwaddr offset, unsigned size) +{ + XiveTCTX *tctx = spapr_cpu_state(POWERPC_CPU(current_cpu))->tctx; + + return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); +} + +const MemoryRegionOps spapr_xive_tm_ops = { + .read = spapr_xive_tm_read, + .write = spapr_xive_tm_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; + static void spapr_xive_end_reset(XiveEND *end) { memset(end, 0, sizeof(*end)); @@ -314,8 +343,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp) qemu_register_reset(spapr_xive_reset, dev); /* TIMA initialization */ - memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &xive_tm_ops, xive, - "xive.tima", 4ull << TM_SHIFT); + memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops, + xive, "xive.tima", 4ull << TM_SHIFT); sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio); /* diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 9e7e5ea57c..0ca7099f4e 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -523,35 +523,6 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, return xive_tm_raw_read(tctx, offset, size); } -static void xive_tm_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); - - xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size); -} - -static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) -{ - XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu); - - return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size); -} - -const MemoryRegionOps xive_tm_ops = { - .read = xive_tm_read, - .write = xive_tm_write, - .endianness = DEVICE_BIG_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 8, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 8, - }, -}; - static char *xive_tctx_ring_print(uint8_t *ring) { uint32_t w2 = xive_tctx_word2(ring); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 97bbcddb38..dcf8974515 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -462,7 +462,6 @@ typedef struct XiveENDSource { #define XIVE_TM_OS_PAGE 0x2 #define XIVE_TM_USER_PAGE 0x3 -extern const MemoryRegionOps xive_tm_ops; void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size); uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, From patchwork Tue Dec 17 04:42:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296689 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF620921 for ; Tue, 17 Dec 2019 05:28:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C46982072B for ; Tue, 17 Dec 2019 05:28:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Igf5mJnK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C46982072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5P9-0004ex-N0 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:28:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34604) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jC-0001Pa-NG for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jB-0006oe-GF for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:58 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:46239 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jB-0006HZ-5C; Mon, 16 Dec 2019 23:44:57 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWZ2TyWz9sT6; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557818; bh=nZ5yfF0vhIxWHx0QMLrYt8s8F6FlZSGETDaImhofivo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Igf5mJnKDxNQHKNjNPSNijPO5KkMWeNjozivLTfe4g18CVhEdG6hUqbfuXUle5HMC OMVzaJG1l7ozQyKcAGOqDsPkiuRaS5ev8X8J5L1LN5bmdqOuJnP6/JkNnITXScjuNY LNX7IoGevHXkEjsk1kMEMmsmJZNv62GWXE8g9K68= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler Date: Tue, 17 Dec 2019 15:42:39 +1100 Message-Id: <20191217044322.351838-46-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater It is now unused. Reviewed-by: Greg Kurz Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-16-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 13 ------------- hw/intc/spapr_xive.c | 8 -------- hw/intc/xive.c | 7 ------- include/hw/ppc/xive.h | 2 -- 4 files changed, 30 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index c14a2d1869..216ebc150a 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -460,18 +460,6 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) return xive; } -static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - PnvXive *xive = pnv_xive_tm_get_xive(cpu); - - if (!xive) { - return NULL; - } - - return XIVE_TCTX(pnv_cpu_state(cpu)->intc); -} - /* * The internal sources (IPIs) of the interrupt controller have no * knowledge of the XIVE chip on which they reside. Encode the block @@ -1900,7 +1888,6 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) xrc->write_end = pnv_xive_write_end; xrc->get_nvt = pnv_xive_get_nvt; xrc->write_nvt = pnv_xive_write_nvt; - xrc->get_tctx = pnv_xive_get_tctx; xnc->notify = pnv_xive_notify; xpc->match_nvt = pnv_xive_match_nvt; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 40891543e0..b785066da5 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -427,13 +427,6 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, g_assert_not_reached(); } -static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - - return spapr_cpu_state(cpu)->tctx; -} - static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -773,7 +766,6 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) xrc->write_end = spapr_xive_write_end; xrc->get_nvt = spapr_xive_get_nvt; xrc->write_nvt = spapr_xive_write_nvt; - xrc->get_tctx = spapr_xive_get_tctx; sicc->activate = spapr_xive_activate; sicc->deactivate = spapr_xive_deactivate; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 0ca7099f4e..4bff3abdc3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1317,13 +1317,6 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) -{ - XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); - - return xrc->get_tctx(xrtr, cs); -} - /* * Encode the HW CAM line in the block group mode format : * diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index dcf8974515..24315480e7 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -351,7 +351,6 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); - XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, @@ -364,7 +363,6 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt); int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); void xive_router_notify(XiveNotifier *xn, uint32_t lisn); /* From patchwork Tue Dec 17 04:42:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE8A613B6 for ; Tue, 17 Dec 2019 05:30:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 255E82072B for ; Tue, 17 Dec 2019 05:30:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="cV2iCQoH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 255E82072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5RL-0008Ig-Iu for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:30:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34647) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jE-0001Sf-K6 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jD-0006rU-EI for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:00 -0500 Received: from ozlabs.org ([203.11.71.1]:34267) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jD-0006KY-2e; Mon, 16 Dec 2019 23:44:59 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWZ45MKz9sT9; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557818; bh=gc2VEHorOGzr/BBnU0/1bboHzXgl+whXQBs70dr1m+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cV2iCQoHoeZEZxPwM7YrJQzhDql/IHZf7FSqXeCrudnMRlZk4YP0sJVf3XlzXkGMa omNZB4n0X/kVEyFyKAU3RLgYUpEqZ1x0neE4isRg1RbXU4l4DCpcdk6Meuv9Jz/85H jzrw87jXwOwGF1a89P3iNsKLfHZU+6xOq6uDPRls= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper Date: Tue, 17 Dec 2019 15:42:40 +1100 Message-Id: <20191217044322.351838-47-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater We will use it to resend missed interrupts when a vCPU context is pushed on a HW thread. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-17-clg@kaod.org> Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xive.c | 21 +++++++++++---------- include/hw/ppc/xive.h | 1 + 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 4bff3abdc3..7047e45dac 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -47,12 +47,6 @@ static uint8_t ipb_to_pipr(uint8_t ibp) return ibp ? clz32((uint32_t)ibp << 24) : 0xff; } -static void ipb_update(uint8_t *regs, uint8_t priority) -{ - regs[TM_IPB] |= priority_to_ipb(priority); - regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); -} - static uint8_t exception_mask(uint8_t ring) { switch (ring) { @@ -135,6 +129,15 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) xive_tctx_notify(tctx, ring); } +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) +{ + uint8_t *regs = &tctx->regs[ring]; + + regs[TM_IPB] |= ipb; + regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); + xive_tctx_notify(tctx, ring); +} + static inline uint32_t xive_tctx_word2(uint8_t *ring) { return *((uint32_t *) &ring[TM_WORD2]); @@ -336,8 +339,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, uint64_t value, unsigned size) { - ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff); - xive_tctx_notify(tctx, TM_QW1_OS); + xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); } static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, @@ -1429,8 +1431,7 @@ static bool xive_presenter_notify(uint8_t format, /* handle CPU exception delivery */ if (count) { - ipb_update(&match.tctx->regs[match.ring], priority); - xive_tctx_notify(match.tctx, match.ring); + xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); } return !!count; diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 24315480e7..9c0bf2c301 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -469,6 +469,7 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); +void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); /* * KVM XIVE device helpers From patchwork Tue Dec 17 04:42:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296645 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4DBC930 for ; Tue, 17 Dec 2019 05:17:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 95C5A2072D for ; Tue, 17 Dec 2019 05:17:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="jO+mHOJZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 95C5A2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35664 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Er-0005d7-8i for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:17:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34412) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4iz-00012j-5x for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iy-0006Ud-2Q for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:45 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:53063 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ix-0005z4-OX; Mon, 16 Dec 2019 23:44:44 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWY494Fz9sT4; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557817; bh=AEyG8kMDV7K7eTzUARbjLzoB254Nh5b/bzAWmYEElow=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jO+mHOJZVbyK2GLvx573YVavWb1AAvnMLJN1nhrgmOjoN2CSZ0UxHhfbqOvlbJ8V/ HMSryDhGWb+pzIixJInhvXRfvIpLj+uzwcLckNiFj7msaJzSBvayrrMqsm4ghfRpw3 JuaCiBrZ8vYWEpPQ9bwjZskU5o0hYE4ShN2OQmXI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Date: Tue, 17 Dec 2019 15:42:41 +1100 Message-Id: <20191217044322.351838-48-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When a vCPU is dispatched on a HW thread, its context is pushed in the thread registers and it is activated by setting the VO bit in the CAM line word2. The HW grabs the associated NVT, pulls the IPB bits and merges them with the IPB of the new context. If interrupts were missed while the vCPU was not dispatched, these are synthesized in this sequence. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-18-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/xive.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7047e45dac..e022bb7afd 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -393,6 +393,57 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, return qw1w2; } +static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx, + uint8_t nvt_blk, uint32_t nvt_idx) +{ + XiveNVT nvt; + uint8_t ipb; + + /* + * Grab the associated NVT to pull the pending bits, and merge + * them with the IPB of the thread interrupt context registers + */ + if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n", + nvt_blk, nvt_idx); + return; + } + + ipb = xive_get_field32(NVT_W4_IPB, nvt.w4); + + if (ipb) { + /* Reset the NVT value */ + nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0); + xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); + + /* Merge in current context */ + xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); + } +} + +/* + * Updating the OS CAM line can trigger a resend of interrupt + */ +static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, + hwaddr offset, uint64_t value, unsigned size) +{ + uint32_t cam = value; + uint32_t qw1w2 = cpu_to_be32(cam); + uint8_t nvt_blk; + uint32_t nvt_idx; + bool vo; + + xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo); + + /* First update the registers */ + xive_tctx_set_os_cam(tctx, qw1w2); + + /* Check the interrupt pending bits */ + if (vo) { + xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx); + } +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. @@ -414,6 +465,7 @@ static const XiveTmOp xive_tm_operations[] = { * effects */ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL }, { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll }, From patchwork Tue Dec 17 04:42:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 23CAF930 for ; Tue, 17 Dec 2019 05:07:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EE5072072D for ; Tue, 17 Dec 2019 05:07:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="ciE+6hfZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE5072072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih54r-0006r4-Jy for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:07:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34641) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jE-0001SQ-F5 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jC-0006qg-Tz for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:00 -0500 Received: from ozlabs.org ([203.11.71.1]:33027) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jC-0006oL-Id; Mon, 16 Dec 2019 23:44:58 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWb6DfBz9sTH; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557819; bh=i12A5ZnvX8+6HSOGcBYPXVsT2ReFZORAeCbOhhExg7o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ciE+6hfZWU/jTd08hHd2J0fqBqIRp4Y6IxuI3o4FKqZIMPhIFtnBs/66hnX4UGcIQ HP3vxh9b6m+vnX/K8ofRMvO3oPp6FIObb4Z+izEgNpM5LPQmKPGyuYY6guMu8umN7S 0H0pO+KB579T5JNxqDeZliPltCgQx1dJ9bsVChBI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper Date: Tue, 17 Dec 2019 15:42:42 +1100 Message-Id: <20191217044322.351838-49-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field overrides the hardwired chip ID in the Powerbus operations and for CAM compares. This is typically used in the one block-per-chip configuration to associate a unique block id number to each IC of the system. Simplify the model with a pnv_xive_block_id() helper and remove 'tctx_chipid' which becomes useless. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-19-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 64 ++++++++++++++++++++------------------- include/hw/ppc/pnv_xive.h | 3 -- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 216ebc150a..23e73641f2 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -85,13 +85,30 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, return (word & ~mask) | ((value << ctz64(mask)) & mask); } +/* + * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID + * field overrides the hardwired chip ID in the Powerbus operations + * and for CAM compares + */ +static uint8_t pnv_xive_block_id(PnvXive *xive) +{ + uint8_t blk = xive->chip->chip_id; + uint64_t cfg_val = xive->regs[PC_TCTXT_CFG >> 3]; + + if (cfg_val & PC_TCTXT_CHIPID_OVERRIDE) { + blk = GETFIELD(PC_TCTXT_CHIPID, cfg_val); + } + + return blk; +} + /* * Remote access to controllers. HW uses MMIOs. For now, a simple scan * of the chips is good enough. * * TODO: Block scope support */ -static PnvXive *pnv_xive_get_ic(uint8_t blk) +static PnvXive *pnv_xive_get_remote(uint8_t blk) { PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; @@ -100,7 +117,7 @@ static PnvXive *pnv_xive_get_ic(uint8_t blk) Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); PnvXive *xive = &chip9->xive; - if (xive->chip->chip_id == blk) { + if (pnv_xive_block_id(xive) == blk) { return xive; } } @@ -216,7 +233,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, /* Remote VST access */ if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { - xive = pnv_xive_get_ic(blk); + xive = pnv_xive_get_remote(blk); return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; } @@ -364,7 +381,10 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, { PnvXive *xive = PNV_XIVE(xrtr); - if (pnv_xive_get_ic(blk) != xive) { + /* + * EAT lookups should be local to the IC + */ + if (pnv_xive_block_id(xive) != blk) { xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); return -1; } @@ -470,7 +490,7 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno) { PnvXive *xive = PNV_XIVE(xn); - uint8_t blk = xive->chip->chip_id; + uint8_t blk = pnv_xive_block_id(xive); xive_router_notify(xn, XIVE_EAS(blk, srcno)); } @@ -834,20 +854,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr offset, case PC_TCTXT_CFG: /* * TODO: block group support - * - * PC_TCTXT_CFG_BLKGRP_EN - * PC_TCTXT_CFG_HARD_CHIPID_BLK : - * Moves the chipid into block field for hardwired CAM compares. - * Block offset value is adjusted to 0b0..01 & ThrdId - * - * Will require changes in xive_presenter_tctx_match(). I am - * not sure how to handle that yet. */ - - /* Overrides hardwired chip ID with the chip ID field */ - if (val & PC_TCTXT_CHIPID_OVERRIDE) { - xive->tctx_chipid = GETFIELD(PC_TCTXT_CHIPID, val); - } break; case PC_TCTXT_TRACK: /* @@ -1656,19 +1663,20 @@ static const MemoryRegionOps pnv_xive_pc_ops = { void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr = XIVE_ROUTER(xive); - uint8_t blk = xive->chip->chip_id; + uint8_t blk = pnv_xive_block_id(xive); + uint8_t chip_id = xive->chip->chip_id; uint32_t srcno0 = XIVE_EAS(blk, 0); uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; int i; - monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); - monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, - srcno0 + nr_ipis - 1); + monitor_printf(mon, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id, blk, + srcno0, srcno0 + nr_ipis - 1); for (i = 0; i < nr_ipis; i++) { if (xive_router_get_eas(xrtr, blk, i, &eas)) { break; @@ -1678,13 +1686,13 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) } } - monitor_printf(mon, "XIVE[%x] ENDT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); i = 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_pic_print_info(&end, i++, mon); } - monitor_printf(mon, "XIVE[%x] END Escalation EAT\n", blk); + monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); i = 0; while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); @@ -1697,12 +1705,6 @@ static void pnv_xive_reset(void *dev) XiveSource *xsrc = &xive->ipi_source; XiveENDSource *end_xsrc = &xive->end_source; - /* - * Use the PnvChip id to identify the XIVE interrupt controller. - * It can be overriden by configuration at runtime. - */ - xive->tctx_chipid = xive->chip->chip_id; - /* Default page size (Should be changed at runtime to 64k) */ xive->ic_shift = xive->vc_shift = xive->pc_shift = 12; diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index 4fdaa9247d..f4c7caad40 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -72,9 +72,6 @@ typedef struct PnvXive { /* Interrupt controller registers */ uint64_t regs[0x300]; - /* Can be configured by FW */ - uint32_t tctx_chipid; - /* * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ * These are in a SRAM protected by ECC. From patchwork Tue Dec 17 04:42:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296687 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 105AF13B6 for ; Tue, 17 Dec 2019 05:28:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA1822072B for ; Tue, 17 Dec 2019 05:28:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Ra8bUvVL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DA1822072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35835 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5P1-0004Sx-R2 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:28:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34972) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jb-00022v-Cr for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jZ-0007OH-VL for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:23 -0500 Received: from ozlabs.org ([203.11.71.1]:49633) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jZ-0006st-JX; Mon, 16 Dec 2019 23:45:21 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWc4gK7z9sTM; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557820; bh=5Qx9JZq/b4z8NuNNEqJb3p8l2efckqMTcq8O5CEPJfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ra8bUvVLF4bOicbS5uN224pSu12v4D6O9Ebdb9fmpZNBcIyoWiw1vB3WVZuoK8STb bHIgKeBa76w3+HDmbWnbIAQGe2WZ0xqWmouk1QKBePJqQFtaylKZjGxLD54/q3R1A+ ochV9tmXMZkkCc9FS/H+wYV95CCSuvRztrKQtT6E= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler Date: Tue, 17 Dec 2019 15:42:43 +1100 Message-Id: <20191217044322.351838-50-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When doing CAM line compares, fetch the block id from the interrupt controller which can have set the PC_TCTXT_CHIPID field. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-20-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 6 ++++++ hw/intc/spapr_xive.c | 6 ++++++ hw/intc/xive.c | 21 ++++++++++++++++----- include/hw/ppc/xive.h | 2 +- 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 23e73641f2..43c760efd1 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -459,6 +459,11 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) +{ + return pnv_xive_block_id(PNV_XIVE(xrtr)); +} + /* * The TIMA MMIO space is shared among the chips and to identify the * chip from which the access is being done, we extract the chip id @@ -1890,6 +1895,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) xrc->write_end = pnv_xive_write_end; xrc->get_nvt = pnv_xive_get_nvt; xrc->write_nvt = pnv_xive_write_nvt; + xrc->get_block_id = pnv_xive_get_block_id; xnc->notify = pnv_xive_notify; xpc->match_nvt = pnv_xive_match_nvt; diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index b785066da5..57305c56d7 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -473,6 +473,11 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) +{ + return SPAPR_XIVE_BLOCK_ID; +} + static const VMStateDescription vmstate_spapr_xive_end = { .name = TYPE_SPAPR_XIVE "/end", .version_id = 1, @@ -766,6 +771,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) xrc->write_end = spapr_xive_write_end; xrc->get_nvt = spapr_xive_get_nvt; xrc->write_nvt = spapr_xive_write_nvt; + xrc->get_block_id = spapr_xive_get_block_id; sicc->activate = spapr_xive_activate; sicc->deactivate = spapr_xive_deactivate; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index e022bb7afd..d4c6e21703 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1371,17 +1371,25 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } +static int xive_router_get_block_id(XiveRouter *xrtr) +{ + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_block_id(xrtr); +} + /* * Encode the HW CAM line in the block group mode format : * * chip << 19 | 0000000 0 0001 thread (7Bit) */ -static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx) +static uint32_t xive_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) { CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; uint32_t pir = env->spr_cb[SPR_PIR].default_value; + uint8_t blk = xive_router_get_block_id(XIVE_ROUTER(xptr)); - return xive_nvt_cam_line((pir >> 8) & 0xf, 1 << 7 | (pir & 0x7f)); + return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); } /* @@ -1418,7 +1426,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, /* PHYS ring */ if ((be32_to_cpu(qw3w2) & TM_QW3W2_VT) && - cam == xive_tctx_hw_cam_line(tctx)) { + cam == xive_tctx_hw_cam_line(xptr, tctx)) { return TM_QW3_HV_PHYS; } @@ -1755,7 +1763,11 @@ static uint64_t xive_end_source_read(void *opaque, hwaddr addr, unsigned size) uint8_t pq; uint64_t ret = -1; - end_blk = xsrc->block_id; + /* + * The block id should be deduced from the load address on the END + * ESB MMIO but our model only supports a single block per XIVE chip. + */ + end_blk = xive_router_get_block_id(xsrc->xrtr); end_idx = addr >> (xsrc->esb_shift + 1); if (xive_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { @@ -1855,7 +1867,6 @@ static void xive_end_source_realize(DeviceState *dev, Error **errp) } static Property xive_end_source_properties[] = { - DEFINE_PROP_UINT8("block-id", XiveENDSource, block_id, 0), DEFINE_PROP_UINT32("nr-ends", XiveENDSource, nr_ends, 0), DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 9c0bf2c301..1b7b89098f 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -351,6 +351,7 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); + uint8_t (*get_block_id)(XiveRouter *xrtr); } XiveRouterClass; int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, @@ -431,7 +432,6 @@ typedef struct XiveENDSource { DeviceState parent; uint32_t nr_ends; - uint8_t block_id; /* ESB memory region */ uint32_t esb_shift; From patchwork Tue Dec 17 04:42:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296663 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C11FC6C1 for ; Tue, 17 Dec 2019 05:22:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 969792072B for ; Tue, 17 Dec 2019 05:22:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="T9DZMEm3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 969792072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Jv-0004hG-3g for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:22:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35073) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ji-00027R-7k for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jg-0007W6-Fb for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:30 -0500 Received: from ozlabs.org ([203.11.71.1]:52363) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jf-00071S-If; Mon, 16 Dec 2019 23:45:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWd3lBSz9sTN; Tue, 17 Dec 2019 15:43:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557821; bh=vomrH429h1FwgoecOnUgRXJ8QtgZWOpq3eZ7u7hPP/s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T9DZMEm3MCNx9CWDB0KVOJh9NVkP1L9z6OzW3NWQVxmbbhOWTsjWGkQ8hDqNUorqE x9wORSD8CGF1EQqMScc5YhXpLogDJmo5gf+iaKu51KmsH3p7hcq65wv7vEne+DsfBI Nen+bPin2h6PUeU5159NJJ1JYYa45bUlSTj+8zVI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 50/88] ppc/pnv: Dump the XIVE NVT table Date: Tue, 17 Dec 2019 15:42:44 +1100 Message-Id: <20191217044322.351838-51-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater This is useful to dump the saved contexts of the vCPUs : configuration of the base END index of the vCPU and the Interrupt Pending Buffer register, which is updated when an interrupt can not be presented. When dumping the NVT table, we skip empty indirect pages which are not necessarily allocated. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-21-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 64 ++++++++++++++++++++++++++++++++++++++ include/hw/ppc/xive_regs.h | 3 ++ 2 files changed, 67 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 43c760efd1..a0a69b98a7 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -527,6 +527,44 @@ static uint32_t pnv_xive_nr_ipis(PnvXive *xive, uint8_t blk) return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; } +/* + * Compute the number of entries per indirect subpage. + */ +static uint64_t pnv_xive_vst_per_subpage(PnvXive *xive, uint32_t type) +{ + uint8_t blk = pnv_xive_block_id(xive); + uint64_t vsd = xive->vsds[type][blk]; + const XiveVstInfo *info = &vst_infos[type]; + uint64_t vsd_addr; + uint32_t page_shift; + + /* For direct tables, fake a valid value */ + if (!(VSD_INDIRECT & vsd)) { + return 1; + } + + /* Get the page size of the indirect table. */ + vsd_addr = vsd & VSD_ADDRESS_MASK; + vsd = ldq_be_dma(&address_space_memory, vsd_addr); + + if (!(vsd & VSD_ADDRESS_MASK)) { +#ifdef XIVE_DEBUG + xive_error(xive, "VST: invalid %s entry %x !?", info->name, idx); +#endif + return 0; + } + + page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; + + if (!pnv_xive_vst_page_size_allowed(page_shift)) { + xive_error(xive, "VST: invalid %s page shift %d", info->name, + page_shift); + return 0; + } + + return (1ull << page_shift) / info->size; +} + /* * EDT Table * @@ -1665,6 +1703,21 @@ static const MemoryRegionOps pnv_xive_pc_ops = { }, }; +static void xive_nvt_pic_print_info(XiveNVT *nvt, uint32_t nvt_idx, + Monitor *mon) +{ + uint8_t eq_blk = xive_get_field32(NVT_W1_EQ_BLOCK, nvt->w1); + uint32_t eq_idx = xive_get_field32(NVT_W1_EQ_INDEX, nvt->w1); + + if (!xive_nvt_is_valid(nvt)) { + return; + } + + monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx, + eq_blk, eq_idx, + xive_get_field32(NVT_W4_IPB, nvt->w4)); +} + void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) { XiveRouter *xrtr = XIVE_ROUTER(xive); @@ -1674,7 +1727,9 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) uint32_t nr_ipis = pnv_xive_nr_ipis(xive, blk); XiveEAS eas; XiveEND end; + XiveNVT nvt; int i; + uint64_t xive_nvt_per_subpage; monitor_printf(mon, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id, blk, srcno0, srcno0 + nr_ipis - 1); @@ -1702,6 +1757,15 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon) while (!xive_router_get_end(xrtr, blk, i, &end)) { xive_end_eas_pic_print_info(&end, i++, mon); } + + monitor_printf(mon, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id, blk, + 0, XIVE_NVT_COUNT - 1); + xive_nvt_per_subpage = pnv_xive_vst_per_subpage(xive, VST_TSEL_VPDT); + for (i = 0; i < XIVE_NVT_COUNT; i += xive_nvt_per_subpage) { + while (!xive_router_get_nvt(xrtr, blk, i, &nvt)) { + xive_nvt_pic_print_info(&nvt, i++, mon); + } + } } static void pnv_xive_reset(void *dev) diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 1a5622f8de..09f243600c 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -252,6 +252,8 @@ typedef struct XiveNVT { uint32_t w0; #define NVT_W0_VALID PPC_BIT32(0) uint32_t w1; +#define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3) +#define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31) uint32_t w2; uint32_t w3; uint32_t w4; @@ -277,6 +279,7 @@ typedef struct XiveNVT { * field of the XIVE END */ #define XIVE_NVT_SHIFT 19 +#define XIVE_NVT_COUNT (1 << XIVE_NVT_SHIFT) static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) { From patchwork Tue Dec 17 04:42:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55D9C930 for ; Tue, 17 Dec 2019 05:10:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B71E2072D for ; Tue, 17 Dec 2019 05:10:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="JvPGq8Sf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2B71E2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih57W-0002er-Rh for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:10:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34847) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jO-0001hk-NY for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jN-000761-B3 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:10 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:43285 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jN-0006bE-04; Mon, 16 Dec 2019 23:45:09 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWb56VTz9sTP; Tue, 17 Dec 2019 15:43:37 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557819; bh=HsIVagByvmKam4iCJYnc9UEUs0SR2UwTtQMiFTEdpi0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JvPGq8Sfdb0PERR+ZThx+8lrmfyDNtCGS7IFEahq8hdomoOIKXKgsGgjz7BlYDydp U/IM3Nvwf3eXV9THYTRw4vtNyr4uI2YuB6d1OWp0XWTwJ2PgbBtKQ5S8AT+tcUTM2K 4XPN9FWwU4hCuNd/7oe1sw9e842IwTas/5YMK5HU= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper Date: Tue, 17 Dec 2019 15:42:45 +1100 Message-Id: <20191217044322.351838-52-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Vladimir Sementsov-Ogievskiy , aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Vladimir Sementsov-Ogievskiy Make kvmppc_hint_smt_possible hint append helper well formed: rename errp to errp_in, as it is IN-parameter here (which is unusual for errp), rename function to be kvmppc_error_append_*_hint. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Marc-André Lureau Message-Id: <20191127191434.20945-1-vsementsov@virtuozzo.com> Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/ppc/spapr.c | 2 +- target/ppc/kvm.c | 6 +++--- target/ppc/kvm_ppc.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d9c9a2bcee..e3c7d487b8 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2564,7 +2564,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) " requires the use of VSMT mode %d.\n", smp_threads, kvm_smt, spapr->vsmt); } - kvmppc_hint_smt_possible(&local_err); + kvmppc_error_append_smt_possible_hint(&local_err); goto out; } } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index c77f9848ec..7406d18945 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2076,7 +2076,7 @@ int kvmppc_set_smt_threads(int smt) return ret; } -void kvmppc_hint_smt_possible(Error **errp) +void kvmppc_error_append_smt_possible_hint(Error **errp_in) { int i; GString *g; @@ -2091,10 +2091,10 @@ void kvmppc_hint_smt_possible(Error **errp) } } s = g_string_free(g, false); - error_append_hint(errp, "%s.\n", s); + error_append_hint(errp_in, "%s.\n", s); g_free(s); } else { - error_append_hint(errp, + error_append_hint(errp_in, "This KVM seems to be too old to support VSMT.\n"); } } diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 98bd7d5da6..47b08a4030 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -28,7 +28,7 @@ void kvmppc_set_papr(PowerPCCPU *cpu); int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); int kvmppc_smt_threads(void); -void kvmppc_hint_smt_possible(Error **errp); +void kvmppc_error_append_smt_possible_hint(Error **errp_in); int kvmppc_set_smt_threads(int smt); int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits); int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits); @@ -164,7 +164,7 @@ static inline int kvmppc_smt_threads(void) return 1; } -static inline void kvmppc_hint_smt_possible(Error **errp) +static inline void kvmppc_error_append_smt_possible_hint(Error **errp_in) { return; } From patchwork Tue Dec 17 04:42:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F9FD6C1 for ; Tue, 17 Dec 2019 05:20:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5364E2072D for ; Tue, 17 Dec 2019 05:20:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KG9QV8+O" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5364E2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Hw-00023b-Sy for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:20:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34749) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jK-0001bf-JV for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jJ-00070S-6l for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:06 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:37427 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jI-0006Th-SR; Mon, 16 Dec 2019 23:45:05 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWb257xz9sTQ; Tue, 17 Dec 2019 15:43:37 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557819; bh=oFqXJ1bVqdgNlGJhZqQ6IZxCwNPyaxw8gt/RF4wb3xk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KG9QV8+OXaRx58yZUiHCwDPlhSt0j3Coq65NXD3zYd7aF0NanHpFL9luHSAIeCYRp hHsvWkdy+CFew+U24weuFXhcSHvD2nq8yoPppE5yNDYwWhkI1bhWnAg2B7+Zfemnre 0s2i2w5hMdwE3D0107LGW2o+JHNwMcNpD7ehCZvM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover Date: Tue, 17 Dec 2019 15:42:46 +1100 Message-Id: <20191217044322.351838-53-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, Cedric Le Goater , qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" PAPR allows the interrupt controller used on a POWER9 machine (XICS or XIVE) to be selected by the guest operating system, by using the ibm,client-architecture-support (CAS) feature negotiation call. Currently, if the guest selects an interrupt controller different from the one selected at initial boot, this causes the system to be reset with the new model and the boot starts again. This means we run through the SLOF boot process twice, as well as any other bootloader (e.g. grub) in use before the OS calls CAS. This can be confusing and/or inconvenient for users. Thanks to two fairly recent changes, we no longer need this reboot. 1) we now completely regenerate the device tree when CAS is called (meaning we don't need special case updates for all the device tree changes caused by the interrupt controller mode change), 2) we now have explicit code paths to activate and deactivate the different interrupt controllers, rather than just implicitly calling those at machine reset time. We can therefore eliminate the reboot for changing irq mode, simply by putting a call to spapr_irq_update_active_intc() before we call spapr_h_cas_compose_response() (which gives the updated device tree to the guest firmware and OS). Signed-off-by: David Gibson Reviewed-by: Cedric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr_hcall.c | 33 +++++++++++++-------------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 140f05c1c6..05a7ca275b 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1767,21 +1767,10 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, } spapr->cas_pre_isa3_guest = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); spapr_ovec_cleanup(ov1_guest); - if (!spapr->cas_reboot) { - /* If spapr_machine_reset() did not set up a HPT but one is necessary - * (because the guest isn't going to use radix) then set it up here. */ - if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { - /* legacy hash or new hash: */ - spapr_setup_hpt_and_vrma(spapr); - } - spapr->cas_reboot = - (spapr_h_cas_compose_response(spapr, args[1], args[2], - ov5_updates) != 0); - } /* - * Ensure the guest asks for an interrupt mode we support; otherwise - * terminate the boot. + * Ensure the guest asks for an interrupt mode we support; + * otherwise terminate the boot. */ if (guest_xive) { if (!spapr->irq->xive) { @@ -1797,14 +1786,18 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, } } - /* - * Generate a machine reset when we have an update of the - * interrupt mode. Only required when the machine supports both - * modes. - */ + spapr_irq_update_active_intc(spapr); + if (!spapr->cas_reboot) { - spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT) - && spapr->irq->xics && spapr->irq->xive; + /* If spapr_machine_reset() did not set up a HPT but one is necessary + * (because the guest isn't going to use radix) then set it up here. */ + if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { + /* legacy hash or new hash: */ + spapr_setup_hpt_and_vrma(spapr); + } + spapr->cas_reboot = + (spapr_h_cas_compose_response(spapr, args[1], args[2], + ov5_updates) != 0); } spapr_ovec_cleanup(ov5_updates); From patchwork Tue Dec 17 04:42:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E29F6C1 for ; Tue, 17 Dec 2019 05:20:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53FC02072D for ; Tue, 17 Dec 2019 05:20:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="M5UZYxJf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53FC02072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5HQ-00017U-Uj for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:20:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35074) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ji-00027S-7Q for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jf-0007Ul-Mk for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:30 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:33205 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4je-00070D-C9; Mon, 16 Dec 2019 23:45:26 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWd03LLz9sTF; Tue, 17 Dec 2019 15:43:37 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557821; bh=teDKDGq3dNeff5zj6qtCOnSpMhJGW5rjS89bzWKzkDA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M5UZYxJf0e5jTMYIEWYM6vyLSLTbF6kSn+ROf0UpdZTpUM2vKXYruHWIM5twlnb4y +ISC+Ib882K64EUA/Ioiix/Ck8/Sba/DDoqJzhv8KQq2Y8WVLkiJxsAlpk1FvycMAH DLflyAMfg/rUJT1ZfHzCLI1eW8fftV5iBeNoh+nc= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 53/88] spapr: Improve handling of fdt buffer size Date: Tue, 17 Dec 2019 15:42:47 +1100 Message-Id: <20191217044322.351838-54-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, Cedric Le Goater , qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Previously, spapr_build_fdt() constructed the device tree in a fixed buffer of size FDT_MAX_SIZE. This is a bit inflexible, but more importantly it's awkward for the case where we use it during CAS. In that case the guest firmware supplies a buffer and we have to awkwardly check that what we generated fits into it afterwards, after doing a lot of size checks during spapr_build_fdt(). Simplify this by having spapr_build_fdt() take a 'space' parameter. For the CAS case, we pass in the buffer size provided by SLOF, for the machine init case, we continue to pass FDT_MAX_SIZE. Signed-off-by: David Gibson Reviewed-by: Cedric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e3c7d487b8..df5bea1bd4 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -917,7 +917,8 @@ static bool spapr_hotplugged_dev_before_cas(void) return false; } -static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset); +static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, + size_t space); int spapr_h_cas_compose_response(SpaprMachineState *spapr, target_ulong addr, target_ulong size, @@ -930,24 +931,17 @@ int spapr_h_cas_compose_response(SpaprMachineState *spapr, return 1; } - if (size < sizeof(hdr) || size > FW_MAX_SIZE) { - error_report("SLOF provided an unexpected CAS buffer size " - TARGET_FMT_lu " (min: %zu, max: %u)", - size, sizeof(hdr), FW_MAX_SIZE); + if (size < sizeof(hdr)) { + error_report("SLOF provided insufficient CAS buffer " + TARGET_FMT_lu " (min: %zu)", size, sizeof(hdr)); exit(EXIT_FAILURE); } size -= sizeof(hdr); - fdt = spapr_build_fdt(spapr, false); + fdt = spapr_build_fdt(spapr, false, size); _FDT((fdt_pack(fdt))); - if (fdt_totalsize(fdt) + sizeof(hdr) > size) { - g_free(fdt); - trace_spapr_cas_failed(size); - return -1; - } - cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); @@ -1197,7 +1191,8 @@ static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) } } -static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset) +static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, + size_t space) { MachineState *machine = MACHINE(spapr); MachineClass *mc = MACHINE_GET_CLASS(machine); @@ -1207,8 +1202,8 @@ static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset) SpaprPhbState *phb; char *buf; - fdt = g_malloc0(FDT_MAX_SIZE); - _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); + fdt = g_malloc0(space); + _FDT((fdt_create_empty_tree(fdt, space))); /* Root node */ _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); @@ -1723,19 +1718,13 @@ static void spapr_machine_reset(MachineState *machine) */ fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE; - fdt = spapr_build_fdt(spapr, true); + fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); rc = fdt_pack(fdt); /* Should only fail if we've built a corrupted tree */ assert(rc == 0); - if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { - error_report("FDT too big ! 0x%x bytes (max is 0x%x)", - fdt_totalsize(fdt), FDT_MAX_SIZE); - exit(1); - } - /* Load the fdt */ qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); From patchwork Tue Dec 17 04:42:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9FAB66C1 for ; Tue, 17 Dec 2019 05:15:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 761292072D for ; Tue, 17 Dec 2019 05:15:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="E8cuLaTs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 761292072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Ck-0002Ha-VU for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:15:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34942) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jZ-000208-E8 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jX-0007Kq-Om for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:21 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:46733 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jX-0006p1-DY; Mon, 16 Dec 2019 23:45:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWc0jldz9sTD; Tue, 17 Dec 2019 15:43:37 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557820; bh=hkPBn2/1LAP40JftgW8huc2iGZcCsof5koenWFEaSME=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E8cuLaTsBop9RmepwipQMz1Z5B78KvXd+DkQCPlYW+abbSga+htxlaxzTR9+l+9jx L1NGRmBfJG387Hothi8P+xLYtwBNNdB3DggKdPsUBLh0oQZqZakjaBS5ksXDrQVnEW c4LaSY6shMQdwJXEVeAaLBw+RF4c5WBn61cQF6PM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support() Date: Tue, 17 Dec 2019 15:42:48 +1100 Message-Id: <20191217044322.351838-55-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, Cedric Le Goater , qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" spapr_h_cas_compose_response() handles the last piece of the PAPR feature negotiation process invoked via the ibm,client-architecture-support OF call. Its only caller is h_client_architecture_support() which handles most of the rest of that process. I believe it was placed in a separate file originally to handle some fiddly dependencies between functions, but mostly it's just confusing to have the CAS process split into two pieces like this. Now that compose response is simplified (by just generating the whole device tree anew), it's cleaner to just fold it into h_client_architecture_support(). Signed-off-by: David Gibson Reviewed-by: Cedric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 61 +----------------------------------------- hw/ppc/spapr_hcall.c | 55 ++++++++++++++++++++++++++++++++++--- include/hw/ppc/spapr.h | 4 +-- 3 files changed, 54 insertions(+), 66 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index df5bea1bd4..3dedb41d48 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -76,7 +76,6 @@ #include "hw/nmi.h" #include "hw/intc/intc.h" -#include "qemu/cutils.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/mem/memory-device.h" #include "hw/ppc/spapr_tpm_proxy.h" @@ -897,63 +896,6 @@ out: return ret; } -static bool spapr_hotplugged_dev_before_cas(void) -{ - Object *drc_container, *obj; - ObjectProperty *prop; - ObjectPropertyIterator iter; - - drc_container = container_get(object_get_root(), "/dr-connector"); - object_property_iter_init(&iter, drc_container); - while ((prop = object_property_iter_next(&iter))) { - if (!strstart(prop->type, "link<", NULL)) { - continue; - } - obj = object_property_get_link(drc_container, prop->name, NULL); - if (spapr_drc_needed(obj)) { - return true; - } - } - return false; -} - -static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, - size_t space); - -int spapr_h_cas_compose_response(SpaprMachineState *spapr, - target_ulong addr, target_ulong size, - SpaprOptionVector *ov5_updates) -{ - void *fdt; - SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; - - if (spapr_hotplugged_dev_before_cas()) { - return 1; - } - - if (size < sizeof(hdr)) { - error_report("SLOF provided insufficient CAS buffer " - TARGET_FMT_lu " (min: %zu)", size, sizeof(hdr)); - exit(EXIT_FAILURE); - } - - size -= sizeof(hdr); - - fdt = spapr_build_fdt(spapr, false, size); - _FDT((fdt_pack(fdt))); - - cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); - cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); - trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); - - g_free(spapr->fdt_blob); - spapr->fdt_size = fdt_totalsize(fdt); - spapr->fdt_initial_size = spapr->fdt_size; - spapr->fdt_blob = fdt; - - return 0; -} - static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) { MachineState *ms = MACHINE(spapr); @@ -1191,8 +1133,7 @@ static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) } } -static void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, - size_t space) +void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) { MachineState *machine = MACHINE(spapr); MachineClass *mc = MACHINE_GET_CLASS(machine); diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 05a7ca275b..0f19be794c 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1,4 +1,5 @@ #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" @@ -15,6 +16,7 @@ #include "cpu-models.h" #include "trace.h" #include "kvm_ppc.h" +#include "hw/ppc/fdt.h" #include "hw/ppc/spapr_ovec.h" #include "mmu-book3s-v3.h" #include "hw/mem/memory-device.h" @@ -1638,6 +1640,26 @@ static uint32_t cas_check_pvr(SpaprMachineState *spapr, PowerPCCPU *cpu, return best_compat; } +static bool spapr_hotplugged_dev_before_cas(void) +{ + Object *drc_container, *obj; + ObjectProperty *prop; + ObjectPropertyIterator iter; + + drc_container = container_get(object_get_root(), "/dr-connector"); + object_property_iter_init(&iter, drc_container); + while ((prop = object_property_iter_next(&iter))) { + if (!strstart(prop->type, "link<", NULL)) { + continue; + } + obj = object_property_get_link(drc_container, prop->name, NULL); + if (spapr_drc_needed(obj)) { + return true; + } + } + return false; +} + static target_ulong h_client_architecture_support(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong opcode, @@ -1645,6 +1667,8 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, { /* Working address in data buffer */ target_ulong addr = ppc64_phys_to_real(args[0]); + target_ulong fdt_buf = args[1]; + target_ulong fdt_bufsize = args[2]; target_ulong ov_table; uint32_t cas_pvr; SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; @@ -1788,16 +1812,41 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, spapr_irq_update_active_intc(spapr); + if (spapr_hotplugged_dev_before_cas()) { + spapr->cas_reboot = true; + } + if (!spapr->cas_reboot) { + void *fdt; + SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 }; + /* If spapr_machine_reset() did not set up a HPT but one is necessary * (because the guest isn't going to use radix) then set it up here. */ if ((spapr->patb_entry & PATE1_GR) && !guest_radix) { /* legacy hash or new hash: */ spapr_setup_hpt_and_vrma(spapr); } - spapr->cas_reboot = - (spapr_h_cas_compose_response(spapr, args[1], args[2], - ov5_updates) != 0); + + if (fdt_bufsize < sizeof(hdr)) { + error_report("SLOF provided insufficient CAS buffer " + TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr)); + exit(EXIT_FAILURE); + } + + fdt_bufsize -= sizeof(hdr); + + fdt = spapr_build_fdt(spapr, false, fdt_bufsize); + _FDT((fdt_pack(fdt))); + + cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr)); + cpu_physical_memory_write(fdt_buf + sizeof(hdr), fdt, + fdt_totalsize(fdt)); + trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); + + g_free(spapr->fdt_blob); + spapr->fdt_size = fdt_totalsize(fdt); + spapr->fdt_initial_size = spapr->fdt_size; + spapr->fdt_blob = fdt; } spapr_ovec_cleanup(ov5_updates); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index d5ab5ea7b2..61f005c6f6 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -766,11 +766,9 @@ struct SpaprEventLogEntry { QTAILQ_ENTRY(SpaprEventLogEntry) next; }; +void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); void spapr_events_init(SpaprMachineState *sm); void spapr_dt_events(SpaprMachineState *sm, void *fdt); -int spapr_h_cas_compose_response(SpaprMachineState *sm, - target_ulong addr, target_ulong size, - SpaprOptionVector *ov5_updates); void close_htab_fd(SpaprMachineState *spapr); void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr); void spapr_free_hpt(SpaprMachineState *spapr); From patchwork Tue Dec 17 04:42:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296681 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0B90921 for ; Tue, 17 Dec 2019 05:26:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96BBD2072B for ; Tue, 17 Dec 2019 05:26:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="iZeqzRrj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96BBD2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Mw-0000ws-NB for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:26:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34962) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ja-00021z-Lw for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jZ-0007NP-7V for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:22 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:43839 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jY-0006rQ-TN; Mon, 16 Dec 2019 23:45:21 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWc2bLwz9sTL; Tue, 17 Dec 2019 15:43:38 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557820; bh=q6p3XQaAEcDfb+tvvOzabLiHVE3dNiJvf9oyM10gy0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZeqzRrjvO7I/cPVJUxUQ8mF+YxUeLvCFvrpaaAU3hxRiiuHvxgwwWepyY4u4WdSH H8n0H0j6YSTLgpIOzsfYE0viIH7LKuLLQGIRP1EHAjB3g4rVAvvhzGwzXwhs0B8bsC a0nFJ4FsSy9D+ss0p02A4zOOB53vrE8C71pSZM04= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 55/88] spapr: Simplify ovec diff Date: Tue, 17 Dec 2019 15:42:49 +1100 Message-Id: <20191217044322.351838-56-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Mike Roth , aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, Cedric Le Goater , qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" spapr_ovec_diff(ov, old, new) has somewhat complex semantics. ov is set to those bits which are in new but not old, and it returns as a boolean whether or not there are any bits in old but not new. It turns out that both callers only care about the second, not the first. This is basically equivalent to a bitmap subset operation, which is easier to understand and implement. So replace spapr_ovec_diff() with spapr_ovec_subset(). Cc: Mike Roth Signed-off-by: David Gibson Reviewed-by: Cedric Le Goater --- hw/ppc/spapr.c | 14 +++----------- hw/ppc/spapr_hcall.c | 8 ++------ hw/ppc/spapr_ovec.c | 30 ++++++++++-------------------- include/hw/ppc/spapr_ovec.h | 4 +--- 4 files changed, 16 insertions(+), 40 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 3dedb41d48..f11422fc41 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1840,8 +1840,6 @@ static bool spapr_ov5_cas_needed(void *opaque) { SpaprMachineState *spapr = opaque; SpaprOptionVector *ov5_mask = spapr_ovec_new(); - SpaprOptionVector *ov5_legacy = spapr_ovec_new(); - SpaprOptionVector *ov5_removed = spapr_ovec_new(); bool cas_needed; /* Prior to the introduction of SpaprOptionVector, we had two option @@ -1873,17 +1871,11 @@ static bool spapr_ov5_cas_needed(void *opaque) spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); - /* spapr_ovec_diff returns true if bits were removed. we avoid using - * the mask itself since in the future it's possible "legacy" bits may be - * removed via machine options, which could generate a false positive - * that breaks migration. - */ - spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); - cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); + /* We need extra information if we have any bits outside the mask + * defined above */ + cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); spapr_ovec_cleanup(ov5_mask); - spapr_ovec_cleanup(ov5_legacy); - spapr_ovec_cleanup(ov5_removed); return cas_needed; } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 0f19be794c..f1799b1b70 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1671,7 +1671,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, target_ulong fdt_bufsize = args[2]; target_ulong ov_table; uint32_t cas_pvr; - SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; + SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old; bool guest_radix; Error *local_err = NULL; bool raw_mode_supported = false; @@ -1770,9 +1770,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, /* capabilities that have been added since CAS-generated guest reset. * if capabilities have since been removed, generate another reset */ - ov5_updates = spapr_ovec_new(); - spapr->cas_reboot = spapr_ovec_diff(ov5_updates, - ov5_cas_old, spapr->ov5_cas); + spapr->cas_reboot = !spapr_ovec_subset(ov5_cas_old, spapr->ov5_cas); spapr_ovec_cleanup(ov5_cas_old); /* Now that processing is finished, set the radix/hash bit for the * guest if it requested a valid mode; otherwise terminate the boot. */ @@ -1849,8 +1847,6 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, spapr->fdt_blob = fdt; } - spapr_ovec_cleanup(ov5_updates); - if (spapr->cas_reboot) { qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET); } diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c index 811fadf143..0ff6d1aeae 100644 --- a/hw/ppc/spapr_ovec.c +++ b/hw/ppc/spapr_ovec.c @@ -76,31 +76,21 @@ void spapr_ovec_intersect(SpaprOptionVector *ov, bitmap_and(ov->bitmap, ov1->bitmap, ov2->bitmap, OV_MAXBITS); } -/* returns true if options bits were removed, false otherwise */ -bool spapr_ovec_diff(SpaprOptionVector *ov, - SpaprOptionVector *ov_old, - SpaprOptionVector *ov_new) +/* returns true if ov1 has a subset of bits in ov2 */ +bool spapr_ovec_subset(SpaprOptionVector *ov1, SpaprOptionVector *ov2) { - unsigned long *change_mask = bitmap_new(OV_MAXBITS); - unsigned long *removed_bits = bitmap_new(OV_MAXBITS); - bool bits_were_removed = false; + unsigned long *tmp = bitmap_new(OV_MAXBITS); + bool result; - g_assert(ov); - g_assert(ov_old); - g_assert(ov_new); - - bitmap_xor(change_mask, ov_old->bitmap, ov_new->bitmap, OV_MAXBITS); - bitmap_and(ov->bitmap, ov_new->bitmap, change_mask, OV_MAXBITS); - bitmap_and(removed_bits, ov_old->bitmap, change_mask, OV_MAXBITS); + g_assert(ov1); + g_assert(ov2); - if (!bitmap_empty(removed_bits, OV_MAXBITS)) { - bits_were_removed = true; - } + bitmap_andnot(tmp, ov1->bitmap, ov2->bitmap, OV_MAXBITS); + result = bitmap_empty(tmp, OV_MAXBITS); - g_free(change_mask); - g_free(removed_bits); + g_free(tmp); - return bits_were_removed; + return result; } void spapr_ovec_cleanup(SpaprOptionVector *ov) diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index 7891e9caac..2bed517a2b 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -66,9 +66,7 @@ SpaprOptionVector *spapr_ovec_clone(SpaprOptionVector *ov_orig); void spapr_ovec_intersect(SpaprOptionVector *ov, SpaprOptionVector *ov1, SpaprOptionVector *ov2); -bool spapr_ovec_diff(SpaprOptionVector *ov, - SpaprOptionVector *ov_old, - SpaprOptionVector *ov_new); +bool spapr_ovec_subset(SpaprOptionVector *ov1, SpaprOptionVector *ov2); void spapr_ovec_cleanup(SpaprOptionVector *ov); void spapr_ovec_set(SpaprOptionVector *ov, long bitnr); void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr); From patchwork Tue Dec 17 04:42:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296649 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C5836C1 for ; Tue, 17 Dec 2019 05:18:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 029662072D for ; Tue, 17 Dec 2019 05:18:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="bvEC2WDA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 029662072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5F8-00061n-KA for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:17:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35075) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ji-00027a-At for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jg-0007VS-BS for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:30 -0500 Received: from ozlabs.org ([203.11.71.1]:37031) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jf-00071A-Dz; Mon, 16 Dec 2019 23:45:27 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWd2MzYz9sTK; Tue, 17 Dec 2019 15:43:38 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557821; bh=gzHHLUuZkYUSgdIhhuqRz76mOFpXx2kVpf/11Jd9AYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bvEC2WDACRV8Z9GYkbkys5YHwqpQRmJqXNyQKFKhnAH2Fg/gOsheHBDJMZWj6nKes MJhuOze8cQrkHcqdZTOLG+IvZhkbRYcj+a6bhXACI9RZVChHlQSEvJq3qNCiMOHjoJ u84DJ/atd0d+z4S7m42L1EZozuIic+VAjJxIcXLQ= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset Date: Tue, 17 Dec 2019 15:42:50 +1100 Message-Id: <20191217044322.351838-57-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, Satheesh Rajendran , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz When a CPU is reset, QEMU makes sure no interrupt is pending by clearing CPUPPCstate::pending_interrupts in ppc_cpu_reset(). In the case of a complete machine emulation, eg. a sPAPR machine, an external interrupt request could still be pending in KVM though, eg. an IPI. It will be eventually presented to the guest, which is supposed to acknowledge it at the interrupt controller. If the interrupt controller is emulated in QEMU, either XICS or XIVE, ppc_set_irq() won't deassert the external interrupt pin in KVM since it isn't pending anymore for QEMU. When the vCPU re-enters the guest, the interrupt request is still pending and the vCPU will try again to acknowledge it. This causes an infinite loop and eventually hangs the guest. The code has been broken since the beginning. The issue wasn't hit before because accel=kvm,kernel-irqchip=off is an awkward setup that never got used until recently with the LC92x IBM systems (aka, Boston). Add a ppc_irq_reset() function to do the necessary cleanup, ie. deassert the IRQ pins of the CPU in QEMU and most importantly the external interrupt pin for this vCPU in KVM. Reported-by: Satheesh Rajendran Signed-off-by: Greg Kurz Message-Id: <157548861740.3650476.16879693165328764758.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 8 ++++++++ include/hw/ppc/ppc.h | 2 ++ target/ppc/translate_init.inc.c | 1 + 3 files changed, 11 insertions(+) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 8dd982fc1e..fab73f1b1f 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1515,3 +1515,11 @@ PowerPCCPU *ppc_get_vcpu_by_pir(int pir) return NULL; } + +void ppc_irq_reset(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + + env->irq_input_state = 0; + kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); +} diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 585be6ab98..89e1dd065a 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -77,6 +77,7 @@ static inline void ppc970_irq_init(PowerPCCPU *cpu) {} static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {} static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {} static inline void ppce500_irq_init(PowerPCCPU *cpu) {} +static inline void ppc_irq_reset(PowerPCCPU *cpu) {} #else void ppc40x_irq_init(PowerPCCPU *cpu); void ppce500_irq_init(PowerPCCPU *cpu); @@ -84,6 +85,7 @@ void ppc6xx_irq_init(PowerPCCPU *cpu); void ppc970_irq_init(PowerPCCPU *cpu); void ppcPOWER7_irq_init(PowerPCCPU *cpu); void ppcPOWER9_irq_init(PowerPCCPU *cpu); +void ppc_irq_reset(PowerPCCPU *cpu); #endif /* PPC machines for OpenBIOS */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ba726dec4d..64a838095c 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10461,6 +10461,7 @@ static void ppc_cpu_reset(CPUState *s) env->pending_interrupts = 0; s->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; + ppc_irq_reset(cpu); /* tininess for underflow is detected before rounding */ set_float_detect_tininess(float_tininess_before_rounding, From patchwork Tue Dec 17 04:42:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1AE2A14E3 for ; Tue, 17 Dec 2019 05:33:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E15692072B for ; Tue, 17 Dec 2019 05:33:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="CmaxjR9z" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E15692072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5U4-0003Gb-IX for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:33:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34768) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jL-0001cf-BG for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jK-00071l-9O for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:07 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:57659 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jJ-0006Vo-VK; Mon, 16 Dec 2019 23:45:06 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWb3HC8z9sTJ; Tue, 17 Dec 2019 15:43:38 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557819; bh=gKTXY6PIFlGqQkjlQe3AzKVDyV+OH7Fw3zyDvKgJzpc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CmaxjR9z/I8fsymqZJUtk2RrfDSOX/x063IEx0/+7Ta5uozXmvsOp5CxQfiyZx9lw 6ksP4jWO12wctUXaJbmQMGP5Ys9n0bSOzMzLMewLdcW33cH6IpgJokvl5UH5Q0VLrO XgfXO3folmt49nVH53F8gpOJ5R1q1SKRPTXzGR7s= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 57/88] xics: Don't deassert outputs Date: Tue, 17 Dec 2019 15:42:51 +1100 Message-Id: <20191217044322.351838-58-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The correct way to do this is to deassert the input pins on the CPU side. This is the case since a previous change. Signed-off-by: Greg Kurz Message-Id: <157548862298.3650476.1228720391270249433.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/intc/xics.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 0b259a09c5..1952009e6d 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -289,9 +289,6 @@ void icp_reset(ICPState *icp) icp->pending_priority = 0xff; icp->mfrr = 0xff; - /* Make all outputs are deasserted */ - qemu_set_irq(icp->output, 0); - if (kvm_irqchip_in_kernel()) { Error *local_err = NULL; From patchwork Tue Dec 17 04:42:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296633 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B3C37930 for ; Tue, 17 Dec 2019 05:12:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 89F502072D for ; Tue, 17 Dec 2019 05:12:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="CWQ7tT3r" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 89F502072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5AE-0006mL-3q for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:12:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34733) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jJ-0001aM-NL for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jI-000700-Ef for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:05 -0500 Received: from ozlabs.org ([203.11.71.1]:35339) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jI-0006Rh-3B; Mon, 16 Dec 2019 23:45:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWb0n0Xz9sT7; Tue, 17 Dec 2019 15:43:38 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557819; bh=PYsIZv4wWScv1e8Bh3X6QiwpEh8GrxqKPfNCFUsPPKU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CWQ7tT3r7/HRDZog0D6DFUou8YeTL7QI5w0oeK3PnNjFCgWNwheJ+Enz97s3M4C1l MBEtP2v5PPpBMlSk4MTNzhMFViRl9BjPXzD6XSkELwV2+n/B8Khjus58tUBZ4Et7PP cUVY0Plt++1PpVm2UR0TWSnulJqxC8hPCoSD1aNg= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models Date: Tue, 17 Dec 2019 15:42:52 +1100 Message-Id: <20191217044322.351838-59-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The power7_set_irq() and power9_set_irq() functions set this but it is never used actually. Modern Book3s compatible CPUs are only supported by the pnv and spapr machines. They have an interrupt controller, XICS for POWER7/8 and XIVE for POWER9, whose models don't require to track IRQ input states at the CPU level. Drop these lines to avoid confusion. Signed-off-by: Greg Kurz Message-Id: <157548862861.3650476.16622818876928044450.stgit@bahia.lan> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 16 ++-------------- target/ppc/cpu.h | 4 +++- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index fab73f1b1f..45834f98d1 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -275,10 +275,9 @@ void ppc970_irq_init(PowerPCCPU *cpu) static void power7_set_irq(void *opaque, int pin, int level) { PowerPCCPU *cpu = opaque; - CPUPPCState *env = &cpu->env; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, - env, pin, level); + &cpu->env, pin, level); switch (pin) { case POWER7_INPUT_INT: @@ -292,11 +291,6 @@ static void power7_set_irq(void *opaque, int pin, int level) LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); return; } - if (level) { - env->irq_input_state |= 1 << pin; - } else { - env->irq_input_state &= ~(1 << pin); - } } void ppcPOWER7_irq_init(PowerPCCPU *cpu) @@ -311,10 +305,9 @@ void ppcPOWER7_irq_init(PowerPCCPU *cpu) static void power9_set_irq(void *opaque, int pin, int level) { PowerPCCPU *cpu = opaque; - CPUPPCState *env = &cpu->env; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, - env, pin, level); + &cpu->env, pin, level); switch (pin) { case POWER9_INPUT_INT: @@ -334,11 +327,6 @@ static void power9_set_irq(void *opaque, int pin, int level) LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); return; } - if (level) { - env->irq_input_state |= 1 << pin; - } else { - env->irq_input_state &= ~(1 << pin); - } } void ppcPOWER9_irq_init(PowerPCCPU *cpu) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e3e82327b7..f9528fc29d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1090,7 +1090,9 @@ struct CPUPPCState { #if !defined(CONFIG_USER_ONLY) /* * This is the IRQ controller, which is implementation dependent - * and only relevant when emulating a complete machine. + * and only relevant when emulating a complete machine. Note that + * this isn't used by recent Book3s compatible CPUs (POWER7 and + * newer). */ uint32_t irq_input_state; void **irq_inputs; From patchwork Tue Dec 17 04:42:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296685 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DA8717F0 for ; Tue, 17 Dec 2019 05:28:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 329BB2072B for ; Tue, 17 Dec 2019 05:28:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="WWiMzqOy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 329BB2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Ot-0004FM-SC for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:28:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35428) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4k9-0002MG-G7 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4k6-00082W-1J for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:55 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:54171 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4k2-0007WF-CT; Mon, 16 Dec 2019 23:45:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWg4R8zz9sTc; Tue, 17 Dec 2019 15:43:39 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557823; bh=xZ5+eSjBmXhW8eTHhL7F8PZe9+G9Eaqb505vaM9HCi8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WWiMzqOymUtFm/gwdDyWiuiujLcU/HJtZ46pLUYkgb9IpTyfh1Kh6n5U8plNHdA0p 3rX+p6IhW0xSyCmu2/vLPXjwOCr2VWWkPXh9lrupk1ysjLGOjLNoTqO8dQ/zhnoJ4N RWLTwKqAlRkwrHV1UYBaFiJmMTSlhFum7AXS3W4E= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM Date: Tue, 17 Dec 2019 15:42:53 +1100 Message-Id: <20191217044322.351838-60-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz This only makes sense with an emulated CPU. Don't set the bit in CPUState::interrupt_request when using KVM to avoid confusions. Signed-off-by: Greg Kurz Message-Id: <157548863423.3650476.16424649423510075159.stgit@bahia.lan> Signed-off-by: David Gibson --- target/ppc/helper_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 85dfe7687f..d78c2af63e 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "sysemu/kvm.h" /* Swap temporary saved registers with GPRs */ static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -102,6 +103,10 @@ static inline void hreg_compute_hflags(CPUPPCState *env) static inline void cpu_interrupt_exittb(CPUState *cs) { + if (!kvm_enabled()) { + return; + } + if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); From patchwork Tue Dec 17 04:42:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296709 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B901514E3 for ; Tue, 17 Dec 2019 05:36:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8EF5C2082E for ; Tue, 17 Dec 2019 05:36:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="hJSjFhMV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8EF5C2082E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Wi-0007D1-JZ for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:36:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35350) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4k0-0002LV-Ib for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jz-0007xj-GE for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:48 -0500 Received: from ozlabs.org ([203.11.71.1]:37161) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jw-0007Oo-7q; Mon, 16 Dec 2019 23:45:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWg16NBz9sTT; Tue, 17 Dec 2019 15:43:39 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557823; bh=n8oIL2+nZlBzgcIXuaZwztF3/7D7XKvuOUrx0Eqt9sE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hJSjFhMVW78KPVlwr0fANyBoB0doLE9l2tF4Q5zNpEBUckYaIOp17/RLyHS9TM1PW ehp8PYXSgoclv/8o8VDbKq/gRa0WzVBIQsVcnTlHirxicMbO79D/yy75kX0PeN5gi/ aDG63tCaxVJSBasM4GNgX6bBmQMSZoW6uwO6gp3o= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type Date: Tue, 17 Dec 2019 15:42:54 +1100 Message-Id: <20191217044322.351838-61-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz PPCVirtualHypervisor is an interface instance. It should never be dereferenced. Drop the dummy type definition for extra safety, which is the common practice with QOM interfaces. Signed-off-by: Greg Kurz Message-Id: <157589808041.21182.18121655959115011353.stgit@bahia.lan> Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f9528fc29d..60cf030ce6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1222,10 +1222,6 @@ PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc); -struct PPCVirtualHypervisor { - Object parent; -}; - struct PPCVirtualHypervisorClass { InterfaceClass parent; void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); From patchwork Tue Dec 17 04:42:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296715 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0EAAA138C for ; Tue, 17 Dec 2019 05:37:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C8C0920733 for ; Tue, 17 Dec 2019 05:37:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="QD2a6ZnS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C8C0920733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5YO-0001LX-NB for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:37:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4k6-0002Lr-1N for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jz-0007y6-Hq for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:53 -0500 Received: from ozlabs.org ([203.11.71.1]:42423) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jw-0007Nq-8X; Mon, 16 Dec 2019 23:45:45 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWf6p3Tz9sTY; Tue, 17 Dec 2019 15:43:39 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557822; bh=rlTeDJpdg4rEEZiWHjdxU1vrmoe+ccL1RPnnRbfaP8k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QD2a6ZnSOJcp9DeE+4ltVwVwrURg0r6ErUnZqaJ70KpROXRXYTbKVHMG+sN/HuUhE E6//WjHkbTOMDJXzc6cxPIXSx++7Fos7i9Cwv2j9PuB2UWveUjg1ayPIyAJ9ZBPHrs /NHbR1SrEtC6JWK94vsr8Geec5Brei7gbW8jby2M= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information Date: Tue, 17 Dec 2019 15:42:55 +1100 Message-Id: <20191217044322.351838-62-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater This includes in QEMU a new CPU model for the POWER10 processor with the same capabilities of a POWER9 process. The model will be extended when support is completed. Signed-off-by: Cédric Le Goater Message-Id: <20191205184454.10722-2-clg@kaod.org> Signed-off-by: David Gibson --- target/ppc/compat.c | 21 +++- target/ppc/cpu-models.c | 3 + target/ppc/cpu-models.h | 3 + target/ppc/cpu.h | 1 + target/ppc/translate_init.inc.c | 215 ++++++++++++++++++++++++++++++++ 5 files changed, 237 insertions(+), 6 deletions(-) diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 7de4bf3122..f48df25944 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -51,36 +51,38 @@ static const CompatInfo compat_table[] = { { /* POWER6, ISA2.05 */ .name = "power6", .pvr = CPU_POWERPC_LOGICAL_2_05, - .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | - PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS, + .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS, .pcr_level = PCR_COMPAT_2_05, .max_vthreads = 2, }, { /* POWER7, ISA2.06 */ .name = "power7", .pvr = CPU_POWERPC_LOGICAL_2_06, - .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS, + .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_TM_DIS, .pcr_level = PCR_COMPAT_2_06, .max_vthreads = 4, }, { .name = "power7+", .pvr = CPU_POWERPC_LOGICAL_2_06_PLUS, - .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS, + .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_TM_DIS, .pcr_level = PCR_COMPAT_2_06, .max_vthreads = 4, }, { /* POWER8, ISA2.07 */ .name = "power8", .pvr = CPU_POWERPC_LOGICAL_2_07, - .pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07, + .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07, .pcr_level = PCR_COMPAT_2_07, .max_vthreads = 8, }, { /* POWER9, ISA3.00 */ .name = "power9", .pvr = CPU_POWERPC_LOGICAL_3_00, - .pcr = PCR_COMPAT_3_00, + .pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00, .pcr_level = PCR_COMPAT_3_00, /* * POWER9 hardware only supports 4 threads / core, but this @@ -91,6 +93,13 @@ static const CompatInfo compat_table[] = { */ .max_vthreads = 8, }, + { /* POWER10, ISA3.10 */ + .name = "power10", + .pvr = CPU_POWERPC_LOGICAL_3_10, + .pcr = PCR_COMPAT_3_10, + .pcr_level = PCR_COMPAT_3_10, + .max_vthreads = 8, + }, }; static const CompatInfo *compat_by_pvr(uint32_t pvr) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 086548e9b9..4ad16863c0 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -774,6 +774,8 @@ "POWER9 v1.0") POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9, "POWER9 v2.0") + POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10, + "POWER10 v1.0") #endif /* defined (TARGET_PPC64) */ /***************************************************************************/ @@ -950,6 +952,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "power8", "power8_v2.0" }, { "power8nvl", "power8nvl_v1.0" }, { "power9", "power9_v2.0" }, + { "power10", "power10_v1.0" }, #endif /* Generic PowerPCs */ diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 4fdb73034d..ce750b2d55 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -373,6 +373,8 @@ enum { CPU_POWERPC_POWER9_BASE = 0x004E0000, CPU_POWERPC_POWER9_DD1 = 0x004E0100, CPU_POWERPC_POWER9_DD20 = 0x004E1200, + CPU_POWERPC_POWER10_BASE = 0x00800000, + CPU_POWERPC_POWER10_DD1 = 0x00800100, CPU_POWERPC_970_v22 = 0x00390202, CPU_POWERPC_970FX_v10 = 0x00391100, CPU_POWERPC_970FX_v20 = 0x003C0200, @@ -409,6 +411,7 @@ enum { CPU_POWERPC_LOGICAL_2_06_PLUS = 0x0F100003, CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, CPU_POWERPC_LOGICAL_3_00 = 0x0F000005, + CPU_POWERPC_LOGICAL_3_10 = 0x0F000006, }; /* System version register (used on MPC 8xxx) */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 60cf030ce6..fbec1b0cd5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2364,6 +2364,7 @@ enum { PCR_COMPAT_2_06 = PPC_BIT(61), PCR_COMPAT_2_07 = PPC_BIT(60), PCR_COMPAT_3_00 = PPC_BIT(59), + PCR_COMPAT_3_10 = PPC_BIT(58), PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */ PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */ PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 64a838095c..7364d36b07 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -3354,6 +3354,11 @@ static void init_excp_POWER9(CPUPPCState *env) #endif } +static void init_excp_POWER10(CPUPPCState *env) +{ + init_excp_POWER9(env); +} + #endif /*****************************************************************************/ @@ -8996,6 +9001,216 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; } +#ifdef CONFIG_SOFTMMU +/* + * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings + * Encoded as array of int_32s in the form: + * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy + * x -> AP encoding + * y -> radix mode supported page size (encoded as a shift) + */ +static struct ppc_radix_page_info POWER10_radix_page_info = { + .count = 4, + .entries = { + 0x0000000c, /* 4K - enc: 0x0 */ + 0xa0000010, /* 64K - enc: 0x5 */ + 0x20000015, /* 2M - enc: 0x1 */ + 0x4000001e /* 1G - enc: 0x2 */ + } +}; +#endif /* CONFIG_SOFTMMU */ + +static void init_proc_POWER10(CPUPPCState *env) +{ + /* Common Registers */ + init_proc_book3s_common(env); + gen_spr_book3s_207_dbg(env); + + /* POWER8 Specific Registers */ + gen_spr_book3s_ids(env); + gen_spr_amr(env); + gen_spr_iamr(env); + gen_spr_book3s_purr(env); + gen_spr_power5p_common(env); + gen_spr_power5p_lpar(env); + gen_spr_power5p_ear(env); + gen_spr_power6_common(env); + gen_spr_power6_dbg(env); + gen_spr_power8_tce_address_control(env); + gen_spr_power8_ids(env); + gen_spr_power8_ebb(env); + gen_spr_power8_fscr(env); + gen_spr_power8_pmu_sup(env); + gen_spr_power8_pmu_user(env); + gen_spr_power8_tm(env); + gen_spr_power8_pspb(env); + gen_spr_vtb(env); + gen_spr_power8_ic(env); + gen_spr_power8_book4(env); + gen_spr_power8_rpr(env); + gen_spr_power9_mmu(env); + + /* POWER9 Specific registers */ + spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_TIDR, 0); + + /* FIXME: Filter fields properly based on privilege level */ + spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_PSSCR, 0); + + /* env variables */ + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + init_excp_POWER10(env); + ppcPOWER9_irq_init(env_archcpu(env)); +} + +static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { + return true; + } + return false; +} + +static bool cpu_has_work_POWER10(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (cs->halted) { + uint64_t psscr = env->spr[SPR_PSSCR]; + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + /* If EC is clear, just return true on any pending interrupt */ + if (!(psscr & PSSCR_EC)) { + return true; + } + /* External Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_EEE)) { + bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (heic == 0 || !msr_hv || msr_pr) { + return true; + } + } + /* Decrementer Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_DEE)) { + return true; + } + /* Machine Check or Hypervisor Maintenance Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + return true; + } + /* Privileged Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_PDEE)) { + return true; + } + /* Hypervisor Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_HDEE)) { + return true; + } + /* Hypervisor virtualization exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && + (env->spr[SPR_LPCR] & LPCR_HVEE)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + +POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER10"; + dc->desc = "POWER10"; + dc->props = powerpc_servercpu_properties; + pcc->pvr_match = ppc_pvr_match_power10; + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | + PCR_COMPAT_3_00; + pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | + PCR_COMPAT_2_06 | PCR_COMPAT_2_05; + pcc->init_proc = init_proc_POWER10; + pcc->check_pow = check_pow_nocheck; + cc->has_work = cpu_has_work_POWER10; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBSYNC | + PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_SHV) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + pcc->mmu_model = POWERPC_MMU_3_00; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; + /* segment page size remain the same */ + pcc->hash64_opts = &ppc_hash64_opts_POWER7; + pcc->radix_page_info = &POWER10_radix_page_info; + pcc->lrg_decr_bits = 56; +#endif + pcc->excp_model = POWERPC_EXCP_POWER9; + pcc->bus_model = PPC_FLAGS_INPUT_POWER9; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; +} + #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { From patchwork Tue Dec 17 04:42:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1665614E3 for ; Tue, 17 Dec 2019 05:33:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C95BF2146E for ; Tue, 17 Dec 2019 05:33:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Jy48gU/x" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C95BF2146E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5U5-0003Fn-Ev for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:33:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35515) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kB-0002Nq-NK for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4k9-00083v-FE for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:59 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:34107 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4k6-0007ac-Ev; Mon, 16 Dec 2019 23:45:55 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWh2P6Tz9sTf; Tue, 17 Dec 2019 15:43:39 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557824; bh=nD6rEAj61/oIlfmU5mHCM3f6/i6i4am4uzRT/VwDHRo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Jy48gU/xtwbA+XzYdAQP9TOlkwCJaoQPgMpwewdZgR4diQ+rOuJpx36OPZ4zsRPk8 KybZqkV+SexuTtf23mVG3pOEyTv5tv/Z5fI9FIh4sPgwLaOOWXFgBkWhNcVEJF3At1 r6t6RAjAA9+vvZmMyxAXfsLTAfExFskSEEWSEsbk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine Date: Tue, 17 Dec 2019 15:42:56 +1100 Message-Id: <20191217044322.351838-63-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater This is an empty shell with the XSCOM bus and cores. The chip controllers will come later. Signed-off-by: Cédric Le Goater Message-Id: <20191205184454.10722-3-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 158 +++++++++++++++++++++++++++++++++++-- hw/ppc/pnv_core.c | 10 +++ hw/ppc/pnv_xscom.c | 23 ++++-- include/hw/ppc/pnv.h | 33 ++++++++ include/hw/ppc/pnv_xscom.h | 19 +++++ 5 files changed, 232 insertions(+), 11 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fa656858b2..d99cd72840 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -317,6 +317,23 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) pnv_dt_lpc(chip, fdt, 0); } +static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) +{ + int i; + + pnv_dt_xscom(chip, fdt, 0); + + for (i = 0; i < chip->nr_cores; i++) { + PnvCore *pnv_core = chip->cores[i]; + + pnv_dt_core(chip, pnv_core, fdt); + } + + if (chip->ram_size) { + pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); + } +} + static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) { uint32_t io_base = d->ioport_id; @@ -467,6 +484,7 @@ static void *pnv_dt_create(MachineState *machine) { const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; + const char plat_compat10[] = "qemu,powernv10\0ibm,powernv"; PnvMachineState *pnv = PNV_MACHINE(machine); void *fdt; char *buf; @@ -484,7 +502,10 @@ static void *pnv_dt_create(MachineState *machine) _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); _FDT((fdt_setprop_string(fdt, 0, "model", "IBM PowerNV (emulated by qemu)"))); - if (pnv_is_power9(pnv)) { + if (pnv_is_power10(pnv)) { + _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10, + sizeof(plat_compat10)))); + } else if (pnv_is_power9(pnv)) { _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, sizeof(plat_compat9)))); } else { @@ -528,8 +549,8 @@ static void *pnv_dt_create(MachineState *machine) pnv_dt_bmc_sensors(pnv->bmc, fdt); } - /* Create an extra node for power management on Power9 */ - if (pnv_is_power9(pnv)) { + /* Create an extra node for power management on Power9 and Power10 */ + if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) { pnv_dt_power_mgt(fdt); } @@ -578,6 +599,12 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) return pnv_lpc_isa_create(&chip9->lpc, false, errp); } +static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) +{ + error_setg(errp, "No ISA bus!"); + return NULL; +} + static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) { return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); @@ -618,6 +645,13 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) object_property_set_bool(obj, true, "realized", &error_fatal); } +static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) +{ + /* + * No interrupt controller yet + */; +} + static void pnv_init(MachineState *machine) { PnvMachineState *pnv = PNV_MACHINE(machine); @@ -822,6 +856,11 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) return (chip->chip_id << 8) | (core_id << 2); } +static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) +{ + return (chip->chip_id << 8) | (core_id << 2); +} + static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { @@ -859,6 +898,27 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) pnv_cpu->intc = NULL; } +static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) +{ + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); + + /* Will be defined when the interrupt controller is */ + pnv_cpu->intc = NULL; +} + +static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) +{ + ; +} + +static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) +{ + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); + + pnv_cpu->intc = NULL; +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -886,6 +946,9 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) */ #define POWER9_CORE_MASK (0xffffffffffffffull) + +#define POWER10_CORE_MASK (0xffffffffffffffull) + static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 = PNV8_CHIP(obj); @@ -1246,6 +1309,56 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) &k->parent_realize); } +static void pnv_chip_power10_instance_init(Object *obj) +{ + /* + * No controllers yet + */ + ; +} + +static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) +{ + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); + PnvChip *chip = PNV_CHIP(dev); + Error *local_err = NULL; + + /* XSCOM bridge is first */ + pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); + + pcc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } +} + +static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PnvChipClass *k = PNV_CHIP_CLASS(klass); + + k->chip_type = PNV_CHIP_POWER10; + k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ + k->cores_mask = POWER10_CORE_MASK; + k->core_pir = pnv_chip_core_pir_p10; + k->intc_create = pnv_chip_power10_intc_create; + k->intc_reset = pnv_chip_power10_intc_reset; + k->intc_destroy = pnv_chip_power10_intc_destroy; + k->isa_create = pnv_chip_power10_isa_create; + k->dt_populate = pnv_chip_power10_dt_populate; + k->pic_print_info = pnv_chip_power10_pic_print_info; + dc->desc = "PowerNV Chip POWER10"; + + device_class_set_parent_realize(dc, pnv_chip_power10_realize, + &k->parent_realize); +} + static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); @@ -1327,10 +1440,12 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) &error_fatal); /* Each core has an XSCOM MMIO region */ - if (!pnv_chip_is_power9(chip)) { - xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); - } else { + if (pnv_chip_is_power10(chip)) { + xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid); + } else if (pnv_chip_is_power9(chip)) { xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); + } else { + xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); } pnv_xscom_add_subregion(chip, xscom_core_base, @@ -1558,6 +1673,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) mc->alias = "powernv"; } +static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); +} + static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1595,7 +1718,19 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) .parent = TYPE_PNV9_CHIP, \ } +#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ + { \ + .name = type, \ + .class_init = class_initfn, \ + .parent = TYPE_PNV10_CHIP, \ + } + static const TypeInfo types[] = { + { + .name = MACHINE_TYPE_NAME("powernv10"), + .parent = TYPE_PNV_MACHINE, + .class_init = pnv_machine_power10_class_init, + }, { .name = MACHINE_TYPE_NAME("powernv9"), .parent = TYPE_PNV_MACHINE, @@ -1635,6 +1770,17 @@ static const TypeInfo types[] = { .abstract = true, }, + /* + * P10 chip and variants + */ + { + .name = TYPE_PNV10_CHIP, + .parent = TYPE_PNV_CHIP, + .instance_init = pnv_chip_power10_instance_init, + .instance_size = sizeof(Pnv10Chip), + }, + DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), + /* * P9 chip and variants */ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 5ab75bde6c..2651044278 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -247,6 +247,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp) } snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); + /* TODO: check PNV_XSCOM_EX_SIZE for p10 */ pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, pc, name, PNV_XSCOM_EX_SIZE); @@ -308,6 +309,14 @@ static void pnv_core_power9_class_init(ObjectClass *oc, void *data) pcc->xscom_ops = &pnv_core_power9_xscom_ops; } +static void pnv_core_power10_class_init(ObjectClass *oc, void *data) +{ + PnvCoreClass *pcc = PNV_CORE_CLASS(oc); + + /* TODO: Use the P9 XSCOMs for now on P10 */ + pcc->xscom_ops = &pnv_core_power9_xscom_ops; +} + static void pnv_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -337,6 +346,7 @@ static const TypeInfo pnv_core_infos[] = { DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), + DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"), }; DEFINE_TYPES(pnv_core_infos) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index f01d788a65..b3d3b6e350 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -69,10 +69,16 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) { addr &= (PNV_XSCOM_SIZE - 1); - if (pnv_chip_is_power9(chip)) { - return addr >> 3; - } else { + switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { + case PNV_CHIP_POWER8E: + case PNV_CHIP_POWER8: + case PNV_CHIP_POWER8NVL: return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); + case PNV_CHIP_POWER9: + case PNV_CHIP_POWER10: + return addr >> 3; + default: + g_assert_not_reached(); } } @@ -307,6 +313,7 @@ static int xscom_dt_child(Object *child, void *opaque) static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; +static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom"; int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) { @@ -315,7 +322,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) ForeachPopulateArgs args; char *name; - if (pnv_chip_is_power9(chip)) { + if (pnv_chip_is_power10(chip)) { + reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip)); + reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE); + } else if (pnv_chip_is_power9(chip)) { reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip)); reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE); } else { @@ -332,7 +342,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); - if (pnv_chip_is_power9(chip)) { + if (pnv_chip_is_power10(chip)) { + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, + sizeof(compat_p10)))); + } else if (pnv_chip_is_power9(chip)) { _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, sizeof(compat_p9)))); } else { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 3a7bc3c57e..bfa61edfba 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -43,6 +43,7 @@ typedef enum PnvChipType { PNV_CHIP_POWER8, /* AKA Venice */ PNV_CHIP_POWER8NVL, /* AKA Naples */ PNV_CHIP_POWER9, /* AKA Nimbus */ + PNV_CHIP_POWER10, /* AKA TBD */ } PnvChipType; typedef struct PnvChip { @@ -105,6 +106,14 @@ typedef struct Pnv9Chip { #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) +#define TYPE_PNV10_CHIP "pnv10-chip" +#define PNV10_CHIP(obj) OBJECT_CHECK(Pnv10Chip, (obj), TYPE_PNV10_CHIP) + +typedef struct Pnv10Chip { + /*< private >*/ + PnvChip parent_obj; +} Pnv10Chip; + typedef struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; @@ -144,6 +153,10 @@ typedef struct PnvChipClass { #define PNV_CHIP_POWER9(obj) \ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) +#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0") +#define PNV_CHIP_POWER10(obj) \ + OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER10) + /* * This generates a HW chip id depending on an index, as found on a * two socket system with dual chip modules : @@ -203,6 +216,16 @@ PnvChip *pnv_get_chip(uint32_t chip_id); #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL +static inline bool pnv_chip_is_power10(const PnvChip *chip) +{ + return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10; +} + +static inline bool pnv_is_power10(PnvMachineState *pnv) +{ + return pnv_chip_is_power10(pnv->chips[0]); +} + /* * BMC helpers */ @@ -293,4 +316,14 @@ IPMIBmc *pnv_bmc_create(void); #define PNV9_HOMER_SIZE 0x0000000000300000ull #define PNV9_HOMER_BASE(chip) \ (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) + +/* + * POWER10 MMIO base addresses - 16TB stride per chip + */ +#define PNV10_CHIP_BASE(chip, base) \ + ((base) + ((uint64_t) (chip)->chip_id << 44)) + +#define PNV10_XSCOM_SIZE 0x0000000400000000ull +#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 67641ed278..790eb3d8f3 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -70,6 +70,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 +/* + * Layout of the XSCOM PCB addresses (POWER 9) + */ #define PNV9_XSCOM_EC_BASE(core) \ ((uint64_t)(((core) & 0x1F) + 0x20) << 24) #define PNV9_XSCOM_EC_SIZE 0x100000 @@ -87,6 +90,22 @@ typedef struct PnvXScomInterfaceClass { #define PNV9_XSCOM_XIVE_BASE 0x5013000 #define PNV9_XSCOM_XIVE_SIZE 0x300 +/* + * Layout of the XSCOM PCB addresses (POWER 10) + */ +#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) +#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24) +#define PNV10_XSCOM_EC(proc) \ + ((0x2 << 16) | ((1 << (3 - (proc))) << 12)) + +#define PNV10_XSCOM_EQ_BASE(core) \ + ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) +#define PNV10_XSCOM_EQ_SIZE 0x100000 + +#define PNV10_XSCOM_EC_BASE(core) \ + ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) +#define PNV10_XSCOM_EC_SIZE 0x100000 + extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); From patchwork Tue Dec 17 04:42:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296721 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38F38138C for ; Tue, 17 Dec 2019 05:39:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F45320733 for ; Tue, 17 Dec 2019 05:39:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="jpWxkqBq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0F45320733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36012 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5a4-00043f-Un for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:39:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35427) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4k9-0002MF-G1 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4k6-00082T-1H for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:55 -0500 Received: from ozlabs.org ([203.11.71.1]:43161) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4k3-0007WJ-Vn; Mon, 16 Dec 2019 23:45:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWg6KvRz9sTR; Tue, 17 Dec 2019 15:43:39 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557823; bh=9x8gEiCBBz8Y4SRiMXedwXwlBbOLRMLDFUsvTWQEkMk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jpWxkqBq15DNtCnkWfwg2+7fI1OJXQmdZQNdEeGAmP9HFY0LL0CM/EcgAcozcWIs9 dTvAgKvdcb0zlc7IuO33jLotBritGZS9LKzlZmrGi5G86uSBFC4E56ZYIWn0X3BOR5 gwPLtzjMNXsCJatA9KGQDU9torOcqH8G+mbukknE= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 63/88] ppc/psi: cleanup definitions Date: Tue, 17 Dec 2019 15:42:57 +1100 Message-Id: <20191217044322.351838-64-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Signed-off-by: Cédric Le Goater Message-Id: <20191205184454.10722-4-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv_psi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 7e725aaf2b..e6c266ac4a 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -608,9 +608,12 @@ static const TypeInfo pnv_psi_power8_info = { #define PSIHB9_IRQ_METHOD PPC_BIT(0) #define PSIHB9_IRQ_RESET PPC_BIT(1) #define PSIHB9_ESB_CI_BASE 0x60 -#define PSIHB9_ESB_CI_VALID 1 +#define PSIHB9_ESB_CI_64K PPC_BIT(1) +#define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47) +#define PSIHB9_ESB_CI_VALID PPC_BIT(63) #define PSIHB9_ESB_NOTIF_ADDR 0x68 -#define PSIHB9_ESB_NOTIF_VALID 1 +#define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60) +#define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63) #define PSIHB9_IVT_OFFSET 0x70 #define PSIHB9_IVT_OFF_SHIFT 32 From patchwork Tue Dec 17 04:42:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB48F138C for ; Tue, 17 Dec 2019 05:30:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C12792072B for ; Tue, 17 Dec 2019 05:30:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="VRnXcZ6e" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C12792072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5RX-00005n-Pz for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:30:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35127) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jm-0002AD-CR for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ji-0007X5-9s for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:34 -0500 Received: from ozlabs.org ([203.11.71.1]:48103) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jg-000727-Fn; Mon, 16 Dec 2019 23:45:30 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWd4y1gz9sTG; Tue, 17 Dec 2019 15:43:40 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557821; bh=tUWiTimI4vG2ukDtApEV0gwVGlWRs2/TqcyikECZ2zc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VRnXcZ6exeFF/z3VWfvFvpnWGqEbs2cCvPyujP0s2xqLsatjYvQ0oSMmtbYU4f3AR EQLHMg4EIVk8Rhd1ve6wAeud905xKDX8huN8LtHsK+FjXdwM+TAUOfd4y7JFJVRdbV Cmc/KC7Chij604l1KZ23XY8iH7Gy9Zu2Pg6pAxPw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10 Date: Tue, 17 Dec 2019 15:42:58 +1100 Message-Id: <20191217044322.351838-65-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The POWER10 PSIHB controller is very similar to the one on POWER9. We should probably introduce a common PnvPsiXive object. The ESB page size should be changed to 64k when P10 support is ready. Signed-off-by: Cédric Le Goater Message-Id: <20191205184454.10722-5-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 27 ++++++++++++++++++++------- hw/ppc/pnv_psi.c | 25 ++++++++++++++++++++++++- include/hw/ppc/pnv.h | 9 +++++++++ include/hw/ppc/pnv_psi.h | 2 ++ include/hw/ppc/pnv_xscom.h | 3 +++ 5 files changed, 58 insertions(+), 8 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d99cd72840..09263ab747 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -647,9 +647,9 @@ static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) { - /* - * No interrupt controller yet - */; + Pnv10Chip *chip10 = PNV10_CHIP(chip); + + pnv_psi_pic_print_info(&chip10->psi, mon); } static void pnv_init(MachineState *machine) @@ -1311,16 +1311,17 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) static void pnv_chip_power10_instance_init(Object *obj) { - /* - * No controllers yet - */ - ; + Pnv10Chip *chip10 = PNV10_CHIP(obj); + + object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), + TYPE_PNV10_PSI, &error_abort, NULL); } static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) { PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); PnvChip *chip = PNV_CHIP(dev); + Pnv10Chip *chip10 = PNV10_CHIP(dev); Error *local_err = NULL; /* XSCOM bridge is first */ @@ -1336,6 +1337,18 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) error_propagate(errp, local_err); return; } + + /* Processor Service Interface (PSI) Host Bridge */ + object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), + "bar", &error_fatal); + object_property_set_bool(OBJECT(&chip10->psi), true, "realized", + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, + &PNV_PSI(&chip10->psi)->xscom_regs); } static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index e6c266ac4a..572924388b 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -538,6 +538,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x"; static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x"; +static const char compat_p10[] = "ibm,power10-psihb-x\0ibm,psihb-x"; static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) { @@ -557,7 +558,10 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); - if (ppc->chip_type == PNV_CHIP_POWER9) { + if (ppc->chip_type == PNV_CHIP_POWER10) { + _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, + sizeof(compat_p10))); + } else if (ppc->chip_type == PNV_CHIP_POWER9) { _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, sizeof(compat_p9))); } else { @@ -909,6 +913,24 @@ static const TypeInfo pnv_psi_power9_info = { }, }; +static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PnvPsiClass *ppc = PNV_PSI_CLASS(klass); + + dc->desc = "PowerNV PSI Controller POWER10"; + + ppc->chip_type = PNV_CHIP_POWER10; + ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; + ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; +} + +static const TypeInfo pnv_psi_power10_info = { + .name = TYPE_PNV10_PSI, + .parent = TYPE_PNV9_PSI, + .class_init = pnv_psi_power10_class_init, +}; + static void pnv_psi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -938,6 +960,7 @@ static void pnv_psi_register_types(void) type_register_static(&pnv_psi_info); type_register_static(&pnv_psi_power8_info); type_register_static(&pnv_psi_power9_info); + type_register_static(&pnv_psi_power10_info); } type_init(pnv_psi_register_types); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index bfa61edfba..47b7370b27 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -112,6 +112,9 @@ typedef struct Pnv9Chip { typedef struct Pnv10Chip { /*< private >*/ PnvChip parent_obj; + + /*< public >*/ + Pnv9Psi psi; } Pnv10Chip; typedef struct PnvChipClass { @@ -326,4 +329,10 @@ IPMIBmc *pnv_bmc_create(void); #define PNV10_XSCOM_SIZE 0x0000000400000000ull #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) +#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull +#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) + +#define PNV10_PSIHB_SIZE 0x0000000000100000ull +#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index e82df9709f..a044aab304 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -69,6 +69,8 @@ typedef struct Pnv9Psi { XiveSource source; } Pnv9Psi; +#define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10" + #define PNV_PSI_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI) #define PNV_PSI_GET_CLASS(obj) \ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 790eb3d8f3..a40d2a2a2a 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -106,6 +106,9 @@ typedef struct PnvXScomInterfaceClass { ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) #define PNV10_XSCOM_EC_SIZE 0x100000 +#define PNV10_XSCOM_PSIHB_BASE 0x3011D00 +#define PNV10_XSCOM_PSIHB_SIZE 0x100 + extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); From patchwork Tue Dec 17 04:42:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296679 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 260A06C1 for ; Tue, 17 Dec 2019 05:25:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F049F2072B for ; Tue, 17 Dec 2019 05:25:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="LCAA6eFI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F049F2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Md-0000UZ-H2 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:25:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35311) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jw-0002Is-6r for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ju-0007sk-Cm for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:43 -0500 Received: from ozlabs.org ([203.11.71.1]:59281) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ju-0007LS-0o; Mon, 16 Dec 2019 23:45:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWf1RW7z9sTd; Tue, 17 Dec 2019 15:43:40 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557822; bh=64a+yA1L+5XUCbPgZCq1xv2EeBj3e0aHAOWcvpUe778=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LCAA6eFIi8hB8GS355V+2svtMaYyJG9kPrvMuKOTop+jPUpnW+j3GSGVf5DcyUUNR 6uPbpqORMxUzDwZ96TwixpjTtLAULN+bGadsbXz8yM6umLOCd/ZkLEbZyaLpajwrfJ G0m0dAmfgrDHiZ3qMGjKgt8sQUhOAqUIOXC6ZHuk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 65/88] ppc/pnv: add a LPC Controller model for POWER10 Date: Tue, 17 Dec 2019 15:42:59 +1100 Message-Id: <20191217044322.351838-66-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Same a POWER9, only the MMIO window changes. Signed-off-by: Cédric Le Goater Message-Id: <20191205184454.10722-6-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 25 ++++++++++++++++++++++--- hw/ppc/pnv_lpc.c | 30 ++++++++++++++++++++++-------- include/hw/ppc/pnv.h | 4 ++++ include/hw/ppc/pnv_lpc.h | 6 +++++- 4 files changed, 53 insertions(+), 12 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 09263ab747..67d0ad55b8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -314,7 +314,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } - pnv_dt_lpc(chip, fdt, 0); + pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); } static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) @@ -332,6 +332,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) if (chip->ram_size) { pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } + + pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -601,8 +603,8 @@ static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) { - error_setg(errp, "No ISA bus!"); - return NULL; + Pnv10Chip *chip10 = PNV10_CHIP(chip); + return pnv_lpc_isa_create(&chip10->lpc, false, errp); } static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) @@ -1315,6 +1317,8 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), TYPE_PNV10_PSI, &error_abort, NULL); + object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), + TYPE_PNV10_LPC, &error_abort, NULL); } static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) @@ -1349,6 +1353,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) } pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, &PNV_PSI(&chip10->psi)->xscom_regs); + + /* LPC */ + object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", + &error_abort); + object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), + &chip10->lpc.xscom_regs); + + chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", + (uint64_t) PNV10_LPCM_BASE(chip)); } static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index dd5374c838..18256d9ba3 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -122,26 +122,26 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) } /* POWER9 only */ -int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset) +int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, + uint64_t lpcm_size) { const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; char *name; int offset, lpcm_offset; - uint64_t lpcm_addr = PNV9_LPCM_BASE(chip); uint32_t opb_ranges[8] = { 0, cpu_to_be32(lpcm_addr >> 32), cpu_to_be32((uint32_t)lpcm_addr), - cpu_to_be32(PNV9_LPCM_SIZE / 2), - cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_size / 2), + cpu_to_be32(lpcm_size / 2), cpu_to_be32(lpcm_addr >> 32), - cpu_to_be32(PNV9_LPCM_SIZE / 2), - cpu_to_be32(PNV9_LPCM_SIZE / 2), + cpu_to_be32(lpcm_size / 2), + cpu_to_be32(lpcm_size / 2), }; uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32), cpu_to_be32((uint32_t)lpcm_addr), - cpu_to_be32(PNV9_LPCM_SIZE >> 32), - cpu_to_be32((uint32_t)PNV9_LPCM_SIZE), + cpu_to_be32(lpcm_size >> 32), + cpu_to_be32((uint32_t)lpcm_size), }; uint32_t lpc_ranges[12] = { 0, 0, cpu_to_be32(LPC_MEM_OPB_ADDR), @@ -691,6 +691,19 @@ static const TypeInfo pnv_lpc_power9_info = { .class_init = pnv_lpc_power9_class_init, }; +static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "PowerNV LPC Controller POWER10"; +} + +static const TypeInfo pnv_lpc_power10_info = { + .name = TYPE_PNV10_LPC, + .parent = TYPE_PNV9_LPC, + .class_init = pnv_lpc_power10_class_init, +}; + static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc = PNV_LPC(dev); @@ -764,6 +777,7 @@ static void pnv_lpc_register_types(void) type_register_static(&pnv_lpc_info); type_register_static(&pnv_lpc_power8_info); type_register_static(&pnv_lpc_power9_info); + type_register_static(&pnv_lpc_power10_info); } type_init(pnv_lpc_register_types) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 47b7370b27..56d1161515 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -115,6 +115,7 @@ typedef struct Pnv10Chip { /*< public >*/ Pnv9Psi psi; + PnvLpcController lpc; } Pnv10Chip; typedef struct PnvChipClass { @@ -329,6 +330,9 @@ IPMIBmc *pnv_bmc_create(void); #define PNV10_XSCOM_SIZE 0x0000000400000000ull #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) +#define PNV10_LPCM_SIZE 0x0000000100000000ull +#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) + #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index f659410716..c1ec85d5e2 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -31,6 +31,9 @@ #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9" #define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC) +#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10" +#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LPC) + typedef struct PnvLpcController { DeviceState parent; @@ -97,6 +100,7 @@ typedef struct PnvLpcClass { struct PnvChip; ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp); -int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset); +int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset, + uint64_t lpcm_addr, uint64_t lpcm_size); #endif /* PPC_PNV_LPC_H */ From patchwork Tue Dec 17 04:43:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296705 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FEAE138C for ; Tue, 17 Dec 2019 05:35:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65A15207FF for ; Tue, 17 Dec 2019 05:35:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Noa+Efdl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65A15207FF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Vk-0005e7-9a for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:35:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35645) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kJ-0002ZL-Nd for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kH-0008JC-Vr for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:07 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:33581 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kH-0007to-LV; Mon, 16 Dec 2019 23:46:05 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWh4ZdJz9sTV; Tue, 17 Dec 2019 15:43:40 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557824; bh=YlK/tUICTVr5Vv0darORvjbxvkstbvsYCLK3WqmknOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Noa+EfdlmFTvtU4hmt4Qyj256y8knXZXR7U60/ACQ3qAQd0YTIIUDxDVdsDBFymPI K89QRUzLrQ5UCdnX9rXgZk+aZGReWfhWOATAsWHK9RtrAxDj8z9g8HohomswkN3K1k DcDt3uUzRelbVV+9Ts3mnHI3QgCTI+nz71J22zJY= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 66/88] target/ppc: Implement the VTB for HV access Date: Tue, 17 Dec 2019 15:43:00 +1100 Message-Id: <20191217044322.351838-67-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, Suraj Jitindar Singh , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Suraj Jitindar Singh The virtual timebase register (VTB) is a 64-bit register which increments at the same rate as the timebase register, present on POWER8 and later processors. The register is able to be read/written by the hypervisor and read by the supervisor. All other accesses are illegal. Currently the VTB is just an alias for the timebase (TB) register. Implement the VTB so that is can be read/written independent of the TB. Make use of the existing method for accessing timebase facilities where by the compensation is stored and used to compute the value on reads/is updated on writes. Signed-off-by: Suraj Jitindar Singh [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater Message-Id: <20191128134700.16091-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 16 ++++++++++++++++ include/hw/ppc/ppc.h | 1 + linux-user/ppc/cpu_loop.c | 5 +++++ target/ppc/cpu.h | 2 ++ target/ppc/helper.h | 2 ++ target/ppc/timebase_helper.c | 10 ++++++++++ target/ppc/translate_init.inc.c | 19 +++++++++++++++---- 7 files changed, 51 insertions(+), 4 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 45834f98d1..d8c402811f 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -682,6 +682,22 @@ void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) &tb_env->atb_offset, ((uint64_t)value << 32) | tb); } +uint64_t cpu_ppc_load_vtb(CPUPPCState *env) +{ + ppc_tb_t *tb_env = env->tb_env; + + return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->vtb_offset); +} + +void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) +{ + ppc_tb_t *tb_env = env->tb_env; + + cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + &tb_env->vtb_offset, value); +} + static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 89e1dd065a..d7a95608f6 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -24,6 +24,7 @@ struct ppc_tb_t { /* Time base management */ int64_t tb_offset; /* Compensation */ int64_t atb_offset; /* Compensation */ + int64_t vtb_offset; uint32_t tb_freq; /* TB frequency */ /* Decrementer management */ uint64_t decr_next; /* Tick for next decr interrupt */ diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index d5704def29..5b27f8603e 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -47,6 +47,11 @@ uint32_t cpu_ppc_load_atbu(CPUPPCState *env) return cpu_ppc_get_tb(env) >> 32; } +uint64_t cpu_ppc_load_vtb(CPUPPCState *env) +{ + return cpu_ppc_get_tb(env); +} + uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) __attribute__ (( alias ("cpu_ppc_load_tbu") )); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fbec1b0cd5..eb7d2c7637 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1303,6 +1303,8 @@ uint64_t cpu_ppc_load_atbl(CPUPPCState *env); uint32_t cpu_ppc_load_atbu(CPUPPCState *env); void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value); void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value); +uint64_t cpu_ppc_load_vtb(CPUPPCState *env); +void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value); bool ppc_decr_clear_on_delivery(CPUPPCState *env); target_ulong cpu_ppc_load_decr(CPUPPCState *env); void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f843814b8a..a5f53bb421 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -649,6 +649,7 @@ DEF_HELPER_FLAGS_1(load_tbl, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_1(load_tbu, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_1(load_atbl, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_1(load_atbu, TCG_CALL_NO_RWG, tl, env) +DEF_HELPER_FLAGS_1(load_vtb, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_1(load_601_rtcl, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env) #if !defined(CONFIG_USER_ONLY) @@ -669,6 +670,7 @@ DEF_HELPER_FLAGS_1(load_decr, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_decr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_2(store_hid0_601, void, env, tl) DEF_HELPER_3(store_403_pbr, void, env, i32, tl) DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env) diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 73363e08ae..8c3c2fe67c 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -45,6 +45,11 @@ target_ulong helper_load_atbu(CPUPPCState *env) return cpu_ppc_load_atbu(env); } +target_ulong helper_load_vtb(CPUPPCState *env) +{ + return cpu_ppc_load_vtb(env); +} + #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) target_ulong helper_load_purr(CPUPPCState *env) { @@ -113,6 +118,11 @@ void helper_store_hdecr(CPUPPCState *env, target_ulong val) cpu_ppc_store_hdecr(env, val); } +void helper_store_vtb(CPUPPCState *env, target_ulong val) +{ + cpu_ppc_store_vtb(env, val); +} + target_ulong helper_load_40x_pit(CPUPPCState *env) { return load_40x_pit(env); diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 7364d36b07..226aecf8f4 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -312,6 +312,16 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) } } +static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); +} + +static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); +} + #endif #endif @@ -8174,10 +8184,11 @@ static void gen_spr_power8_ebb(CPUPPCState *env) /* Virtual Time Base */ static void gen_spr_vtb(CPUPPCState *env) { - spr_register_kvm(env, SPR_VTB, "VTB", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_tbl, SPR_NOACCESS, - KVM_REG_PPC_VTB, 0x00000000); + spr_register_kvm_hv(env, SPR_VTB, "VTB", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_vtb, SPR_NOACCESS, + &spr_read_vtb, &spr_write_vtb, + KVM_REG_PPC_VTB, 0x00000000); } static void gen_spr_power8_fscr(CPUPPCState *env) From patchwork Tue Dec 17 04:43:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296651 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C2C26C1 for ; Tue, 17 Dec 2019 05:18:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2266B2072D for ; Tue, 17 Dec 2019 05:18:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="dmLMQ+LC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2266B2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Fo-0006zq-3D for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:18:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35742) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kR-0002lY-Ay for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kP-0008V0-N2 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:15 -0500 Received: from ozlabs.org ([203.11.71.1]:36349) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kP-0007zB-BG; Mon, 16 Dec 2019 23:46:13 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWj0nyKz9sTg; Tue, 17 Dec 2019 15:43:40 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557825; bh=A4wOr8sJUqg+WOlinsZsHjPg3iy96yxVrwBRRM8dIeM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dmLMQ+LCL9vTuZv7ayYr2uyG1d+tBbjgdcPOD9EOKKjzGK+D3MwaXJX8jcZfq7xzE J0ustDbUMeB6+d9hSa2eDQmfEyBPa629OsKgKuI5uMX/RGiRDVvZ9fh1sNSXrb6zOH 7J1pdEznkP+nhUhLAQrYHCckw0lE8IKKE68dUPSM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 67/88] target/ppc: Work [S]PURR implementation and add HV support Date: Tue, 17 Dec 2019 15:43:01 +1100 Message-Id: <20191217044322.351838-68-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, Suraj Jitindar Singh , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Suraj Jitindar Singh The Processor Utilisation of Resources Register (PURR) and Scaled Processor Utilisation of Resources Register (SPURR) provide an estimate of the resources used by the thread, present on POWER7 and later processors. Currently the [S]PURR registers simply count at the rate of the timebase. Preserve this behaviour but rework the implementation to store an offset like the timebase rather than doing the calculation manually. Also allow hypervisor write access to the register along with the currently available read access. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater Message-Id: <20191128134700.16091-3-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 17 +++++++---------- include/hw/ppc/ppc.h | 3 +-- target/ppc/cpu.h | 1 + target/ppc/helper.h | 1 + target/ppc/timebase_helper.c | 5 +++++ target/ppc/translate_init.inc.c | 23 +++++++++++++++-------- 6 files changed, 30 insertions(+), 20 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index d8c402811f..2856d69495 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -809,12 +809,9 @@ target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) uint64_t cpu_ppc_load_purr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; - uint64_t diff; - diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start; - - return tb_env->purr_load + - muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND); + return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->purr_offset); } /* When decrementer expires, @@ -973,12 +970,12 @@ static void cpu_ppc_hdecr_cb(void *opaque) cpu_ppc_hdecr_excp(cpu); } -static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) +void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) { - ppc_tb_t *tb_env = cpu->env.tb_env; + ppc_tb_t *tb_env = env->tb_env; - tb_env->purr_load = value; - tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + &tb_env->purr_offset, value); } static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) @@ -995,7 +992,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) */ _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); - cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); + cpu_ppc_store_purr(env, 0x0000000000000000ULL); } static void timebase_save(PPCTimebase *tb) diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index d7a95608f6..4ea5436095 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -33,8 +33,7 @@ struct ppc_tb_t { /* Hypervisor decrementer management */ uint64_t hdecr_next; /* Tick for next hdecr interrupt */ QEMUTimer *hdecr_timer; - uint64_t purr_load; - uint64_t purr_start; + int64_t purr_offset; void *opaque; uint32_t flags; }; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index eb7d2c7637..da44cc8809 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1311,6 +1311,7 @@ void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value); target_ulong cpu_ppc_load_hdecr(CPUPPCState *env); void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value); uint64_t cpu_ppc_load_purr(CPUPPCState *env); +void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value); uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env); uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env); #if !defined(CONFIG_USER_ONLY) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index a5f53bb421..356a14d8a6 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -655,6 +655,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env) #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env) +DEF_HELPER_FLAGS_2(store_purr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_2(store_ptcr, void, env, tl) #endif DEF_HELPER_2(store_sdr1, void, env, tl) diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 8c3c2fe67c..2395295b77 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -55,6 +55,11 @@ target_ulong helper_load_purr(CPUPPCState *env) { return (target_ulong)cpu_ppc_load_purr(env); } + +void helper_store_purr(CPUPPCState *env, target_ulong val) +{ + cpu_ppc_store_purr(env, val); +} #endif target_ulong helper_load_601_rtcl(CPUPPCState *env) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 226aecf8f4..c5e4d45569 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -287,6 +287,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); } +static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); +} + /* HDECR */ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { @@ -8013,14 +8018,16 @@ static void gen_spr_book3s_purr(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ - spr_register_kvm(env, SPR_PURR, "PURR", - &spr_read_purr, SPR_NOACCESS, - &spr_read_purr, SPR_NOACCESS, - KVM_REG_PPC_PURR, 0x00000000); - spr_register_kvm(env, SPR_SPURR, "SPURR", - &spr_read_purr, SPR_NOACCESS, - &spr_read_purr, SPR_NOACCESS, - KVM_REG_PPC_SPURR, 0x00000000); + spr_register_kvm_hv(env, SPR_PURR, "PURR", + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, &spr_write_purr, + KVM_REG_PPC_PURR, 0x00000000); + spr_register_kvm_hv(env, SPR_SPURR, "SPURR", + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, SPR_NOACCESS, + &spr_read_purr, &spr_write_purr, + KVM_REG_PPC_SPURR, 0x00000000); #endif } From patchwork Tue Dec 17 04:43:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B25F414E3 for ; Tue, 17 Dec 2019 05:41:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 881C220733 for ; Tue, 17 Dec 2019 05:41:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="pp3QAFPf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 881C220733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5c9-0006li-CE for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:41:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35424) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4k9-0002MD-G8 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4k6-00082c-1m for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:55 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:52743 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4k2-0007V9-3s; Mon, 16 Dec 2019 23:45:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWg2mZKz9sTS; Tue, 17 Dec 2019 15:43:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557823; bh=5/a5TMrvK4EzeFh6JE4d9uQG/td8uvROAlRqOMDCQng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pp3QAFPf4XCm3gCh3bHQR27GX9dZJPZt/k2mZ5ohGxI6JSZYnkOxB7SyrTZQSddI8 aJm4p2oXplpdp4uNxYXWvxSBOe27bCJkqdtdxqqyKa5pfTkLdWSrdhn8/c8mZYPX8y GXri7XvK9GU4oQtxelFbqcn8KCcY+2Tc0hPgd6fk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 68/88] target/ppc: Add SPR ASDR Date: Tue, 17 Dec 2019 15:43:02 +1100 Message-Id: <20191217044322.351838-69-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, Suraj Jitindar Singh , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Suraj Jitindar Singh The Access Segment Descriptor Register (ASDR) provides information about the storage element when taking a hypervisor storage interrupt. When performing nested radix address translation, this is normally the guest real address. This register is present on POWER9 processors and later. Implement the ADSR, note read and write access is limited to the hypervisor. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater Message-Id: <20191128134700.16091-4-clg@kaod.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 1 + target/ppc/translate_init.inc.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index da44cc8809..e99850c3ae 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1778,6 +1778,7 @@ typedef PowerPCCPU ArchCPU; #define SPR_MPC_MD_DBRAM1 (0x32A) #define SPR_RCPU_L2U_RA3 (0x32B) #define SPR_TAR (0x32F) +#define SPR_ASDR (0x330) #define SPR_IC (0x350) #define SPR_VTB (0x351) #define SPR_MMCRC (0x353) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index c5e4d45569..c850a9d065 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8295,6 +8295,12 @@ static void gen_spr_power9_mmu(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_ptcr, KVM_REG_PPC_PTCR, 0x00000000); + /* Address Segment Descriptor Register */ + spr_register_hv(env, SPR_ASDR, "ASDR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x0000000000000000); #endif } From patchwork Tue Dec 17 04:43:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B0A9138C for ; Tue, 17 Dec 2019 05:13:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 317272072D for ; Tue, 17 Dec 2019 05:13:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="AtcrKPeb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 317272072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5AM-00070m-Oj for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:13:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35129) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jm-0002AG-CH for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jk-0007Yo-2p for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:34 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:44639 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jj-00076W-9d; Mon, 16 Dec 2019 23:45:32 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWd6btmz9sTX; Tue, 17 Dec 2019 15:43:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557821; bh=H93vcA7eu+QF3H1KRJ06dJ+D+jFIDrmans7KndV5UnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AtcrKPebrh8+S6l288JGCKjlftDliHrPYlQTLU9nxwElZBbjM3rGZZYUeqbuQvuek V2wtZi1U2gIjS194XX6hKrDoOD39LI/75b2YomjzJ5SVJhXE4J38OFMYUDZgzQYww/ RdLFg6y4nAWrik9CUHBdp0PRHwCBe4AOrdgvGHIE= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 69/88] target/ppc: Add SPR TBU40 Date: Tue, 17 Dec 2019 15:43:03 +1100 Message-Id: <20191217044322.351838-70-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, Suraj Jitindar Singh , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Suraj Jitindar Singh The spr TBU40 is used to set the upper 40 bits of the timebase register, present on POWER5+ and later processors. This register can only be written by the hypervisor, and cannot be read. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater Message-Id: <20191128134700.16091-5-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 13 +++++++++++++ target/ppc/cpu.h | 1 + target/ppc/helper.h | 1 + target/ppc/timebase_helper.c | 5 +++++ target/ppc/translate_init.inc.c | 19 +++++++++++++++++++ 5 files changed, 39 insertions(+) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 2856d69495..4c5fa29399 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -698,6 +698,19 @@ void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) &tb_env->vtb_offset, value); } +void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) +{ + ppc_tb_t *tb_env = env->tb_env; + uint64_t tb; + + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->tb_offset); + tb &= 0xFFFFFFUL; + tb |= (value & ~0xFFFFFFUL); + cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + &tb_env->tb_offset, tb); +} + static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e99850c3ae..103bfe9dc2 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1310,6 +1310,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env); void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value); target_ulong cpu_ppc_load_hdecr(CPUPPCState *env); void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value); +void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value); uint64_t cpu_ppc_load_purr(CPUPPCState *env); void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value); uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 356a14d8a6..cd0dfe383a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -672,6 +672,7 @@ DEF_HELPER_FLAGS_2(store_decr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env) DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_2(store_hid0_601, void, env, tl) DEF_HELPER_3(store_403_pbr, void, env, i32, tl) DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env) diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 2395295b77..703bd9ed18 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -128,6 +128,11 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val) cpu_ppc_store_vtb(env, val); } +void helper_store_tbu40(CPUPPCState *env, target_ulong val) +{ + cpu_ppc_store_tbu40(env, val); +} + target_ulong helper_load_40x_pit(CPUPPCState *env) { return load_40x_pit(env); diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index c850a9d065..d33d65dff7 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -327,6 +327,11 @@ static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); } +static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); +} + #endif #endif @@ -7853,6 +7858,16 @@ static void gen_spr_power5p_ear(CPUPPCState *env) 0x00000000); } +static void gen_spr_power5p_tb(CPUPPCState *env) +{ + /* TBU40 (High 40 bits of the Timebase register */ + spr_register_hv(env, SPR_TBU40, "TBU40", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbu40, + 0x00000000); +} + #if !defined(CONFIG_USER_ONLY) static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) { @@ -8404,6 +8419,7 @@ static void init_proc_power5plus(CPUPPCState *env) gen_spr_power5p_common(env); gen_spr_power5p_lpar(env); gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); /* env variables */ env->dcache_line_size = 128; @@ -8516,6 +8532,7 @@ static void init_proc_POWER7(CPUPPCState *env) gen_spr_power5p_common(env); gen_spr_power5p_lpar(env); gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); gen_spr_power6_common(env); gen_spr_power6_dbg(env); gen_spr_power7_book4(env); @@ -8657,6 +8674,7 @@ static void init_proc_POWER8(CPUPPCState *env) gen_spr_power5p_common(env); gen_spr_power5p_lpar(env); gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); gen_spr_power6_common(env); gen_spr_power6_dbg(env); gen_spr_power8_tce_address_control(env); @@ -8847,6 +8865,7 @@ static void init_proc_POWER9(CPUPPCState *env) gen_spr_power5p_common(env); gen_spr_power5p_lpar(env); gen_spr_power5p_ear(env); + gen_spr_power5p_tb(env); gen_spr_power6_common(env); gen_spr_power6_dbg(env); gen_spr_power8_tce_address_control(env); From patchwork Tue Dec 17 04:43:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296641 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB8CE6C1 for ; Tue, 17 Dec 2019 05:15:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 755F22072D for ; Tue, 17 Dec 2019 05:15:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="HMxjXq9v" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 755F22072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Ce-0002Ac-Uv for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:15:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35426) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4k9-0002ME-Gf for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4k6-00082N-0S for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:55 -0500 Received: from ozlabs.org ([203.11.71.1]:39273) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4k4-0007Xd-Ek; Mon, 16 Dec 2019 23:45:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWh0trzz9sTW; Tue, 17 Dec 2019 15:43:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557824; bh=1amkbfv/C6Cb1XKFIBX0BD98zbGySF/FrizpzYukWV0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HMxjXq9vQfEbE1NXt7Z7vgA+k+bbVHG391rl7/UOIPwYO4f2b3R6YZb1YakK+oP+/ bGHE+hJFlbn+UOHlANiU5XBoNcPEekU/p3SDO9LBKN8Spa1nhHechMiVYs0SvWSuGc rqzjcLxA9eYBZM2jR97R6Eydxzd6pT9ewcS2DqaY= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes Date: Tue, 17 Dec 2019 15:43:04 +1100 Message-Id: <20191217044322.351838-71-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Some PnvXScomInterface objects lie a bit deeper (PnvPBCQState) than the first layer, so we need to loop on the whole object hierarchy to catch them. Signed-off-by: Cédric Le Goater Message-Id: <20191210135845.19773-2-clg@kaod.org> Reviewed-by: Greg Kurz [dwg: Corrected error in comment] Signed-off-by: David Gibson --- hw/ppc/pnv_xscom.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index b3d3b6e350..760571037b 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -358,7 +358,12 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) args.fdt = fdt; args.xscom_offset = xscom_offset; - object_child_foreach(OBJECT(chip), xscom_dt_child, &args); + /* + * Loop on the whole object hierarchy to catch all + * PnvXScomInterface objects which can lie a bit deeper than the + * first layer. + */ + object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args); return 0; } From patchwork Tue Dec 17 04:43:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296707 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2717F138C for ; Tue, 17 Dec 2019 05:35:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F08C62082E for ; Tue, 17 Dec 2019 05:35:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="aGD8BR9w" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F08C62082E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5WO-0006l4-TL for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:35:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35675) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kL-0002c8-I9 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kK-0008MI-CK for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:09 -0500 Received: from ozlabs.org ([203.11.71.1]:49031) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kK-0007xM-0h; Mon, 16 Dec 2019 23:46:08 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWh66Wmz9sTZ; Tue, 17 Dec 2019 15:43:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557824; bh=eOGD8QwMNRe7LTWiMEshk2Ag9kxPUIVvcEXGfVAnae0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aGD8BR9wclJpDi2Fbf8BTwDV3UhIeg0OVXD3zybczDCzs0nCp3YIRUfhEE8hVIU7p v+c1WgeWWvcZtyOiGhOM1MC9kD2N+8mkgQjMjskVjbFcae69f33isjZuLPrWTsgiDS xoEe2e0gzWMDoN916vheJxsTcusWNeOYq9oN7OZ8= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 71/88] ppc/pnv: populate the DT with realized XSCOM devices Date: Tue, 17 Dec 2019 15:43:05 +1100 Message-Id: <20191217044322.351838-72-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Some devices could be initialized in the instance_init handler but not realized for configuration reasons. Nodes should not be added in the DT for such devices. Signed-off-by: Cédric Le Goater Message-Id: <20191210135845.19773-3-clg@kaod.org> Reviewed-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/ppc/pnv_xscom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 760571037b..fd48d4ee37 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -304,7 +304,10 @@ static int xscom_dt_child(Object *child, void *opaque) PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); - if (xc->dt_xscom) { + /* + * Only "realized" devices should be configured in the DT + */ + if (xc->dt_xscom && DEVICE(child)->realized) { _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); } } From patchwork Tue Dec 17 04:43:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296735 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1DBCC921 for ; Tue, 17 Dec 2019 05:46:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E745420733 for ; Tue, 17 Dec 2019 05:46:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="SRX/8pUO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E745420733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5ga-0003zF-G4 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:46:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35833) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kW-0002sw-Ea for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kV-0000DU-Dz for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:20 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:40095 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kV-00083m-3f; Mon, 16 Dec 2019 23:46:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWk26l8z9sTk; Tue, 17 Dec 2019 15:43:41 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557826; bh=T4BYW9/N11n3L6izTyClhxscVQnqQ73DyXta2qSf7iY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SRX/8pUO8dhc96mjTvJRbSOEfbotiskh/4+uFbXm8FllXwaPvEGCduRyECibNB4Cb 9blp7ibJ1uOe1r1jf342Fn5o8sJiwzqm5nZAKxx4UlNjx4pF4c/0V3Mq5sdJYzFfcE HG1bawy967gkBL8+QQoHzwEfg/jz0UN0vySF6X+Y= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 72/88] ppc/pnv: Make PnvXScomInterface an incomplete type Date: Tue, 17 Dec 2019 15:43:06 +1100 Message-Id: <20191217044322.351838-73-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz PnvXScomInterface is an interface instance. It should never be dereferenced. Drop the dummy type definition for extra safety, which is the common practice with QOM interfaces. While here also convert the bogus OBJECT_CHECK() to INTERFACE_CHECK(). Signed-off-by: Greg Kurz Message-Id: <157608025541.186670.1577861507610404326.stgit@bahia.lan> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- include/hw/ppc/pnv_xscom.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index a40d2a2a2a..5ad2735d1a 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -22,13 +22,11 @@ #include "qom/object.h" -typedef struct PnvXScomInterface { - Object parent; -} PnvXScomInterface; +typedef struct PnvXScomInterface PnvXScomInterface; #define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface" #define PNV_XSCOM_INTERFACE(obj) \ - OBJECT_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE) + INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE) #define PNV_XSCOM_INTERFACE_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvXScomInterfaceClass, (klass), \ TYPE_PNV_XSCOM_INTERFACE) From patchwork Tue Dec 17 04:43:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A27D514E3 for ; Tue, 17 Dec 2019 05:39:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67DA620733 for ; Tue, 17 Dec 2019 05:39:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="o5tc0U+3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 67DA620733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5a2-0003yt-9Q for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:39:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36246) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ks-0003Tx-QN for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kq-0001DI-Jt for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:42 -0500 Received: from ozlabs.org ([203.11.71.1]:46087) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kp-0000AN-W2; Mon, 16 Dec 2019 23:46:40 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl4f8hz9sTm; Tue, 17 Dec 2019 15:43:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=h1zrQwJriYh526j+AxdEjT9IrOCRMk51rehKSepN5tg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o5tc0U+33byeYzLnzle9Yfbn6Qn42fd8PNtZFTdhEq+neCNXLMXDSNpUHPsvfzsCT glaFOzD/LeOe//9U6qCD++Q0EExAQeigz47BBnIy3/kZsIu92TliRnvdKaAYDV5IXb cQt5HRbYzCrukWUBd5nYScgIYowISd8qeaEf8njk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 73/88] ppc/pnv: Introduce PBA registers Date: Tue, 17 Dec 2019 15:43:07 +1100 Message-Id: <20191217044322.351838-74-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The PBA bridge unit (Power Bus Access) connects the OCC (On Chip Controller) to the Power bus and System Memory. The PBA is used to gather sensor data, for power management, for sleep states, for initial boot, among other things. The PBA logic provides a set of four registers PowerBus Access Base Address Registers (PBABAR0..3) which map the OCC address space to the PowerBus space. These registers are setup by the initial FW and define the PowerBus Range of system memory that can be accessed by PBA. The current modeling of the PBABAR registers is done under the common XSCOM handlers. We introduce a specific XSCOM regions for these registers and fix : - BAR sizes and BAR masks - The mapping of the OCC common area. It is common to all chips and should be mapped once. We will address per-OCC area in the next change. - OCC common area is in BAR 3 on P8 Inspired by previous work of Balamuruhan S Signed-off-by: Cédric Le Goater Message-Id: <20191211082912.2625-2-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 12 +++- hw/ppc/pnv_homer.c | 109 +++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_xscom.c | 32 ----------- include/hw/ppc/pnv.h | 16 ++---- include/hw/ppc/pnv_homer.h | 3 + include/hw/ppc/pnv_xscom.h | 6 ++ 6 files changed, 134 insertions(+), 44 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 67d0ad55b8..af7317a86d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); /* OCC SRAM model */ - memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), + memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE, &chip8->occ.sram_regs); /* HOMER */ @@ -1077,6 +1077,10 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) error_propagate(errp, local_err); return; } + /* Homer Xscom region */ + pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); + + /* Homer mmio region */ memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), &chip8->homer.regs); } @@ -1274,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); /* OCC SRAM model */ - memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), + memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE, &chip9->occ.sram_regs); /* HOMER */ @@ -1286,6 +1290,10 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) error_propagate(errp, local_err); return; } + /* Homer Xscom region */ + pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); + + /* Homer mmio region */ memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), &chip9->homer.regs); } diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index 994a378108..a08b7914f7 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -17,6 +17,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qapi/error.h" #include "exec/hwaddr.h" #include "exec/memory.h" @@ -25,6 +26,7 @@ #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_xscom.h" static bool core_max_array(PnvHomer *homer, hwaddr addr) @@ -114,10 +116,67 @@ static const MemoryRegionOps pnv_power8_homer_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +/* P8 PBA BARs */ +#define PBA_BAR0 0x00 +#define PBA_BAR1 0x01 +#define PBA_BAR2 0x02 +#define PBA_BAR3 0x03 +#define PBA_BARMASK0 0x04 +#define PBA_BARMASK1 0x05 +#define PBA_BARMASK2 0x06 +#define PBA_BARMASK3 0x07 + +static uint64_t pnv_homer_power8_pba_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvHomer *homer = PNV_HOMER(opaque); + PnvChip *chip = homer->chip; + uint32_t reg = addr >> 3; + uint64_t val = 0; + + switch (reg) { + case PBA_BAR0: + val = PNV_HOMER_BASE(chip); + break; + case PBA_BARMASK0: /* P8 homer region mask */ + val = (PNV_HOMER_SIZE - 1) & 0x300000; + break; + case PBA_BAR3: /* P8 occ common area */ + val = PNV_OCC_COMMON_AREA_BASE; + break; + case PBA_BARMASK3: /* P8 occ common area mask */ + val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000; + break; + default: + qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } + return val; +} + +static void pnv_homer_power8_pba_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); +} + +static const MemoryRegionOps pnv_homer_power8_pba_ops = { + .read = pnv_homer_power8_pba_read, + .write = pnv_homer_power8_pba_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + static void pnv_homer_power8_class_init(ObjectClass *klass, void *data) { PnvHomerClass *homer = PNV_HOMER_CLASS(klass); + homer->pba_size = PNV_XSCOM_PBA_SIZE; + homer->pba_ops = &pnv_homer_power8_pba_ops; homer->homer_size = PNV_HOMER_SIZE; homer->homer_ops = &pnv_power8_homer_ops; homer->core_max_base = PNV8_CORE_MAX_BASE; @@ -210,10 +269,57 @@ static const MemoryRegionOps pnv_power9_homer_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +static uint64_t pnv_homer_power9_pba_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvHomer *homer = PNV_HOMER(opaque); + PnvChip *chip = homer->chip; + uint32_t reg = addr >> 3; + uint64_t val = 0; + + switch (reg) { + case PBA_BAR0: + val = PNV9_HOMER_BASE(chip); + break; + case PBA_BARMASK0: /* P9 homer region mask */ + val = (PNV9_HOMER_SIZE - 1) & 0x300000; + break; + case PBA_BAR2: /* P9 occ common area */ + val = PNV9_OCC_COMMON_AREA_BASE; + break; + case PBA_BARMASK2: /* P9 occ common area size */ + val = (PNV9_OCC_COMMON_AREA_SIZE - 1) & 0x700000; + break; + default: + qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } + return val; +} + +static void pnv_homer_power9_pba_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); +} + +static const MemoryRegionOps pnv_homer_power9_pba_ops = { + .read = pnv_homer_power9_pba_read, + .write = pnv_homer_power9_pba_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + static void pnv_homer_power9_class_init(ObjectClass *klass, void *data) { PnvHomerClass *homer = PNV_HOMER_CLASS(klass); + homer->pba_size = PNV9_XSCOM_PBA_SIZE; + homer->pba_ops = &pnv_homer_power9_pba_ops; homer->homer_size = PNV9_HOMER_SIZE; homer->homer_ops = &pnv_power9_homer_ops; homer->core_max_base = PNV9_CORE_MAX_BASE; @@ -233,6 +339,9 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp) assert(homer->chip); + pnv_xscom_region_init(&homer->pba_regs, OBJECT(dev), hmrc->pba_ops, + homer, "xscom-pba", hmrc->pba_size); + /* homer region */ memory_region_init_io(&homer->regs, OBJECT(dev), hmrc->homer_ops, homer, "homer-main-memory", diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index fd48d4ee37..df926003f2 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -36,16 +36,6 @@ #define PRD_P9_IPOLL_REG_MASK 0x000F0033 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034 -/* PBA BARs */ -#define P8_PBA_BAR0 0x2013f00 -#define P8_PBA_BAR2 0x2013f02 -#define P8_PBA_BARMASK0 0x2013f04 -#define P8_PBA_BARMASK2 0x2013f06 -#define P9_PBA_BAR0 0x5012b00 -#define P9_PBA_BAR2 0x5012b02 -#define P9_PBA_BARMASK0 0x5012b04 -#define P9_PBA_BARMASK2 0x5012b06 - static void xscom_complete(CPUState *cs, uint64_t hmer_bits) { /* @@ -90,26 +80,6 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) case 0x18002: /* ECID2 */ return 0; - case P9_PBA_BAR0: - return PNV9_HOMER_BASE(chip); - case P8_PBA_BAR0: - return PNV_HOMER_BASE(chip); - - case P9_PBA_BARMASK0: /* P9 homer region size */ - return PNV9_HOMER_SIZE; - case P8_PBA_BARMASK0: /* P8 homer region size */ - return PNV_HOMER_SIZE; - - case P9_PBA_BAR2: /* P9 occ common area */ - return PNV9_OCC_COMMON_AREA(chip); - case P8_PBA_BAR2: /* P8 occ common area */ - return PNV_OCC_COMMON_AREA(chip); - - case P9_PBA_BARMASK2: /* P9 occ common area size */ - return PNV9_OCC_COMMON_AREA_SIZE; - case P8_PBA_BARMASK2: /* P8 occ common area size */ - return PNV_OCC_COMMON_AREA_SIZE; - case 0x1010c00: /* PIBAM FIR */ case 0x1010c03: /* PIBAM FIR MASK */ @@ -130,9 +100,7 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) case 0x202000f: /* ADU stuff, receive status register*/ return 0; case 0x2013f01: /* PBA stuff */ - case 0x2013f03: /* PBA stuff */ case 0x2013f05: /* PBA stuff */ - case 0x2013f07: /* PBA stuff */ return 0; case 0x2013028: /* CAPP stuff */ case 0x201302a: /* CAPP stuff */ diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 56d1161515..301c7e62fa 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -244,12 +244,10 @@ IPMIBmc *pnv_bmc_create(void); #define PNV_XSCOM_BASE(chip) \ (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) -#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull -#define PNV_OCC_COMMON_AREA(chip) \ - (0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ - PNV_OCC_COMMON_AREA_SIZE)) +#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull +#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull -#define PNV_HOMER_SIZE 0x0000000000300000ull +#define PNV_HOMER_SIZE 0x0000000000400000ull #define PNV_HOMER_BASE(chip) \ (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE) @@ -312,12 +310,10 @@ IPMIBmc *pnv_bmc_create(void); #define PNV9_XSCOM_SIZE 0x0000000400000000ull #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) -#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull -#define PNV9_OCC_COMMON_AREA(chip) \ - (0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \ - PNV9_OCC_COMMON_AREA_SIZE)) +#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull +#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull -#define PNV9_HOMER_SIZE 0x0000000000300000ull +#define PNV9_HOMER_SIZE 0x0000000000400000ull #define PNV9_HOMER_BASE(chip) \ (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE) diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h index abaec43c2d..1e91c950f6 100644 --- a/include/hw/ppc/pnv_homer.h +++ b/include/hw/ppc/pnv_homer.h @@ -33,6 +33,7 @@ typedef struct PnvHomer { DeviceState parent; struct PnvChip *chip; + MemoryRegion pba_regs; MemoryRegion regs; } PnvHomer; @@ -44,6 +45,8 @@ typedef struct PnvHomer { typedef struct PnvHomerClass { DeviceClass parent_class; + int pba_size; + const MemoryRegionOps *pba_ops; int homer_size; const MemoryRegionOps *homer_ops; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 5ad2735d1a..09188d74b0 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -68,6 +68,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 +#define PNV_XSCOM_PBA_BASE 0x2013f00 +#define PNV_XSCOM_PBA_SIZE 0x40 + /* * Layout of the XSCOM PCB addresses (POWER 9) */ @@ -82,6 +85,9 @@ typedef struct PnvXScomInterfaceClass { #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE #define PNV9_XSCOM_OCC_SIZE 0x8000 +#define PNV9_XSCOM_PBA_BASE 0x5012b00 +#define PNV9_XSCOM_PBA_SIZE 0x40 + #define PNV9_XSCOM_PSIHB_BASE 0x5012900 #define PNV9_XSCOM_PSIHB_SIZE 0x100 From patchwork Tue Dec 17 04:43:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296713 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74ABD138C for ; Tue, 17 Dec 2019 05:37:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4AC1720733 for ; Tue, 17 Dec 2019 05:37:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="eBku1mLS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4AC1720733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Y4-0000me-71 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:37:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35798) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kV-0002r8-8u for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kT-00009j-SK for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:19 -0500 Received: from ozlabs.org ([203.11.71.1]:35459) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kT-00082r-GH; Mon, 16 Dec 2019 23:46:17 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWk0d4Fz9sRh; Tue, 17 Dec 2019 15:43:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557826; bh=IBWkRFwx/vIV/i59CX152JuOWpLUoM7587gE3heFvug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eBku1mLSpKH5yermo1D60LiF7wiQEVVVmIgVLnPeASJoB4x/p83aQoYywdzxRxnQE 43SeBw63KFz9T6QIaPxu+A8XrvV6rT/MpBvRzz9RQTjaDXQ0xhVXNHYtxZQVxRyjN7 Pph3OezXuH8ZzNGkzcZ5ooeINv/UTWHBHl/OHhdI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 74/88] ppc/pnv: Fix OCC common area region mapping Date: Tue, 17 Dec 2019 15:43:08 +1100 Message-Id: <20191217044322.351838-75-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The OCC common area is mapped at a unique address on the system and each OCC is assigned a segment to expose its sensor data : ------------------------------------------------------------------------- | Start (Offset from | End | Size |Description | | BAR2 base address) | | | | ------------------------------------------------------------------------- | 0x00580000 | 0x005A57FF |150kB |OCC 0 Sensor Data Block| | 0x005A5800 | 0x005CAFFF |150kB |OCC 1 Sensor Data Block| | : | : | : | : | | 0x00686800 | 0x006ABFFF |150kB |OCC 7 Sensor Data Block| | 0x006AC000 | 0x006FFFFF |336kB |Reserved | ------------------------------------------------------------------------- Maximum size is 1.5MB. We could define a "OCC common area" memory region at the machine level and sub regions for each OCC. But it adds some extra complexity to the models. Fix the current layout with a simpler model. Signed-off-by: Cédric Le Goater Message-Id: <20191211082912.2625-3-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/pnv.c | 4 ++-- hw/ppc/pnv_occ.c | 11 ++++------- include/hw/ppc/pnv.h | 4 ++++ include/hw/ppc/pnv_occ.h | 8 ++++++-- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index af7317a86d..0be0b6b411 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); /* OCC SRAM model */ - memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE, + memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), &chip8->occ.sram_regs); /* HOMER */ @@ -1278,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); /* OCC SRAM model */ - memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE, + memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), &chip9->occ.sram_regs); /* HOMER */ diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 765c0a6ce5..924fdabc9e 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -167,9 +167,7 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) PnvOCCClass *poc = PNV_OCC_CLASS(klass); poc->xscom_size = PNV_XSCOM_OCC_SIZE; - poc->sram_size = PNV_OCC_COMMON_AREA_SIZE; poc->xscom_ops = &pnv_occ_power8_xscom_ops; - poc->sram_ops = &pnv_occ_sram_ops; poc->psi_irq = PSIHB_IRQ_OCC; } @@ -240,9 +238,7 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) PnvOCCClass *poc = PNV_OCC_CLASS(klass); poc->xscom_size = PNV9_XSCOM_OCC_SIZE; - poc->sram_size = PNV9_OCC_COMMON_AREA_SIZE; poc->xscom_ops = &pnv_occ_power9_xscom_ops; - poc->sram_ops = &pnv_occ_sram_ops; poc->psi_irq = PSIHB9_IRQ_OCC; } @@ -266,9 +262,10 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, occ, "xscom-occ", poc->xscom_size); - /* XScom region for OCC SRAM registers */ - pnv_xscom_region_init(&occ->sram_regs, OBJECT(dev), poc->sram_ops, - occ, "occ-common-area", poc->sram_size); + /* OCC common area mmio region for OCC SRAM registers */ + memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops, + occ, "occ-common-area", + PNV_OCC_SENSOR_DATA_BLOCK_SIZE); } static Property pnv_occ_properties[] = { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 301c7e62fa..92f80b1cce 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -246,6 +246,8 @@ IPMIBmc *pnv_bmc_create(void); #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull +#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ + PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) #define PNV_HOMER_SIZE 0x0000000000400000ull #define PNV_HOMER_BASE(chip) \ @@ -312,6 +314,8 @@ IPMIBmc *pnv_bmc_create(void); #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull +#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ + PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip))) #define PNV9_HOMER_SIZE 0x0000000000400000ull #define PNV9_HOMER_BASE(chip) \ diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index 66b0989be6..f8d3061419 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -29,6 +29,9 @@ #define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9" #define PNV9_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC) +#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000 +#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800 + typedef struct PnvOCC { DeviceState xd; @@ -50,10 +53,11 @@ typedef struct PnvOCCClass { DeviceClass parent_class; int xscom_size; - int sram_size; const MemoryRegionOps *xscom_ops; - const MemoryRegionOps *sram_ops; int psi_irq; } PnvOCCClass; +#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \ + (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE) + #endif /* PPC_PNV_OCC_H */ From patchwork Tue Dec 17 04:43:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296693 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06B9B138C for ; Tue, 17 Dec 2019 05:30:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF54E2072B for ; Tue, 17 Dec 2019 05:30:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="O1s4FwXL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CF54E2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5R2-0007kq-4l for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:30:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35489) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kB-0002Nh-4r for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4k9-00084n-Pj for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:58 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:42157 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4k9-00082n-FN; Mon, 16 Dec 2019 23:45:57 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWj2Z0Gz9sTb; Tue, 17 Dec 2019 15:43:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557825; bh=APu7qN38GsprHR5Z7/xsS8JIgH+fS44UWNOeJDQ/e0Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O1s4FwXLefvnUWEySZT10FYWSO2LKNQzGFSw9RFY/LHY2/C5J8XxZpRqpAbf74OsX 23rAsRyWcgtShfDduKlNBxesWjuoNGSDksJtLO2ELwnmCPzSsJlMI51lOTypPuAnaV nTY003ZDvw9Vr2BkeFRR47jg82O3UVhToon3SssA= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 75/88] ppc: Drop useless extern annotation for functions Date: Tue, 17 Dec 2019 15:43:09 +1100 Message-Id: <20191217044322.351838-76-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Signed-off-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daudé Message-Id: <157623837421.360005.412120366652768311.stgit@bahia.lan> Signed-off-by: David Gibson --- include/hw/ppc/pnv_xscom.h | 22 +++++++++++----------- include/hw/ppc/spapr_vio.h | 6 +++--- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 09188d74b0..2bdb7ae84f 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -113,16 +113,16 @@ typedef struct PnvXScomInterfaceClass { #define PNV10_XSCOM_PSIHB_BASE 0x3011D00 #define PNV10_XSCOM_PSIHB_SIZE 0x100 -extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); -extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); - -extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, - MemoryRegion *mr); -extern void pnv_xscom_region_init(MemoryRegion *mr, - struct Object *owner, - const MemoryRegionOps *ops, - void *opaque, - const char *name, - uint64_t size); +void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); +int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); + +void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, + MemoryRegion *mr); +void pnv_xscom_region_init(MemoryRegion *mr, + struct Object *owner, + const MemoryRegionOps *ops, + void *opaque, + const char *name, + uint64_t size); #endif /* PPC_PNV_XSCOM_H */ diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 72762ed16b..ce6d9b0c66 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -80,10 +80,10 @@ struct SpaprVioBus { uint32_t next_reg; }; -extern SpaprVioBus *spapr_vio_bus_init(void); -extern SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg); +SpaprVioBus *spapr_vio_bus_init(void); +SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg); void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt); -extern gchar *spapr_vio_stdout_path(SpaprVioBus *bus); +gchar *spapr_vio_stdout_path(SpaprVioBus *bus); static inline void spapr_vio_irq_pulse(SpaprVioDevice *dev) { From patchwork Tue Dec 17 04:43:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296717 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5815138C for ; Tue, 17 Dec 2019 05:38:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B92520733 for ; Tue, 17 Dec 2019 05:38:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="LUl5y+Us" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9B92520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5ZA-0002cK-LF for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:38:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35865) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kX-0002uQ-EZ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kW-0000EV-4t for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:21 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:48539 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kV-0000AG-Qc; Mon, 16 Dec 2019 23:46:20 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl3KnJz9sRp; Tue, 17 Dec 2019 15:43:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=np9HcZx1KFwcdtSNbC/6aMTF85SHkdWiNq+VeNbUHxQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LUl5y+UsDMwQYqxEFOcV16ZS9koA9Tz8+pPDbG85i5MtOHrsBJnC+aISTYUzTNysj +/zOWpd4gW6DbNwyokYI6lUTLoXCoQrbWb9ImjDG9Xm/XVGrv8lJvHsq6vrImedbmR TA59GeT4QAePL0kt87Rdyt7z7sLGnitBROwY3gxw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat Date: Tue, 17 Dec 2019 15:43:10 +1100 Message-Id: <20191217044322.351838-77-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The Processor Service Interface (PSI) model has a chip_type class level attribute, which is used to generate the content of the "compatible" DT property according to the CPU type. Since the PSI model already has specialized classes for each supported CPU type, it seems cleaner to achieve this with QOM. Provide the content of the "compatible" property with a new class level attribute. Signed-off-by: Greg Kurz Message-Id: <157623837974.360005.14706607446188964477.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_psi.c | 25 +++++++++++-------------- include/hw/ppc/pnv_psi.h | 2 ++ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 572924388b..98a82b25e0 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -536,10 +536,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) qemu_register_reset(pnv_psi_reset, dev); } -static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x"; -static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x"; -static const char compat_p10[] = "ibm,power10-psihb-x\0ibm,psihb-x"; - static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) { PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); @@ -558,16 +554,8 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); - if (ppc->chip_type == PNV_CHIP_POWER10) { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, - sizeof(compat_p10))); - } else if (ppc->chip_type == PNV_CHIP_POWER9) { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, - sizeof(compat_p9))); - } else { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, - sizeof(compat_p8))); - } + _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, + ppc->compat_size)); return 0; } @@ -581,6 +569,7 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PnvPsiClass *ppc = PNV_PSI_CLASS(klass); + static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; dc->desc = "PowerNV PSI Controller POWER8"; dc->realize = pnv_psi_power8_realize; @@ -590,6 +579,8 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; ppc->bar_mask = PSIHB_BAR_MASK; ppc->irq_set = pnv_psi_power8_irq_set; + ppc->compat = compat; + ppc->compat_size = sizeof(compat); } static const TypeInfo pnv_psi_power8_info = { @@ -888,6 +879,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvPsiClass *ppc = PNV_PSI_CLASS(klass); XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); + static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x"; dc->desc = "PowerNV PSI Controller POWER9"; dc->realize = pnv_psi_power9_realize; @@ -897,6 +889,8 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; ppc->bar_mask = PSIHB9_BAR_MASK; ppc->irq_set = pnv_psi_power9_irq_set; + ppc->compat = compat; + ppc->compat_size = sizeof(compat); xfc->notify = pnv_psi_notify; } @@ -917,12 +911,15 @@ static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PnvPsiClass *ppc = PNV_PSI_CLASS(klass); + static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x"; dc->desc = "PowerNV PSI Controller POWER10"; ppc->chip_type = PNV_CHIP_POWER10; ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; + ppc->compat = compat; + ppc->compat_size = sizeof(compat); } static const TypeInfo pnv_psi_power10_info = { diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index a044aab304..fc068c95e5 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -83,6 +83,8 @@ typedef struct PnvPsiClass { uint32_t xscom_pcba; uint32_t xscom_size; uint64_t bar_mask; + const char *compat; + int compat_size; void (*irq_set)(PnvPsi *psi, int, bool state); } PnvPsiClass; From patchwork Tue Dec 17 04:43:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296749 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 229A214E3 for ; Tue, 17 Dec 2019 05:50:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB27E2146E for ; Tue, 17 Dec 2019 05:50:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="OBnGOYAN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EB27E2146E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5kq-0002Ol-Tp for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:50:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36046) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kh-0003C6-W4 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kg-0000eq-SO for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:31 -0500 Received: from ozlabs.org ([203.11.71.1]:45995) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kg-0008Ml-Gy; Mon, 16 Dec 2019 23:46:30 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWk6TzBz9sTr; Tue, 17 Dec 2019 15:43:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557826; bh=dvxrJfW6c+Bk0ahYO+qDrE1ZifZjK+c5PPctx0EOceM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OBnGOYANRdRyXC/PfmjVsMDrrk3JhfPheo1E7oWnqnBuumIY0qexvh4nQqpFyb1xs od9j8WzVrKCQbycP4rnNve//5iZHx3ARhqcVD2Ng23ACaV3hADnNJZIInVZeW/D1Lb Z2V3/k5hmenCDtz2Wuj6KRMT7+pVcNEylp8ZfN6I= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 77/88] ppc/pnv: Drop PnvPsiClass::chip_type Date: Tue, 17 Dec 2019 15:43:11 +1100 Message-Id: <20191217044322.351838-78-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz It isn't used anymore. Signed-off-by: Greg Kurz Message-Id: <157623838530.360005.15470128760871845396.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_psi.c | 3 --- include/hw/ppc/pnv_psi.h | 1 - 2 files changed, 4 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 98a82b25e0..75e20d9da0 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -574,7 +574,6 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller POWER8"; dc->realize = pnv_psi_power8_realize; - ppc->chip_type = PNV_CHIP_POWER8; ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; ppc->bar_mask = PSIHB_BAR_MASK; @@ -884,7 +883,6 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller POWER9"; dc->realize = pnv_psi_power9_realize; - ppc->chip_type = PNV_CHIP_POWER9; ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; ppc->bar_mask = PSIHB9_BAR_MASK; @@ -915,7 +913,6 @@ static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller POWER10"; - ppc->chip_type = PNV_CHIP_POWER10; ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; ppc->compat = compat; diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index fc068c95e5..f0f5b55197 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -79,7 +79,6 @@ typedef struct Pnv9Psi { typedef struct PnvPsiClass { SysBusDeviceClass parent_class; - int chip_type; uint32_t xscom_pcba; uint32_t xscom_size; uint64_t bar_mask; From patchwork Tue Dec 17 04:43:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296815 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DEEE14E3 for ; Tue, 17 Dec 2019 05:53:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33E822072D for ; Tue, 17 Dec 2019 05:53:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="iTTyGSHw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 33E822072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5nC-0005Qq-E6 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:53:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36225) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kr-0003SY-P6 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kq-0001CP-As for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:41 -0500 Received: from ozlabs.org ([203.11.71.1]:48053) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kp-0000AI-Va; Mon, 16 Dec 2019 23:46:40 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl2GQnz9sTt; Tue, 17 Dec 2019 15:43:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=BHAjypE4bBeB+KWlgsru+K88rpqi194TxyMC+bbKMsg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iTTyGSHw4+a5aHopO9J5Pb2jNuN0IEqgH8ysm1kmV7JcvhlhlvINvKT2xLTxZjGNN 26sGCAGR+aItuDgq6XZi3dOBAXLo55WFu508EdGbe9f1NGEfTuaz7uM9ynSBoQzsmC ryng1ijmKXCpdD5Wp6fAkFBHX0cLqw2kUKn+j4q8= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 78/88] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat Date: Tue, 17 Dec 2019 15:43:12 +1100 Message-Id: <20191217044322.351838-79-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The pnv_dt_create() function generates different contents for the "compatible" property of the root node in the DT, depending on the CPU type. This is open coded with multiple ifs using pnv_is_powerXX() helpers. It seems cleaner to achieve with QOM. Introduce a base class for the powernv machine and a compat attribute that each child class can use to provide the value for the "compatible" property. Signed-off-by: Greg Kurz Message-Id: <157623839085.360005.4046508784077843216.stgit@bahia.lan> Reviewed-by: Cédric Le Goater [dwg: Folded in small fix Greg spotted after posting] Signed-off-by: David Gibson --- hw/ppc/pnv.c | 32 ++++++++++++++++++-------------- include/hw/ppc/pnv.h | 13 +++++++++++++ 2 files changed, 31 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0be0b6b411..97845e7bde 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -484,9 +484,7 @@ static void pnv_dt_power_mgt(void *fdt) static void *pnv_dt_create(MachineState *machine) { - const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; - const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; - const char plat_compat10[] = "qemu,powernv10\0ibm,powernv"; + PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); PnvMachineState *pnv = PNV_MACHINE(machine); void *fdt; char *buf; @@ -504,17 +502,7 @@ static void *pnv_dt_create(MachineState *machine) _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); _FDT((fdt_setprop_string(fdt, 0, "model", "IBM PowerNV (emulated by qemu)"))); - if (pnv_is_power10(pnv)) { - _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10, - sizeof(plat_compat10)))); - } else if (pnv_is_power9(pnv)) { - _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, - sizeof(plat_compat9)))); - } else { - _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, - sizeof(plat_compat8)))); - } - + _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); buf = qemu_uuid_unparse_strdup(&qemu_uuid); _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); @@ -1692,6 +1680,8 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); + static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); @@ -1699,26 +1689,39 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) xic->icp_get = pnv_icp_get; xic->ics_get = pnv_ics_get; xic->ics_resend = pnv_ics_resend; + + pmc->compat = compat; + pmc->compat_size = sizeof(compat); } static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); + static const char compat[] = "qemu,powernv9\0ibm,powernv"; mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); xfc->match_nvt = pnv_match_nvt; mc->alias = "powernv"; + + pmc->compat = compat; + pmc->compat_size = sizeof(compat); } static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); + static const char compat[] = "qemu,powernv10\0ibm,powernv"; mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); + + pmc->compat = compat; + pmc->compat_size = sizeof(compat); } static void pnv_machine_class_init(ObjectClass *oc, void *data) @@ -1796,6 +1799,7 @@ static const TypeInfo types[] = { .instance_size = sizeof(PnvMachineState), .instance_init = pnv_machine_instance_init, .class_init = pnv_machine_class_init, + .class_size = sizeof(PnvMachineClass), .interfaces = (InterfaceInfo[]) { { TYPE_INTERRUPT_STATS_PROVIDER }, { }, diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 92f80b1cce..d534746bd4 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -185,6 +185,19 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") #define PNV_MACHINE(obj) \ OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) +#define PNV_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) +#define PNV_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) + +typedef struct PnvMachineClass { + /*< private >*/ + MachineClass parent_class; + + /*< public >*/ + const char *compat; + int compat_size; +} PnvMachineClass; typedef struct PnvMachineState { /*< private >*/ From patchwork Tue Dec 17 04:43:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296675 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CC9F930 for ; Tue, 17 Dec 2019 05:24:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 033502072B for ; Tue, 17 Dec 2019 05:24:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="FX0w8UiF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 033502072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Ky-0006Nu-KG for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:24:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36254) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kt-0003UM-1j for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kr-0001JK-Uz for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:42 -0500 Received: from ozlabs.org ([203.11.71.1]:41657) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kr-0000EE-Jn; Mon, 16 Dec 2019 23:46:41 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl66Mjz9sTj; Tue, 17 Dec 2019 15:43:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=97r7TzXK+1Ou/D6VolXeUHodoCbDq+0CZLkcFo2DuDc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FX0w8UiFnAj4wBixpRcCpXcetm2ollHht0h7be5O+fmJUssmSfhVIJUyoPvjOWo09 igMouJevZp/f4jwZWXuw0p7Uy3yU4OD5hYmhoFQ7jl9RLD8HPDvLVZAkJgGK5KkS1L 30pg9WehN3tOydgj8jpl+6OqrxYUQMA0Mghex82g= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 79/88] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() Date: Tue, 17 Dec 2019 15:43:13 +1100 Message-Id: <20191217044322.351838-80-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz We add an extra node to advertise power management on some machines, namely powernv9 and powernv10. This is achieved by using the pnv_is_power9() and pnv_is_power10() helpers. This can be achieved with QOM. Add a method to the base class for powernv machines and have it implemented by machine types that support power management instead. Signed-off-by: Greg Kurz Message-Id: <157623839642.360005.9243510140436689941.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 10 ++++++---- include/hw/ppc/pnv.h | 8 ++++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 97845e7bde..a2ad7258f8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -472,7 +472,7 @@ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) &args); } -static void pnv_dt_power_mgt(void *fdt) +static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) { int off; @@ -539,9 +539,9 @@ static void *pnv_dt_create(MachineState *machine) pnv_dt_bmc_sensors(pnv->bmc, fdt); } - /* Create an extra node for power management on Power9 and Power10 */ - if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) { - pnv_dt_power_mgt(fdt); + /* Create an extra node for power management on machines that support it */ + if (pmc->dt_power_mgt) { + pmc->dt_power_mgt(pnv, fdt); } return fdt; @@ -1709,6 +1709,7 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); + pmc->dt_power_mgt = pnv_dt_power_mgt; } static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) @@ -1722,6 +1723,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); + pmc->dt_power_mgt = pnv_dt_power_mgt; } static void pnv_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index d534746bd4..8a42c199b6 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -190,6 +190,8 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); #define PNV_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) +typedef struct PnvMachineState PnvMachineState; + typedef struct PnvMachineClass { /*< private >*/ MachineClass parent_class; @@ -197,9 +199,11 @@ typedef struct PnvMachineClass { /*< public >*/ const char *compat; int compat_size; + + void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); } PnvMachineClass; -typedef struct PnvMachineState { +struct PnvMachineState { /*< private >*/ MachineState parent_obj; @@ -216,7 +220,7 @@ typedef struct PnvMachineState { Notifier powerdown_notifier; PnvPnor *pnor; -} PnvMachineState; +}; static inline bool pnv_chip_is_power9(const PnvChip *chip) { From patchwork Tue Dec 17 04:43:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19F85921 for ; Tue, 17 Dec 2019 05:48:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E3A7420733 for ; Tue, 17 Dec 2019 05:48:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="gBsv/bXi" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E3A7420733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5iC-0006fE-S1 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:48:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35855) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kX-0002u4-8A for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kW-0000EJ-14 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:21 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:38431 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kV-00084z-NI; Mon, 16 Dec 2019 23:46:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWk3ZZXz9sRm; Tue, 17 Dec 2019 15:43:44 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557826; bh=TnBNdG+3SdShSrmyjXjRpG/CG/lHE/VGGq3tKwTGdB4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gBsv/bXivXwIWmCNu8NVW82d7l7Nqu3ees1WwMIGa6u3sEMEHzlBtyjstjXDWn+aD zKSeWt3GDLtwAnBIRyYfCBkrt8mfmJEnLm0r589Y/FEjOEfCEoMokHiqiVaBRK2bMn UrTc87sZrGnc3dU54HnItORHMnTRipb8Km9iVr00= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 80/88] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers Date: Tue, 17 Dec 2019 15:43:14 +1100 Message-Id: <20191217044322.351838-81-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz They aren't used anymore. Signed-off-by: Greg Kurz Message-Id: <157623840200.360005.1300941274565357363.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- include/hw/ppc/pnv.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 8a42c199b6..c213bdd5ec 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -227,11 +227,6 @@ static inline bool pnv_chip_is_power9(const PnvChip *chip) return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; } -static inline bool pnv_is_power9(PnvMachineState *pnv) -{ - return pnv_chip_is_power9(pnv->chips[0]); -} - PnvChip *pnv_get_chip(uint32_t chip_id); #define PNV_FDT_ADDR 0x01000000 @@ -242,11 +237,6 @@ static inline bool pnv_chip_is_power10(const PnvChip *chip) return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10; } -static inline bool pnv_is_power10(PnvMachineState *pnv) -{ - return pnv_chip_is_power10(pnv->chips[0]); -} - /* * BMC helpers */ From patchwork Tue Dec 17 04:43:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E84E5930 for ; Tue, 17 Dec 2019 05:44:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEBC320733 for ; Tue, 17 Dec 2019 05:44:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="pVQ871x7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BEBC320733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5ej-0001Zh-Kz for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:44:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35796) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kV-0002qv-9A for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kT-00009o-SN for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:19 -0500 Received: from ozlabs.org ([203.11.71.1]:52861) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kT-00082s-GS; Mon, 16 Dec 2019 23:46:17 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWj40twz9sTl; Tue, 17 Dec 2019 15:43:44 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557825; bh=beiPXhsZUwnNaLKV4yJfMDkkiO2d9SgIWAQnhLkMIzo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pVQ871x77OBqoeUI0mrRHDW/ZjzdRSAMuBqHNTRoN863Q0u3/QWKm3HSkWfKcIJNB kEyz8txojuu4WxM9tXN4O6Q3N0sGJdiRYNHGpqndGINUB0cXxUkqdLdF86BVIsUb1i VYNfInoBpbFX/jzD+LQ7e+nVlb55i3fdoBcQ0MvM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 81/88] ppc/pnv: Introduce PnvChipClass::intc_print_info() method Date: Tue, 17 Dec 2019 15:43:15 +1100 Message-Id: <20191217044322.351838-82-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The pnv_pic_print_info() callback checks the type of the chip in order to forward to the request appropriate interrupt controller. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. This also prepares ground for the upcoming interrupt controller of POWER10 chips. Signed-off-by: Greg Kurz Message-Id: <157623840755.360005.5002022339473369934.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 30 +++++++++++++++++++++++++----- include/hw/ppc/pnv.h | 1 + 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index a2ad7258f8..35416d1b3f 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -831,6 +831,12 @@ static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) pnv_cpu->intc = NULL; } +static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, + Monitor *mon) +{ + icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); +} + /* * 0:48 Reserved - Read as zeroes * 49:52 Node ID @@ -888,6 +894,12 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) pnv_cpu->intc = NULL; } +static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, + Monitor *mon) +{ + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); +} + static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { @@ -909,6 +921,11 @@ static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) pnv_cpu->intc = NULL; } +static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, + Monitor *mon) +{ +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -1085,6 +1102,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) k->intc_create = pnv_chip_power8_intc_create; k->intc_reset = pnv_chip_power8_intc_reset; k->intc_destroy = pnv_chip_power8_intc_destroy; + k->intc_print_info = pnv_chip_power8_intc_print_info; k->isa_create = pnv_chip_power8_isa_create; k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; @@ -1106,6 +1124,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) k->intc_create = pnv_chip_power8_intc_create; k->intc_reset = pnv_chip_power8_intc_reset; k->intc_destroy = pnv_chip_power8_intc_destroy; + k->intc_print_info = pnv_chip_power8_intc_print_info; k->isa_create = pnv_chip_power8_isa_create; k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; @@ -1127,6 +1146,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) k->intc_create = pnv_chip_power8_intc_create; k->intc_reset = pnv_chip_power8_intc_reset; k->intc_destroy = pnv_chip_power8_intc_destroy; + k->intc_print_info = pnv_chip_power8_intc_print_info; k->isa_create = pnv_chip_power8nvl_isa_create; k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; @@ -1298,6 +1318,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->intc_create = pnv_chip_power9_intc_create; k->intc_reset = pnv_chip_power9_intc_reset; k->intc_destroy = pnv_chip_power9_intc_destroy; + k->intc_print_info = pnv_chip_power9_intc_print_info; k->isa_create = pnv_chip_power9_isa_create; k->dt_populate = pnv_chip_power9_dt_populate; k->pic_print_info = pnv_chip_power9_pic_print_info; @@ -1378,6 +1399,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) k->intc_create = pnv_chip_power10_intc_create; k->intc_reset = pnv_chip_power10_intc_reset; k->intc_destroy = pnv_chip_power10_intc_destroy; + k->intc_print_info = pnv_chip_power10_intc_print_info; k->isa_create = pnv_chip_power10_isa_create; k->dt_populate = pnv_chip_power10_dt_populate; k->pic_print_info = pnv_chip_power10_pic_print_info; @@ -1574,11 +1596,9 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - if (pnv_chip_is_power9(pnv->chips[0])) { - xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); - } else { - icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); - } + /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ + PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, + mon); } for (i = 0; i < pnv->num_chips; i++) { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index c213bdd5ec..7d2402784d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -133,6 +133,7 @@ typedef struct PnvChipClass { void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); From patchwork Tue Dec 17 04:43:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296797 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 935AE921 for ; Tue, 17 Dec 2019 05:52:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1F6B520733 for ; Tue, 17 Dec 2019 05:52:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="UbLl3kzQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F6B520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5mB-0004F5-7V for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:52:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36156) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kn-0003Mk-Kw for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4km-0000wd-7t for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:37 -0500 Received: from ozlabs.org ([203.11.71.1]:39065) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kl-0008WV-SX; Mon, 16 Dec 2019 23:46:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl0k8gz9sTn; Tue, 17 Dec 2019 15:43:44 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=erWSHyC5lwCGEGfTSMrCkh+lwueXLVKO1d9GXDjoZFg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UbLl3kzQV+63G/sw/RVkDN06ZYKPIIMJ2yC5f8Hss5pIffV6kPshKynzPtot83MPM QbU7mMsdZwNE7KIaEYF5VkIbERinOn8u/WqwEiycShmGmQyJi1NKspH4qd+oMi+6ZL vjvbZI+swxf3Nfxq2RrpjHFeD+gV4wOo6f2WjFHw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 82/88] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method Date: Tue, 17 Dec 2019 15:43:16 +1100 Message-Id: <20191217044322.351838-83-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The pnv_chip_core_realize() function configures the XSCOM MMIO subregion for each core of a single chip. The base address of the subregion depends on the CPU type. Its computation is currently open-code using the pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. Signed-off-by: Greg Kurz Message-Id: <157623841311.360005.4705705734873339545.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 31 ++++++++++++++++++++++++------- include/hw/ppc/pnv.h | 1 + 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 35416d1b3f..16f4e407ee 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -615,6 +615,24 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) pnv_psi_pic_print_info(&chip9->psi, mon); } +static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV_XSCOM_EX_BASE(core_id); +} + +static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV9_XSCOM_EC_BASE(core_id); +} + +static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV10_XSCOM_EC_BASE(core_id); +} + static bool pnv_match_cpu(const char *default_type, const char *cpu_type) { PowerPCCPUClass *ppc_default = @@ -1106,6 +1124,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) k->isa_create = pnv_chip_power8_isa_create; k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; + k->xscom_core_base = pnv_chip_power8_xscom_core_base; dc->desc = "PowerNV Chip POWER8E"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1128,6 +1147,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) k->isa_create = pnv_chip_power8_isa_create; k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; + k->xscom_core_base = pnv_chip_power8_xscom_core_base; dc->desc = "PowerNV Chip POWER8"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1150,6 +1170,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) k->isa_create = pnv_chip_power8nvl_isa_create; k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; + k->xscom_core_base = pnv_chip_power8_xscom_core_base; dc->desc = "PowerNV Chip POWER8NVL"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1322,6 +1343,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->isa_create = pnv_chip_power9_isa_create; k->dt_populate = pnv_chip_power9_dt_populate; k->pic_print_info = pnv_chip_power9_pic_print_info; + k->xscom_core_base = pnv_chip_power9_xscom_core_base; dc->desc = "PowerNV Chip POWER9"; device_class_set_parent_realize(dc, pnv_chip_power9_realize, @@ -1403,6 +1425,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) k->isa_create = pnv_chip_power10_isa_create; k->dt_populate = pnv_chip_power10_dt_populate; k->pic_print_info = pnv_chip_power10_pic_print_info; + k->xscom_core_base = pnv_chip_power10_xscom_core_base; dc->desc = "PowerNV Chip POWER10"; device_class_set_parent_realize(dc, pnv_chip_power10_realize, @@ -1490,13 +1513,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) &error_fatal); /* Each core has an XSCOM MMIO region */ - if (pnv_chip_is_power10(chip)) { - xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid); - } else if (pnv_chip_is_power9(chip)) { - xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); - } else { - xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); - } + xscom_core_base = pcc->xscom_core_base(chip, core_hwid); pnv_xscom_add_subregion(chip, xscom_core_base, &pnv_core->xscom_regs); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7d2402784d..17ca9a14ac 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -137,6 +137,7 @@ typedef struct PnvChipClass { ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); } PnvChipClass; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP From patchwork Tue Dec 17 04:43:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0884C14E3 for ; Tue, 17 Dec 2019 05:36:58 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D2ECB20733 for ; Tue, 17 Dec 2019 05:36:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="fYnBEn3Q" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D2ECB20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5XU-0008MU-Os for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:36:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35793) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kV-0002qf-3X for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kT-00009a-QO for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:18 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:48477 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kT-00082o-Fp; Mon, 16 Dec 2019 23:46:17 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWj5gTRz9sTs; Tue, 17 Dec 2019 15:43:44 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557825; bh=ljmL1lYaXFyfFF9azN9Hfb8Gm1J0BuKOdNiP9RTy5kU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fYnBEn3Q97fzOecWLnZ4a4awkx9f7ReJymTAUJRx2FNwmNtuA3kr8QV0KDHNGwPXy LCbRnR/SFseP+DwKhoXif2sKMaLqB2Zj34MGSCtpFrKFbQF2uj+VdoBcPo5vsn49hl ShZurNJ+boqCSISIWtaWqDauyWSpCLPppECqxnCM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 83/88] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() Date: Tue, 17 Dec 2019 15:43:17 +1100 Message-Id: <20191217044322.351838-84-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "reg" property. Just pass the base address and address size as arguments. Signed-off-by: Greg Kurz Message-Id: <157623841868.360005.17577624823547136435.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 12 +++++++++--- hw/ppc/pnv_xscom.c | 16 +++------------- include/hw/ppc/pnv_xscom.h | 3 ++- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 16f4e407ee..c0a5703b74 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -282,7 +282,9 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) { int i; - pnv_dt_xscom(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV_XSCOM_BASE(chip)), + cpu_to_be64(PNV_XSCOM_SIZE)); for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = chip->cores[i]; @@ -302,7 +304,9 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) { int i; - pnv_dt_xscom(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV9_XSCOM_BASE(chip)), + cpu_to_be64(PNV9_XSCOM_SIZE)); for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = chip->cores[i]; @@ -321,7 +325,9 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) { int i; - pnv_dt_xscom(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV10_XSCOM_BASE(chip)), + cpu_to_be64(PNV10_XSCOM_SIZE)); for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = chip->cores[i]; diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index df926003f2..8189767eb0 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -286,24 +286,14 @@ static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom"; -int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) +int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, + uint64_t xscom_base, uint64_t xscom_size) { - uint64_t reg[2]; + uint64_t reg[] = { xscom_base, xscom_size }; int xscom_offset; ForeachPopulateArgs args; char *name; - if (pnv_chip_is_power10(chip)) { - reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip)); - reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE); - } else if (pnv_chip_is_power9(chip)) { - reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip)); - reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE); - } else { - reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip)); - reg[1] = cpu_to_be64(PNV_XSCOM_SIZE); - } - name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); xscom_offset = fdt_add_subnode(fdt, root_offset, name); _FDT(xscom_offset); diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 2bdb7ae84f..ad53f788b4 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -114,7 +114,8 @@ typedef struct PnvXScomInterfaceClass { #define PNV10_XSCOM_PSIHB_SIZE 0x100 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); -int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); +int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, + uint64_t xscom_base, uint64_t xscom_size); void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr); From patchwork Tue Dec 17 04:43:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296661 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CB376C1 for ; Tue, 17 Dec 2019 05:21:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 124222072B for ; Tue, 17 Dec 2019 05:21:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Ni2znKjV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 124222072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5Ic-0002vh-IS for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:21:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36016) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kf-00038a-Se for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ke-0000a4-Ht for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:29 -0500 Received: from ozlabs.org ([203.11.71.1]:37773) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ke-0008Jk-5u; Mon, 16 Dec 2019 23:46:28 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWk50zcz9sTh; Tue, 17 Dec 2019 15:43:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557826; bh=6Nu5aL34GOYK0IMDawQWJzLfK3WQGy47SluL54q3xhg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ni2znKjVFrqnfj4OlHb9kDl1zg0cYeK8EMsiMjzotGYwRCEuSN2WXPKupQ7djnQXW 8AgDCkMVwrsNH4mgkc3lmLxYvDAUJHMZGhPgQAGE4jmc6ySUZCxDVv9lpGv1m7wx6Y YvgiqXSobvh4z79sJPVCjxtKVOiUrC/SzHqcDNf4= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 84/88] ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom() Date: Tue, 17 Dec 2019 15:43:18 +1100 Message-Id: <20191217044322.351838-85-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "compatible" property. Just pass the compat string and its size as arguments. Signed-off-by: Greg Kurz Message-Id: <157623842430.360005.9513965612524265862.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 12 +++++++++--- hw/ppc/pnv_xscom.c | 20 +++----------------- include/hw/ppc/pnv_xscom.h | 3 ++- 3 files changed, 14 insertions(+), 21 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c0a5703b74..b3388038c6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -280,11 +280,13 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) { + static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; int i; pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV_XSCOM_BASE(chip)), - cpu_to_be64(PNV_XSCOM_SIZE)); + cpu_to_be64(PNV_XSCOM_SIZE), + compat, sizeof(compat)); for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = chip->cores[i]; @@ -302,11 +304,13 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) { + static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; int i; pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV9_XSCOM_BASE(chip)), - cpu_to_be64(PNV9_XSCOM_SIZE)); + cpu_to_be64(PNV9_XSCOM_SIZE), + compat, sizeof(compat)); for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = chip->cores[i]; @@ -323,11 +327,13 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) { + static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; int i; pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV10_XSCOM_BASE(chip)), - cpu_to_be64(PNV10_XSCOM_SIZE)); + cpu_to_be64(PNV10_XSCOM_SIZE), + compat, sizeof(compat)); for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = chip->cores[i]; diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 8189767eb0..5ae9dfbb88 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -282,12 +282,9 @@ static int xscom_dt_child(Object *child, void *opaque) return 0; } -static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; -static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; -static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom"; - int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, - uint64_t xscom_base, uint64_t xscom_size) + uint64_t xscom_base, uint64_t xscom_size, + const char *compat, int compat_size) { uint64_t reg[] = { xscom_base, xscom_size }; int xscom_offset; @@ -302,18 +299,7 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); - - if (pnv_chip_is_power10(chip)) { - _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, - sizeof(compat_p10)))); - } else if (pnv_chip_is_power9(chip)) { - _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, - sizeof(compat_p9)))); - } else { - _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, - sizeof(compat_p8)))); - } - + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size))); _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); args.fdt = fdt; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index ad53f788b4..f74c81a980 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -115,7 +115,8 @@ typedef struct PnvXScomInterfaceClass { void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, - uint64_t xscom_base, uint64_t xscom_size); + uint64_t xscom_base, uint64_t xscom_size, + const char *compat, int compat_size); void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr); From patchwork Tue Dec 17 04:43:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A05FD14E3 for ; Tue, 17 Dec 2019 05:40:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63F4520733 for ; Tue, 17 Dec 2019 05:40:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="aWIoqsuI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63F4520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5bB-0005TP-9S for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:40:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36272) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kt-0003VL-PJ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ks-0001KQ-Jh for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:43 -0500 Received: from ozlabs.org ([203.11.71.1]:44487) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ks-0000Eu-8M; Mon, 16 Dec 2019 23:46:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWm083dz9sTp; Tue, 17 Dec 2019 15:43:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557828; bh=WPGhRLVgvuo1dfcfSmYeMRPiaxlknfIpHytSLFhG/OA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aWIoqsuIfjjubhESYx8NAuAV0YlJAbe4andXIa91KzeDo/v6kzdbOpbQ5BXEyoTat 0CAqaKui3/i9QD1hcr+gROqKRHotPhqErpu+h/A8FnVCUq+zrzthPltsfk/SVYWNx3 h+2yVExEi9dkDyHMEhiGaGbdp2/pflED9pHOkq6c= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 85/88] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers Date: Tue, 17 Dec 2019 15:43:19 +1100 Message-Id: <20191217044322.351838-86-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz They aren't used anymore. Signed-off-by: Greg Kurz Message-Id: <157623842986.360005.1787401623906380181.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- include/hw/ppc/pnv.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 17ca9a14ac..7a134a15d3 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -224,21 +224,11 @@ struct PnvMachineState { PnvPnor *pnor; }; -static inline bool pnv_chip_is_power9(const PnvChip *chip) -{ - return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER9; -} - PnvChip *pnv_get_chip(uint32_t chip_id); #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL -static inline bool pnv_chip_is_power10(const PnvChip *chip) -{ - return PNV_CHIP_GET_CLASS(chip)->chip_type == PNV_CHIP_POWER10; -} - /* * BMC helpers */ From patchwork Tue Dec 17 04:43:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296827 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A13F14E3 for ; Tue, 17 Dec 2019 05:54:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 702092072D for ; Tue, 17 Dec 2019 05:54:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Sejz2c9O" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 702092072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5o7-0006JX-Ji for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:54:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36277) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kt-0003VX-SD for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4ks-0001KB-GZ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:43 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:35953 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4ks-0000F6-5x; Mon, 16 Dec 2019 23:46:42 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWm0zKgz9sRc; Tue, 17 Dec 2019 15:43:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557828; bh=jJaUvC3L1J19szq6Xx2t4DAcLfJF1KIsBpr7HLRkc1Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sejz2c9OpmwdASBQpfvQUZzBPFIIfXcZsD5g4r4E7SXFbnG53Eq5hrNPjBLekwKdB nUVKXqYulIVsuOmGUVG6A9mDqyML1IUGNTUYpSO8h+T0Xt4E1OdA/sN++YWAlTk3t+ nTFfpixPtZaSUivunTFU/iMN1xGA5EDe0aVN2i8M= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 86/88] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method Date: Tue, 17 Dec 2019 15:43:20 +1100 Message-Id: <20191217044322.351838-87-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The XSCOM bus is implemented with a QOM interface, which is mostly generic from a CPU type standpoint, except for the computation of addresses on the Pervasive Connect Bus (PCB) network. This is handled by the pnv_xscom_pcba() function with a switch statement based on the chip_type class level attribute of the CPU chip. This can be achieved using QOM. Also the address argument is masked with PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different sizes with other CPU types. Have each CPU chip type handle the appropriate computation with a QOM xscom_pcba() method. Signed-off-by: Greg Kurz Message-Id: <157623843543.360005.13996472463887521794.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 23 +++++++++++++++++++++++ hw/ppc/pnv_xscom.c | 14 +------------- include/hw/ppc/pnv.h | 1 + 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index b3388038c6..41e5d762df 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1120,6 +1120,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) &chip8->homer.regs); } +static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &= (PNV_XSCOM_SIZE - 1); + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); +} + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1137,6 +1143,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; k->xscom_core_base = pnv_chip_power8_xscom_core_base; + k->xscom_pcba = pnv_chip_power8_xscom_pcba; dc->desc = "PowerNV Chip POWER8E"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1160,6 +1167,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; k->xscom_core_base = pnv_chip_power8_xscom_core_base; + k->xscom_pcba = pnv_chip_power8_xscom_pcba; dc->desc = "PowerNV Chip POWER8"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1183,6 +1191,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power8_dt_populate; k->pic_print_info = pnv_chip_power8_pic_print_info; k->xscom_core_base = pnv_chip_power8_xscom_core_base; + k->xscom_pcba = pnv_chip_power8_xscom_pcba; dc->desc = "PowerNV Chip POWER8NVL"; device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1339,6 +1348,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) &chip9->homer.regs); } +static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &= (PNV9_XSCOM_SIZE - 1); + return addr >> 3; +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1356,6 +1371,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power9_dt_populate; k->pic_print_info = pnv_chip_power9_pic_print_info; k->xscom_core_base = pnv_chip_power9_xscom_core_base; + k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; device_class_set_parent_realize(dc, pnv_chip_power9_realize, @@ -1421,6 +1437,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) (uint64_t) PNV10_LPCM_BASE(chip)); } +static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &= (PNV10_XSCOM_SIZE - 1); + return addr >> 3; +} + static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1438,6 +1460,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) k->dt_populate = pnv_chip_power10_dt_populate; k->pic_print_info = pnv_chip_power10_pic_print_info; k->xscom_core_base = pnv_chip_power10_xscom_core_base; + k->xscom_pcba = pnv_chip_power10_xscom_pcba; dc->desc = "PowerNV Chip POWER10"; device_class_set_parent_realize(dc, pnv_chip_power10_realize, diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 5ae9dfbb88..b681c72575 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits) static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) { - addr &= (PNV_XSCOM_SIZE - 1); - - switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { - case PNV_CHIP_POWER8E: - case PNV_CHIP_POWER8: - case PNV_CHIP_POWER8NVL: - return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); - case PNV_CHIP_POWER9: - case PNV_CHIP_POWER10: - return addr >> 3; - default: - g_assert_not_reached(); - } + return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr); } static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7a134a15d3..4972e93c26 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -138,6 +138,7 @@ typedef struct PnvChipClass { void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); } PnvChipClass; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP From patchwork Tue Dec 17 04:43:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E9A7930 for ; Tue, 17 Dec 2019 05:41:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 43F182146E for ; Tue, 17 Dec 2019 05:41:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="VmE1pc3E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 43F182146E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5cH-0006wR-51 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:41:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36459) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4l4-0003kl-Hs for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4l3-0001YG-EV for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:54 -0500 Received: from ozlabs.org ([203.11.71.1]:48091) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4l3-0000g2-3O; Mon, 16 Dec 2019 23:46:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWm43QMz9sTv; Tue, 17 Dec 2019 15:43:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557828; bh=hAkVJ+pdy5kFzF3todD0E6oMTylecfVF64CKJc42ZPI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VmE1pc3EZuaek8lTVma21UoA4Ov6/cFuXSqluCm1nM1cn+m44OYXhU6EeLdp/YXQg q26HWjjgHGL5hORxT7joOudFgwuAkCgFM7zUiBCFXL0aNa57EOWLYk4BZt+PGwuDf6 E20XOYuVLq9etM0b4OMnQryPJt+lkCWDx5g4p4To= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 87/88] ppc/pnv: Drop PnvChipClass::type Date: Tue, 17 Dec 2019 15:43:21 +1100 Message-Id: <20191217044322.351838-88-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz It isn't used anymore. Signed-off-by: Greg Kurz Message-Id: <157623844102.360005.12070225703151669294.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 5 ----- include/hw/ppc/pnv.h | 9 --------- 2 files changed, 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 41e5d762df..f77e7ca84e 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1131,7 +1131,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->chip_type = PNV_CHIP_POWER8E; k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask = POWER8E_CORE_MASK; k->core_pir = pnv_chip_core_pir_p8; @@ -1155,7 +1154,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->chip_type = PNV_CHIP_POWER8; k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask = POWER8_CORE_MASK; k->core_pir = pnv_chip_core_pir_p8; @@ -1179,7 +1177,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->chip_type = PNV_CHIP_POWER8NVL; k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask = POWER8_CORE_MASK; k->core_pir = pnv_chip_core_pir_p8; @@ -1359,7 +1356,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->chip_type = PNV_CHIP_POWER9; k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask = POWER9_CORE_MASK; k->core_pir = pnv_chip_core_pir_p9; @@ -1448,7 +1444,6 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvChipClass *k = PNV_CHIP_CLASS(klass); - k->chip_type = PNV_CHIP_POWER10; k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ k->cores_mask = POWER10_CORE_MASK; k->core_pir = pnv_chip_core_pir_p10; diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 4972e93c26..f78fd0dd96 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -38,14 +38,6 @@ #define PNV_CHIP_GET_CLASS(obj) \ OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) -typedef enum PnvChipType { - PNV_CHIP_POWER8E, /* AKA Murano (default) */ - PNV_CHIP_POWER8, /* AKA Venice */ - PNV_CHIP_POWER8NVL, /* AKA Naples */ - PNV_CHIP_POWER9, /* AKA Nimbus */ - PNV_CHIP_POWER10, /* AKA TBD */ -} PnvChipType; - typedef struct PnvChip { /*< private >*/ SysBusDevice parent_obj; @@ -123,7 +115,6 @@ typedef struct PnvChipClass { SysBusDeviceClass parent_class; /*< public >*/ - PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; From patchwork Tue Dec 17 04:43:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296731 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 239D514E3 for ; Tue, 17 Dec 2019 05:44:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 97CAC20733 for ; Tue, 17 Dec 2019 05:44:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="nawX/p2c" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 97CAC20733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5ef-0001S9-G3 for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:44:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36576) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4lC-0003wy-W0 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:47:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4l2-0001X1-Er for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:47:02 -0500 Received: from ozlabs.org ([203.11.71.1]:44193) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4l0-0000cC-SX; Mon, 16 Dec 2019 23:46:52 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWm2WV2z9sTq; Tue, 17 Dec 2019 15:43:46 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557828; bh=A3wl0DtEUtqtnlikDYXCVf0USpA5i5kM+r/iT9KjdsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nawX/p2ccWJT1nxGb/JDX6EubKIzMBA3AHBbWDIEaLo0neYtIAxtYCYoPesHpYuT7 DvVS0I7KSpSQJeB3wpWC0RBebMZgCDGHCbKdo+LjqrPhNPV1LM3eehIedtIjh77jnf ubacoioebLmqozpA6L2O6YiUJvcMYFgOAZJSHIRA= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 88/88] pseries: Update SLOF firmware image Date: Tue, 17 Dec 2019 15:43:22 +1100 Message-Id: <20191217044322.351838-89-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexey Kardashevskiy This fixes PCI bridges support regression. This enables IOMMU support in virtio drivers. The full list of changes is: Alexey Kardashevskiy (12): allocator: Fix format strings for DEBUG virtio: Make virtio_set_qaddr static client: Load initramdisk location sloffs: Fix -Wunused-result gcc warnings in read/write pci-phb: Reimplement dma-map-in/out virtio: Store queue descriptors in virtio_device virtio-net: Init queues after features negotiation virtio: Enable IOMMU ibm,client-architecture-support: Fix stack handling fdt: Fix updating the tree at H_CAS version: update to 20191206 version: update to 20191217 Michael Roth (1): dma: Define default dma methods for using by client/package instances Signed-off-by: Alexey Kardashevskiy Signed-off-by: David Gibson --- pc-bios/README | 2 +- pc-bios/slof.bin | Bin 931040 -> 931032 bytes roms/SLOF | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pc-bios/README b/pc-bios/README index 91218c69e9..269d99afe0 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -17,7 +17,7 @@ - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20191209. + built from git tag qemu-slof-20191217. - sgabios (the Serial Graphics Adapter option ROM) provides a means for legacy x86 software to communicate with an attached serial console as diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin index 50fc9b1e1cb837809c38fed1e9099b262e8600f1..78d8b26cbb88a1913c3b262fd5be29ff89afd554 100644 GIT binary patch delta 217484 zcmbTf33yaR);C^NH-Qd9Xkvh{1Ujrq*uvgf=|I3vnk7I2sGv;%2@GnhIMYZ%cUUwi zYBDTEkfjlV!HqEDG&6z*1q_NaaYP3dov0`YpcA+E4O{yAow~P4GBV%y{Qvzt;oPb^ zb?Vfqb55OF?xnWgdbZwLGPcXv#Y>hCNgO?Dj5Tq@d~3qO(GM-U|IvhvF+94BrCUVT zPQy!Gk?nt&>}=hmcE$y=eg1+_K27`o#e@u)xSNMb*TdW*w}$cVV(EvJ zh>;(M@$dK?d88d5$g}17c6<%5mif2wj{s8I^AUYcR5`(#b+tFvF6KQ%&xsbsQ^&KA z()hny9D$~_@_05+m6@@;r+lS7kLTT_Weks!4ej{=F~43$b>P$Z3V(hFKAwvOAIO)( z`AoiIOGn;WcIwE7h{liowvN1uNsRhfT81L`{;oVu_)f@L3s2ZGi1(G3x^gpEE$PN1 zr8$bvig>)7_^2Pw*swi}*>)xsOLr7sz>8$bXr3UwU3nL=dWEd&#nUzJ-ArWTWdC^H zDWV`#)f~at;J%EduTFGIdpv00uz>p=alD)O{X^7nqMlg(ib3R&G9u!L`JXE@7^_BB+XsV`w{Ttx`Th7jan}u5)epluV!J%s4;;99BjFr! zQ)6y7d!Gzk_bz22m;Qyud3L!p4yP>xf*Ar>VOG%-fxzM}Upp^p03Pp<6?{$?*~!C&!{ zfj~2VSvRQJe$tx(1uzfiW|Q|}7Gmeq3S~nA^t>(_qiOEO+lVRUq&%baMAoM*5}99+ zP0SLr7RkD9{2r0BPTITkG%<6E-t3OZo#za-IR zz5zGulJZ)MkXy%X~W^In}lPy^b^Tz{w_b6qVq zhwAucyY)7u5^SXO4MAI_iL!PGAIFskm?fUsE!{);gZvmZ1xpx)-aIi+umAWdz5cq+ zIYL~vV zuaDF%RRo$6O>15C@rTf1;XEotDd5)OJYLNER&Uc8&ZFhWBY2{?r%akh zVy?MoxO9%>WBJFjaun|^{UiBEF|VBRddRk;cn>izQ!kk?ib}faB^#+^?ole4A?7}< z%lmE^oZ;I$$uGj;&8BqV-NNUl6X(Qfhu(G2m0FP=ee(hPM-QzPdT;{bbLvyelu1qsH>t+~wae zmL?RoUDjCn?<0D|QuB#6IHAlyUHw;Vt87dH{ZT!5f4L)x_ZKtcZt8lZT#?8VBSJR} z+Rub-N4M%>`&o!>XXtX7odoH9o5=5s2py#t_Sj$)_N2mC*=Xa_!mbZ{frX^+WQSyS zI-FWmqg}VSes4EhVqD<5`$FURVfzD3)(ed1nnKdj zw|Di)?D6pKlT$G>7med1Wn(gA-FbtYoC2bqb7X!Bdf*+;LvMQD;uM|~+NHQKZiM{% zEQqo;1->WBE2C23A$;TE>#D}_tTCE*PzCj@OXIK#>Y0}B*`IAglamYEB}IDn+ibS& zU2W(DD~wBuOy7B~uCUz%x3t^P1$#129&KNbCX4UGpcY5j(s$gxH+}o<1%+|iKEx?K zN$J*y;ScKQS#P8AwJ4t}k0kRH6U5cVw)1u-YauQp)ww{W{OD?LE-$3<*@7LBwsFvt z$~2x33ocQ|Y|*)ltZ3#ka(gqEpBBg(8-`%=3|LTY8gDBf9Kl1SD~+f7caP_HwiA50 zygr%7Y0yU5ZwenQ4^M|y@#*{p*)SbpPQ`RgIP{O-IfYBk^QCJb1lKT?x8+Xhn#RZY zmrmn%@wqx9ETx$dme9<|DQ97pExRyN+ef0?$e<>&HIJ#|%P>|zY7Ac{)8 z!T;4MTlR1-{a=ATfF!0-eK^AzCGoR|)V2m#qy1vyA>)IA#bvKLk#4kz>GZ5$fI+J%DMJ=L6 z6KXV}Ml97(e`uw=9TRA!>Gd!sTDIbEn8h)3&M(;2kWGQP)yYDWn@HS$n&MgWjoZ!} zUnd%#b>FxP7WQzX{5F&gw|ZGS&o|dl{=bW)eGb(BQJFu7j~xDC^4H!up5s5egVY>> zgGY7D#{P=Zx7S)wI=EY&p2KI(pF${941xygGM z>}_vjGh+wldDec@qQ3{GP#rt}RhL}rW`_SqGckIo&(yLAQl$|9!w152ya7g95SREOV^dU?G(KaaoBIaL*vUkVNZT6yU&^3Xl}kvLs!t;X}E;e_5=bT38A?0flv znEMqarHc(8s^?Z!U!3B%IC(f9vtMsgA^v;!ZxQ!LQ(o&f_J>JS?k9`q^I@ZPzFMhv zg-%DO8TwnA6-ClkBjRM|JRUcuVu(Ue$Ul_c0$GWxH3KhP(HYp92L{SjomLFIpwm$_ zzyI~OG+%f~XQ2NA{?~a=tMa{+{<_ouoD59jl-Qwmj`R?4<}iOOpw zmEE~2Pj%{oF12Q+;1qU`rt*ym4|kR)oLDCx)qnZURQaoxZI`dn$Be?mAB?{SCOitxcv58CyQw1sln#1`Lg}* z_?}KjgLnk({M%?*^*i2m$!3+^s>z)?N!8?eko?akcg|OJRFmgVsOMIK*_j@!(>#0a z93pMYu(z|bQ_HfF0?<~o+m0)8`7*w-)1y?ZQ1aGT?fk|f8FfFO)McyX8p5n(gfPjq za3jy}%}>tTR4kX@k4fz-x&40lnWtp~rBLAkfK+LFfWO6`{_}(U0ZlY^@M8~f@ojwc zMsseo#y{S?F(J3)Hlv-hc7Ex#_j414JniL|c<#oAIo&k=;a@hkzjKp;vo^}k>o&f0 z=NJC$H9U=r#h3jhYxywFkNT_D@qmI)@PG2mkBMe$7w0{u@|3vV?XR9&iOaj2@><)C z_i2CadcHv8nf{EY`T5AG0+ZNxZFiu~>f}+4oS7SA0>d4Fx4zi22U{5Lye^~mV77nf ze(6Ly>787nn6scw+ORb&%(gRd#=44Wj=(#qD!-sj8qy(14^iorDs6HE-j0@)d-#a( zrf$#eV(ox~pzrN3WWydl$9yG~v9eSafj_e&aHCw#*~_hwsn{W15x3?%m0tRaRXYNK zBXaLvJ~H}OB3)O+TqT7pADgGYP}-Wew#v>=X3Ago^11Em`!cp7uI)GJtL0tge5a@9 zT4tpXrfwngPW3ViD%|{0T->6(`2SH}a;tLpi*3KTHa~FoT2Y|3prD7F@=j(Up+QzfMH9fg#$pTm&D>HL zH~o`>^_J{{wQUc%clPdA7~2qU$RJxO?^n#@cCR0BzQBXv)r);(&PwVhFmqwMtjL0; zlVcNO(Ldkh!H&QY<&5jcvDic#*6o=;k{n8)UT$I%-SJ)m11(0FdxgH>3~ESyKep9q z-0Uvz-LGItZ2VMjHnWh*)n_oTyL`ZTQoVwuvGG$@GmCpE>r=3#hdXCMRa&mSDs6h- z@x7+o@z-}!+I0J*H1~qGCkqx#aJOg_LXul5c(0af{ALCJtA~0!Xe|?@W`?OwPv4!!p8HwEimZ_HSE5<*ia4F%m3gcLM9*8x z&6>MBIda9@JxE6$`cO$Cf{vIkk!3?iXqbpY@*3V%%mq<-n0rC*evZK5 zMO4tZifx6qR}w-{rq?)G;YA2E3K^0%mL$jVbZeA z955*j;}+sR$t>14n1wnwyG>OZp8L&gW8kz2;&^lfPvSo!i5L-31d|McAfyPs!D5M^ zA~s188$5H8L2Ocxm|ni}Xve)lTAritMG`Z~N6p&GqZqF@Si&(9IyXl$cEl0rr5J}bJ`7E+vMGtr5O6G&hucSPZFu`Omx&L*DJl^a~X_TuCj27jc z2*G0KN7dYcNv2Wy)`@62?XU_i)E7aSSnF4)!AZ5Y-=m@8uS4P-XAs2}uwJ-J;T z1!MCjSLsbtbJR@TQGIIG4d}|R-d)%oNn^Y)t?ePtT03_40=0D>77NYty4RAjyso;1 zJad%Mh_ycTrb;d>f~LsrFZ15f!>J9T3vpPj0}LL{$)1`<}p4>)hdCat@?&c$+lc9A%qV_+u@7)0408Ki*8+R?7je^0#lM(^va{dX*37p7|J; z6YeGOjEj1>F{hn(FHz=KLNSdlxEm*Q*tElQDryBxb1ghraq@0>EC|4Z_#Q*osVGKI z&yQoK!hUTJl_Kp3Twg)udj0F)6V5{@M?0=-|AMfb0s?h@Nt>Q#5$ZuVNo0wZKww2$ z$7j&ZWt46?jd`$_VqLw?W#@;ZNi0@pAfODJ>e3(ZDGwf_82MXU)EgPgOa)QY!@9^Cl}~RWTG1@p#`VN* zb3@FX;$@ubx!0~a?_A4lm^23|?7S@+h$Cd2iR()3 zJH-2X!YGSWQ0MQbQZvLWT&X$Y3IJyh7&p(25)-tKVoG{8kVzmCBFstOorm)!6=AJ{=(WPv7%a02M$ zgFRQj3LK^=khF@XXd2uCiGe*jNO>6Q4LC3rd_K}$a2>%L2HfyAF=a}LuPMt;ObrAI z<37U~1DzX)>LAxwkFgTHcUP5Wxqr_r1&i7qdiWF%*j8&E^VK5ey$W^2eB;BET!DC? z67H&oh7MX(ydt*kH+$Y=0#*?@`#nsj)fqzzvnIH6?+HmOD6jtqxwuRBvXaH?y=+es zgU2}B$F@@xrwT^LLcBD#EH_Z`Gp4ZzRN*u-bs=Y6{bK^qN9D(oC zX-pnj&v?PLgP&l|XGvc$4m#SZPZ0WDU=}cLBD$z2R(S>^aJWBXC)T zcvRVQ6b)FQ1dItV!pT2ak6}E447`u2F>ipm>U$f~F}3}sFfAGJX5uG>aShok;#7l? zvx-lq&3XcoG9|lnBSYW?5!}RQMgD0$3n^eBFOzhWzXW{}@$4@Nfy@yiK4pkF4kAWi z{~AQ!tkFLx1{{I%qr`}H!R^KFRm@^%&G7{hNBIsa_pE7vE->?M42x%dHO?9W6csU& zp5CGFM=l~nm1&3sBAp)0BP88}exFKt>!EO-1@f80JSypNlbu&?rd-U~>>{-2BDClt z)D82t58+V-!lOz|UNtb7S~8f6Q1wetb!mH+cOHa_WGsq6-nt49D^t%vCW61Iu-K?T zdX;M9EYVaJTWFa$m~<*Jt}LOzH$~|g=@&fyaw0|z{D+IJwetgN8YNDNvs*P5xpBkH zFi(3-hX|gp?haI3Jr<}eczuvtSt}1zk%iKzT#E@*W35(Ga2D2iCE49-J!h=tlIJoP zSu9yLmMK^#*Qf5 zQt%Wgcz|)LKReJuzo}Do)G6pUI`!H`L%$I-I|7$pr^a`uL0_Nq*ljpVJCkZ*TgTP1 zt@Goycozh=c#Ol)NJ6CXExfnwq475MGBrvS6YmWKJnPSrve!{hNeX(;E-Lq{dQY>y z>g~n;L}wU`0;}Uqg|_2^iy%_ZdK}tz+`;UnNRWa+QEKFdM>MOaFmopO3>>Cv)O_nE z>dPs=brbcal!rRYjahvylJw)=+tjs#eQIeI6PORj!!JEqmNX1((~N7|$@`H8mb_PH zy$0jLoZ!K1&q`?bsbHr*`$M%V9f5{doS@h|H8&`GZ87Dwn3@}62sb!2BVsDCdeLV! zE&bS;%9_&`Kc=)XMOPHX+;wv*ZZU`c`$IxX$%EkcL9mE{)G^G0MP@teo=au0=1Pir z;0|czywzAa`)H*^tE8!3W|1XFc~{RmLZ|jH_OZ<~>A%0AdJYL18^$(-!*sLRR?x8do z+XKgGE1L4Hd5@p9^NNYmdW;VWt-@nxnSYF1JcV91Ksn6$fvs1I0=|MnaF}qO*T`Xh z385*q)XL4wDN9w{R}uNZIyw*9Kct2s)D(xZcI z%9w6O2PvqhJ4`(~xalyz*1Z{e?CE#2bIQ2V|H#^tG+?A^dM7nC(Ue_;v63ZWqTfbe zF7DU0$F+|XE^u)ota$-7>~+LfW0<&_j;)X#Oi&%OW2ZQ?g`ckVd#)-N?9|r%`!hhF=Qd!V{!{cP6c)>V^o|aaQz(qCeh7YX``p|2; zJqYsQe{oS|A`w8;*pDEIDCqEMmN9S+Qduw`mhg~~=5*Yz>)F@yj66XbR7PGVNYv>M?!G~H_j^=} zEeN-8_1}G{&cL~g0LQjG_jUc2M zg!U7m`Xpx7H(`Vq1ly&KXZvVXc&&(4(fAT>X?$4<7+FvF!8}KxR!J6V52phPooKBZ zD+*C4XhrW#dUT*sq`l9(pezMSRBc@ldeObW8tVv@^(Uf)LrT(Efc=%7!bU62afsZn z&1Z*`YY|9eoj|M5WFRM3F`k@QmI4KBuZI4JhnZC1`d4P2eG0z%JOW%e2#OwN{~D5p zI8!9v5qfcD0KswAr=P6IViwQQ8Icr?I0EMs1Kv+zm#7a37>m2mi*#9qXkZ~G3Qk^( zT=^xlI0Bz5^Qpg!nGu;sCH7!^rDt)+y~BzTL-c5SXjVnW&=py2znS&o$uzpeM{8l& zpeZ*uB<)WKesR8)qXJ-v9l>uDMBjQtIbI)mwZ1gkk>2+Z zFz%*ovI%0v>g7;5spdaok?bVdhW`B*TR9kCX4BMIt|9(C6dXdl=BJo+J=mtEfHgWC`bTX5;@eLix&@}d-Up?0VfSfqa`t6?Z> z%Tns#kxR$1_SUs9mbGLoTX+zM>R?2ebrZF5%^^@1Htny{rXD;+113E3;MdfTxmn-RIDo`tO0kG+<0 zh+Y@eWqax;Z1Jp#wYdvnje&F=S=zJ7LeqEf4LDFTd%ne0F)zkOt^7VyJ@?=OLNeY7 zq7@^>oBH*!$Cc#3v^nK#whyN?TX)}q&X9q`!t%4=pAI6!+k}Iq)vRA`e8$k+0VmT6 zPR?}CuFn`c`ywng%i+#}>&U$~B&{$L`!!kEugS85duCaYg}oUZIAJNOFI^!aI{Kl8 zC^jKUfo^1O{K>T3fr!?!u&0w5l7^!pLCjmdZAeo-Jt$ot@NOQ+JGi_F9t`GA07rL# zqYE^D;4J(ioET&dmyW|!Oho@5q0NWqZdPG zdwRB85^VwGDWCgr^CE^!jTH+Pspr6T6W#dzxhhdbL zr6{$)-jkiL*+DEIpfUr$Mn(SnLl{DTne}(x-IMHLcrOI&OK7pD0TtLY^<-^$8zG2(#~^J;YCxKP27qUVv2sCoxH133#wALMlM` zw1RL1J`M{q1WO)AQwdx71QeXkBZ%mL_hIU1z9l5A01jgXU`F&_qgDW^!F|FyV;e>O z^mpE;3rT|ZXb5li(co5zjIZJS!aw;+H3wOerpbz@L_g{4r-j@_GyYUBvlybAj8U9R zo}ADzx?VfqS|6+m2VD$rMNvZ)sb8yTK_A&lRHGmFhRM%r5b>;YBBk~dlzE=(OlcKl zA>BG2{agjXm@JJm1!JopczQhgrD8;n68Ku8Lx0xQPx$lzZmXIZTF^!S*DiQO^Z5>0 z@*(!gn?1!R6RA3a34~nSM29rA9g3TMJOW~)uBx7 z(KJCzzU#WM;GGeXG=SurF`)X!uR0X_#|ol{soKME(iSzl4mT~n?6@}>8(X<;;SJhk z3?1|qj-25k3NDOvdrtjCH!w^&z&qGW#R6MNF7@-8(PEK_3A8loo@b#}T~|RKUf3uPQmQO@#(9&j%UEkkudYK^^u}u^u^p zdV|h4hIr_L3sg0E0jwVT0JO%ZDEb;j)GgNd@D>z)PdC>1Ra=W#ow9bUe8~6Cj>9@1 zeqHT_CWfTpu(SfF-APhQt@#SGV&LejvJ3BOduYWy zFw_j%r)B-_s#tE z(Nu0M*PXjl(W~{fm^%XJDN?4zCUuH>jgBdQ0Yk5(Kmj)apZ}N->S6c=pwo!g+4&}A z&ZGtEOxr_Ok1$GVedA+Z@JJV8Fd|JqChx}j1IA$I1)mZh@KUt)EHPq=Il(vr9k#a= z)XjOW7<;KZx&7KP&agS-DyW;erQpK!PYT=GvR9aT+Y95yM|v=kg%nyQ4~C^CGzTL* z^8Z$;2z6+hCT2aS;QJxep#M+)5_^#++8&}!69^@p7)LY}qGAfYGivTbM;QFRXCH>Y z7(vCH7C{BY6m#gT2R&;YQ=CFffs?SCF$GS-{%cI}o}nU;nu;mV&TnIiF|C6Nato?g zN=^R$D{)^upSdnUgw_~tR;xY?nap0uqaxHLq6u^_Mqe;sZoKC#?}oQ-+-JE(`m(i1 zi#mW?Qsz`}eObPO`^#Jko+@+8!)I|z(Isoo@~-_6cUshH!OkCBLT%UIt7GDr#S7K) zUdhCTS94BJY5kPn-dPc)A_{Bk)|R=F17%LX^HctNE{aX^>}Pyxm*ObHz#l?TUp5Xi zEs(r2<#Yab?w0M(;f>|uSUKt(?ksx!?Y}@S_sVl$@=Kl1qGBzUt6oQ-@d~XNu`=}f z&;1MRg5Qv@_#*)BulRE@u4~t!2nh7CFzSc{)^7BAFkU55ove>TCr5qF{}*%zf5V?e zt4F@!8-zl>4J2X-(`(5CFYg3$H%`5i$ z8!zz1oR>&vJ+69|$V2sfBtTs~e=ck*7{=`D`B0Xe75(MGi#+dUUb>!_eu=LRwJAc? zm-rhzG+R9vf6se_@W1F+l&gQ_Kl9!4$WPqQSIFf*|A$}W z{C??e#MRL+WMv~>)?Ls1HI3*z|4{b4iWhHkrS&S_!R+jJU*)&)&?;-*daJ})@g6>0 z4!+LEOkJ!dchIe*3t*1G!YkAk+Gl!z$oiqI!s-+Gj=*9yA0Z9xqV&QK2$$>@+Fs=d zEc!rJUPni_%27A)rsr1w-WzyXteZLqr%m9bO;rg=&#y1RM1ifBd&^`_fZxqi{gnZT zpJ%^*UR)A*jj%=&L&aU+ZwV0}g<|u2(K^{aRP;0lqa(TkiEdQOkWi5&o;1tsP|>x+ z*+ND!bl|!*?@5bX9xCn)JqxTxc{WtM)lGS7I1q9+36Gt_5jr-(9D%uzS{pHpzv8cL zBYJT$>-#Mx(U+f+{Y+xy5bRGqImgcD-=JOw|B&ZOej^Y-z6uhPda$-heV+8nwWtCu zJ8Tl3ROOwq#~QWj#B1(V3!ihZny?Yg-K8k0^{5Yi5)ljXl>F7I5Ue=@vvG4dOzgqi zPEqZI1i{L7qAMRQtJ{e?Fv#ZH#GwAwc7AU(G1NR1vsAiyC}!gw^4r9CF}q&wMHO6U zuDMM-+i4!v!nC1IU#xjgF~6(5Sjq8H>E#aMIlSpw94=5u*HDC`Hi}lVIkY^|g-)6^ z4XoTQ-r$we8Hp~flkQ0Idy#oVHbe>sKPXc=iwUI7okf@UDasP)@)xEdnjDbY{ln-Q8XR!<2bK+7Usd*QSA2{6JRro{0sJF7JtB91#qA)r~r7ueS9Uo|L zbrS>Q8t}6FFChFOy~iFAx;PiXL+ za#J*H>y$hm4F%lcZ-^G{xES}Nyxt3A^ntYWM)qzwxwq&po{5$Dy+v~3ej>T*+c(^_ zp|$Fr*I*zSn<;N)U)+lHF{gf;A)|=$D5^o9oQ^(En;yf?j}8xEo&@jywrc)BE|}MK+>`WuYT57D_%4#L9fKW}uiV$||HK782f8B~t*~lvQFM(kJJ}!rYh3##r$} zw+4zLh?4dBjm3?p%6vw2Q6Ue=PR;{_TmPYlwbLY8;}8o6F(F%FE3uA1_i|Z139cjww;q}e{}C~+9VcQ~p;gw&P7jMAM6LD_y;{g}R9mE21rxN%lbE&btY;?p+k61cPf@EscmAN}C zNGk73VoJ5(2FTJKvGe=lJ+Y>bM=KG(wIfO?%aR=l!^+k1=()P!z;oEn&XrN6lsqg^7wiaLpEp~*78u8w9WBa&_xDjohI2-R3P!yIWB)BO#mh{% z!whE5%%{3W{Ea@GQTuesRpd(o&h@D_W<*$aS+`mIp|c&n-<*8c4x3@P(;ZFkub0cWh%sYMe?@|!9ffi5 z#n!4o0HHug-CH~Cg-KD_>SY+L0IsCiEO_JREU`#svUUp^N%dQ#xF&F^tLHXMDNitI z-3HFU;5N|%U^_rqInl3s6LqS#iLTv<6--OG5?+N7ERT&+B&oOo#i-=mDmrVFwmc_B zcCeF-sS0Fjlg{Tv?;={NWNuLk7U&tySf-<+?wp$3^X0yqfCmW^xd93Js z$#;E`FWt|Jm-<)O*}KXPv1K=xxDPI`>Djt^Yph;t4;rnN-aTSXD3-&ZW7-R@4$Dz{ z#S5YNj;5p0vUV?G);ZE#4%A1bygR@TZ<#J4$E?EQ6IXk&F z@SKvNx6NT%SUH-GJSt85#2>H~yF|Kpv(B5=U=9uCG2KH**f-hXsvY(<_ ztK7ODJWZ5`_lu`ME#pOTFTmax#jtdzoxP=En_;^GP5Aywop-m`ss!Uq5Z2XYUa-C` zr=m@o`-PKz-1{Ey<1U|sYv{jrs++It2CKminEqQV23cnh!$t z^JVry@p-38P~MCi-}O4>*~etcpTy@7T-0k=Q!kYZU!%F*EMI;N0xUMmn%58`l$qtS zLokq~{^CR8PeN=>kSTsdC=baEeu%qR{^A#D-JgRqJlL5!O@C@ZoA+ES^0=IQSd8sv z!=th-TwdKkC}1UkQKMl0K*%Zy|@c&X}ab7N2D%bGXD05LUGHohVL zO_XkzSC5EjXlT??(L1`@&R$VWAgVeO)bQk5^4;4TWX@5j6AtB$iqE^b?ChnFi83%J z8!bEsEQ{R!CS=vZ zK?kELW~7%>IvBPg?Uq$FA{lL5uffbxAiW=om7UzlcYWi+jigAd^j@;AbDlgSu|9P0{{h7YOS<}=arvEJ(ma*#-|#QdLqN4Fz7iL>%U|-f7@>*HCVBi@L?B-5!ef!@mci>8w6>r_#^f&td1XjF#@i)r^=g3U*2AB9Wko%8)?ZsM zI@0k$!$s)nc4@gJMuw?%oug^_hjQ*EtRa?T&bcK15L#?!t8(Sbmqm)qxQt2CCo3*v zdaaTn-;2A1&m^7SizYG3C!IfFS+-rC`vJZ2`c3~9w{vV{_iPYP^q)g->d{SRb;gFB zV~9zeuU(D73OUc0ko2~%SXMW{A&mA((~sgp2c>^WyV;)|O%Dv0*MGz~q|2T^VZy?y z`zNJ-4L@Pk0sPpXku32q`&s-+6DPL%E&nTqhKSLXGW!~)13=d`ENVtq$f|2_;(+I` ziL8jx6*#U5u@>?uXhev0Eh^fsi+cni_?pDf?#UI&UoqEf#iP$a)ee-|M}GnpI#3!v z`mC&L5)X^ym*w1mcu^!*$l3xPwb`N#=#C*UdWo>-0Byh03o*%Gj;`43)TRzitt1jx z;ztKz1)Swypg8nd+XH3ssfQg+_g*3408Zb0PTScf^@y%t+)no(39Tp#EthaDK74dV z{iM;AR|bx*xH16UtmfJzk$Oa$g?2YWg=Iq9N1ch(v=Q;i6*$*#Ln>PN-RLtZU$X<$ zxw5wClt8EKqtEIbjIl|VruFKR{4%Ajz7X2)eJ~XAbclABNIfiLL$&w2C7^kY$X?oQs=IW|)Iioko%XkH zqqX7PlV2`PNj+j`nY*bCW2IqUvmIR;+*TXfC-pE@E{#vEO37mfybF@?o>$F0!liWG zg49ZXL0j!9j&IzV!ZbMlN_i$sn~L`R{n}|ed9T#>3j5=$5pnxm^v)jkjPcr{*av5E zpeQc&w5+{N>&<;z+G_*iQ%}6s zpLUT(q~NVV?r{)k^2*d|+Ka_I_@R!bshx;1N7Ixg1otCS_r0l{>VZLEu3%r=QI+qd zU6!>G+C41 zVSG|#>43C4x#@Oo0eaSWyY^y4+7E-)hi**Y5t5PeJUiekM-zu4wZ*xNzTi+&kIQzp zfKp-1-=CD)(;9Z)!`hW*;!-ELRDYOEf(BL^KdwCtt_p8SwablflQ!r{))uddZb}_b z-$`t|EM1+o@!@Hg$xJZb2M)%k{ea^UeIUk~LNP8Ep7r}f378|g_fYn{Jv7K3> z4I~6RK$hmcFwRtOO1mf{yJ`cdYD!maF?3>YSDm6MO6wiX2$RHLbVu6tqF6AUg*P^F z#8Ha0%!tA;VYo`7wEF~P&={rlYM0hPOj4($rJI)QF_DB5ah<8LZXCn3a{!CN10|>M zO>y+cTE%!Ue6TX~mkCB*IXQq)E=W6zmT^HKbdz=U-uyN1@SH0M#1u;&9#uLpt&W~c z2aan`aO1maH3X?n^4q?%D8HWa^&~<_ttKW)Gr=3+!OXN@2v&xrT~_%^Qcn{sIhEF^ z%EQurfX;tPgy;`bK^0DSwC-I_R5+R@JxzIzritGYtWQDzv%71vv2{|>T^rwS;#Wp- zqWlGE(z=9~ar&9tL;HOg*UK{QlxKQqeUeU8kUOE-x^5TmqsMyxK1ev&gTM?obs{~Z zYz&?00B88M|!~zWXoTAX+wKG zk2RA+Eeu3fPXk1|fV!atsyZq}Gf}|YDnt5c1H+=M?_f{i`R5zt zs6N^qomAiI-W%7>`i;u2k{gg68U@|NbqeEgPmS!?*T}U>S6?l;QwfYag%|;;C_E=@ zd6Gw&DTCq;vW826aryr9eYI%<3&2qWpiKF4!vJk2LZR9LT7cref!e#B`%@i9)7V0S zdJsJJnEyzuhA&LH{FmdjZ#ZJOnnBuwpyRg<)n4Fn`9>T_Q8JwOMDMkFW(|507&gZx zX6v;b#32~_T=E%-ris;L*@;;bi&LBdbzzDeruF0? zw{#EJ26e)f%r>hCr3?ztcyXLp9vZI2_Zq6Ut{qK7l{SO#p2RNRAsKcl%35VXEmy_d3kUd3)*h!Sv)l zd%b1-pwp{&d1d4nZ5J%y&=}Bn$*8d)Tp_JvA=XN{VJtKOG3{85!p~pEB1D;3<4>`| zSmMlf7NbN>BHOxTQYWOkjFE$zG1P{sVlKaHe_h;@K||h zqV@)WYm)YdXzPEeZ$o{X47mgKtww#DOt=H}t@4*Uw70s&l7?J~pOj!gs{w7YBpY9d zuCr?$u>sa-*ZOuIPLe_#%+#8ez5sXQShP&YR4y$)6Bx&Si&6E8^krgL?ecOayi=Ca z4^ciRIj`JFryWVPP)@w>o%D7&)+<@sNPHS@Sr$|!UAA{XGBI+nL+jP$E#<3QH~!}L z(&>N*a0zEJ^yhVHoeWlRK0a9+cxMS&a&lmjJvg7i)MFHTdF5O2tgBF7IUMheFjAwU zxJh=3_;AS8NO;)#^;+}Fv9}Serk)^q!v=x2V=3R+BahPP@ zjph$D7Sgx`8MSw5cVO8Pdp8>6g`NyT24bSq-Qms#~OTSWA=?|jC zp4+}TbY%wzq{4CI(x)4j88L|wEhNFJxGA*2o?8|=F{o3E!iIYs) z+}cO{(~XlCjFR>h+Ng~QxKdZJ0!|}aR<6*xh+OP(1M*q&zzVIam{TQfk70WA>7{pJ z-AY(@8`yVa-9XrLb?mt%dhy&^SwpoFbdars8olryrvYoFb0v_lx+c(|=Q=BOI6vEf zMy)&}omV3p2;HfJ1|4gm!Pg?Drx#U9Zvn7M^yFfrc(Kn&SLtwxS%*uF{NEY*_gCuq z57a6sA1Ks@!wh|eAZb+jJ=0PC;MJkqsIme^y9#ItI`HX0rwff&LiHFlJVxEMIDw!# zB|0!DJ?_*gKVGB5_1QYyfjfR4V7v6Buf%|Q8)COXbhl6C%U3;Gl-OOXBki#nutC-m z4X2(gH?k`l^z@5H{)<&cx>iB?omcC|v$qsAxBhCSj!~&&h=T?JtJGn1t*oNrY#lgtpd;gd;n@YkqMxGNMOckGi3u{hST(4CK{>^&Q%or_ zV1o`*vvp{5%37-B)sqvPI-FRm!%0T|9ZXN(fxV;kK*y#C0RwBQQ!kxnq-PlET=SME zfn}uN@sz~wH7m#$>-|`46fZU^=hw=T7PXeT^jb@O2CR{mrxZ~IN_1MwbXxa&b)@?n zbocy~2>3503vYsge6`O18ke5E&LSJAic?QMWwh{A zjh=qmX24nDO1*GPl@7N$b-2wU&CjCPptaqrXYVkIciQx{uU3bz zTci)@a@Vt3ltGdo(YZb1(@~Dr;7k}4OLS1B=N>Z}IN{aPr(6cCRZ#9L0m0MqEdo$* zBA}Ou53q++iX;>oK#ncdhKY|YvX=62VoZ6mRJ&JvlAu%k#Gw3HiJtzF8L&aR{)jqe zJz1M=K%W6?6qJAaBZic1*$7Od|EFB&!BK-8!;AYdePo1XmHfQ?=~eYIAH z*Ny7eOQdBJ(BVNg!DFyW9hxjU40GzRU9AqoYY3{@i2ziXYIQTPd%EidJE7HT@a|zOGg-d zjPmN~(N#Je1C=GT1U+f3)nSs3F2_jlkqiecfx~oQv^U;pZ@kgM1e;!ULZuEfvZZ+| zYMFIlq>N^pvyPRW zZ9w>B!glJ(83xfAI=XDL4O)c5^ldA-gK_quWuc=D54ytsN zc}Cm!7*+3qCO@Y*RludE4CKWYz0%@J1J>#=-?C-9qO4kf#2~r6L@!#&}kjal*?t&7KDpdYW$tDP|E@I#vp|3|&67#?Ai-yUAv zs{HnFr=AYh|H#(5yn~TGUZV1E&#u+WjkKrBr}0L{Ssk8?GSUV^RkeEh=WGRU&#uwa zr*uYcA7W#siL=rt=ceZvvQgz`hf~KNpx29dPw#j{uw%cfc0A}=l|qd8r9p=$4S3bm zIvuR|i@`upB17irctHjS81;Xy)AJ2RBi=i!r%xF9s$CBQ10__z7+3#>M^vjc@)coZ z#!^9e#0iT54aTYrc-%_)_$k=jp&(to_!e|gzn4;-TB;p>d%RtT2~HitYdTM8UD`R! zM!KJ!E|Dq)8KJG?(iFiFhZLwa-qUG=4O8Om{6DSiu49OV5!XS=)r>0uYlW?`mzsQgpI!V_JS!>q;N* zBQYFzGHr6E;+fKByV3e_FKd%AEhkeKKk~O5_*Z~U49rNQ zy7UV-Pr9sN#0hBf3>!Vu5BU`eMx2<#LT6-W-fierxOrlNQQ%^s856T}lsKt^(X$i9 zkObw&7=$baJ}wH(xLE;oP8<1$rTG*D>^71$j1Qtm^$Ry=1o>-Vd`K`G&1D$;ois77 z{A&>3VB;kAE+@~lXHHUM1$+x3gh!mTf{hmW6VB=Ro|DrlsH1>2UJ| zonXXCFB8*R2zY|oz{iNsxmgfy9&hyXWF_M^LQy~D2kBQc4pDiU3+B=zIIU%3g3ZWA zkH^Ov`Hjd|!c}Q=x*?%=G2*jZ;HMwf@!!RW&u)odVB}-OC*QgLm3|N?i>`f ztkB-5;9_FV%?jaW+gT&O82K&mZHDf@>tpS6r>0NNykqLbj3GhRP%lSjzpq7lf=nUD zklnjyTh<6N7j7OG>`G&+a-&U@J9SQ~@wu54dQ?B;htLD&1uMP^cC#Sdto|2YaozpU==~a;LGU!yoNT!W53c}4v zQAU0>zJrr7ZSpkTpu^3HRYpNAYnw4`P_Te9@k4n(1tY2(seJOp^jSAuq$;=8>E)-Q z@EQ7POq`<}SVvVcwb-aQM^>K3Oqgad(pa7%?Mb#7=@J$)1s;o1 z#8A>&1tU(Ohcj*#gqz1y8Tshpl$!;}w;K7iz@L;kc`_wIXLPNC5vLkio4Y1V%bjZ2 z>!>P~?}>QN%);z2%$qKq@=;Nb0vS`PgQ0vc7SSW{R58j&Rw%rP_p({L36RIsAhVgacA5d25D`i~km{*&o|L7;;1gkW(C#ti(3_h8^R ztG6uYM*TX*N8GBuKqe{a`zFRm-U>m}3A`W6_^4Zz8%q1WopB|7h0`oKW-{vMLvnqG z8+~X|4$;CbfdLB4`;Pc6g2f0#zQwQFLjD z(LPSsgNUb1Ftb~6+D>QWbOIB@f}uf6MhsD(hPe-$t+Uxuhj4h0UwFi64D~QwGbs%Q zsD1hwqC8y!ggJUvD*}cnPgkOR>i?y@hJ{R+XefV627~n*m^N%ea6Uuu;&Bo&aAv@h zY7oM22B069QDJtA3PF4?s-fO*@NK}Kd<%Tvt?@k{xKLrvEh<#qy21xO;7`2;e(it3 zuVLDR^x%x&9AST8QTU#SlLXO|V95P9#_P|uVR;cF0)`i9 ziik^iF+hMAKvT6E5HwngDI!LT?CQ_j)S^u-GF<=Gre5n!t@WnVYO2=eQp9MvHbtrt z5mw5zDOHP%j7_fhL3{9{O@EIEy}`>Gpf+@dJ_4;MHpW!8l!B zuL&tDO)_@3Xu*7$X6Q&TCvA5JF59F)<(eb!Wn0TNbQ#bg0)~#q|I6J234bkT!c}Wl zNfZ$>20l-tpqo6}*QwfL&sXSje~&J?owowmfM1tek=3}sSzNn7&4V=m{c{DZ=!FO= zk_EbMUkjZr`w4H+B^zWE;~aCoxl%IvQfBjFU!7#cK?+zQ3pj{Ldd*tC{51m1p29xz z+|Vbj+?m-5V@#(@oc|3&qm?_$hvAnc(kgh`r^|mrs&nGkkXE)c409*u5GZK6ZqzEz}%VGXQ6^Nv{ zigxi=sQiz{4pj{_fa^v;6Ozf#09H)pq2_^d*bv5zybde3b`{nMdi*&San>KSwIDMp z%60t^jSe1OFZFAjXSjV8G#ooL9wdhiOR=Z_Ob}cC8%)jU3bVdnUau7e8qSgB2(bey z-J&Toe*dXQt)I>#&Vf(o5XS#+I<1_UW-G<%3J#Gs`LL9EmsSA4Xfdqywr0kHld}y zWkX+UvvStXJX?pfF7*>bLP)qAhqCdEZ*-`j7_hlE3uzPSFbFPx8(PCDt_ZxPdjE*pBb;mOP9*v ztX8|$Ty}deK3~UhTe6^fpZ04FIP+ER4fMXy(3r^GNsZFBd; zFw}b(nhG_s`hdvd1y$5~eqkt{- z@_D^uph1T#Bt2W?rN{Vxz1PFgfIT3lcZJj_AkR6Zhp{18ZanZRh{g_=c;w@3xRxEj z_&2B9*PAtAmdE{I@KMlJ?@#|mnKk(0rE98|stZ*|KFFS8~_{|1g8aX)WtyoYeK^%^pgK1Td@o1KE^qPkRv1Q&h=9@j}A|ug9V7(UXH7rQp z(J~mQM}*X$Eifyo|A~P|F)^<7IXUhx*M@Oqj&@mL-VD%smH*h#?AL_etM8+IU@*5r z977Ggr|*v?aF*7W)B_yj>lCm2W2qW2_$V+8UIo|=SbWi9HJi92cTC!kTrwv?HAl`zclR|Fq>eL3j z)vwF0KDv%)jJLm&7%9~3>6@*DQ(toZc;i5vBV-~G(d`_1 z_WXD^wxm_W^}J%Ha8~%KL*7FMP^jM^!}qso+!#_$bkuI#V_RSDd|Kl^W?zm;JLY`Yjpg?V=R-5f3X?bi%dI>?cx>65ECJuhd5GPX1d5= zQuJo4uAfK{PL6oG$Ql1U;cz58gqB5u3|&CoIM8GbUg8(2PBKV!1;)QO`B*V~cA{A` zu;+)HNC0`XzlGZCWQn6({)xtpQOS{I$9TR_xLQ|G$e4h;ggyB$?8L0)E_cljJPcU@ zhno4`wya#k=Hg?=GB6PF$I7ZkTl`;Dx-?YhR2hTv&Rl5yTbXoQtNDzOE zF3G;pv0rvjL%lAIf&HT84>`qimlOUwqT@*aj&P1N*O|W;k5jt&du=V>@UuKhC6;ga z@zTjVt^j%YdmBg|@pIkqW3gU&@v>Fk>oe0Kx+7ye@iO1(&`Zn7S^;f(&Cn9@e>-8J*nb$QnM6 z!jt9Tt1})O!&PR;>Bf5@#tKh1ScB`TvlW`IN@&kcHVyRfBpza_HXb^Lau>3paz9s3 zHzeryogP6w2$hfJ98wc<@|bhgYtSF?m{XlkFYm1JY`Nq4K{Ax@1#%?Wp#6Q?0VPL{qIX+x#~KfhYEe=9 z+zp!G-5x7v6+iajiVW}b_zINra0R=HE*IVB&euz{TsNN@MeNagxJaMJ50beQzEGhV z`BcO!#I%H=FlYmd=t7DNbi5KZ`s(EdbW%6FEoDXKHfoQgar&G?YXo5tKGUZwSPpj` zhn~B-y9EAA!Q8+C|ESLHasuPM8AWGC+p&Jl*QE@@|4Chcr%jg}v6B%GPPuU)t??IA zHeKg*640#6KQ>r-ddmJ^8qlESoJ{J{7?#%c1FgDDy%=ObFAPu<&HvGWUacs=fK)8V zfIdV(&vgGw19p?*h{u3-T|dw%ODx(04L}6+-2ZEGLWifV$@>4ijE$#5o^;rcADp%F6nScl1_3dye&-T*&sRVb- z7p&3Grn?M&o^piehd)uS@chE~^IcLe?v@&YJ_W>HY||xADBgC)`ErG?vp6DuN?L=~ zRMoE156!vGA-0yguTGXY>g69Kt5MJ+0nCWKR8rTNb~4ZykRZAWD%+_fkD1OG)?*D) zk(Fc|F`2Bq+xRC^%nTpk@r{Y*T@0rS^yD9neb8!!&6^q!xU5V`rax%MZQzN9z~R>f zXwO*rqOw0{__bcnKU>&dShcox;bKYa#PEY|Rd-&?p^&k~f5zEvzP<=heBPw_GhTe` zcdd~2QpkRtB)Ke~a84TUYe3xR%%|TQaxQiMoVLQ11D=YM@^K{OA0*wM@%Tlh-&2iw ziXe8X1Om(y;krpleS4|`PdzQDtzAraPx0KRK86y19p1)Sx^nT7#fukF3ksGa&yWQ~ zh{rG%ui)1+5NU^6GQ>`yj~BXzVOD!5?zVoeM)i}sr?SqbDmS7rHDSr5T|Yt*H8UJV z$j~J;-To9c7!TXY)&SE~1J6**SQCFKX$a!6`Lf8MSN}O~)EYkpI^`9Gcomb6#Vew)EF;bWDxq=@) zFnw)nI=+x$KJNRCVco9IF=~a>tbq@4N2rq559k645xu1ljeUe=`=Z4Q@rIh2Pr>MT zd?2aid_)eh101Q3Dy*EU#dVShhvq~4@reFz1;hdwo2)^r7Oo++jzZp33gp9sDm4pu z)^+%Pp4R#h5#9fM8s&>gV=)$~YgR2 zqkdI4Go-gq|7PRuiB;7UE!s403|3u*@o%1L?9v3Be4k(kWa4~@$-@clD@j$4Wpxc1&Y|5;5i#;wt(>yy zXG&%qBu|e2zau50!(sfpuE$RG$$z3TUfCE%tZG*qM#C4kS~R_(!yW6j zest88r&2)*GFEuHd$C!s1#?%ifjl}m%iWK{NDiw^^YJ}7PRhS@YCL7$j*n=7yMR4s zPeLW=Gh>nQn3q^_i#+-t8iZGLO0;6O=u;cih6vHT=guK-mUF~Ds!@7O7il_-f1df+ z({Kd@S4m=dIGzRyZdP<2!9H?ZAlExl$??zE={$_GrdC@ih;i5Of`aD-vkXrX-ELj- zjtEDX=YD$EKpCvYzge$$YDN=@UMqCIgw)|gg02OP$4sBI8!xPyleI(7$=BZ@1v$%o zbN;vfx2svYMr04o`Mq2#GI*!1b8>Rzo=;HLzR{ow_NhAlPv|<|7v(jeNls6fn6)0| zLQa>kBe|}x59!qMy4rMU^h9)>yOblv7e1bxi|6!s_$i{CkTBCYZRJ6(x&-MBon&MgG7~bbaB^lh&d80i0d43lS8zCG0Xc-kHRKWSffjG?Mij& zuo_*gD68+wNB~7(faU+da5k7j&m~8i%6M+CTHWFe912yI0h}9bKtda2LP|K_95YGY z@F@*%hX3fh_+V^ME~u`iN7kKrfv*ENseYZ*f*I#|B@gq^RN15sAO1esfcIQ8s*LCL z>pHKl8eywFI<7Ql<%1N9yO&AJ|Gz_%d$BYx`h1L=YMe03d<;AB<(j|6DO7~QyV zJYWNQ@hu7eh`(Jaj_GaxDD&g~0}044lU=~;`0NN!=*+V?d?VE4LP9H`WQ#{A`_1B+ z3^4kziC$Bk8o1dc`-m4R9C9;kNI`e2R&p&hdiF&t8poJG6>=YcsX$;eOH59ASsUR zP2iUZa*NmNonL%QkM=Y^1e;y*YlM^@$B_7t5>iYhJ1_*_!m}Fh%`L2&hA$rC>65n+ zq}*?f4{e(ojSs2A*Zr(oxn^-4$yOS8(;DqfN*5yum-JMuwt>k zMsgy>UFz*B6EPaD@6>5WjJz7`Z!TTA+#_#vys$zWR9Np}Xce~YGLRMb+a9`ZJa~b} z*L5s8B9cZP(fH7a6)CI5Q^*Ud`SMKS-aV}NQ0xNWYlvUq>uP6IXnQHaNx$ zr3g7Nv_vU1OHR*diWju1b|a4?GqgtTaY_4BJ6|)$wY+MqHG4FpiIh&l_|T-rjbfrR z22xiTMff@CqTG>Z)@!yX9+4?qvUKGl6_)IPL~BHQk*fo^$IYzKq~w@Y2oHXGY{KbS zGB>JI-`T69c=07SpW@89yhh2#MTGXtxt4F#ieI79oVuFHu|}&B9K18qLR^o31QZICmLuR>XNs@&c0QWwY#}h}*dN zFiED86ywZhd_K4|ZmS63;(#Ne6`HFajs%yiz%0olN^s2E)pmzy91aJU)ysAqYO^sK zFDkbRmabT_c+pbK4Cm`6mtpauDv4oewdnG2lP)=MMRiub;g?P7a8k$&u^!og8(o|N z99fE#qo_?0@)dQA&uB*BZYv@KD8C9o=~91;Lc_;BY|fmWl2C4RX-o8tC+V3MVD3M0 zI~#b4B5GE^+%qMT5i9EsU3z;Ui(dAmJQee~`duZ+S(tjel!v#uE=_7hocvsRyE=yV z8Ef!83HlbCD>4CGswQT2E%p>c2SvSWy-oFlSd z%khSeL(hueZPkJ~2jVybtzN#g=3=#v;CRT6c^z=%N&T|V$>XdY@QC^Z;JY~72iw~#Jlj3;1Lh~DX zd`~Ipy$?~uN8l8uzbsMF^Qkkow_DZYBdW9hUH zh03HTbr?S9xf;DXQH~?cF|Q;grFjM+KC&bfx=b-E+~fc!C-*(?Q5c-MfNrRp$Y#l} z!;SSd>itMH%$+-TN@+AcvLh6_G~0mqNQ%^Zn$BFUjqI^PpU&WYMi^Iq{@m&@k^^0yRMd?CsnTq&s^E04#%JoT5)`6y=;I%ZK~uhikEb%dc34Wm5w}It<7DzN?v}*20ENq&dm~< z_Yyv>;8A6v(77znS*OHH>Lh3kbPVZKczmdiXevI^6RJ_^P3VqHxq^Bni^&HdIgLrlUo6597_pwm?Sm3x8AiY<$y7q_ax1Z+ZgQstTErm zoqfqYrqdd9)~A@D==5qPu6J9djlmOFiZ8*(bZbJM8h?@0bBA##!x*R%@=U<#Kng5!;xc;~{6_a4kD zpSx^-iFTZmnghae#wJ387RX%fL#`I}E&Q-lsjhZee`|ur`G>_0!Z6Y|fDHLA1 zL`nU}g6otbui#+0-Jx8h)=DkedBuUJ==j(QE$}oN=IrUXvQX|~{S-|)btFU(Q>Q&VjEuOZB zHUeGQZbpx1)Ud&(Ysc4x230P;fF7)cA-v$>zU5(S6t`k{U9iAms8bw(IqFHVQj;0to#mQx`tiaA?f&t#wTP%aVm zc$vWK6E>K8gs)eECPZ^(x?AZ>nVcX7&IQLHGK?LYXobT3Eza&pQffGSdXO0TJP5iv zm15F^4I7?WO$59O@hj8(_0XS2p;4p_V26w$6e(?}T*>jdf(_we%^pvx2<7s-W^My` zo-hiv;jAz|u|#|7op&a6ga+}~SIdcw&&pY&^k?2(xtPOl3McD_LSA1JKJQV76F@}H;m#O5T;zz{kL@yiCQF_@+~F9}FN z967Us;~gSisePd3ndJ)O{MhXCsS0Ib%)6yz2pe@fM~HDQIY%Z}SW(QpYgW~|ZOk^1 zXKcRsPI2;agE53GXPj4b#_}3%nDH=x-Ww5PaE~>3)$(a^+zbp~{{<;a9ntt1%_1`; zSN<&dS-EF~Iz^c*dPU7yxnpC?nT%-5Y>_@o?mDY8F*iozWl1Z4b=9hi2maWG6AgZ- zn4F52)k$7wE2FHz8nSYgSAvUQ4{csWrm_XJSwm`Yms9>tfp4%oSIw8rzpO3#nlPzE__?d$l4mC)T8Mmu45SG3rcepbE=zc zi0IN>V0P*{U1%=UTmFb*mLl6%K)kG+1U9QOerAnmoaUU8%;SK3%IRt&g{rskzp^+Q z*Y}mo6>O+ zswpv{6}_S(VIFQVmq!h%-Av48uTJAe;b8LAs~DcJX}*rrmYy@(>!c$%s7nL)kxC>{G=5f#D(Nx||3@@FRpZN@s}~|M;c|!sd?L2=^Q;y(;S8At-@=uJxQ9465kvu##IbT6l z8sHQuudyO4@WWbo|H-ux4i6=nIim3yWuj$vF22^rVDcZ}_<@s)Yw?xs10?wHH;D}R zO%BdTDt?}H%;dq7$iQ7`(5fy(4wA#1Iy~l>kMaG~vs@>-lu>v}M?Cx1YeXByv!uz@ z3XSt5z=rVPFpq~(&u}}H@fi)0ztCBU&1l^<#}yFH*%=*L4|mYaPCU=LuohRzuKsc5 zde)5(Tk)H@fHS6`Ps^nZ3T{vFjR%wKGw~jsqtE0zPs{OHT7jXTh4=8~uMaI=t#Vpw z!D0AJkFnx`j}l!LjTg2n2J?IauiH5Svv!B@Ge#`l5zL;=(){d^V_3gv{ESb8y%Ez7 zc4VE1vjQ_4Uqmf`2+_OI!9ABHw@mq!V#7>Hw|b1Bvs6t)-_2dyX5ix6_ z57Gk_W+}ppzj*p|f!gtLaw|~Lvc7@x&hB^D=i!OH9tD^#n1h!DH@SKZt zFpYiIiJ)1|n)X(FBlgn8^gi7`kI2%2hVtgSx&29JM6bQe<8!)0d9Gi|klx@h3Qc77 zB}`Uw8^=FWAv)(e4#fvX%9*V`lMY2{R;^xBvudSl9y0p4CwO`_tI;l+x6KJHq3raY zdCl6utYvuNo+Y4M32+?L3QVq2@^gC@?pf@`KhqH!eCfgz9xG5c%pH%4scZOaJ-CZ2 zT0%LOp22t59eRo!E9NrG03!#l`3xFJd@? zCiD@_$B*Ol)$Z#ReA}}@6R?G!jfBGdBQLJpGC2~s5HB0pMZ6cm^AdLv8-O!|zB2L7 z{GV;JB9)7)7F@K{{G=fyJCQP*?Viy*x6B$ezjDSa+8$dA<2!b5a5E zx%K$!7VyoNRhObHMiRu4n!8)r^K*+!m)9#k?{JOJ?G{P2o7K<2bD%i|a;})sc`kN@ zH)OwwX-3;e6luQP=2Z~As}}PtR#HK4XvfdR9qESujiP4duvbxlp6jCVbK67V>;E^3 zI{zn%qVahpqVxRRk@@wCEj}+TGO{{}s;#?{xy1!Dd#Tzf5=pe~q$+M8$f~|C5kJoo z^|D&1ThB{~w5&csRs4c_5*Jr9Nc4I2){us+(>8Becf+)+H*S$cIHLBnR#nFFlZQFA zl}TB_5w&MDsWN^Z-f69^9IsG`msb(q3H;)ugR>d<`ml-agJi8#bpmMqr6OGSrum*$X%5^s=9=rSy@wQlnz;A5aux`u7X&WdykS&{WH8HiH!iEvcuTpn6iY$>yC@Z4mvkT1V9ukyt3H z$56dPR4qhv2URnoQC8RJYBC~rOX?{Js+WsS*-WaEb)r{R$*^Qv*o%-8luyYvQNAd5 z+?kINZ0_3(t6h>OIy7@$a$d2$5Qxn^$l~gN7^dOT&td#8j4v z4q2Z}Vk+@Hq^f>^=$k}jiEO7dsKob-qMn+32eo(M*HKqjPODnDXxh@1&ZY9?Dr)a@ z+UYky(GayK7wYzfHnlGu$bWh_wPPbt$w#}3|1A4->h6U#)=)`+OQl8A@J%C?k`D?_ zr~Y5qDEg%Xr&IqgL_S=ANnlb&(Zv^bh@`4NO!Xd7uj&-Ah4@Oy3&1~VxNcumBHCnq z;saDqif&0ik$QDegXly1l!*~)Z?=Z6zyA6yU%cV!X&X0hzJ9ZWVc&#KRmK;!i;619 zn{XY~yG6aKPojFiXqNTy)B%eVq8;@q_Bei>#M^K=mroBkN-x zpnBu3YT2Bm>TXdc>!T=~Rh^=y8u2N~PRj8NM9;!n7N>sN{70OqFc{ugZGAKtqH9SJ?z1E<_6v1kIZ%fTZE(PRSb(#DLcL%o*Xa!gh+%?m_-ajpQVN-%`l4?hJHXecGoXNPFGVEIW4PqP!%aHt4FAc z;dCJ~eCTjpUm3x#cPw6*lr@g(a$-82fpPHDuY^6*bcqRxe$wfA3lm49O^h_{vsM zR-1i8I`;EUQ3rfD?Uu#1YJu^Ueb#VsX>IN(yhO&Au<=#45@sF_;OnGS3He=n@;m5M zyFG-GXH~t()FN1EZNsXjU8_-hjA}Sjtj-;mdWWhVxF}pPO}-DVq)1eHnBS(#_$vH} zIog-hE_Q8H$o4h5y~e_q$l+@?t7H}UkVAyy?Se%M_|+)$#A%-*!+^M?rotM$$b7MY z<7|zRE3Ns3e81cO`RxNlRGxN-1=(8np}Ja;WPNDiZyvh&lTY- zhn^-r88&pBIIUwy>5v;HBsP3;-L$JVZ`>#@d}&Zz?CKbD_E18TbM&21SDm45(E~z8GS4Vim!1Cc1QTImP6`>x{ z@kZX|;UCzdjU2TbZ~l}@1L#P|G8%ileb-U6cA_;V z5jtqVJ)RNeNArqH{~fS>3pdJ&{68A|_k^gI>`5TQBt%C?Uq&Kwk=nZLO8CnkD<96+$ApVFg0gHjco2i^G(^!?UqO%gJdyyiMVCZTH?hW=?ePx_%JV z5TW!zPTe^dtXykd_oIn*U4`E+_|xT&{^-$;F`w+IzUAW!7A~BdC==7lqo;|yxANLT z9isiMyyEbk-JD1bCHek}oLkI`SdNj79LgSXi;|M^G!tE_P2uBf`=+NK9RxbiR&B5<()%1hG7y68Y z-;`E3HsRo6XmJsDc=6Fr&0r;fU+5^lF+wE$f5E|bl@UD@=X}$_cgqmV zLppXt%4uk>SFmMCOTXga-yj8{*}z*IgYIUJ!4?t@y-Ad*z`yU{O>9sr@TUovH)!u= zLCt8`=P>MSB7<<=9df^e-$Dk-*3cmbPp64K1N?-8f302PGVMZr4!*5VEq?$a6yZTm z!%f`x*8wlGP2YdJkrbc^pXt!wnjyRz_&jvw5Lu6o1gARE_#3{!p}(V7b5Kj_fk)hPldYCP~kA_;t)*&o^j<7)6e2xQZ%`=R5)Yni%3w6HZf-7}98P_3?Jn5NZM5 z;wTn9nm!N1GRHMKwwGxUi<_}vZL)X@n1rz{5#Xxy6Cc&GvmuX95*_T^rUhZDem z@8Ib!ja%D*pK|aN3{*$CW#zhN(r+XPuL53dMn{RVN9LdWCwGD)XcsA#9^_6zD}_{@ zv`AL&IS&0TH5v>dt8*7R_pKT-UJN(NFXzfS+(8x1&$v@^9{6962|aPojnd@-XH!+|r-8EBJpg>IW7mDKpN~Ne4*m94LNTEZ+NNasN%S%`1`l)aucfJ>3i#;`en&UqIJFF(|hq)zJd{G6(+}b&bsJ!8bVg_FhdMz61E}4&DrYb>LJnc&CG>ZieORNTA_ySVRWh z2g~^w{EUO&J)BX?8pi7lCraWHF18cj)+m_jd0}OSK-3PxK?W4%=p8= z&vWowGFp(#mAuss{?^qaS> z$)H>*sM%3`TQ@1#0$fjo0HU#UJK=4>A9Cn#uBY)QlPJ$MF1I6O@(6zb{1*i*sbZqPhh1Mkyn3ow!WD{6hf9p&M=`XNoabt znvb}K(|s9gfT2Tb966$d@Y!H-b=gg%*h&Le=Pu-*4AHmBG(&g|Z27w*XltLwtpi}F za|{|!u#Ga}nqr%qr~z^!H#>6fYbP8z6uHg8x2KZSP=^NBxV*JXLcHj#yT{Yqh_vlNd6+IgZ6&-M_?bnBzh1PKTu3-F#maZBL%!PRVvtiNO;C3u zsrV@P4@bc_>ouB_hMW}+ep5S9?*M)&<5;QPMIOs_MZT*qchnHW2H-a_Lp1iy7E;g& z{Oc~9`aTDI`Tw7Trz=QKKX6x9-jxI{^G^=H{2$rIvn{#AfFj>@*{~}~IQl;S7Y_Xn z>Py+0@0w!oV0svk|CVFWmzjPzQa}Gsj-V}_BK@bliK)R3?M(?O6~|@xbr9E5W@n3r ztxn(xhki#p;gDTW=HT}x2!99oYzJ>?)i|aCtKeLXBPP*U6U}yXmBg= z{SN)Tq`+DO+%@v<=pe-(13%^ruzC$!xl(_@pPYt9-H?_=!N&&QyQoPw$N@9NwN|;0 z6;}Ws;xY(zb)J&HWn z?EUpVjfWq=6Wyc9P`M`gdXsLDEAzrhj-VSd8kc_yXE>hS*Fg9-;I3TR-l6f_8sM(Y zns4=Ld{8-XSFU^+^mAoXxD^fcj)HG>YX*72UPu=&a-L{u*0>yIh5w(pt{>M_ZMG8- zM4FGnA3Nf9AaL>+o&?)74t`gig00ZQz+ZImRGY@-1wi3z4t^W>)gj~bUm92Q*RAc; z0LH=(9flnljpv|!=upSdK|6>Z#n5r4r#pV!NjTQOLtPWY1no%^0|j<9>{52TL*Hl~3 zhkS&b4TIg%8Fk1={LT@yt%Yz5mZAL)eg_PcM+kh;5%@!cZOc@R%fHca4t;7zS~tkA zYL1@aG<>5$<8p5%>RQI$+(z_$z!y36ckb4B&I#bP4t_5TR|g^zz0&F8A9pDf@drV4 zlf#he(e$C6z;AZ&+Zr`)jRF332vUNh#YZ!QCx8ow{?>kt=b%06y1?Jn?4sY3G8XN< zTwA0r;-aplOsZZp$bG`-K}W$oRU}Ay_FD)4TE>OHkMMC9+(9^sVSI%l=dY$-YG_Bp zP)E?cWKgIaxNBK@SEHuSK@tsfb=hrYBnOIy%{Gqh{u043#Tqsbf7u{(72>atVXo!p zw>k)fXTw|<@=PqRJceE87@DF;gbo3BUC8f*;p*rFeveTcyAerCN6H%ZZO78v7>b!2i=R=xa5Ew*Wr@`H+WBiapjx_(tIB;!nARiG>Q3njOT^pCTDn)2PglyN+@y?7Um#+@nOB^}(aJE~$XmDK>exrsM zh6BIU#n3|dJm6P3_#NDhjkiyS#$mJZ1L%k4nJMyKK43_u*=a^S8$ z+lsn6(Dy~Ih1cDUgrh8SUF4-Rgzp9}mzslQJsP`-ag3&v?Yf@WiqNQI5g7i>HXeKl zbv}yP9YHsj5ZVX&{SN((LZ$}(Ylr^sq{hSGE7D6%>3=l#FW^XuPCxQMnhyJDr0ChB?;Vh@&YZ1c70H5>J)NsTO zJyn|%`FW15pDDg#!^Rt~ykgyk4V#~`^CIWuJauV7WOn$e*22h-4T*eSMA39; zwgH1{A^BW}mlmFdhKV&LkqO~5%SBU33*P@UEJc$pEGs{F@N#tDlh)0%~ zTYx3SqEV3xmilRVgtRMbK&lRC*c)Kger466QIUzGS|u$=-$NmdArWWb8}>^h=lW@j z$S6xIJlZ0AfceBL@}$JY&eF)l^IGvQv_)XpKy8G-k8(Udo-jsENnCtT8u@w((f5mV z{se!k^3liYU2~7fd?cyDJznI?T=9u<{v{fZdEL&(D?}yvBT{z$qXC?c6YkZ7874FW zjuqfz4m|IMuJE-0!SRcGfy}1|#m?gVqLf{r5)OdJ-Ga&hW@MJ1vV!da^z4jR{vJs$ zr(%znLuCAY;yFad-zSTPTnBs+=P1)o0fcwlFMptl1AopcFeG04@z zT+#VW*}sJWnO7K)d4=o!6%}3;py;6h`bQ-06WYR~0Sw3e6$~x)ryt6WdAe@sN*BG< zuaBrbv^GG&T`mSDM+k@B6F~o50R7%7Do^uz0vS7QnEK8BF{&J@=)@pkdns=x_JP*ZQIO z=>Uf3JPb-d=-&&Vf8U?pp5jlRlJA=Nb%A}kKZCtKfPPm1{rv&-FDo4WBWaui58NO0 zXDAx%ub`+PfPQ`eeWjb;^gmuPxFvvr`_j|LMUMy2?{O<&*C79-4?T7n>>}<$`*yEj0=O92XWUuK=8;sIS2ce>2PA92F_DBL$5 zgW^m44T^KucTzP}^IoKqf0iW?x~K1=*& zcBE)#alq_Ve7}D*i@QZ8oIhfgU3@Y?YrvQuIZ5=L6DgiKlCAP&?#O^lAK4&Uney%uK84JD5RFgzNdpi3l5^G951 zm%JUo$UWid=TW8p^rOc5D;m`(((@4MQMU*1-5J1#2i#{N(xZ+C@Uh(<`%1CpVtqL~ zpGyNWq;!eD{?az!r(5DH>3loKEfuIO7ON5+_dDRK-l*Kdj(QzzQX5x+4H`Wrmvp#Z*j5WA1E<9FHwe>ta3 z_Lp%cP zQJ!cPjkhC-5*%Vr=o60y7`hM9dLlbwiK7Afj|a#(2^sUPv$B@kiT6}P*8DtvjOd&U zgU2uPS2TX5zoPLMkvxxs<1Y!&vkiD1J_Y!g1Fz{ni^>F_tRMe!fI$ZX4Ek8q+z3Y| z@VNIFHerfC--OG6%RL~EVH3EAy>d1O$Y}>2wZw>T<=eCD344jk%e_B+8?e@e60}SA~#FOw7KZXqTgT!%!HZkElIqhiLq=9J`Yq^><~`wZ)8$x$^I3B44={-P zTp3gdMs?sjMDX1hXCW(3e>H&da6m*p5bdK8$;mN)zR8>$o(N2?06n7PHGJ~Q06De( z`X}QYkNf-C=lIFHMa!*Ny-a>qG~OI3UN$)c0fT)Mo(fR-p})d2hVNPcf6qX!`;Fc+ z<^-_GoFA91{)}q_rKcIE-mw*?7y=E(rY_xwGPZ*Ey% z%r;;O2AN-?PMH!QN3Q6qEwS+yB-oUI>1ay8bTnl*nE%Dch&=&DJQ-j_4`j4i;+zL@ zB|jw~5>o;qaaOr#`6z;+tckPao{>#B@08H(O6H z6Ww1#@TXS>@GS}8+bPl~Wd2WoG=TB(0LBwA`YZT&qCfq^06Cxd%Q;()p$+2U^CGd- z*$AFr2Amy`0cSV*+i>=s0dnpNumO7~)&@&_?>tOnX9x8B*#SL&_Q(E4l*jyyC@=Om zqFkO7v=On?vH;$d0ldutHar+0=b->O`+zUN*B36iJz~!+NACJ{NBLoY?iseo+$vAd zGbZ~p&X^Lw*Z}k8$CFDlwgDe>hW_+N=Pikh=pKm7j zriX9lJg9s(+w_^21jxDE-}ISx0KW*^(O<+#Z04>2=KBMfu@52#|IGIS_}=&Dn^h<> za>ky;{eto598r7L^Z>ppQJ#^L#;o=J3TIsvz$j1of5pes(X+T$yaw=C^hABOyck&` z?)VNSjoC;xOO726?`$}wa4+vg{x;9%9`n+p$9(0(ci=d4dl~KxU_h_>8q^N_HGDil znY}l_(EaYZmRI&Ztbf_b<5 z8#M1=0R5}}^r`a(`!k$Z;LmU#C!?p!&I_24&O@jNc&wrqwa>dp;qc$%@p%E$>v_)w z7<4i~LBJ@OKfz6J`af#VpG*xNgXRYqG(W(g^8+G!zF$P;GZp6tB+>cT`g?qSfI;U6 z7?dpb@8V=BKU3lHI2q8#$xHkVNaVE3u1-=bbLhZ1?-u} zfdwlA=xe?5m3|1~;pEBc1$TNGq;k-6sJ--i1L)rmFer7(pP>>{uitXE5(@p!ik0gF z=sCAM5vqJp)2F;Ek;;bx6ucau;GjSK!k9n(!hv1J{U5a#1|;3WfTUY^e}Dq=%sa0v zbdrt}2qk_(df{<@4;D@ESFmVu06m8qUE~~5dr`nJUi2vBqUG#W>g7*Rpdf%UZ zF%0p`p~Z6?dX7H~j@paoqi~;{lpDY+3HKz?;_U$nZg&(Y5iAFz$@+JEoCrz%P;eJD zcop0O+|QtU3HQ<;44{8Cfc`M_`-X^<#j60h;_(0g9C({>5B(C(6~|*mzhnyOE%Gu< z7o962BbQ40k@$FD^QnRuzak)g5?te6s#vfNIvI)95|p9d%9q`#{uep zFa&vkq*L#ac@-e(6z)|JkaWwB`Z|!Zmmh~9`C^+_!P|s;6jYb`N2r=3=cSjCL;ri_ zS5KC>^xw;HNq~aO3HQ>=E;#0+Kz4z|z4Y!bp!kC-YF7tzLAC4x`T7?{XmS$&OM2M_ z5>MiT!{Dz5IKW-wG6*(85c+0-0^BH9_;JFMvJM4=%U8)g;~1?`dj+!EZ``ja6^S*t zHM0U;WMO*tMr6gx0C}|m@-Bjm@8RP~nHA_cg}WS7c0niXLaeJ#?HA+D z)`govj9qOGxn>35E%@&z_;?Jsa692116FSqc3os-Xsf6niAOY6cZy`4Eb*&Us(eS5 zBS%STuAyeh9Y=(1&0NtcxobqXEH>!kI<--nW3Nf;`VP^$4Kmj}rts1B8qc`WK0sPV z(T{qYl(DI*L^Ez8NG%_e__emE|D4jQicO+V)*88WyGUGudb1|ltqXi-$7n64|<#zDvg7qB$Z1aMWBfBZ(46C@KF&?Th9M`%*L`1Jpaa3da8td}Q+yk(A9C zyQ-P{!KUU~(I}fALe&+}Pzg0ZDq7KuuVvSEUPJ~SQU;2zUK$xDqL)P?r5C+N0ys#G zB%n`}Uk3RY0B-qKt8TtHD(cY;hb2|0Ty#rg*i*K(n~3KrD@NNF%j}ibvN9%EqxfaN zOQX5pFGj!1dW$aFbn&b%;K>{Wxh^K!Kab0XQjg>e>WE^Uyl;tHW!_;?cL^|8+^i{Xz8s#^qvpr9T_n-G^iDLp{is4+ayJLCJxKH%m^Pw+NVHxqop@CxOxI+d!ksb@cjpRiHXPl^`V{*IDAQ= zt_~*=mz1gcsK*Cd8LHP-UhT9Jo# z3VU6oRMdv^<2m-FeWC{MX5`qHO%aXjAdF`QN{x^VB|>`HBGHOw%nUk_FWaE&4>SAY zyVisIIS}XKqq%R}Bbg=lN!2QI+^@A?2^npF-s?$=X8-(p(E{nAEh?Cy&x=2<$}i5b zKfhB4_w&d|gue9iCqeE?rcf)fzb_J3B5Ya@bMO0v02y0z^3NunIhp$c8#8CF@VBiZ%W>3Uihhg4yvVj2LU42gP2H=puo zqULpY{aDII;M8opZj!2JC0?JFwr;&hUj_0lii$dG-A*l|O|u>*O=L(|aw1XI9T)c1 z2*tV&L`I6RNaOn9x?ZLVui~(+x!123tye3>l9?2*->F&KG%KHsSaE__-xK8xP`ti> zR|6yzs=pk8$rTTf}HeG*i*B3CnHoionl;8MX7n)}_zADO9JNGHK)6}u?gqG4r zQm@Jt^y7b2yh2SwsK`0%7h@ow$IRh^nc=^u$-R*_;&ihHcM zs+aZP5qAhhGOL1Tfvd}PU7sVxo7Y83M|lHJr;Dra5shDjrWPzBm&F*wtAv|P$a*aKVrFk%_Bre5g6G|1fKq!lqCG=f%HZo7O#y^k6e|-MWPXfnFC08 zPQ4a#Epk{=-63r)4u4^|oJvQIT7=fu@bUE3rU!R@39TMOb7+ukdO`^)-E_0~Ua|P#U#b(G5Et5^3(S@Yt7bT)m))Kmw)CDGn z8}Lmu4I+tGhr;$2asCaFl2DUqy#Y&z%AZ8AgxG?0VNU*t(e{=Hkl8W#HUuAYMC~n) zF#(2vFTnvtFw4HN4s7-Kcp`bD9ChilOWlG)hs%YIR`FnK!-ukhUQ@XvxU(WVDyKX`Pdqz}F zpO&`0LzK(r`%!f%%dOGPsRu>9Y<`rQ%O#9V=jNwH%T4ehEo}|qqtoBo{*I)I+UZvb zCqBk+&(*fyq07>*yaYP8`ZVg`|H?s;Xo9a_Iie@2uk=xgBvn zB%U@6H{;i5Rhdv_>TAsq=M&?vzYnt)qHU1W$4Auu`YFQYkTwVK54D?F^q&y!q2GaP zdaDyJ3=GbsMEev3@WB&Qeyq#y45xAum9rIN*#3?f z_vOgQ@OQQlencct$9X^+6t-JM3f0oqtdDBO92=|kaTMY(+cZrQfecy2<46xbyu+x;*%PyZUFe{r!EQ@^SF{{mS6dN2P`- z*^(aJCmQD>fIr+J>g8nh!^cG9>5<~l55*Oj>%u?m7U^jc#?MYFvJX^!{o|Do<Wt#5ng1Hj{c~J%8x}FFRor`?}>UO*P{-}dt@fNJ!>RfX0j_K2GtYJ znaq|j{TS8dp*`aIxd{B82GtMYJxwD00PNZGfVO8(o9?GQUFw~I@E-h{vh1KAm+AH& z&n8EH{IDkY@c~^vF<*54KM+2#M5J$%MKRNs@ICd9TLAtWK?|<(cez=SVf*A z+fV57Cxuk*5J`N&Lii^;>GJ<4SSeu}A!YyMh=20_q|YCJ5;LY>vOhV2BFTN4(UE*o zrn5W3jLW$=F4kNhi7k6l=83y^(x{`?p5#2?USM3FKNjFqfR8yqzgI?MWauRwj3*Du z;Ef#hDoEr!ucdtVpejLqRK{{-=(q~y`X}E9iBA$gd5Ul{0yP|9$H`}a(H(^2_E^Vbs)tfPjrhm+r`VA5i~CRI8qS7FPb_}g9)KSN zt&E25r|%xD!2fXPr^gkJmj{y)u$+cd!u|>jd>RXLHTa&Mq?7pRB$b!xLGbi-dJsH~ z#ho0SPv0-P!C3nAqYxLyhXNRp)axTs>_)GXd?cbQnz2z%!Ev z;)5Espl3WOX6UCAJt;Qy<-%@8$Jb~(pTW!P(%xrwDhEf~&pZM?pAbE>M(6cz_P24CeRc8 zrFpIqHJI@>efEB~L)4rh<@STFJzMV2JagpW8qmQ0pLym&gO_NzKdTmL-1(UKvui=_ zwyS~oHxaJv!4C~F-bnno4e^5f(vF{b9ZQn{uVajpV?Wc5g@1-0TZV({pTkhGp2f!# zxaaDC-Ry&J1?Dzf1_zEmcMIWcIOE%t;ib<#(bFAdSX7@{)8 z_im%1w)X*jLfYG@$L?ONAmj;b?+Ge#!jko0OjV5Qf8p)(E**kjaG&eh#Nr|Li_H`= z4k^=f7Z7gfY32Ego!Zb}bWwSTCY^m_MDiYt*){s^#lCvR8#Up+4k`}{ThhHPGIyis z)$Z*hcb+fQZaqImQWb}vpDr3D^*p`Ye*O}Iw`%xV9mVJ0(NW*O9ZtCic2Wmn|DB>+ zN})x`{sX$(_xI^>{z4rE{e?|ReCP#n47P<|xI^{9%opyZSWyh~q*SEk3%dxXSQ&h` z===uMq3dLyzHo?EnO$Mg_)TnM#fXi>4ert6y1c`iaT?xTx~s!o+gM(^R?vkTM{45l zdPyXqAoQ}xw4lf^-N&K@tMc%RwkpMw-;9jHo=-PO#W2Jr{37-}@0J98!u|}(m(UBi z1y%ZzTx9vg^Q8$go}imaWxEdOFQcO6UMP+!aWjAE$;rGj?dUHzQvf(_jAQi49i{_g zMg6@{e?XpQq>ikfdh>wb@MxWJB+LoM!KXv(-PN?Su9HJ$&$?T@NC!4nFEp+=)62I!Kq92m4X= zNvKx}fcrT93etWz3~tw>=aqeW^t>W7!H@i~CO@geb?7?fM(H6=C_OEF_aKG!&`XML z*>A!garLOf>fa0|JSpo~7S_uGxYybS!lR=6KCBXc6GPo?UL&>3X-MKpS%*BvOGQ2S z!oL|S`gUXW@|(G6_2ZY_?Z;mO+$XBPxrF3iuH>eEBklB~+Z-TwD>~b;14QzG|5!9A zyj&ytFL2rW4!skv#}#g#^>G^Z5JM8BJHSr{D1JIX@pIsIE9SuNB|M4JDs)ABzo_{a zETdkNOg<5LO03X@Y=7`#_%|XRI1!ZI-@cD#OMDjAIOFXHjpqa1Tg{qsckJ|4c zocS2vEi#jkNv~l7^6P=u9`X-F4|alA$z6h;GX7_tUN!VoF;Kq?d%fYFO*%JvHmlqS z_v{k(_a%P6NUE|`B>y1q@4n7AfM1_S5?*i6#=VXOke_j{Bc1%x<8{8Nc9c@AK@FYq% zU!Mxk(RvlGS@uzkVL$$(7{dxrqIB^eZI=9E`gbEm;`;j{d18tD@9(=KdEsMs=#U>n z()xw`*uDNC&)CYO4AvfUmdi}g8JD3P&tMYp6PMvhfX0Th6JzSF3MKBXC0g8D*e1fH z8GfrlC(2t#w3Tli_ZR!t+x}J_U!%kxU$4a;zeWIRLi##};(@tDMILR^emn$55 z9NfSR^`ib^oMQKizK0RU|JpBFP@Pfi5l^SMw@W?Z8Bgf7*4yX}DQ%^aB91*C!Lu)K zpA`1L%emz3K2h^Mv~Crd$7TI@w@}0H(!zcO4HHD;BUncCPWEUgTYIO7R@Lqqr4eq& z?uHc8DO#t)m){qva^~-m3Ik$ThB{*Sd!)huoW%V8r07H}N`L_V&h8>bB@VtVL=gjekE>SL<+tIWzyZPPWyYQVM;ddwL;xX;OyLbi*On9HyO6~wuwFow`r>PKGx+Q6V(34Y66Jhk3FJusXQz6>41d$lA56JGUDiaOb?#_ z#=Tm6XU>)Of6MfAr(F_tgzUfPcu=#;#(Hol=;IDX)1HF-B{}uPx@Niek{_8GKy3amj+h6Y| zTnFd72MPZ$>`(up>^>>SL;n${4b6u6HK0N8KT@-vd^lS-mxl8Ta_o=!D(G*+Mfnerw75x%jw$`y zGSE1(t^6|7A>(f~nyg*4fO^yxfZ1tLWT{K4;xN9|1UqCXcZfca&yWtg9ZaKcMTU zKjAMEPR1Mh!vk?ckLz5VIa1*S+JA|U>xP6t2E5P-Xysj&L$7!t{Fw;)WiV#R!+!+8(jz7F2;q3O`81q_m)p@K*^Z;fDT* z5>lFb($h|SgCe5+M@Y2NfntZ(qYib0cp4?K22Uuq5T2C#AueqPVfWW(ZYmliC(kMP zczSw}blneEb6IhC@HQ3m(M5SN5V~Vok2>tiE8g{E4B3QoE}S=2wC=%}tU;Sk59Z-1 zP;~Xoya&~G>eKvBfo zJ3U%M#M?WJ_h=3Ig`yAs%$N;w9|!Vf=lkFVHClhcJGvZ_ROR|1mw?{o=#UC+#*oWB zc!Kavgi|jMVSKX(XE}J#k_DsK6811`4QWHYgSIDpOI zQJmpI%hBfXF1iz#Pp?F~{qbRS8jpDe4eQlYkWU1XP`kq7> zj>xnxE-fnbS6H-0pM#28sZ@)k;&9Q&l)o`N{V(Uh*d!Wmv3dTIVt4{j5vs)vIyCly zKVkeNa98FHrH&gOCY(GmI35m_nKU9-m8B!3D?XVtqD*Dd=%Nve{4;696Qa8VQ-Egx z7Pdkj5^BV&q6HBRkLXckGq|f~%4X~#$@xf~{|`{!##b5V$K93Tsf8a$Xh5=cM_Esh!L; z?MDaVL)(ZiqbHk@Y1DnfG7?)!2utZmIT`u2KTGXB0qyD1?4 z_Y+PXXYdDf1xc;;!+B$wL4dd+^CoEBVow2bhX zyX0JX+8k;ot4wo+mR_%dU0O7DH|TtNW1LtO&L0^b*Qxs;QKGC_pWrb{&J;FktqG5n ztS-S;k{O0x@=NPI<|VL4`g6=Io|r|Gq{b67gCEdr?~_!rE?Q4)9}>>m82?zLJE6@p zAw`=t+jw@0*%+Uy*iu)KRIM#HNgX);+5y@e95apIiE~2f06EsMB0VzT zwG{VSf0Dno`u{#>o;f>bILYU8GCSYrb)I=<&dfPy&o=Ky&J5lF4n4XV)Jfw@jB|YG zH6J$qrm$W^96m9~Atry#ILF}v#xI>K!tEGvm(CLryS!1Pb|Z5i6tO?Ti%U1Nn6g$U z)m^&PP^a+iws^lZ!sG)>5wWYk;=rXJi1ce%Twi(;n3nh#G!PHy%6rvYDaOyB)Pmvg z+@d=86^^dy z(E|tv#io*;jS_EEBf=p(hflhJ1W_PBeW~L~#$RDvhT*Y83g2zu3CVxi0+cz28hczy zCqx*y>?S5iMGijH2Y&M2Xu;54j7xq}g1_RxQ0hnB(FEhgC~w5!($ffmAQMbQCBR9M zg+uFtp)`JU103q10~xnaYF#jNy$rS6Fzhx1Z=_HdhDTiQEihs(;|BlOh2H%3TSYze zk2{j%pJMxJ|0@oRJLYZR%6VXT7>6r##epjqh+3SB%dh+zG#VBLeY{V^_F~D?0g}g@ zU)3pMBXO#(`bt>)Fs`p!O&3tH)xTvACxulevJlepO9O>8X zD}21cpFkbjsoV2RIY24%r{d16Rku>5&mvi{FpN-I&1D zM??laTz)l%klthd0@UH!)%bqxpOL7zH?SYYBDwFHvQ#d2ro^~>)aL592Qm~BBQ2+7 z>}^PL|FxH>RZ zC7I>ceBi%K2oOo^iE#x&p06bZ)3SIqZ5iKA&nr<1mua|$O>lR#u0WH<+DbD z(ZiEjmd)5dFss#D)2ueR!k=}(Tfyw>y1~qPi1_!JcpD)3M&6){=h@h#N)wLq6gy41GXompN> zrwlJTwhFW_rq{oC(Z7QSKxiud&UK>p5RBsLHi~}KDi3YnX=iRc#!44%zJpZ28MtQd zI`Gp(CVTj?x6}BHXw7|uaoJ-z{3UPv2E3-=ZFsSi?p)%k{0%YidF1%KkQ~MH$VU&m z^T-dv4ZHKI-v;6l4i^LJQ_dP6f^q2)KY5sd* zd9wH(zR7z8=9U8X=+a1oh=PoJ3i4w5_a9<)GNtkYF{$qR>lv3_o5LR#X~>V+V2CAI zY@;Ej@J&+ekRirH`1?l;F@@u4*Q4-uh@6WT&H$T7qZX=3d*Kd|BL0XhFlbS;7p5K^ z`U80_%D1RMPGyVawWR#O&A17POz_>jNW?mzZMj|8r)v*2Hy@VybMr?c1MWuEKQf>_ zuc5Rh2R{2;KHCVgG} zIE#N`h%;VKZtMK4ww{_nxM8lozWEqJvxEMd3(L2a&Q}asg)1Lqh@2+W(+Kjg^`kKT zki$hk2>fUvGblk;_@kQ*L4~VWDSmF$k5(A`3QveEwF--u6X^dXeMRU!REIRbk7ezW z+YRF^w4@tlOYSuIGpHjGmfXX*im1ZxWn4MSjaahA#{WIn1&XlF5a8K!2@PoqqlE)I z)VCE*V^iHoOlYiN0 z#udN9m-3KZc23ek0NJr@vmwasShkmOqq~;vH~2HCL(h-#U>D|w#=wuS^A7ZnZ|nwN z1)RQzUqp)39~7>~XOGDIxSRa?vF+GM2q}*_1V4V06&az4_TkV(r+Hh7&N2i!G*Ojt z%1{P;2tjm-!LM-KK(<2@J;V%3P$@iO2rB%T!OtyGO7UWf9{RN;=(e16KCI02>R0=+0kpU?md56JOK~o`!IlSoC2*uzV%9pkA_g ziwjL_zJ?*f|1o0RAwoMa%l#w>Q9aMtwV$Z;QL#|?T!Wuu`;!HXD}IIJ0uN&6`$-Fy zK`5}urBMFlu(y{#`Kb9MrfBH$YQvp9MVQFget42`RS4upHQ}o6XV>qdIyF_fsBm+V zVb|}PW$-K93_%ur$nm@8N&cW?KoMT1w%4qx@OFFE+&+TiE-++EDLg;LAjy9apNzxxJo`SQff&VnFz@yNPTyl62> z1zzHSVhl|Z+FrM>g*pOwH;voe`ajRXTSaU&UERI=X=acu%IjOtf-f0@3QtMvcq|G5 zYrLnM;dxIlhS$NvL>r&(WS&EyNO?>sjd9>R za2WGKBfhRl^JJ{2UDm`@h8hNAb8Um?*o!5-^~UgmJktA9yjBcl`Mo!SkAlVaFYLl+ zG~`~HS-yJ@$U%J{PmK3%_vXJZCH&A=bKhyuJ=(Ln4{+*qqn)d(yWxLO+FhL#snhUt zb-Q;4{%om;Tuk>*e%4?w9s37<)&h+lE&AE^=F?a(zwGVD8tOm~zt>cBgLjiKYdCIe zj!Xa7%DDN~j-+;!_PCDW?Xnx1@N%d7$^E7WMdZH_)thB~^VX@`BDoE~V} zYcTX>h9ivgNI#-*H3M+o9Px_??0hH0VxO>>LuTAwtl+a!=V$yg<~Q-r>7_v!xAz+} zh-$$7K^C+~QQl)mLR1t7?#GkRQg9&Zddn&B#4wa`i|P;3ki;w;MCO3q zF9)Kts5)Xh40Th$rSmJi#=t|UlX+Z_!m=?xaDT@BFgCDmFbMjT7MGms$WeVtQ+S0) zW-${|g!T5ZqwBh9z`7asRnE$F*Bf%&{&jO1w@_+vSr=isB|vq1+|YH)7`IT8oWk** zTzbZ6U7Y22gQ_>Pjo6C=>nH*BW-1(S>7iy)9_nII7Nb1W#T0&AUZ{Iuq%{9P9f$dW zg%HsF=XgDEGvgLYt-~L{+q&R?BRR?Q{H1CL&-X5+RV#F_C2djZ!2)QLLc`k)#(lqY1zPX+K26nfwkKc!pG zybI46q7SZ;5q%KXChg4qc^_V5{~T|{-H8zW{1sLyP32w0q5Zk)a_MpoZ?`ozJ~Y@i znHy6U>TvNP=}OKMg^vbV4{0^?n`2Pn3z*-QM+g)yLy23NDmFGlao`se8#16`tnie5 z6}d4!jp>G5d=}$2KMb*4`~!oZ9f+Sa_!^-Z2b2#dt$Shn8j zlIuCW0CfcNm-jL*+mplJ1g;0tLY?@JF>cp$?fB&h##OtOzudmYJSD({^#i>H)(>Xf z9Jl#$H;>9 z*z?h|%Imuz=dtwq6@H2s-?F$i@T+oGY_#TA)V<`Og@cA9JNPRzeH6Z0-n{tLVG+jd zt;&b7YW6bx>&f1Dvz&q}n;!vPODlf)NT7KGr7fdF#7o@>n3-gO4;dr&GQW`-;yCbJIyw`b z_z3vxIP5eP$NyDOR4%gJ@Z!oS?naik(Bw&pB2yb5=&v}?5|-zOmKCUabV|#ej9VzR zhR41xfG5>GKAJ_Ro5paIMea^_ZEA!n{oT-WE$7!yjQlA-G6kW2!D-?cr*>QH0Kx@@#txhm_SR( z-{C5ErTxJ#A1i(0pLp%|YDiE345{C35SeeF^>>sP+B%@L7Ioys@33R0$D)3BS|kf_ z^<_hW2;m8rg&Q_9zl>F0-;Ctnp!6_aO5Q@xhOHhO0H)8AvWON~1qLYJc}fB%6<{+OOf`29(k(Vd}~larky^o_l#wD}VYMfgHI z+?2SP*;SjkixW!>HSJPOVwr&}{-~{f4t0q~4=2{Mm@*S*b&nY86rPaYCPn5QBy3_2 zkLt(9gWn@H9-GE^nDpj3De%|~`@G)x*dm}F^VeglIqX-NEnggXYz6qWC_4Bm;Md?V zQs}X6=EujjgZCy{-I)S-xC}{^A9ySyvJ-IW^RZ5F4)oBRZSIGD+UU0xoug;tXy95- zmhpVGkpiVRK;e^V$d`_p>lW)@fjY8e;{vysgGX#JJojR6{5Cd-)ZH{IZCq`C7#rBA z#-<8nJu5WQu}tCkWfu4`hx+o{IE?T-PSYx#c}-k3OPNW62Yx?}pD4lw0KTR61DdVDWx^z5*7q{m|!d?rWsqaa)+qJwWL0Con4 z(V$J`z1Jfz+mPi+Je(fK_NYfXh&hoCUUwlu;l>Q zJ$hkFC-7}JjGSxj1I%MuXe|T&q6fd3qa2G?nwISQwH7{T(?ly}j~0ZoERl-?tq(EI zL2&Sg?G>4?6%RU7_qJktNad4xB3g*{;*q@N)G1Gz^I(V6`{Wcuufi=6jul)aepgr+ zr1wZdS7C-lA~wkvcv5^?QCM2}cvXu;OK zj9VzR7Hm@&y|#_C2Ty)r+YC7fw!stZe*mmvK%Osrfo6ZOT%fY;i&;E@f5Cq+BToM!CT^~stcXOZaZiW54Lu#UEi8O`Q8)Be-QbjC zdPX#%j$!fidd5{oC>&ugwi`sFq5Nq?s>gX?HHPyud9s(D32|w0d86Hpm4Rnguzs4G z@Mpgm33i{k2Nm*1*-a7^xM;*{PRgH2cqiI3t#Wz#%*#CKKBF>B>USdg%zmh&94@m#en(fHibZs<+G zeKg!jc}jVYmOr2B2B*&R;{V8dY(Ad_{_p7QmkR>rJIE;y;T;3) zFxTvu2fEgX@(Ai^#13OQ;NUlc?9r$lND2Fv>5laxi`JL#P|@L3ET?`T#rWNqzStIR zMoqKZpQuEp8I*7qb8y_)fmjbb$c(T2HU@T34(sw|sFVCBj4OGCpGHv5{eiT=jxXJM z%G;!#7bs;kKOCImc@5(ZG5Nd1fGTaw}KDO?%aSvYn_AhHS3)e zg`02~jofKOeLw|xNZ)5DG<^=)oF*N^%r47b5$6YXT`w%i_nT{| zkD?BI%0cNEX_#Yu68EB z#JK7ih2#8APN{X#i&?wDV*@Ysax3azD;2#|>{jI9ei7{tMQX&nbR9?TrA0DwFR63b zOD%M6#@7Ty{9YPtFJbpiD}|Rna9bQu%@#j#TXgW#wng)eGX1-x*#8(4ii7vGv!L>S zO5Eo9r&*5jQR_Yj57}}xf2arDK410&pfX^&3Ks9P+{R!Q3jVuP@R1*R=5$8i(8ogPLa9{OP$?DXdL>zhQ1iftub(J-0pP- zt{U->fvZL&aaNy=U%fkn7y13MO6JcWo9u0NeqaxNlo(s_{((K$LHz%4P>h_v;=rB; zDX}NsJQy=TtCGXJTpz{VhSGb3`Vh4Z(DR%_a3g8&MhISlgS!=<@CQSiQ4k)cy7~jY6`wW7 z26PY&_|tBDpu%^G>>!*y_8JqlLw{NL;fHT;M!MBSZk5g%Y-r;=*+*WIb@s}B_YSP@ z8waclhtVHbs@S#=h&!NzQ zkewBY(2O6#Fr0K0C4fqUwe|m^U<(QsvuMEW{oQrSF0Eb5pzHyUC{0Cjb zeq$jRjyP)Yf&QTXW)y>P$Sxuff555B372LG#2;`Y7wc9rZselE-&_ECPdrGYa#021 zO`1vc26Ic^BuDkYDV!YDaqfUO$x%&D-D=d~=$p4|{MZa{RfK~BLC7Up-k>TeaBw&a z$VhA*z%4sCT2ll)4qhp&smP&&H-PRD`hz!$>Y$mCoJj}GjAT4*W+dxL4>sDZ@I`iea~F+J z#b0qCji0C)h0I(n{Y*b<`#(02-VCx9ftzB?zm;*0fP-(BJJj?J(5bU%XgGhclcIaq zzVu;xquTh^M9?(#Dv)nYVcZDtThk2w80v8UtyzpKeub|A?vXEVt+R14b82D0_g0+x zsKoac-Woui^j3;H?=4*Epx!z(l(lnq)$wZY&~V0;RfTT??vYh*)9}c7({m=D@7}(d zaj7SV%PAVYB@H|2{`Ng~`ug6E)128Dc>5)GM5RA>_uH>9&JGSx_z9OIIlX3Da=yR) zg`r2`Uy>d%V`^cr{IJhk=izeO*UH1>n@3k49`DwzQs6LNgE+RZM63xH1{&Gk;d$Ng zK4j>Qp^mgTydH%|zz;tHoP1Fo7sF@b-+)5rzg6N34sT|H(L;x680Z2^q`={)4SrU1 zm^zC1m7XQS8iNd*c?-+!Hs}i9%ed^|o->y+|9*pC;m3gM!HzM%yW>@+iEmXF1{SJx zJbZ?Q&FFj%+#{{u8O;3Bxvh0E)Dg{h)Ua{%hoVNdSuCwHyKw(IXjOW zGWZ!kYM57N(Z-{O0Yx~v*R4q59YMF@n|SHfQR3!z@PTfAN002V=_(DkI)sI8ft!Ab zIwH|wgx|rp+cV|0feuQIVK|CNK>Za5-tC3YS{~lS{rPS&a+h6W{BBP0z6z&1+}}d~B&mosaG2F&bc+LDjNjuefnF%N*P7cErKE>4Nvl zgf$-L$qJfy#|GXz3Gv+c&l_Z+j)1-Q8RN2jIlN0Qa*vnUf$JYQPUlIFF?Ag8{-tx$ z@x%5xNt_&CSmt|Q-IacS2%n+epKPC@eDAA;$NQUXpyq@Tcol~eM&KPh>g~sgJtBg; zB$X$qK^}2EVV)UC4+8KP{Pe&O>X^UaCkLw#u;U_pC)G23MGSTOoz4$|)#%^<#rt8f za2gx|OA+fe+n-W!s_{1fk$V_h8B4BSH4) zi4P+pdKDV5l&^1mxJe|a-o{<Kw$;}iah z10Tgjcp_#abxx|Z@oh^uk{{7IDK`t{aAc1CV;qLPk7$a|^;C|ZQq@Zj_uz0|WNcf) zi-eE9HUt>|7#D)kML!69TmuG=F8X+Z+k-_h)X~t7Z$d%*M%R731eoU8q8RGL|FGSq zjUQ74G&_T;nZB8E*5}}@z!Nx($b3w5gRZ9*b+SWqfacdAh3^5L$UAqj{4svub~1YG zm|MTNAe@6w0j3!k zqzudw3G9MuPF~lI+@fyqO~5^_q@PU5F?bR;)9ou!r^q1>##3{FQ;!?Derg`$vPYfV zJ+;Ekzw}Ym5usCS-24vyAn^0W=T{eA*aNqw;7fks)D97vVvk$<;o4IvunfdubkZsN z;aXp3PkVz>*|`ubdgvmk!*VC(tkyS!6uwm6E9=C*&oDTZTe2vnYl-;rR6H8s&Ev}Y>56V}JW6^E#FSR$9f$Swy%5u^EmgSOH#Y`O zp8Y;WRB6EXO_L&q7lC;`h&nfXjJ)dP#)k*J+MIC!^w%-2GKXCRDaO*)yq7F@GTkVI#!LXAVEFvH^ z6oYJx7&WUfFj#?IE;8)8G{R-azJeM+g zYH#t?(~Qf&=J1!?`c+DPwb#b6a8x~^44jtJ;a6XYSPd4CDpNSnE0T~y$NZ~=^;%TV z+vecqsA=(1gYI86M-pz~png$$2BW6)vm5^!D)9x5fFe|Y;KNab1ApaF`VWVUR9w-< zxSfjl%7&#t#@*1{D68 zn_p$fzrJwuEBxyM5xx!q54y!vhkdOA&K;ow__Ye41vv^V$LVVhpc6k1_}9b1rFVql zA1(1|=Lp=+0&G~d`|A~q8}0u3LAxE!qV{X~q$Ir-H#87pc_(og0sm$R>r)M6 z$G*9fakirx_{|zOzl!5G54rIbDb&%S-?X5>h;KZ{@J0}{j$Ouc(l=Y(xSGShp`k|n z?2v=2p{5*FdR}qq8M{qQZr|*6D{}DtE&>&O>5#Zh4%sdsOb6a!ofuxSG*vMW=wj+ zaP4=oQOmm?ESjjpHrI`FcLnnzo)cy;Z@I7{xa^$QNhWc)(=^E)_=tNgqXY6Ga2DZw5Tt8HVw-tBIF2R{vb zTi!WW6oUB!>||OP%wOWxsCqJAX`}!_2Tv5id}9DR{P(aP6$v?U2J^+I$fxrB_1%y+ z$pGc6;ik;V2|t*>+mKVZ8f}U{1-`uEVE%rCU*T^u&iszship7|=5z>$<#*45`R17- z2??_F0c*6V?wm7&`8d_mk~`QlM2}0-2P6SKfg0?IEzx(76+P1;^Y2uCPRUhL{;dI| z00(8Y^H&`F7M_EJs%wMax)G=sgVA{^O}@1Z{MxW}aQyQ8zhiXokcD)kve$U#R}4_KJ}Osdf{i|?nIb+b=qO*AMEv&H)C&k zaXUZQJIt}~joaz}frjF1^O(lUd&j+}rQVzDY01|cmgd1y?@lU9>Cq&wa2L=lqRl!h z+KI6^STLM%i|R-P{EPzB&0TSTs-Vw8p>>CY(`eR~f1w8EznSqc)${TkJSxJsViqm9 z7ohHkvZDg528Hs^oTU_hGwYFd;5S)=zZ+5H{OUPV`L)%?an6?lIl^<@2<&9s_?j_<-zgd=Y<{iDC)U?H_M=V{*H4#p{UbJKbbpDZI-*iEDg*F#S4DUL{C zD{zk#Eu@BPJ+U&4I{8HnC)~n;jBs%BZ+V{hkMH6!fWjgAB7FYxO;)eF>1_zT79Kkz9iwBB*>YTzDGK5s5?y?q?z z^X5t1S>>uQpGN~o7vP4Uw}f#EC3TC!m&?=jd8_TR@;pidEv-UL#16-s8Rrgg@JCsG zJC|4-W8U$dmt}old+Y1t^VZkLFZJ{p!sR$FvEM|-TpP51Gm)G(GN#X+z&sk>N1dH5 z(6xs5X=26pMQi+AaVytxH;~pZeKK}KD*MpD^wRqo;}%Ly@AIbiYTjy*z3xUI$Tf z!NQ@dOnQ&h;zQudC1}r?F%l~d7E|*Gw{SqCgMUIb9Mn|O-$_Mr@B$jOJ?ZDwECMt_ z5H(FeO$8T}FfK=cGZS1eK=>n=szS66zo;>IK?V4z&y57VfMTlYU3nUHa)e?>IO}!r zjlet_dckJKEtHT{4ZWZZHF;5OZ195JM8ct3t&Htu+%%SM{yxtB6hmE#a-Up0W=JXg z1A`yGVuiiVTqnj~8gd+a{{rB-rsb*0#D5dx(z_hqAQG!+8R?I!4@sF!{ylQD;>S)A zW24cZg@$=JjNto~Cn_G?f&lU9!B@EIY{k#<3zQrD3LgR-Tb~ye76u#DjKi`GAW;+p z_o5(M77iqwgRe(Tk2knaNJG<7%O z(tv{pgTQo$m_OJ}FPnyi(Cmn)*aSr(f9X9D3SC zA8OK@e~1)S>MvaACaZL~@Mgv>lv{dd2 zxe>iY6~w5;uJ%z9??XcL686w;S{`A_4kD zb+)m;Z$!M*!OkD#?nOmkZL|;(_!^O1hV^twlf5(cmEaQ5Ex6#h!Nu;ZuSzyDZlOfr z)Viw#t8Og(#s*8a1Eyp#?e8RZ92O2eAzv2JrI;SEbivQ$<_Amrhy>MZZGHWNrFG!; z&{tY-3yckxJ_3eZ!yJ!FRSPW8HBU=Fk_|2WoD7%v%J52?TVXJ48@x7HRt0VkgJsmQ z9(KxZV%$Qh*(r|4JLzgRJL0pXkb(8MjbU z92I^9wVW9z3}wd{w@_;C_4A>YrjwIZtx``d?q|jzb$~S@7K!f+I|Pr2fVS&Uh?+Ck4f7f%EvWF z@tnqWkUWXQNV4)pBGyW(%9j%xejU_)MPRUej}pgE0@-@{_oTP2obwB&{0*sK|G`kM z`$}zvul$xEsB>^FrP{m)mDW^q&yxTrY~X#`x6146cf9|Q-`Nk9*$VjSO% zf++^Sg*qG_FpF^&euZDh2J38tjlqk{!KiHt`j0~$3N9YVxK!YC@EYKngM-VM|9ZyR zpo7l?u8rab#ZUQRf6+|}Y;y=Vu_Eq*OIuJUhn6tT1{{1T@Gcz2NVxbR=4U;FZ8_*! zuj!$iw+`VEL!cUUGQ5Ft)iQ;v)KdnCo%pvJ{0e`Lam63AfAAFoFBt+L*oqD@t^_h7 zyBtG5!{pBla+e6*QCNBv#R6^&R4K>Om--nmVKEg)g%59Dfk~IRwM4(v=7KhrPf8mH zVW83NmnwWA>rwnswr=*K!q=)Ni_B#s4U9FT?v;4>jy+3J-^Q(3`A?TRg;%Is3NOP)M0zz=se@=$ z>0u~jr2pW0sV@{nsX6T6<)W6(6rq7``XyPGnOCdin>4w1eya;V_yq1a}E=e-m%ey8zz;%@1Cd$Ct7%>%)uR z%dltmT8my5YF=fpLgbqHvIZrH&BR>@^3b00;m6?60Z`y^jcKU5Q95)+^CMWK4yB3A zBdSB^G9E@rP35Q#Jub4V$k6BZda8eL*hnJdFxoh52EEG$K^R8+F%O0cv=!GZD=Vl! zbq_eG6*LzRZsE{^U9n0e??w#pyH(iFmS5fn#B;w77Q8&hp}G8F^+DcE&JSL$ZqyG~ zw~vQMMfyp~gy9=yx)0wBt-A4g@}W35VhG1~#AMVx;ydC&#jvRx26cC0L`sAk(T;XD zJtD(?j>Hc#+>H>Atg(G*9I3jVu@{sLK&B!A_Jt8x*6Szk}Mpa;)H3T#xKStpPck!6+wZTzM z-3YE{Lu$MeADTC+nQ@Eixj{Ip)sCNdJ%(%0igzbCbY~U*ayL%x22L}fv`PB$2b+5t zm!m<#gzv}4V>k@{@=-Lc6TuWX#uo!eodA(SX)=5Q>_Z%e#!+7~Zt#!xiSPQi@DK2g%;*sCIbbomaWoD8-+DY}G|Gc`wD~n72)6&H+93?BB$~zz5?ANy~DU_Vec!$)#}3`k-)@M8K&;n z&bULWQHRsv<0uk1j4*`Hi0IF8W)FV>nl4w1I?2)5{@m}C1jlqU0gu6!=VzE->g~dQ z_&+~5249XOFl&#M#$Y9dj*M}-4T<72j8#(TbetnzNoPhKuVa2XGio@0?<-ijka131 zNB92zHRrU@fmK7+sL@opTls&&O4S@~^rH?(ucX09I6La#$64+q z)473-0n|y3`a_pf_-R|N@yag^xuBFA?=$2SKGfhZV}2SxWXGa<-nK@C*Py1gM+JWT zTpPze-oghuX>*T^pNE<*KtV=B#xFpT8=yUBasrKC#{3pa(xdoqM=h7vIsWCqsd0A4 zi9Qb$o;OAffl9zI?x?;OH7^yb`Ghe3K`;!&VI;wLJd*;~obZvT{fbUaRg-ziRds{?d}d|UMo4%>scJLh(vs7}D*R3X z7BTt3t139LubKf)ilNb_t8SE!G+q^DlULniuLSxBuc9z{tOTw~^0l$6J^;fdIArtj zf&PkvSDi#bxO9p@`~m+2MXnKfL*k5|VVwCL9JkSajwlZXS&MRGNQzAy%D6>!q-KbU z;^4$ZywaT*L)~MrPfT%4Cej(tBPJ8OI2Mx%MC2ii@&T$ooMSU-G$cJ@GwDW-&7}2U z@QBT%X2y-!Ofu)=6!_4XNgGh)ay4&=!V?sm65nJ$yEb`<{o&f+4E!YcAH8VU5yXf7iSy8(lZBm_R zjkK=-^bcA$g1!QW(TUblk@y$w;H@}_Kk{IZn~lbxg)?1`As!6K`5t{d@J?WNo{L{Y z9_XE3fjV5jrkHVy>KJ_rFGsDXSiY_>xbPZtgxU!L+2O>4!@@zb3ZI6Wm#ym=w@~V~ z=8EV#g!h_xK)v)m%rn6?NicZi$~Enr5!W2IKa34dD`8bUrK@I5vzrB)g+p^;+ES6l zYepe>2(X9m(y|&&S z)5XDc_}!A}G!N-+De>lR#1C-DrhfzmkC09OibFO-%?~r?$(GDmV7J6KV>^drW;d~% z*-b2G4wT(FbFkqXr^n2p($LJ|wxNYHX%hBm+f3>^J>(YZ2<1!)v3CBsEX4RtjN5kd z@*Es}OAmI=jET6wC`C4*=(pd{!W}yEO_9QdE8k39h_a=yVkD`ac42M>8>^-5S!T*B z{CW}kEw<0I=7NvfB7NKD$jvjnsA7E!4P5EF7q}i1g|B0N)pm~ctcPq|{Oq@df$~|# zN$4^qyn|O6v(mDyAKAIlKRCM%(p@-;a5#U(!P!v}{S9KW$_|lO_M5_s#Xr7Xc%g50 zQWEx1h)c?=XF%v09EN;#o%~irHRk6iVqF~X zSp7BQs@06o@d2kOQ3lZ{=Z4Pdg_=h%%)xf$w^*T2qU&a&BwZYwLy4}Pyf0Ju04X-u z5NlvDnl^PYg;z*1Gwqd=D(z*Xa?Vc?kpxm{&MZT1g3Xbjnm5j;Jk7b=b7mZM zxI4d?af|BM@hDtnnu$*XmzN%uDki@S^9W~v{8SmB=|YRM!oRyngtyW@M5MXAp%vgo zq`qeiO$S$FkNGdlFu#gOnCdu3Waxi!@cYA2^uQtceczkG_-Gqr%;DGi|{Sk$5`Bh{KJrlfsC(^!iN&y z&DY7_(+%F-B0~4!D#gu5&=~p|7j8W%CABvnW1L&>;JC$2a*HucyyO;7^p;y(EeFEl z8%1;@I@g#vhT3L|gNv8J5Tz%Zb?^ofEAiFWi+FFkVOEdx20n}p{^$_6weDDanp`ao z{s;}TajD6t@Fhsg#}SZrk$oHrm*6c5RP7_Hw^WEYRaZ;&fV{(W%W0A+@hvSQE}Ew7 zVv%gp(wKdFDL=S$lc?PUa)B(uB1W}Evfyv`-1@L2;`w|c`i1`q6nHm26^rD#ZW(q+ zM10x)&4>Kpvg0C3QfZ6ZQNPu6hT5ZQp+Y9*fJ zYKMpu+Ys5z+woH;RE^rGIJ&veFTUAaSU__d;VD@lC{)9hi!I2zAqcaUcY|AG_?O2; zjK~{Ny$y$vUduO&B*@TATs?3HkACGjct=EiXxQa%1p$xXRXkaEMWH3Nu4obAC-Iid zl}{G>3qy>dF@$Y-vhaeUc_{|lC3ut=6O3gf)_W_k7-L>?9?_WzA?jKrvyv4gE1r=26V;ZuI z6rUx2f-pK8vLgL7uwhRFOG@k~1rnQ2Se&tt#MTlPW2{PIyMW=R{o0>K7=M^zTD_!| zJ_CL~V=;-%CM>~Ni^NtwgNFSm#b8o`TZmCPg?pmp=ut5GmS#lfGliGpG0i^7!Yg`w zASNdZZ&7CMw1odzaPCV&niQg$ch*VlEHFF>Snw>O!iw)~lBD_1g56^Fgv8bo7G|tX zV!H@SFqW3ssb}H+Pf`qaO0e`f*b0e?=U~e(Nq3cr@N;l&B}giYcZDUkg)ocxswH-m zusCD*Sxl1c{k)w|lKti*9eaVNkD z1h%sH-MH*S;9`Kj)|6=2iD+h|mb-DSifH>t;7N|i-E|T?OW@X8=8Q^k*e-zE6laqJ z=M%U+$(#uZt_A3OIwM+kp@GlDnV6QuQzY@MpTSNEmbMWXk>EXfBGm@hW)t{=#bB8P zR}#1@%^+S#N}O8&`d*BRwl*|S(IS%8`$cr1!tkR2#6RIhC`pA_NnC=9i80AotHcB` z?j{Vw>zS*Z2})8DYAmp!`7c4ofe>RM8(T|k35Kd{ zXcs|QhH7o-6d*jQ+Vv7zrI=$jW%mDonRww=V~Y)~B#519Oxn;Ef|Ovp4IL#Y%7Pgi z>isgT_(j>vuo9A#m|uimMr#&>q+%DVkeDDW!hDv*_UTxi#Lkl1lqmQ^&iPoAB+dT= zRK!?CLSk$GfGGWMhQT%o?jpuGV`+(?mOzn4e-2BCPkTz=#b|{%M26CIG{HSN&=(T0g}cMC?Lm#~ei1 zKEh(G0&@^yXLUY&_bdf$SPFb;$#-vo#O4FT>Zm@2H2YhIX;qT8i}=Hg)k^FXVF||S zC063Rg_)YoUXu<@- z;u5>hFR{fM-+dJl6T2~d&dZ3_-DuZ&Sr(|1#Iq#8#_o$sY}g-xSWoo|4f_*}`9;;AU@XFVG4l}nT98y6 z)?nfxY!_i1*fnX1ogys6vY2>?uXKOTr?q(^vLD#&{mAbhW<=e7f=NMO2c89n86Qf0M-K6P94Ugv8b!LKksjo;4T91 zQeawwryz~1bzKKxEF_hz!`zdGzq8X&>}L#94`C|_3p0kPhp;V#DOpTCgdGKjHgu*n zwU~N{G~q39>NwAMiAP%4pR?dg0M7Wn0g4?N0`MJrXIr1zJ>IDAR`J6!B$k# z9>Cml2(U|J9a>9na11!N9cI1T32ZnWB{W~xfXA(B#MA}8{ zDaNoNC+rkqX~wW0C#>`cu$aVtj{W!%V6zE}GKTFqVJnZIS^F}g=?H8Q2|fOE?8k|A zl=wr8VLMJ(@1wvXjA1)Y*o31<!*-l70SpsF>rvRMWfFGdL^@0C z$~WxBJAe)A$k~4gyK%zi6J|--hp-zbY%O6C#;_YFY!@(Waoam!D#0Xd#)(w=F4$9y zVKYwHY{J5fVKYwHO2XKshp-nXYztv==EGi`u%o~*WINx*Ty#9kG|W54K$~z3{C`>SeP+PJA|DAhUHz?dk7b^$MZz!eUN4!2fHQN<7E@#lG z*tHWj8yKe8y1$@V7PDi|PNXfw9%c+%cEXP87jK`&{*(0UlN4q@{N<7PdKS%wit7Qzc4q+<^Q))5m5Vl3mKtQDE3UcYX|0VOG&4{HH*ga1tt_68p7ZVvA2A zGPAM_R!C3~W1KNdV*7}3j$*8n;8`#tTm`3cUGwWENt%BOIzp@?A+fcD#TaXo*e=4t zjHM-Zim)_eof0eUv_n|Y2~&PaYQ|Q*lR^WM3Rg3>>V$3SguB;gm=Sw*0*?}7gfZ;Z z3G4k=U>0N8s}nW>7`m(aub3WcxyjAgtP@S>{Mf7$wvVtV>%eB6u(O0E7{g}$6JWzW z$=MRvtP?gL7|s&)pX5?QV6RT3UBn)dDg^fGgqMzuov_7(v8@(t z)(I29aJi%PG;AfMiWY3uiFEcfZ2d69Aol764*NTFgc!qKov`_Y)iQ>?I$>)G^D~CM zI$^tj^@xl1zr$97N!Y6ssq{?Fwcq5?jg=BH>r7!lHS0G>Az+QKMj-bN4!X z%i_V95gBF(Nd`r)DicZ2#nWqwdN&4BVK;R|40SSB<;L%bFmAc=sxro_-S{0OPkL(I zxTC+0aBpmd-%Ky3oqqNfEyCJbcrCH(A%bxtz2R16kF)xvq-w4wO27obgUK z|FvH+o;CQB68|F=J;doR3X8;>X9^2~e>CEIInweho}RdNwWv5-INEn@wWzbpKB9@r znzU%M%ZEj$UEUzdx(M$ps=EpYmhZ6*;2+Oba}ESj-7Jc3eFcRBG9e*+4gzYpUvlp6ntDv6ixAqO;p zS*kf$Bh##~r`4c8Dh2l>Me33w&{GC|5!2g6sD$Vp27M&cGa_9|bm~XV{!FS91q4T@LxzLk4{{(}?nE1xVw)9R^)FiOZ-Pitrtgy;+0dM${=PT_W`xV%S$;FjPo}eSTrxh_LPpx#?56 z*Y**g-mFfRt1|f87`H??Li%bA`YNW^q15z^E@Qmj;IC#pDxwREN*3&k8T39(Z$hc- zQ*teC{wW>IpD_3%BK8fI3y(6n%^)|364WMxHyueL}+ht zGfb*w1u>BtP72}%T^VQ*$*YOp>ZVWRRBca+%uPg38T2UX6ak!gZ!0Pp-rnJ+t95UC z2DsMZD-t5r1NtVUfRlWeL2naT(0vnzhyq{Hpznr3*5We0Q;Pkm$`H#kUhC$c)W&$7 zn?H;Tfxe>BtD2ZhtIlt;`<9wYW!m}jQdgQ{ArQS zN3T@kdRcza=%VTf^VNz_&!VA~V_Lah@0J@=!FUX%W~cH&(a^JK(B%mOu0_m*Cl^_JGFxoqIFmCKIaMOWZ5d#C_Y>{x0%g75|v z9$vg*^v&3I<`22~=is$~&?kxuiweJQcs7b!LN=;UXn|I{fHy2RKDHBe;-?PMd{VoK zH|j(h)47;cSmdv9l-IkJILf1Ld|Vmoq&$YgrCcPivJhXR0rrYobJVfX0vQc=Y$V+H zxN6kNMiPa~2IFlgH9ccVFY%`&E~XR}735mhE>UOrMNlX1v>PASz<36w%c_VMVUaSH ztdd+7g=XDpU6&hIt$UNiH2!g|1QZ9~^rLXuVZ02b#y^(y<`s*}&MOMkjO<{h3OAEu zEbPYZ_bZSw3%JXeh@FQ#jd7>m2{E30hb;F}4QE@L9vhZ;qC$eAPx&8X9;HaG6rNxAVW>rp2?X%sFy zjCY{a^p7LGXwU;M79*Yx1Qtf>`svexC6x{|a2CnLHQXiLM3 z#_?@TFGK0_lJO8q&Aag}j8jZCTty)rcH`i!KbNqoy{I^=mOr$J`1W#Z7J;Q3wT)Wv~3MsQ2_>IsxjrJ_gf9kMraj zOefFL7K65$3H89K8SUNZOS|QG3J9h<+&H|;*!tqYNnaL)mw#PuxpAG6|1Bz9VH8#n zQJT=k^fHtl`rZn;<*sZM36fKN{8rdapO8Tv{=H?PaOrEl5aAeE!Q@($nmgmOjMuqw zb;10th#Md27h&itAC+XesGB}MDF6{Y6qNb%`~ zxW3`IOVQKFxUL=Qi|9CRlX;CkDuX(?lXl}HJ49{YqSAi#Ozw1(N7aiM)RvF*Grh}A zM{ANK9+Bij#O7*@$bj6~!sHN2%_(&i`%u`x6@Qf*S6zR|a^qDUsH1U*YEih%OFVd} z4j**GT_SN&QORJw#S=V4&DZFTp{R(AEh-5fih=G@+)S4z9r3tZd<3pzgWl+o0($} zGiBXONQG2CoE%?mD(ZD%@Gu3=rCMa^Qn{KT4wt#5amOq~m)h0*d${5pdTn`8DR!mx zoEIs`6{(ZUI~5|nx~OE@J7KrHn$O>{-1x){>ZG^Y zjpJMzx|kL|C74CtsWXUKQ43E)HqqveBth2V z;l!`ajdOs+3n82eDfXnZ-Q*D&_~=YwM>^benmcf}vgYb~md~Q}@|E;!J}F<1l9&q@ zQM&u-(EV=uM0`Ku5}bnwhPy{YZZbWC0C6WhkA~fJb<^Oe1>EJP2oFYAIA&|zat>Z+ z;G~EAh@jA#p;kXfDJ&YUa`I@@jdK@`2p(;46C8n<8%IM^aCo6Q+Z~O&=~D_&C&v;f zw1$r5dk#lifoqOU;r=_?=H|yap%(WB?L4kL+U^z_6+)eiq}{mVREMyxKxZE91YL7N zoyd-6dB(YvE?HJdWgS##o+)J=1#WywlKIO}x|9oR2zxxdqrxpTs+NVqZX9VGg;33u z4AZMox|A|b@|trh0v&a39Qx9vZ>pc=qA0!eHMr%RAjI4_^o1`&eon0dj)-@(pzzX{ z0IvH-{t|zy8+U@5bmLPas1tt*#kufGE{2Hq_&1n^yxq4wG-Hk3LdLxRP@cdJln_SAiYcd5g* z_E@Oe{BaggV)Yx^c(N1~+bnP$zzhhszG*ag>^Vwkw_( zRumX~1vQ3*6K*EQSgXjqKv!elZ3BZ#dvgUEVTA#ce7jrziWuW*H}2@|aO0NZ?*#5L zgF5NYqR<+_Pi~1{S5PBjlIa)~8j~`1tUzQ&V4r!c40M-rk)=kch##wP%R73hkzRT! zcp7eHP=~X}s!_P?FkXvN<5&BGpIwedSaD{GxS5EdupiwFf-V3>z zl(F|J-1s$VTR8Y$6-t*ekwO}lt1WhHRMe zlpBXK|0oDg8HT;cdmV0K*b){Ii|-<0r$NMdbyQL5C9L>(0mvSWKaPjLg~NaM=(MlA97|dM!##PA%1r*SYa4YDFA!&Q9of zy_=5RNy??S!Jt>5PX5H)I8NnRlABJkAbJZ5m%ofBP-=d{UM&_=HB(YdPa1TK@isTE z9-lo<@zL~+!nTMOXQN^)*Wsp*tPmNOy-qh>CHnEK8=oFQ9qoFb3Rk;?6{dLlnNFqV z&yTMlc>*9>A6j4Z?sCP5?oicEVp|V}l@I6x)DqLYbX}&`FzsdKzXa z2_Z_Fw38-H)N@Ig-qUlc-h10Kr?K7q(%86~<^*DcJZ5L);(Rdig z*ZA%<#>}ez$YV>v@_EhU)LkIIoB7jk2}1cb4e(6pcTXy)Yd-ALl*Tuii+04iaT+6x6Oab11-$3JF3EM z_+7527+v#ChIL2bQ#sAMW#Q5(FQ2pa^$3qW8u;+dm!}$<51SmB>wLlbJ7%s;?n1`PS$nnWlO8x5Sb2bWzj!CdPDEhUisw1-NjByd&blF z6`V%mX^n?|G8)I8xpfh44Q3{DVy!<@&|19Z3V!s8Dd6;8f>2$sco|Y;$ukk{+?syI z*StGlJ~N?l*fp7tThz})W}jyw^6vBMGt5iI#ZLcX@VgSgneVjb@%gB5F{?H{)WWA@ z&&+oBLW9o)$EY`;7d}UQrmcB*3_a6{;B6By4cGi6T86g$pA;1&w3E5ttPh% zY2xPspf>8({IfZziE6j7J2cO0d{55QVRzgX{K5p>xOWwvEon78BD@6N-O7KqqUk+z z7}NU%gifwVJ2wZC2^xKH=In$(Hx5A%oYJLx!OuHG4b4}3B zt*K{cHE%x~3_i zA-6Mmj&m=}xh8OTboBiN;7I4WJcMey#mNgheqkAQ;Vp&dikjasX6p1i!fB%4vgX4w zD;noziGJT-1WvmN%?~#wcZ0szrAzlBEzC*={HWU?KR2cMu#3|g-yJhm+J$YJ(Y%|j z=UNdQ8)W7a+69`&9lAF8(7vsCTnD_%#Z~=z(6XKnBnS))K2O6ixTB4B#WYWf4SCO|gfp6L04<}o>mJow9F*1j0w(`R6Md zztUAX0bEsS>hL#yr3ak()*!@e@ANHR*LWCbO5<0u9{QPvP;o5YgcSa5Tyy>vcn@hf zuu3hhgd?bU1$ydRdJa0ygy@aMGmf)Kcl_CU5!6WY5d9t z#;EaUX$YN%w+DG#*|dBXQuy16YZUnKUdqq%n!mDb?TV1fufQI}su zpZJlf)tfuhuTDp@YChb zS)$+zDQhJssBbpHvo6M)gXk5nt@W?Q zPFlu$f#xC~yrvo`KB4&nemQop$ma!5^VhI$Q$>pL*rvYyGRMCi5XNA1_oj&)0YrU)TJ#*kgka=j#RbL-hCB z9LB7p3DGN`8Q?-6{cba!JLX@QJ%;ywo4o7KoaVWHz=!Ygy}*75|JP1njC@{;9RSDnP~AkS-CmLG%cl}}OIx$n@u zSkm}z*26eujpJs29dU+2J74qoq}d|xc0w;!HJ>R?j^WzM>gjz7LS<<(W3YC!@#3_$ z-jp*%ns==EOoYY>7Upqx5quHvH+~p04vKf-kVT|;D znb5eKykD|BsZTxXdm6_}qCVn;i}RP6WB7*RbDGDb2jKU7umPO@#~@TYEnb9_`J^pg zisB}BooN3rE1KVlU$yJ@x2~!=2M60mCqD#k5je zB=}`hJ!bHl#>wuTAVF(n23^A2tzZ z{zaUZ650r}-3Ga5gvlY;OP=Q4s(mS~@x4wz3tR^)+<;(wvFDtZ^4iEP#g_^iM<;w3 zh3B)EikklrhTY`K5Gt6(BTHg4i)1lAgy;}%{RD_J>h6`lRMUK}jWO-&8pk7m+>N+D zh_^|~km1`sFR=;2KbIQ#Js)CI=qG^amG2yIVdp*;y~Owe-`1YI3E|v|dl{^xF?Sio zvut6Gbc*2je`tz^1A{N8A$p|qaz@*^bY5l|!k@cby`0lHrmu-O;a%UC3z~Odv3z+< zF%I;c}`pWb`E1i=+@Pvpmt2_ zqo8_mp`f;>X%y5dvY;Gry3J_*nv}&O^XLj{=d}LjvB`a?2S3{pJFbmagjmn{`$RqM z$OQd%(+2P%d)0I71U2`Gdg?F}6M%Z!NMNC!$OK)}gg)#14HMKRFZ^xB$H)C)L3V;Z zv|kn!nV{dv!2=@vilRqBzdCk;g8d5x{mO%xNB{*TZe~Gc`h(ky=C2Jb{u?IfS2?Y} zdBWu2FYbQH;8%8%?!H;n^sC4u{Z7*c@gaNFbj&189uOtfVWmsT9FQeN=IGi2^jYd} zn4@1cwLg?pgujK7>@+=cK$aAlrm-BHAjm5eJxY4z*lF?(F4Xjj2Qyt$;UJ#yx@meP zGELX8Lkt(4CNmDN8#X&Suid&?dS!l=#s^<1Y6W+ic%`KAu_nfhSAh`aoo{>liVs}m z|KS|Q)UQGaefNUED>dN9pMn2u#J~8*UH@L0!azF0PjKHN?xemFnZyr|(HenfAbJIA zX@6myK;s{Fh0JN(He`74m9{26%*qh>*D(kY`10w=Td^2F%zQ{^qO`?xkg`s?r+xuK zxZ_R<{)RS{EnkEbcDM=Gz7^{zur$>KJ<>2<3BRc5u9Ls^HNVMRUBWL8d^iBi=v7T~ z7Xz3xReMsCEUvt`Z zDd5bPv!%Laar5v4xJP;qemD`&iR&;4OMEo}72Tm0`AyAv(^oysZ%R+zj`im{^lC=a zuEJNd8g~`Gn$x)3Z@!w>xSOC?3lV$*~(`|D*A>S4_{-ucb8Y+`UG((%r1p&uV>s`{@q2o3b>Mmu52-FKFED zdS4sUIC_w~18e98nj!nw$`CsHdY5M!goRe-ktHy0jIOh2XHpkImTXS(|4 zGl%dvGIUyxC>2cO5R$#3&jgVBZ=@3jX+emjt{_Z2fDlc%v1V}=BlU|G??4KD?5@jq zVIgg4%=51&G>_d|9ejKwu)JsL4`NIFqr2j(@v6vV83$s~QaMQB`o?LKDZ{n90>3^M z;c?3d=H`13@)sapXBVY4o`S);`xgbSAAFr{5UiW)*L{uOl)@NodA$nJqx{!vTK|T? zv|W_(!PloW8%AMsMD&|j38OS2dPSK5F7(|Jf4!ygu;~GD^SO`3yBBUK+AU@7SB048Bik9NMOo`c?m9B zo1ErvnzeWVQip0G)H)ZcsLeJdCXc}DWzM>+X?L0GR3doIWN7E!n(DAnnQaGSR#w$` zre=z;3%{4%sYm!C# zgTYQ)TUzQxLMCK2yG% zKhDx;>X75^l=%krMf_r8-u}&)w!eJZ;;D#!%i?LR@6K~?W+M8{uD*HX9{jjUG3X8k z-^@XZB;3{U&Ai4@Wb+<8vu<0nBBZR5W7Pg;2|~EzALzIjJ>BA4zM^@zsNS5=_zel; z({3Nl=(nbMcP4wYuJIf4rUAQnSVm*=6F7N4e=mMG#C>P-&8D_-*YP)J=D!-TrUK(hQZxyxG{ytL#8{Ub2tE~Ajy^6;7vkay; z0io81X~N&oDE*MHL5Q{?UR%YR(tH@Nq4E6%jOnilq2m=kj_Njl0C&FMYJpV2Fs9M0 z#`&4=~D!+lbGdsgEg;6yQxK;!NM;@jkfA3kP5obaLA z+a1m0^+xY^vG|?+JCO-=b-k0&b~jI8j6B})Aaq?m{0;4AJ>)YGG9UbG6M1*idMBrO zZmqzN-fZi9XAHdZk1_ogA%x%kEt9(+cCMfAlr`@@IlU8^cf7?~rk#7}_73Y3e%%)7 zovOxh{M2DLKEi%7pStG5zD;TTfQK>lry+XP)dVi$Zz*6*{TYqhbF(>r9G?lW=!@fM z>H#*J%5ANTrdGl4Ip6~a|85MTNAPzOz(w%=RHuGQoJ88u zKC5|`=es$LBhLcth7PoV({2nx`x^|HqCc1;8B`0E0JkC*iECfg@5 zWo~NTt!wpz9>#RjfKX8_J`E|lvomG!rpDdUe>Xa1wXVMT<|px4)UC&NXSMN;v}qy9 z@JZjhbDGB+1D`@?4_3Oq2H&ITk?VUgZFY0V6k!*hZr)?=q84|$dC$|hd&U2~w8q_@ z4`xggal%&?-pgtJK-ILtn}>K9cy%I#P+9K2JR_S}} ziKq#y)Q7(zcglQkLi0E^Ho)KRR_S{+&AV0lUR~pE{k%7&@mtsn<~QMD;|EqhrSbi($>qPYN*1+$fUoQVeG0oqEJrejZ-lCM|Z=J>%@fM{a zdc<3l(fT-$TJSe|aMs%8G`};jcwXZ>#wI6lKHlP4dQ8*yC`c|UMev5zFKgU>C{He` zX#A#{)%P_%oS4Uxi>eVKFij-3(7(FoG0$!Cx3=dUESiQ?eKOu>!P~tr@r)0$Q_Tcjdt3;AA2*Ex z+QB@n)o#R}%l>`1x97R!aaqlme2i(AhtOr$X=l&J$>YYri?r+|FL_*1<6J(l8`{r2 z=(nu-TT7FFK$F>W8IQ9oaHQMp=2Nu% zjOKAPx0T<>?Ao1g^0+|T@$&aM9F@0~tlti#%6A@TDl#AY%rJR;OyhXx$cI1oZM)?0 zsR*B;qk-h{Y`d&4Fahj_?5F$W@mbB|`%;O|WA)hf9AD7%rn1R>9%1df9?9d25x$Kv z!?H{fmK$-{4Gqs&zM^@wwGMv2y(gPIzN&e*T92=3{I({>j5h_*tDUSvOG10iioruh)2 zz^1r3rRiO`9)iX*QSV`%E=r~V>9&-~#d)m`-dB7v!s8|QXrxT0|! zC;{wt?#cm26^kbzgq=ITFRp2Pr;jo9>&E*&{@D%TU(2pf zE}qe>o43U+jo)6!n9=4Sdd%D6HgK7BZSoJ%OnZ|rxrEk|&X^2&cl0btMR@!Y6M6e= zC%Gi8dE6YTcKHS!4IJsml>Ih@@H!{6A4b}gs`&qFCKl_J+d9|epNHNWB zH7!kP{G+TBZkJ{tdaS0US*?$gbny!~>AU5$G#}yVhyKPQcwq5j6gN%yGn>DUpSN3D z)+E1K3)214L2{|DdAHwRI-zkcrbl4s*6h-n=Iu?s z%Vr`D1LM*Sjpild}CK;oeXzj)^llUTdcihJ!(}njV za^yF%cSt_wX?tv*%3qxSqX6|Uq8CmruhnqZt_3%7`+bdMY|OO&8i&i$FX0uUqDg&e z;qMkCW4^XUip4Ks#dH8OgX-jRJd=OqOYuST)4#^IG-GwGkCdA5$G=n1hFzFaq?>q| z*ZVRa5C8Pb@ny%wX6N(y?JsxpDScVwvz&2t%Nj6@*;1FAEhyYP56k&{mU~(s`6M2- ze>dULg?yGrT7>r^%a5`}HO3oAF1IcElSku;xI67FFB$JE@wFFMpwimPe^18;|#$kCw<2cZY@Hcu_0XV}oHSabK%Uc@fOu=rb zoC8j~IS5sjX_I%K%eqTI=81dgkMX3Nz~iN4oYe>x$6o>L&~`Qp-s36F@5amHj06sp_0Z#iu_bhsRGCs!NO2GjhFKUbJ6_fZX@_qNIc+Bkn zDql+opg~(7LgdcF3Yz=NF1I>()ftRwHw7W=++iB0oxt6uH$JWL%VsC*C?RYS4pSVK z=fqoDt=z+4s<3AhmFa9~){VyDq@joK) z<;%6)y|+r`Nh^eg=_QN}4k^zw%@RCnXIq6`IL=r%bkDjLTdI4uMmx@;CW9ZzU} z`^@AY<4E{m#?m!SyO~%~*Z2{x2)b)P^vZKOqMtBD#JToJ*4oWzK8(}S_>qd$pM&fb zr`_$xcydKY8{R|%B)F17^vMNU8PoWYDJnug1t9{tm9;V*(GM`Dehy;M3jD_|QM@AJ ze*0t&Ei=;3Bbd!33~d=gu)JS-Id3n^oV8uZ_D;E-NQY>l^X4xvJJW z(#Du+)imzz&aA9!e5<(&UWeSJWhJLm1pQdW)W3<LrKf#|j3#(z;l22evfB3A8Wivj&q2P~lmcS3hH15hDpuNy{aRz87@WVFF zfTwZSt^wB7;}0Dq2Qu2=Xx%hXQ2g8?a3)qT)hT=_b%0~pkUr!6DH?jWZP>s>gfAMO zygQr+BJ;@47UbOr+<^w{MM3znrJ&2_fHRLKgy4_h9x3uNFa2>mwrilJ$-6y_X~bC+ zMs8y=FsE^TQxwkJH)xXs9nHHB9IF6Jf9{jPs+h*zEUijtd>Fq3g*fq@c{&zlncP+4B$(A-$Dl-`#L^Kt}1FHY)Yyi!}hK!YyL3){xU{;%nY@YE@O^Zi}@lGM$^u`ai?r7ZyIH&2Y6S{29^-`DxAHoi#pq^VkFUyPU~Y zGnx&Pnbo-a;I%4<;wE6UaC+LB$7jpLx8rN~FiHzpAHZW%V$b{ouREOQrJ8{F?wpD6zK4MBkgT_za|~ z$#{Q`^P^i|iCOTXsCzTkF3@;bWIKXWkMTPicS~k9Y2n}E$0t|Ex>XFVW|xG5o8;AA z_mI6lxti@43a;YS%v9j_Rxw55;M8)VtU=>b#*1ed#3zdd^{{! z^9fB~TrhQ*ho1yj0h+&+1u? zyT!3O(0Ikem|dCE_=w-d%_HB#8PTn{)t!hE$1onG5Us<3(?s$^m9phMNL94)8fcv} z&uDXeJS{YEzh(>GOMna?-whVDo_lgKIHqyDYSy5gt9g)9B+_#qt_GQ&#A_yi-JTl) z;4I6B5WIc;GdUQUYPa?WYg#{7HMzgweW!#eLk@-Z(^?Og;5zxRo|fkKW=xB`J7xw0 z&F}Ol|1-|nyp_3Yu&p_F#T;a>Wi4D!sIhy4N#Hmo7vU_tXO&FNUl||y&*I9MOlxPA zz&gu9>UnO%S$OeF=C$4RI8*)a;BO$#WX3d)M@$9qqnlum6MY9r6au`9}-zxa@>!trQm7)Oa`-Ga7f-uM=h? zIQBwMpa^$|>4Z7WL9O@eu%@f7n=b3=K`>?nsrFqOr;{RaNGr*DO8cH!IuIX#C+U~xbDbvn< z##@uu{Kpd*(_ca3IFReG8`_k!d{Ofwcp-)S?v~}tn#Y%g{|jzSxwfwHHGM%5V}_m3 z_?CvnYx9q}4*nNhd)&ow&6HMl7x^_b61^P8LPGG-5zYaFG&R3v#^NoF;{w=*o%^Mm zh? zYTPaLwKa|3$b9++b|u%=H4zp%rE&X`adK@#;~Debe~qu*e}4ur>zsiQb-KH8YiG6D z{mhg4b6VdWVr$zG{kp0CH_XFc`hi`FLQFTNv-#if*y-WF!4t3)S&;;ve8HHL>EU+% z=>2tC!$}rGIC0HNWGFW_%*{dsp5_lVYcn#A-K z{{~+%Y5=Cw97GSN>+-;bPj?G-T|wjSe($<5jfY7Wf%ot~*!?Ig0w8Jc{|u9^Xm4C| zAouuyyIEHudU)-=nkAiPtbQF*;KTS10{n$1s&(v!;Kys$Zd&6<8zz9=(EUxz&uAWb zCjKw@^~Wq9K=#U$OGU=Zm@@2!+?pPux!^yJJ$aY+Nem>15}MCeOp9?{-b0?|-9>RI zt?|1Glm9o`>Mp56SxviZ<4|NVxXa^ELF?mbO_BcG{rI7x=G|p*sH}0fxP~ekM?0JF zH|kFTXW3PV9_<{eX}kOJj@sX%o$k6ZM0?Rrd3tuZc zDKg9W0(hNa3Da#hVxBfFhIQx1lk%GXxki11h};KT1FoYdC5J0?%+XdEx}G-eh)e4L!nG}cN$n%SV*lRZuIO!GhRD=HOB zXCZqOdvZ>jxs`cxLF0&4{vRmPeL3OeqUI5<4u1U8fV=7V5WV6}02j@5chyg>YTVsX zJh`TEx5Q7bYurxGuH?y6nsD7cxuJ3Q>Eq;Sjc3e9{vMAkKAi*1wzeQd9r($d=HH_a zpJra<+nVR*iTwTbdHxg%Q7=CFdH+xN(eIRmX0g-?U`O4@^;0~}yDiWu8I5zPz;3_0 z*q)Np{HNIzWP3_p<8BLgNK^;vaDS4&#(G|7q$oP8mXU&Fxc9sc3zy znlk(ieR|s3Rik#M4&L1V7&a=W)U`31)uM6OtVWcd{72C4usx-zX&kosf5dMcggFPA zciYNS<}@DmvaRtjPDkU}6vpVusT5)**dCg{{YShu=^B1&LMvr_(?${D=f6`u%|9@P zF`Z{2dNlmh9Pndz4uci6OT9a0`TD_;?#<^ zf1rag^PGTCd79im!S2&DmajpIxNettYCVGEbOgI0cXXc`nR~qTS10eTA*VLAJuc8K z#&wspQ(Kz?7-&h0yiYnTK1i>*ur`9u~F0FZ8XW`3LJ5!>^Zs(0()jOZ3h2z>E6Ow<7or z?tZMt{tDjp&BIgK2l#&L|H98oXrd1M;~liz6Pm^w0Ip-CXbgs=-0i&q?Q8Hu>~ws<4BLbd<~VmHe#G7} z9C?P9Jf3%eA9eRfy+HG!U1TmlGi}QB>&`)5WG->ftS;l87Sn$5puhDayiZUBjI>Tm zY5MmZo(A5dOQ&VDzB{B&%W53m$^0|Yd@v83aVSOkNTUcoeDr(Tn5q49d?R0QZqm+O z%TM#Q9bV38gLglglsv7fdDphn*me=m9a5*&H9o<5m|p{;SH06(-yUM-Gyj6?W0>TO zR>G2N{0q*D6BXce9zgVRJ_lSR88)-6aU5rfS~^ncAsT& zj5iIT;#s^2DfGi;;rGR7aR;lV=?4?mY*yo8_(0>I^)Y7nHiQW8ZqlAkT7>^B(}e!% zDG2Dt!&fGYCiqwM=d&|bAq^=E@tGj;Z`kF|zvgs$R z5!3jV8WjhUXRr@KANBc&6Yk{B@HGF~8Pg!|K6;&z(LBy*0r=71uLGz5JcO##;sr<% z_tW_L_rHt2o>A01mj(H-p0eh*G)x_Qc!%%|U-MyqCZf1$skrQm$P3Hmr?MSWnnt@a z;KLK<8Pl5o1GblKn1SfkhL+ZM=YTV2H6E57Xx!d$G=KY3al$;Kt(88DOCgJJC(JWJ z%Nj9fUVszoA5=*UB+pDi^howh54h-!OZLpP#&H$$;g8?+SiU-|IW(*RZs@bjk+Jfc z#}z05A09tvj%of60*q-_f>1e{+*9xy=2QVMaz#$%r?8ueS@Q`^yKBvvY=JOyhxwT` zjl09}%(}*L`e-qY(5|6*ET^Zj6{I&7(bOy^BJ(tg|6IoMvyiGtiwBS*OMD!v!Y=Ms z$(e0aKMvdIzkM3pXjj@s+6p6=;zqVa;I6cd35}z)HiCquZS*vcGoSYiXTTP>kwpl< zD6T;Mb9LY-eq#Yb6=xdc-7U3^MexEN?>7Zqo_W!}9N}k7;#u^zVQF8}y!rer++W|e zeDxT<41P~BuzX$fVOyp&?ry|wWL%Lh-lM5AUTD|UJo0Ig5A9o;$7@E#8b zvH;%wC~NYpLWG~e7 zH|7n`s%!kAqQ#pLoc>wJoN4_$zUI1gBEmQ4`E&+SP9R~}rE?HsVjh~aI2$AM^J!E6 z8J2g-(!Qp#e`tX=x%uyC7NO_|>0$XH$rh+-=pfW5A_8?(U$K;SGSZJNeA&2u=d@#|ufFNu#G!&yzcG>3B$~l>MI=hG|qG)byGn`5g>Lz78SW-is>}`LO(H&Eu5V1RqZ0rWwt< zY24J(IG=0LubakAf#xwC-YeMsgwxU1yvt_C}O%Y%yloDF~6Kdu3^JL*u+&{s(S~vRO21YTBJwHqU6>&B|srO@w)*gfaav zJ&7|N;9F7HxU&jwu+?TUjX-HwsXBn^abmLn-tNBNorr70cmd|T`BrsL-?n%;? zG0o#o?>1k@o}y#TS%e6W_n_J^U+3O1-%`>1uvy>X*I5H=KB4K$@Xd}6qHmhDd`Ao8mK5rl6fpHm$QFq)OJ}B}m~9Pj0L5H?*l~`HJT6Z<;3f(HqK^pU`~w z!pq{S8t3myzKO5x;AQH!P}6rG#G5RchStF^yB0tW?aNxYfCsCv+jCvo@@>t#D@LZH@jvwD^|w+8f5;<%zwz##81c4JPw;NxY-K!w8ykOX z4!E2P44L=V0))`7IlP4bIaYr-xwR58Z~>}O1JimNjjJ&L15HQxqQ#q#G68(g@EuHu z+ZJtYX&&dP;yXBxB&>O$Y5X=&73TcPXp?T-fi_BY5eBEDHu&%xt)uiOdFy{P6~S}H zdzXIObU2V4jr1FS3-2zR=0>yH9Gfej<~OpvG|y|k(lHJ4?us{B)I7dG7|?wUFwM)F zMspJH;fpqBvDxJP2yZ8AbVB3qq&-^YpORfOI9k^{?wFO~ccGgN&DV0K4nBO8Fxrgp z6^xnBEQDNDMT-ZJqWkW2Hae&ATGi^a`$FHY{zuO5Up@3i+naL}&{44-srIjR$N9OQ z_TVmi=dwf6ie8ZUxf!kRF52g2H9qV=((Yd~^syOhme(|%?0bv)*X$3?$25PmVeN_< zcZc`6C5?ZvW%VnNGHu-cL7ecqaPCCJZq78ohZA-#n%6qaUAXfy8vhc@VwgNckN%xk(E4`4Uy?j; zOcU;lC+8J4?$+yhCEy|ee$KOvLc%8}=T)>_SctE2xA4wm15`gvVKEl$mt(+LP#r?V z3;Q_*T-doI_`HV3!+IhM2z%tl;{NbG`15A889svtNMk%qe^&Eh`hmv7`I*!BmrEF< zobxGqlyiOz__5`fZ!YOyy~ovXeo8C3IXU0cPTgAz=clzkZ!9dqn%v4BF_~x3^G-pk!7E=WuerP?v0$$VqWEMr3Z%hxbwoT}DG8EwQd|Nht5 zU!7mqB)*m7EyMBZCgS|adU%vQq0=UWPTq%Icmg}W1zsg@8uS|`8$|3e?E0O95O!Qh z^c&iBG=DvAM#aFpg|;oGdDN2wAJ(%irTItMG}N<=b?JKQv~$PBwyd^uld&zQaU2(| z7>er3KjXKpstw$d z-d59i7@)54uM{w50n-r221sse0vFTh?!|7KA-)3t={_Rv>%&3e#nI=lumU;^AbL5R z11=nXA}~JeZV%_7qj|SpwgZ;_F1MZ89@F}6{cKNYe7Hde1Ig{F?iUx$^YQ*f_^EY! zS}S9*CHiqPcU{|_)%;hctg`}Sk0Q5^X?-lFGW>;KW!qlTJPwXJio3xcUp>=-}y8GZzIOmU(f*g9p)|^diW87u;!Mnd{n9OE1 z9|p}waO~`9=N4L)#f!LZPO`-)ZW045#s`jOWy{C#Iq>0?GfO?;*WDA$PH5cCb+)SU z$2ex3I)s`Oi%&rc|Gzua#m$cfus44!ZIvQ3jTZ)1VcmVTWa$=UFWSd8vVq32 z&WrH3(37_2vGA&l=X$yWwDjw0-x1UJS8G%pNbX2MsQgTO6;9HQW|bmMJoNMuNXMF5$@vmh~gMQuSekb!4ez&$w0DgRX9XR7QAq4Mkj_jP#co?sx@voIJ zrk^jD=wJAi#tWz`l)g4KZ+t-tQaLrP6Hwd{Iz`Y6(h$OKq%nCS z=?P0`HO;jIKD=mMkk|azX06>Aqz+r9Uw6^Eprq~a_aB<{>(<5v70uhnV#y19jqgvJ zHvPI=J{MFq&zGInfZq?eTW%dfmOEn#;1}v?X#VRS#%xm)Lf6xv->{w*c;T0S&w_r# zdIHUd^~`B}f6*k?%6dAQM?E?6uAU2Hn&+cB@L@d{rZoTc35-$Cg=q*~Pm6wCJr`!R z-TuDGlsI%R%xl_}b74W_`)e38+?dAkq%1>!?#9W5CC!KBl{M~8Q5RM;j(u+t{)WEZ z2F`elE6Ur7mkm<=n~&RihH0kyw=9}7ZHg}#ZynIgUQ<}tzkWQcjWXO=!`W};AjI7M zamV6gkRr&I$1Prj6#CytS=@(|`rS9a;h%E?{c*R8{{|Cb;5vjb80MJx6od>=wD>fn z(C6uaQlDeuSqQ1$v3MR*=x=(};sr?a(UbaDxI63b zD@HV@O!XwJk%jpg-O>+)W8Y4umvdKpGSw z77Y5%dDh~rQ0V^&15$qiLh66P;*pO2Nsc(y$VClEX)s0t_%wtJz<|VOA*BAv77rk$ zJ_ABOM9%dI8feZa92Bf|ZA@w;XJ^>;1 zvlgF%r2e?Q(X!DV1s69W21ShNs0AScoY}VcETjy;fYk3mNd3p>@m&-`e|(AoVX(`C zkOn1-ry+&G6a!K}4Rv1B{~rUCIW*?6A)702EH^E(Ptvm z&qnl5uy_u#n-KetfBvk^|H7aMAp)HCsKpsbRPb#Eq`nU!_3er1(h1;FKZh~(ry!*M zc+3*4P#P31J_9KXyr#ujq10zU24Epl{|<{sI{IxU0{!vJScx<^W1hIogOmXn5C)g! zAcX#U>*%sPaH-FL)GtN!?O}XbxvP)<+r#fW9sn9lK*#`eOuPyq0({5e4XuCbkFEZ6 zM4yS!4+{zXBmSv%OUy#b01QZjHbiL9*LTWyEY1q0J`;id?gWI;KlOmcQ;<@>h4DBI zGTPu|DiY5^NQ1V;3y?BE+Tvqc|IZT^FKhji?8R(%h4DpzKhIc$sx~;KZSfkU)Gt`P zq4iI;N5Ssth<@4X&xZQ*$6u;ti2zats9L-ODJnjR0nwq$DWpCF5>G)0{Zl3^?mU?Rj>iO}!<{1Ner*8i@DG4UFN&_BuH<8=@sz;_E6(_jWd z7<7Lnig+uc&w#|+T7PX|aV9MNPtD``6eRqI`~S7RB|J!Jz<>yl&q0WU)>SPY>Ckr> zkoqO9pL*5eWyl5p<9*-rEJ24Nz>q!lcAt|j81#LQ0U2Og>!)%SZ$e6a2BdxfA^fjp z2e|*w&p}Fq8i|4A6%@i?O+Wy63_|KRE$%@|{kp}|kWxRecn)%08k8)NhZF`4!VFx5 zkop;m(@yGp7WW~A{)u*Ku9yIB^}Fl8kpsX0bqHxtvG^3E3{bRq6H@A5Xz>|Hsqb4n zfE4=pEpEm~;5i6sP{$bf9tvq-cQ|`uz@>hZiqQ8Uq`pmPPa3$?4=|>Fj`5`daT0k5 zVel6YFXDfMesY=w^h*#@-?O+6DfR7Q+%o~3`fmUK7dZ^*s16|v24^ik1t|j*E#8Eb z`bRB311a@=iwBTGe{|5E>GsTlkOp;(kMZ4 zJ!`zp7+z=!n>jpc{H|PV8ifDB1QcH|i7j9UZZNqm7`|xA-QgLg&f$Hg#o@}wCo>qW zFqsTTmzpAnkD4lnD}HF29Bwl0?(l%|wqp2Krmz)vXX?7TetQzTGBO*Fm!OAkT-l81 zf576A*?8QycmOGy+y8*Y?POf*Hb;-w=ZUK*ghBkr7LP%S*?YWcaSu}H_n%;LqnN$G z(pgQ%E;Qv)G$nS_)JHK{Ki%5D%>46cfBLw1aq?U|qWFH^8rHO7oXY?WxT+2z^4M6i z_%x)*V|iflCZy2+e#PPeq|oo4i}`8ssV!7P7cI`jj>Erpm)XZL^*sm~ zc*f#6NEx_jaTb2O*>qli|JFGR6$s&9>)PF#zj{pLxR+cwkG<xCAisM8(}#iG5l+%uz%X(__fsScs}$bnVS+rQ?VCw)z?NLZRF3U@2;CiVrG zlNFxjnX2S77OzL}oW-Yp1K!YhKg(bXSe`g-tn|A0@oS#M_jZu@(33M-VMVd4u;xj; zFyG~8HNP@ud3?>V%gH(ri=z`7+}Ik@LyA!U+Hkq6m}rLe@#dD zlC{GZFuHs;!ZRNI=1il@=QTf&uzbM;UA~O5n1I!+hxQed*va@lhN6Lqg5~kEV_m); z;XTVwnR1tBJ;Huf#q!gp4u1S!8BfNy`Ttu?*5PbXf1I#`uA*?2n+50=@R0F2<~A_ycEINDdJ3MG5(!jqTl}H)I9#v zgv1y3efyIglYU?SyT=VqoAgEfmt*T)zNmj&`~;8seT%C2zUM{#_b!?+>0JMV$L&7Z zG;;mhmv_tVTXgk=Y3KSk$A5ZhS9|GCFE#0l``_or-~LqIlrM(2pO(9P-)ViOadH3o z{mc3+Fu2>aFYe#IsQ5&BSO4U_I~En@6&Ed=m*IbN2kzWAa@(OJNB14N`QXSccOSa> z=xui$+I-6qt6{$SME|Mg-Bl~sn^UIyhx(6f@Mv+%;e!XwHGjV(X(p%px2&}2o%_o0 zHIHxn%lgHd|u1jI-(8l+;`-oaZ_G0u=a`ndHqU%*+#2(`o24EyYm7f{! zy7kiYncZ{S;iKNjh-YJsbkjXM4C3uObif<7^?5EM?}GTwZm*9X#;m~Az5@picfCMv zy#JP4Zt;YRLw6nRy0JzkR$BRqRq?y-Ie571qZ`@m+rMnB*?h;!{&n6BVb5$*-l4nh zjUT<+{OZ>J6Y&?47Oya$-?env>D|=l^NsJnbEJe+??Aur-B^9AOa@W%2*!^B0+AYtP!t7VkTHuk|Va!%oemoPu=+dj_lV-qsZ##70u6sxBxb3d}hrE%)m@NJi^)pY0 zUb>ZQx21bV%(rh}xnWQDSiqv`&V*f`cBCAi<hFuDsVgy=KWNn2Kdvx*2w7)UE-&qT=1~3mr9EKeg-~11UZu?KcKD>O@FzeE+heka#cI?uTS&JWE`pAsoh|oi8e+=U9uz zCQj0V3I~5^N%1$Y6YfE5pvaA7cNTSGcd?g+Z48SR6FadkJZq^)>%?ZWpS-&|u}O?S zI9=3-vUy=Y5gpe_eNWR9{>EAEAd6khxswg!SG#!Kce1V~K6b3g?8BmjuN&*i%Lj^r zAuLA3SXi*=6v2kGJmKlV!i6J(-4phFFcE7Qsc9p2YMO1^#8u*O1Y5$s67DEAM)>-( zc6|PmZ4&8w+a%In6Se{D9=3?0Oh`NG_`nIkDPN;D2awfmM6jVU7aZZ?>I_!D&^RvfsSb>|=EiGsmw z0{^6of**$vOA~ni-U>#JG~iNIUR|Q#hhK{9Xf}y|@MmEe0{l~DqA{BF<0%Ui41SVe zq^^Dcl~_2KjpBzNQ5FBxS@?#5^Uuez{-Sym>nO}aSSUYuMA11oQlhg;@zM}BkH1zT zvd5CZ?`FM3V{bO9$HO5~$fGoEXn$zHbj_5scJx^qK~X&vbbDLa^g$1PbsMC3Lb|?J zGhLmlX*ATLHi8XkC2h&N`pa6QHn-LiGa}d^5!IKC>zDZ=q2{dUxjJd>$aRmb|BGKu03TeEWzIJ=q;yGtbDn&E^48x}zuaGM*Iv9R_6=u`!QY@^i-;eAoHQ*{yERMw27hzYB~1gF#;YC3fv;Xb{vk?4#lTSAWg;~Ov{r4P5uLzS^%e#F zF&MQmP?5)v3e!k-_pp=HA$ZvJu`@EvxrC7 zv2Y|3SY5qkepB2A>o@rvS52;<-3SJkM{GIi98u9xp1b>^EWEuTU3aZLt68{`!Wmv|>>^5M4PF%VNV=%#ghrx0UtKM(ovs zY}+6m&jb{Xoxm1^X>~^7E>)Zrft9gx;EGd zCki;4NKIt%qBI`j>mDu| zf)V)%EKLlZ$T~)$I^@%(SXJ*_*;>8xuGZ?8N=0K5`t-0BO5N3&t$JiY;gmmgmoqxDQ=SZBW5uNO)BBSm&8K)LmaU)V2RQGX7Fz#{n*_> z<72+{H@^`Aajy0MDB|xy^JR0{yaCjGpx>ZgByD2_gucFm76kMgFNZ+tggzyWjgJl| zp;ED{GT#Qu*&DMpX6O3Ll%MlxPv^$RWO}`*NMkXifCzUqt2j3g9>|;yy;yn=>n7(i zvWZJf^NY=FlHsIk#fTgOJTwT{i-qG)JEemWZ+(ga?cz(ADvF`W%HO|WQMivL28 zaLj|4f1JxAe%AJ?dCVMyIbIW)_kfkAdCbx=H+ZtMp#xR?=8AC7qbVO)Vj2Bop?`J( zOC?dzK3KaHsa44O5r(U~8EeYf*Xrt4?USy~W^`j=n{GH-yYZC=F+zS}p9`^);-&a6Kj^KzhxKF=BXhPl zIw%ykW@^E4%~bY!C)cwVoOaeE2gbGjf-~pAo=%kCk>Wq_z16LCa9y~L^8ZW~runQd zOBYe|+31mlabLUVyN>_h3{V4huEK1RF|6z2^|q82i;eTyyv3aeg*pO)g#@WONM#z0 z2B-Kd8*U|A`MJTsV#2?bY~>NzyjylC9CZ-@FJLJwQ*2zowhx>mYrOYE8%FlOc599O zWx{bUyU&&6I`)IX*iY|KHObh!?xt48_V;$JyU?b;`#Vt`JNrpV?v`f$`2DTT{P8Ol z&ujaBmVZ*E2f-$ukzz+L{`iLLc>6;rXlGsLzn1fCzi`)*FKCDmM%{-XJ@ld|z7O7| zT%5ZPlh0}qw2-Zt`iQIUdJA{dgB1U33+lINrns;3+_DvnIr63|asD79mNw$-iLz*M zd?DL9^~GP3+P4~{%(s%-w^Wh(_jlCXt)%u%7rPd*H@ozfMY}Hth5)VnVYOIwKl^pG z65B0m^6K}5eyfOH{Zg18VEZG7NlH=|8xP3mTdQ{R);_>O*|>_Et%(21`z2z@SOE%JN;8TeKm?zbE#WH1`aYd6MRp zy}zWnCz$eX<#YG<;>HrhK(LwzS-05rgc0}kTGOp2yZaH!SITi&4rv?ZfM3}?Q+OU^ zv&QXeGgOyvGgP~7GgP|*L$#FMJvO&ZJ4`;`q7%CoQQoaR*fm{Ax@svKG;U`b1}@!( zft|NuU}u1VhuDy@t7W6N=*mttd{V3p4Zmb+=TsW1VdB$=*syUs6v8b8cBt`H1Qz^~ zz>YT*fu#?#;bT?#t@WqMI^`gYv zc^SU%+s^X2)saArJW9=OX~&}kA|3NLEu+`!#67W+j^yK;Bl5YG52D$f@~n|sK|K@g z9%TKBR|2`Lrbx;r>p)VC zX={_)B4r)fWZiE0e2ZMRu|OS!1Qb4Co+|sUXeE~2WgoRID#&Rm{<9dfl5OfNxsfPY z&sy#5=2TI$k|lQ)wbv2X#UU_@tA!KUu`4PrYqMR9c?471QL*q5c$r5;C8bb-K<}bQ z**okJukTUzsLucMofmt458tur&h$Qa2b93j( zJSnO7gXQxrl5#Jmyjv~CJ=5#iz?SGN+8gvDs|$BsKk9GHS=!S{lm7Lu{7n#Q5QG{( zMbr8jk%A*_gD=7Qwie{rFsTofIW{CG5Z>xU&C&+XPI#9=kMIa5cR-5M`E2_Wt_wY# zmqB}$TeHN~`u#*}jbF2X)`EB<6d;nc&F`~j`u#-2xupH^wiVG8_2WhWiWEilIVQg6 zdbz(I#Il>1W^Rh~k4*8u)4ON~_6pzqNkr^Gpz`i(A`|He?@BSIEoql9;#n=kw#|Rm z`i!Qh_}`WKo0iiq0qG#5r9r2yk!e$k|L7u7xr2=gy}4lPcC7<&5U;-5TQu%q^UZ}5 zHLYZ#7KT4_ivPw%F@GnshSPQ~m0bQxt4i_veVJfa?Apmj_Z~}+^?6!$L9Vt8JH0VClbom_~(d&Oto=_i?IF7f-FOP;OET+)brLd_z_2>G{;(NYtYkvQvj zY7rO`4sqJzE@F&!Yh7u0aq+i8!P&wjTM;C4=g6O!}Uj+#cbV%QYu?K~cM&MYxE) zv<*{+r#*KfA?HL2Ee~vICxS>FIoOSA%P!TDEJK?V+t&^Sn0D)68{H-K|Np?PtIMtI z-h7hSjXQEDWZdmR$?}p*Ei5~i1l5r$2XsFm-~XipG5>o9GOzyl^B#=YCFR4IbKV-_yna+GfSOc7-=Z(Ow1^C%C+SS;L$t_ettkT? zv?1xfsr-?|ds7=A3jP3WU8 zah359S~;Q(o%fLRcD8vBDQ`zDQ2CnkckT+%i#u=DiJt5H*Wqi<2i2ioOvVXc!n_mU z@I-RLn)6!Eeu0Wq0E97AD8+I@Z21El6af{gyo_#NMz=4c%K@ccXcL)m%MosqzLb@ zF)vXwfp4wXUM*~Obl(B7(Pn*hH2B|b)}6b9>T-6^2)DCW@~B=tWJm3|5M8ABZ|1f> zUpq?AplMNM*B`&W9lJ6X*-jLhUvB>tXT6xdlJ$xNB{;cSJ9}GBRk0SoALd_$Z2B>G zkoets*1L0F{exPB+MU&g<_$m>I=;sGcKIq3NMy{I&SHpjJKIx6!CzD;DPr1l@aS-u zwr%2@*Vxl-6?nxT+3#D@C~vo)z1xyb+UEUuKO4zhkX-Y7&gJbdV7Gjq?4fi=H$O7m z(q7leh}E{WT4vl)Et~QP2hxbli&W{w(V8iDK>I_5NMjb*(28^8CgH4({@2$du_KbR zq`R3UgF!b3d_#^&y!{Ys=Zeq5+`B{_4Z5(3x2|0uV`qP!Nqwhjk>o|s@(<37=Iyq1 zfDgI+xi^&?_{DgnA9Hg!JHw1~%9Lv+=NB+zXoZ;eI(s}k?}31?X7e!zpU7Eq!MVw? zsJpoMIvd{siW8Wb1|4L{ZPULw$o|QnvIB0@NmoAY4(`@huZxD`B6Ba?w^oRc2ty$~m+u0ii{eCSC zxZ59`Kosz=IW2j=3FI|)YRP-5CGXFaM?>@Q3vMlEHNx23&p+Pz zl;+|zM$RRN`(cZA*F>)E+1Xv=7;;uId#+Y&3G9tLQ{;+bfG76)_8T29WU@kzqTjoVoiu-#l&bopnw(KU|M(P(U& z7JkpGClcJ4J(0Myv6;2L%FYf*rLrRP5|r%{bmkKD=o0ki5_IVj zbm=n9o6sjjh&8a5M(I+a_?H*^H$679otU$Lg}cx`G1S&g(y|z?!eeKZ-%*=HKR|=p zYeT2zGK{CyP3wDRxmB1<^}y#c@VP)fqy5{}6}~TccbB1m6D>@OHI+o=+NKW8ST<#N z#)=aOG$N#*$d5_CFDQX@GADCt6zL`A7YJ1Tm^)PYIBJaIq-%M8&$V)YMb4oi&TB{g zmDj%VAHL4~zUz_xs+{8fa+IzcUce$OGOiTA>pQvT%8fr*l(#_5Zn@D1 zU?8oyQ4A* z(z?Ll$J#WO7gb^8C)sx50%4c>IG!GqSQ zc<3W}XyvI-teA2XS9|)!igicX?12qb9eX)M&N+N1Rsf~`LiCCoRDs z0v>R@2r2oG0KTaj=QJfPZ!I9CDm8vrdj65y@E-$h#<2%Uud*dLQz! z$~7Emc*brtWl4C^!D}kR&___CPD$0x3w2TPl8*^tAewI6<+Oc|u3O+JIz_f{&M(|;UZ*|Q; z^l{(Z@Pjz7m(j;UM4A(D10fm&UXZ>nJbmzqg!CxGAx{rVI1mTt3W-@EDKwl;4X60G z9wFE!`mj)%G*ty4Tgxcj5`ZLt27GEqia=o4wWPD6_6}xu#UVBsf!(3p?wg99{!Fvv znjoL3D#w~A&9XXVP#s;4c;-JdAQR0_a)1nUC4;(HYJz0+%!z}}XLkR=`OJkkTjZ4D zuj@|bSYDPAlz(6^fD1a_H zeTs1*BeF`VrcIH}Ulm3&;MNbz1Y#bZZ*|PFtg|djRE`;)w8eu4;nA84VF06Y|T?IZVkNqL#u31BO?xKS>CNSFcu%>Ko~k49{7GGS=!nFDip3L*6Ejs5#2y zf*XT=hG-eHK>@|O)LBDeOtBV*+2J0oG1jIUKM*CSi$<)_IHnDsk@gws0-0`Eu`#W6 z#YPhOR`%E$$t>iEM5UQ`5i{@Scg7PB@ZgoogYSx@bU>)LdT=81O}WHxA@dNkM9FO~ zL|%}RyLFiSdBB$9G^F&JaJ3QSgK#F!r?KmcvHHZs9%n-&m+8Vku_f`)+>T^Tm$z#L?#~ecxU^y{ zw#=?7NDU?)_qN|3cV6QeN8oD_f5r|9zLc}%@8P-8AALq^D_7}^aJs3I;{V41Vy+<( z_5Td(1P$vN&D`oPgD+uyWyx9IBRpsK*WoEH|3BnVK#R?&vBT-Fik(qn%e7<-ZFoSdCbK#)7`g?q(NM(w!|w;f z)xvU$bz8cKIvp6L6#x0}C{0#L>POG=4+3@t9V0blaS=*uU|=JuY(%lv&K1%AP$`a7 za2#_kpenohoAQpr}S)8<%?^0m~FNN*V_D+6IX@4g*di|(YK+A=4Q;E$A23EJzEQaP* zkd~HX(+d&8gRU2BHY-|#{V6YpU2VF)3#V0?*H_Db7VE*>$}<>VyxZ|lSqL2Bcdp8S7MV)PQ$9o1k*s;{SPf4=HwcXZl5wdeJak9 zb|W?!jOQrWn`xdi?bV=!^pK#0+zz9Qa!n&Y%QZP1t4)XnObA`tPYTE65!g5}$Ij3g z*%oZAW%DE*fm-@Bih1Hd7vT%c&FX?vaMQH?#V}$P=lY}miks#fUyF*eAC-!-Dw_=Bt*i5* zt=Q9kYlw@2p30;$RtmqLO*%}v8*p^c(N&3)v^{b6mQ13}KKE|SBW@VStZv} zGP!PYaMaMwy&8w)!!!0Gf_>EpyC>q@^#Sd0#@i+`#46fiAhmO!D8U_3mz+1Sk1?;v zb$(8ZxHJBa5c@p#CgA3Cmi#-M!b!|4<`jR;ZfcYWQNzZ3p}CfR;ar1#5yAzI^adF2 z!!RNmp6c9*aYZBYG4#=~*v6=D-Nq2*)vRw<>Tlc;XeCf->Y~xaS@LJqY(SrynX*Ah ziHrw6Hv4km>KvE)J#mKi@#4 z6ltv^_5t#tlR4H*u3_h+IIfnAw_qUQ&{RWsIm;1ptSDIqR*Fg05K)*Ka1)?DSBsz+ zea)pob!#r-Ykc)T8}4due<;QOSuhdITL|Nrs98kg$Jn+U{Ep@(rV zXeVvJ)7+nib=rXtIrncS>5xZmFqJs}*SWt9o{F&4{7?Q!#t&4Et~AUjaZ@>k0pu8e zvHl_?Ynf)HNu1<`IS;Z?%4EoED9MZL9(yOnP#vob-GNJHnBxC?5_J>#Iaar#k>dX( zS9TptV3A6%AUV~L57HLWWOkqfY*RKS4^^^TLv-5r{`_&#_zCMe=w=fUfqued{XMh2!0 z!+65wRD@|xF26Aqt?}Qv%XRHq_<;xH6z1AT72u2*1-OAq89!s>AaRObQcuv(MCw6` zf5UEqZI<5=YT3QvManmp-H!5!wCt|I941%Y*pSp%JtTS=lD`}&o?gfMiOdBoxEt!w z6hU<{niY1oc{M$YW$XBuO$AvYVtp1jyJ#Wg(cIufGscBkk80UD$3|oPbGuWGyo6S* zCO>b)F8MgjnV<8JQZhr+o#}UDrXDb5c+R)j%R%L|28ewF&A2SbyiZYv zd>i>$ZhISI787EY8I!_e2jkqoHg#y6A5(2&|DxPzAVfDgatF6RL^q>WPajm5J8(ug z?!h>EN1~VA_JlO z0l(Jv)PD;fk=POp<^L=g$~R`OOxXSZLp-$N{}K>E^b`;UoYVg;C?bWSp;WPMwN#w^ z#acF2-kPX7&s}{Z*)@@*o)ng%>*6i%*<(X)=;Q@si8(mV1dCq-xI&OxV(|U=B z&)HpFBvC4&5V?L`Np+mR#OJkr&VIxA^Ht*T-`T9L&(|0_iVFreOA;{}K&lnJzF;4+ z8gbHuoQ@jA8@smzPag;ecDytGg+hJJ$`WW4114O*!eLEo~!wtK$Onw4+!)_ltzW~@=z z8gMPrAvQPQ)xSnj)xfrf%m>HVWOaQcvTOK2QFw`Ewd5tKyvWOJZ7_@*gm8TKCJQ#p z=VjlqoG~&Fb7u8=8;Yl=<6{@6s&Jb(Ht35buNk!>%*-qR4E* zRm+^j@Y=7^3r*tl8C zcf zH}QUClXu-syja!UN|R4vo@Sb``R(}=c5HB95{gXmKY;tJes&*Qv()Hp>5btFUc-5S`IPCRr$QN}%dk6>rKzIMD1;~8kR zJ@3yNM39M(9)|6)7b5Izv6MeikW{i>h>3gC???VcN>AviwV%-M1)F#fRhV5Ao49M@ zSSm^Sy%zDzd)Q8W5WAt1H=(`zdQ-k!S>pzfx_xt>n$2m&3*J)v^Sg_*5WW-d$~T2@ z0fGe`csIN!RMCM?!!S2?;6n!H+t~w>RO?{eGm%KQ4o1dAVY`D*;`2kqx;yv~_L``? zgTJJ%I3tocMA+z_&+F*O*D$<(dAbwd%6<~dLis$r3iDPd9};Yu@bzyk;z}qV&ti+r zJi;4)C*Q>II#9KlXYm(m#F)-JfxlhjUDcWYi$!iAnlhY3FwnF{n-5={uY^vjfD8Q9Xv~#0!1a5U~DP=l%+(Qc1@Gk z2APb3ME=b0gr^JNj^5e2f+qC5D~1mo=5*uU;ApBOJl%M>NR7bYd@0-!{6l=bz|o!G z9bIW>j-!MDr?#1(HEUxP@?JCY+(urL@O0#y0GF@_gGo_sJ=(ZlZl$qjBIw0Qa%QHeSpfjXognIz*ekZ0|!i%e=k$tgR zOtJ8XgK@R$cVQ6-CHuQdH z7pn%Kd)Z>w0NB7gR#7*A9~%~h*`pF`wEUFjIvK){@a$}`5@g$p?ag(u;_N^e=Y;C%0%SxY%M6#nCX&tro9&F#k&sJ)9oS!%Xy0JB~lWh-jLXyTIvLE8oL^U+c|@ z<=uih$$lrU#av&yHA;9U@|~UbQUfhnjs)H<*n>_S7Aq6@6QNt9Fplo}O{Vl z@s}D!S`zMzWx3Ev)vssL{cnbHk&Qd3_(_w{WMy2?ByeBG>;nKYAaKx!87|w{! z-kcPEnFU*{Sp`n9awaTjktmqS`?4>+l{5L@SeKFo_JJz9Fg#7WR9EWG0G-5MjuGgsZ# z!U{y&^fZlYFy6Ubz)$glYHz{4e6&7sgXHB&x+zRu(Mu?;Zu(y7UB3lOqo=WH^XM+((M;=MV9MChxNQ`F_r(dLtI|=jlyxPZkCs)_XjQqgF{iC8@Ceiv6itLmpkUdbWdqVZu{A-16 z|20qS5J|+avahTc-#^ZW5jEehRkb>lBaA0z!31q4#m?Ajb#1`4(o$_G^>IV=R)<)& z3UMjmp;d^M#tQqBl#CafpX85%CvVVicn^5b`CiLY{GWJ;7v|NxPgf$;NQ8Rf;KD=B z^0%cRGG#S%Y`L&KO{16KUH3Haz^P6_jvP+!*&O~E8-x+c!(QkMb_XrC65iGJO!y20 zOR)n`rX31!=B<8)+#{%_x#8rtCWw4D7hT{ge%MRBmNUKY&PIsRA;#oMw!Q8=Xfa#n zJ+zh_(lYPqXL+0nLuT5DcyyI;Y~0LfS1A5Rx@(^L&x^J8=7{sQ4Wpvfxw7y*-Pc zyx6AfXDogqn>6a(hQ&|jh@mg>X~R~Lu`gL;k{$-zw4OwaGfoKHaeOm&{j>tQ7)_Vl z;?9?43(rgZF)TgJ1(-LMiW>z`UCjK2dX6cWtby_-CTOO3+(xHWUFL3^rGB{$t4!=@HdpvOhuq3C*`=m3%pM*QvkgX3;a#;2 z(>V$^Z^wKTC3<-a~<}&f0CRvSx|HB5DVgbD44Xepw~v@8EwJ zxXiA-KbE*^yPrpC`m?ST^{UoR*=XiY{%kPT!k|;X6I?k(_%8lRa8*k4k%_{$3o&bi zXxs(VmqpZWKDx71=alBZoFrl?&2M6=-wn=2ijBK5ZN`X7fG%ddL%CJT(B1AZ?faxO zzxA@H-_4)GhD_!jM8L)3@E-m!J0&cy!2SMK6H{J+shtwVuRu- z#8|Vo*ixF`{amc8K!j5*_Eqr2F4@ETQU{Mp-v;ygWBrmZtBdv`sx4^}&b?r1peWwU ze+yy*UgZw}tb3J@NV3?qch(c@BewgSZQE|tyUTeorLCDU+`6{J2F|ynRkTZRzH*|U zbI)`AoV$~8o9m~}^^5h7Q=0ETDSmtvwsT5U{(;{UR$QYx`onjsc+qYVu@AC(L^$?A zmgOR6AD_UBed6#w-iH@gi5e{G_BSj$i_E;tKzDmR#;9qpk z2IZG=dALDQ&L|hXUguvxZcVRaL48V0If$vfq*`n|2>CrY)(hF(Z#aS;;=&_|brTKtV5bC(Rev`GO9(j>s=wUv-JBIauv@G16 z-AE{4#g9S2hX@a2ZP6PiNR@ITb?w0_%>&uFNq(db+c$_Ye?b?`V&z{T^!eiSU-&ff z{#*PmG3ZU+9XkNFH=$BTME0Bb=AASxx*AEQlT_xf0S%+E7otSvn|u(Tc~R87iT#K9 zqUtSFbc&|8c;DXncI`FE0V1lifvuysT5yq7S}DdHfht)={t^B~ciaR0gY?|MOf|@F zwPtOt6*+H1P=~$6Z}Wd~R_x6`%17wTA`TzNim$XrG#y8CnuvOjzY{sX@NQ*16Lyqk z#`Y_7Pv}>+Y{J?y=Y*`X>WPx%DKj~y1ZpTYNAMAK(5t{P$e8y}w} zo5pKQq_o;KOs?0;adzs%GbY}+9$H6Y4doFireEugbhK5lyze9LB-3D9Z6gM+%suQ-c2a6ANvc06jU>g|0R&Ax}wjKsPkGr#~K$X1OASIJSS5B z&i~fC8et+`OdMmpwlb93pl%jMU8okeFZk?ESIYZnK?p(r7*~p{(k~#i??vqw{1pf- z{~SNaFf!*aRC{gbX_CSx*#5zLa=6|6ulTpD+ME3~AEoonRbtmg1Ru57fyWB9MlAc5 z?*~#uJ=CXKWY$CGHNsiX?+@KvMGFhMfE;&zNUf-=$AHHOO9MvOD&ia9&1@pS0iCsZ zeGU9hIyX61MMnGasu7+dr`+yCL5CCpuH>t^X&#i(wD@#=rRU10(1?0eOfD z{%Fq_Vv+}T*CMev&f4BM;a!hiR5ZdNjMGGYBmcIO)V~Sk+MiOIADtu4eUEWiEN*;{ z$qEbZe@peN{x{Yez&HJXq{Ex~1AkrT$9#YK4<8=H$C*XUbxZ|-j_X*>j57((bvSUq z&rlos*6aR~!3hy5&6(XvG%3vwJpS@q`nIkKy_9w_JKb0yw7eN;IGgE% zL&upKlE;~^-aXEAbr5=4!SrOFfRBkX{XPT%olye69ZL@2$E z+IuBfZ^wGXcPxxg=w;WYmy-kntB+?((WQ><_2K;zBB*lV-~>y2mbTx$B)%g~-WL%r zrR$d@n7s?z>%V2JK-8P`Q#{@*4u$Bm(7rdQgT9URNf?|v(BjCA-jhv7hS)52l4pRY z*q;}jFjV;N(ECEUYwyqp4Ne$Jw^uebBt+r*LK7IL>yU6f44(N|6*(1hFnQ6(5JGg+ z$D`V^j`|F~!zT`P)bHU5QKDlfh#+y4i0PyYm}gZdWG7mMB~;I%;&q|=kg++$eBLCF z^FXAw3UAtE+qEehD35q*h)x^@KJocJeipEu>Lf_ip(^%E&3Ed*0?4^jf0_t4-Kk?S zZWSxd`f!4!X8jdYjcecsPS=!A#ADy`1!7lcy=%KfYus8-w(xbu-klV0$VK+FXdDci`ETws-WN5%9kCaF_J-Ss%vG7@ksqL`-o#7s;&`>`0@UvM%po4RB5 zX)F*tST%H4;~M$oI6nqCCy^S)xnA&Q>)KsW&mLoGR}qFuj$ACF@a{xAJp-;Jxas}G z7=lzM?p;qY@)yQ`olFP`QN%>ybg%|^V0vO2!OD=tRGGg#fp&L@srj-zBykp0{&ONk zf7UFIyQqiWqw6t*&B?D(7GN;JhIsToriY$^9h3YX`lJrYOchUEAkHF9I%o6YQ?X-v z>c0t50c-P=)#6Z3z2Agm)#OcRs;=M8@PP=rkM^$vR3BRpnBHbhrDv3lqq7{~ts?H~ zmt)Axy;^8T-hr@BRr2_RyO;hfzJ(do8|Dr3FYN;_U>0Zl=)?Pz`|MhZ4EitUF%RxI z{YbUq&@4JwBP@M&S|D5d>UZM^Et3FdWq{5$;9enI_2yJLzRlfN{~NylS!~fq^v23J zCRn-HL?>YtLQCX^%i5ioj4k@zt_WX&buS$CAz<9Qe5$J%1_*nT^f zSv~%e!fE)n>mZ02Z>I$Udz70|j%`u@rZ(lKHszgBUW@YIx0W~8E86X1!cf>G3L|m#L?M~dI2s{>up#DZ~6F%dt$8~nVwBw07I$VS27~$K%BFvOSQ4v|gWq)Fo_jrGO zHpkj8d=Rv$N~|2D&qEyK8>IUw_`6$wzl&6dl;-heR9A(-VWw0?mh zfU6v$KL$Ep%W(Y_7F}gTfjOi)4bf9;uQzDcfFprt2cWLW}5DFp~D=PwTrGD%!%u_%T_V~O1*ZwP5d}k-wqSl zJP!0@MAJABUM3>OL#)|i<#?zOl}K@A1|-8o#}vI!*SEj=CF!@%2wMt7fZI1I(4S95L@HRp!FZ~E z_W}o5a-2W8A~2u9)*~g2tljhRtW+p#cP5@gNR9HMlPf6V!|7HN;bF_yZOz(^osHgd z>IvY8>Qu0GSTv@>=}r|@GcheI{lxGzL?ypUMCe1dbg8c}D!D=g&C>q>U9X%4?go16 zXX)GS=z6R+H+s&;6ESngMnA8w?!PYUYSb|tgF5u?G=ZS8pr+->@ZGCVV~t+ZeP|3_ zt6ivLBUV@z>GMpDv6Jz=kjeAJOKU*Zvq=9T2y@HkEPXKFUFG#<>EAN;;K9aaL%H|t zL;5p1KW^G|dT}4|#0uSpXK`qS-mlLUDF;Kg*l*htLF+D@jq;S6m#=PGnH7U?2nLC$ zUqQ~XqV88%G<@l`t<*yqpVQInctrne2YwtMb9U;Vu&bL=my8intMxG=XEhu~fv8-q zcjf7B1@Fnkxe6vVECC7Bs@!{h60-ZmhfnJfD6FPJTzVmZT{KWYhxf16yYWTYs>&jR z@cm|$zTYD<*8tn1K&8sfj4@!Nf{P18BVm~pC{Vde%m(x*_@GhiLB$qdYE$`38-+Wk zg(Lp3QT%YNDqf~3xZI)O3L}4|k^e}e%x90uo`^?t^^w>*^W=h}QR6o@Rr4vIf=*R~ zuXc-=XMmQifI&CMpqrbiuw4cfmr;A2TllCJW-I~*t>-)n`+2j18wwOG^9hFwXq76t zJzLaL65me)5dXkGe1}_=?Q|%(%OJ6Rw5C9T z!umtDg8Pj0YX;o!Q~8yuoV~6ZdEG$&lK~GKjs2xkp}%QX@NEMgjZx`iM*3K$O26+> zu*$9A2Mz_#WQ)qRU=nBqDpl^s20U9W({MMk$DcY>@uxmvdsYffD*fj%D*FqY0UH(k zhtXE8TT~Nzt;+t|r{D#Tf_0h!D@Eoypv5Sln&#hRs?u+51~l^Pq2lYXuxl{#FDb|_ zD^@RiBs%sMCFfV5((79}{->sh{nMe~_dWv}#D8!L^K(GYR@qk#c-=s6wg}I2uy$Ul zV0)Ejp<+8~@ldnM4s{qXQ^7lpYGzz4d>+(&Dm$V;!S2-x_R)loim@am0PSvr+~1~< z1{k!hMx|JXaO4Bq00!y!7=;~Qso+Gj0kajfxkWA2@~Grww}dQN^#hZs?B+C!0jov! z24H6@tmz7CmQl%}l5ej!;c@trpMtq&k@+HuB^b`1F>1SFRI%Hk;94X9 z*#ebbZxfAF&8?ESA}JgFZKHxOW=hC@rvz14Al$zLc8mfZ1*#QpQLTc-2CXeNVSWk7 z2B}hyD#od}Y+_rcgg7;lWAKIzr@X*ME&+q)TgWB7f6J%fkwy_yfZ|F8YE|x0qlx!C zDt)p*Lh*J1WPQpad{o7zfLj)^Gpf}y@XdwLhS`Ps2!0kWnG&K z^1oNA^m&WO{yn_GKVnq6Hrs$c3B@fK48mX4e(xH;mdhDurb;u;DN^V=~voex$g`CX+nGt>7J+f}xEBY4VW( z8jDK2yMf(HW_RV5OqCz$5Vn_r?NG@TgI)r6a^fI)dkjKUgH zpx{s=JuFjX7D+xNXjG-63_iwqRC;W!g5#j1gzZqtSWUqR2Kt0dm5zhU6+p8nU^F?& zXmXO#$Yh1hCM!uz!7g4gD#a*Zq-qt#WTQp9L2J5McnG;t6{ngFXfTj!RGVp2`7?3I zT_X9Gpi$+{HlQO$r5$j)gas!|z^!uUDw?9t7O6*$Ehx$q5)>%lQ;6vbk!M(BTAbK| z(aC_Dr5ZK`5OPqeR@GQ!GemLvRh2R=ep3n_Rv8qYba)F&^{OCmak-um8EMBmF;nMG#To#=Q1eWmgzsh(&_eH; zg%LQW_X(TXB-3H58;yKiXK0ge&Q|4jIf_O0F})nl z!7Sljj>9T_QZaJZFubQY^`4~E^rSRHII`SqbnLD{s$SSBr>Ym|*pIRu7kcJa1wU3Q zc*1~J4Ne2;mWl-mFCdX&5h@*EaF9{|hYFQ%FdBBMSf$@H@{hZbc0p816q?4U9O){D zg2yFcJVzPnS_2x4y<@;*O_YzHmHuh%P=Kz?z8zhYru9LEyJjgucMV1crDH4#c7W@A zPw(1cdcBc8TsS8@J~Zr|O3jp-G%qb<_FP<@3H(9>A`c7n__(I=NwPDtzIl3$FrU!- zxMrrxblAI@T6@Rr$thFQ<^_lVLbuIExl;><%1=|Jq2|=HMn1l^FnM~Q0Qtp6ex=ra z^7MIWNt073!}y_mAw7nMy<4T-F?se(mt)wZ^yK8JQt_z3oN6%;>a~uJq~z4u$-_Wp zZW`rMc}ksxVaH5b2m90{N83_aUSX6+X(m}db=EC{Ns<4JV`$hhyB3l>#g%qzeQIE+ zL13BIVeagi$@7LyN}AWA&XDXCqdZ@`W2z&`F?ZO^q-oP9Qzm{W-zQ<%u?j6zl~13U zG;H4VdnFB&2N^*4cTpK;pFVviTTEejRBDCPSj_LOqiWF*|Dmxz<_Fjw@JY}jQO^S~y7(IK>4oOgc zq(MlIKkzfPc5_=QfKH>)fKxb5Lcpa)vOr@)=u!TF7T~W^V{mZBFVs9Gz+aWd1_!di z#*_dXwOYH>dG_haie2-R02@tUqiw#d8ye<1Vb)RqFVviLPQtJg81alY_(>j>|2{@M)ke?sbD@G^8t+G- zplyX1LI@3eKSty8ZS+jPP_ylZgkkUF#q;@X@NGULKU3?NJ}W78`m|Y7rwj|QhI)ns z-*>hx9~R&d2!<%%FK&wv;5F2oi2t-|*Z`q?@)xPIl|dul7{n@%)_%(DA%Ox#4((Xo2ED^no;o$@o~ha_qZA<2 ztU3V>YcvxYR2VG?q2@SaW~ge?f~L+7crfG}44uTqrqh_=;;gEnlL%+eASzOw4GlZ# z(1K>dV=0noPd12rbZ~AahJUvw^Gx#1a34+dHt=+wo zXQ$6flX&JawGz6*PF8Cnb{J-h4_6h;D!kJ)DL4$x$$Er^z>~!wJi1B}2s>rgI!uN* zW({jCC4r6EXOu@_CL{W3Nt05I?#Xi55ky7rK<$T(RAi}OW|QCe83dMTEGAGa%Ucq7 z2n{<018=F`wwxLDD>OE$r3%qE5*(1CqEl5G8+|(joib5guQ6#c5~mG;AXWZ>Nn>(U ze_n1f%JJbFd;gI}AKKK1XyKMZ!#<#hyZ@+PB3KLp%cwj#S<-LYL%&fDU7&J>(b|AN zP+ox{kmUg!S&t+^Zjq#I5UPTe-Hy`^MtLJX`4@-<+A?B@`ZUaaL25_7%=# z0)N(R@IC(pzd+L`Ck1AF^f=IgT8Zxpd(WpT26}wPr|B8Dsc;6`Dkb!D{6<7IW|ML4i73ovrVAlyRGiFFzzFi&=^mEM`^pV9LG4-#m>3)uf(3x0-3 zo^W>a&(MHWQ4-1^BbCdoLY2N~0RdwZk zZyx0Gx}4k#Aq2!LQj7=~9@_XQUc$ow0WtwJwLT(6jSkgRDMm!@)z7iiqKy>U`TQIk z9X^L~tj!>`skJuMNK;E|id3UjjFhn{W1S46Ong+o|Jr-4eNN6jr|ma$e!pbj{om`g z*IIj@efB-)Ts;r+{O4L6s(=;k?=}h~XS!A@rxd99>_OgO@ zQ~ss8m4~0qoMW#6U4vg_Pj!(zeg5|X=!q534gvO>&=t_dA&}D2V-(E&E9kv^h<`ls zGN#0pOLgGLm3FvU*Rn!U^m08$1(saq>d2+H`#w#^QPB)@KzUib}_Z_fXSU7ul) zjX3YJQih*fM55R(vFG>Q-7I5Aw7Pv!{9IUn(}#ByfPjpM-0nI zPydo2YdNN7gu<@xWn${e8Uu0^a?izJ=>Qvm@!w|{g&@?Bwh#sE8R?P83zfs3F&)DA z|4lZMKgVvRxS>cOdJ>3T`644O*MjE#cFttEcHB!#kKomhE5E9wK0;vcFvgu;&2VM z^eK(o3GUTa{OXIP4`QhFF?2`r%!R4O?L?Jh2(|;}dp5x&N%#8<=uKrJ`Sa&5AZa*U zi}(8!^fMf!}u?vyDdrmt1P<+3BMC)8$s_;AfD>34W!Q`UTa0H0u+el-F^k#k^Bm4ksC5O`MlQbGiZ?L#UejF#{X-3 zhBCZfjy)iu_w?8*;GTOdDIUhe=yfC34X z-$SqWM}}RzbWQbAeWB{gxAQ>O=%M=cltf~oJ=t&%UnV+AvO!b+yxf!$drR*G)Ajm# z{#(3A{4LKnaWXHw&}sO8%kssuzir3nx}AXBj=b7z=w->*U1{nsus)fYg-&K%mYYfZ zb|6x)c9G0Hu3*c!hXt}h^8Hfe0)xwZv%it)*a5FHpLF1jYU+T0LPXB}j}`em`$l_Y z*viEh@)v_{ha_iZI?x`XbBAavoE-f-IES}I@?=+*tlwqA$nfn>k9@^CvC%$4jALoK~8_J{j$mNu8vL+P2$ zFaNEK1BM_4!r)Wz7PbQxU$mIFy7?lc{+CqbU#r6X@O;VU@o_%71v!8wSya?bRX8wFxuUvngHML>u|u^1`_O5HjrJJevA`G5nXd(>~RH54h6S-V2UqpMhEK)KGbQ+e7bl=kkdslVM}%Ir5vnIco?TD)MDs+Mj7;0nSiCFZ2$@#q!^kMux3japsCudZfD{`%5AE z9UJHmQAT1U!^$e^i40r4;>^0mE3_f5hq%Ym6Dj+)4efx0=y!cXJ7PUrN;sX@VunB_ z9Eq`yFcL`(r4xgNPwLWvqm_|iOM*O=HFAvM82|p{vx+&EN2{5Ed;WT*sf(feYq{O@ zC=%gVA0A-5Zz%l>ogQ4TD>ybHP(osRf}NPP5^~S{Aj434F0K~7f9;GEST+xzgzPOC z2>-hi$iH$Ztbjqhfs%~XhnsBgFx|_I)Zi|R-l@cT!DJ@kHfMz1-?4WZBbmbK)d4dX93);6|%jC1V$ z7sbDisnoxD&Zb>irtdIij+}bNQ>GM;{~q@|)z^3p)a|+U^%*{&+=+=_G;>4BlvZ$u z>Vbjh%BAJ+nNB?Yd!`ppOI`T;9hG|5%im+j`MGZS8&nhc?WObYef<69MxO9X z-ST6xUUl)ZRsQRiVn0HJ~`FA&}r&|%ehge3Gwv1xSezd*_l zhF|o(m!b{mG=X%uF6_$cdg3K!5La5uTTQzaghlwAfKZ4W37xoJLj6)N`cIZggB7UH z?lghP-i)TRqwTE@!`H11!RNH8zuRa^@z@`_hvGkTO#MLGl--#gzRu}1fEe)a<&h#Y zW&igK_!*CqVJMtAddILUKz=z8&u`GPeIs|}wW#xK+p z;O++>=UlP#&7f(2VVf>92}{s!8h+l$1db{F?K08G<%(QqiAVl35-D6$UAM~IH0Mr$ zIbY*8kbESoRnTe_zOaYOzhpq4p_7^Lg(j|ZkHt`HSZkzEdzQ!~#FVTr>JY>e|H+Dl z;eFh`aq60-Rhr%t0yFu?6Yn=f@}!jnuIMzBOrLlkUjv_N335aDep_U?x??bZ>~%Su zo!DMjwYF}d{ua;m;rlHl8=BiqDM7Us<7_wITm%qZPSSjk+V!Dlf%F`E?AIiX#EN*v zMZ8tVY9-{Buh;O486Tu0dFI}8jl1`!rgS}%_yBibR0ZACSY!l!&JSi%oI7nnriq}LPV2R;KVLmH_^4BGv!LW#Lu9+Vn||HX=J z2l@?eM)0L*?LunA;r6^MtLyHJex1c5u6rJ$QIxRSo<2&+xSxIkNvDSMeFKPz2klkq!G(4C5BhU=h35u&qqr-}r8W?swQD_|g(C8p82A}Za%+uiY5chY zi=^kaC%uT7waE5ZHe!l$}dm_;b2-1h^3BDGzJr?@>dOWUbPu4EI z+>tZbOoH6yzCHg({=2JLzDATD$`UJ5VH8KAdeb2H2HLY(iWwSB*~>|4 zlhYRxyVm1e$j6HtV+HP)cwJc|r<>(jJu!nzNX1k8yAAHkxnzE;!7YCW*Za5}98$;q z?*ee?6PP&MI)uSpJ2HNRJt>}hq0`XIIY>Myx9SLPuH-Pf1d!yDv+bw-teAT$IaJUR zDVn-+?TRXSy8)4TMqyW0*K?QkDTB-WrAr!J5<2T*@dyhN4~ffd4)FrUF7JiDloa7; zrhje+<=WNTVRLrP8p52|mm7SD#WXtDBcXANPso>L5a_H!{`wL$atplDE)G2oTU`7!IVEUIZ|ItQ;>v_%r;z?>(#ma&?`I;bc|w z=LDqLfQAqQ_TVK6e~!P2`Ljd#@%+2=pr1k@>-by`u!I3_cWOHoLw{15%)r<+tA5L&M)sp3L%Yu z5oo^!;MmGAvlh2Tim=PRbmfKC&ybMoDVd@VcNzm&zQjB^e2>9N?lj8&5qLInCBLe{ zE07f@e%hz9@q&_dX5$xc*NJHX$r0G>qPGK4&BK=*(W~qB+e7KV2)uM>H6EK=SUnT( z6O!puwh>6~w@-;~nGsKpEXC`6R;^sKxSnOR0yZEyvQjHZj_govV>~CZmsqhV9N8Bs zT)AMyVsnk;ddh}0YYdf{)q0F`<=s-#F7ie>*xy{ba=B05#N^09W6-FSj{z?vbG!z! z;Q#9J(Y4^d3*5bKd?_9w8am?1QQeVPc^z&-UQi>KXN3FrxRRr=3xL-Wv2SgMGs)qV zT2O)~uH*<~a6%SJMbd#@LnjlKZ!{%GH0X9KPdqc)p*=3LPq)h#Jjqd7UJcfot%lKh z$|PZOG{MwEQOtDKK=znbv`w`a7mPnWYuHBP4w>>LOII$^Zpn2B-upRF>4?{1Iy;dP3pV+rH1}xDlnGi6es6$u4knG?zMaqGgg?=p1P`aJsGcv zjM5!5LxrPmBbpr9WB9tVTn_3oIg;hc-K%DLq|;oBAv~BirQK;Z4!46<0u@ggx}0yq z$_*~(Y$>JZcGhA#jemirIkwDB$Y~=;7+>agSuIG!4q>l#xZq&ERji#e=9xe~YU$LrRLLDfl= zSc=P;OHP@x?2?d4dsmhi;tBa$sJqtGZDdMK{k3LO`Xi7-Pm!cku_*o{3y@GsDIt~N zZLdqyMv)}Hl>Sj&jK>*k@tOql6`aR2gS^otUuxPd{#GMcJYm0MU_6Je*U)p)%6yb8 z?qdT>sl>s#D;?{~@={!{N@ybMBr4h=qY?)vTUVAUa6Jq7V}q$n4kT~}TD^Q}?ZvA# zE++!}ZLPlpU0K8bL4{e0+lew~hrG!UN)CttJYQLZC08UjBnND6lp8tHQIYe<*$t+_ z&QDyISV}29O?KmlZVF1K^Tt;)$*yO`$%OWt-BV1C#j8I-@4ts4IToid^KL|~-+Ju1 z7F|z{lVRR!?32qsJxfre1`N&-%b}N!a=Yh^6Sc&M!=Zop9!l3S3QMVugK_D&tOcw= z?L_2ua9kVFX_GrSjy-O!V>5B9{`J2xuoSw+CZ=^rArcO4{(dcqCFEme2jx$E;3t z$C2i^;5CHy;-{oH8oiX+(Qb1GAm1Nc6H?dfQ`8PRlRr$)C#=_jt^N7ucIFZI4|B$#zM` z7#pDdj3kx!uJHHSzT07vrLjni#4oK`?73Qko{UMFWYOTz9+l#2pL272l;qeaN2d%u zzYJDFlq}6^JUPDCw2OyIakX~t%2jmvK@EJkPn_E&wCpAP)q?w@(ep%}n=8pu?J0Ps zks94$DF%*i)p#a3e$P;X3F&Cw!YPE&;fBHr)X9Y=P2(n+DEf7S<`YlYg_m4`%WyWs zmhz8d=o_#0lHHzFjZ3Yk#I+MzqIs(W43=b-(PAeuqc1t34Z7(xFP8IVn6+F^>oUdW z^f(Iv#6PG@cV-)k+l9{08JCHSN_DtGvhgNFs&8YlbfuKyZQ_+Gn;=R zn;47c%?gkU59#r5&$50OiDK~(f64M!d&vK#%)|y5qTR0z#;76vht$kh0}?wftzw!KuJl-6`I;n;J=q&B>XCfC5ki_MzeZ;;ggHaGS| zEljdPu{dcBH7=DGf{TF(FoR(#`=7nBuupKqx5G$uITDX9A zHHgeJKTT?9zD83%Kd4I^a&~k^t~YFh2%cOS&0D&JnCP%MmGlcXp^RI8nXzR-#51go z%;c760a9zFk?TI;AX9YmB)0S z!Vp>TNLEYsish#?V0c})z-6e^21>G85BP>x@)XmNoY0)o5-r4QZkOtvKqRp|CzvD9 zH>|=1V*FoRjfEW9l{+fjQ1$6{>xn59QS3?9V#itUB70+^36rO^nNpHYJTj#byRq~N zV!no5*-UhD#FJC-vo6!zi7h#$o!aakXCf!rIeELXL+Lo_ZD?g;44V+`m1(P%ld+7< zAi3Zg#D>|9bw=~#9nM})a%#AIMuC-Y2Z`wb>%oSN%z)MdK82@li{{JAq5m3%R*^A4 zI%ExzbEnovD>*q=h#~%|_|(B@fjnyFH9+PGtI!xO3X@ZMwTp9-dunsEP~Kim6Puis zbCSEe#|V(scc{SbXrcQu>pvrJz$dTWw~`y;8rL(@BReWSR~jAWzCJr#;m@5Mg#g?n z|4G_RY;MvFb)l;ezhtl)gK4Jwi~tD|&)Jz&w!ScBYen`xeojVGEA7WrNp?s zNcIU3K{6^nHyDXy=3TR@&TC_?fih!@+>9ijG+0B7Cv4B;TVuH|SLkgI!{}R#C;SFa zYmE$BwR~n0Uk2vg@V7*xk9hL5YLz;p;AH#^PWp_3)9^z%ja2MWEoT%=PAt`a^APu_ z&NFD+xl=GI<4LSjhp(<)b@9+&*Kpmz>q}V%Cd*4TpN)5Ud1U0uRelK`ehvqFC6gj*@Fv zcYERQjf|YVu}aoyR%FT3I!&FgDD7p;2?=4hX_u>juB@r^WzfP1Zy62>X+z;55HFVv^P#IBcfmEEi}xK&ul zJ=KCqB+HdcWV;2%IZ9h#bWV~G@HMu*Zn38VtFT%dnmnU2631{`Tvv-{l&lZj5qmIg z=yJXQV}r%x=qUByy`RU|}OfSBl9~60WB^+YG(r=1kn+Fx%51Suxs_ z;0V}3(Qf!{YVcr^-BF2@mERW~W}e^Fd~!}sPGCEDFi%X*9Ml9hg+#zC{J7;DoMT#4 z^PGaoGL5<$V}?yKGC2z=ssoudrEH`h?lg7zCP4aWH_#;0!uSlo=WV)7C;~;%3x?3X zPfIq?tRg3Z!@VM()e(v6M==QYoP%Un*x9D>M0X>VH2dfj!RHhK@#L&tUD})cxM$)} zd)7P?kNW=2T6v1Z%?L^17mVlZ=IsadMlRntu6_lLoU#HB*51d?FhgY@_k&w$jyHcgja>q(?HkpA?9!#6kw>(G;-IfN8 z@vvRBN$N;03cuhlaAc*m&lrh#SFrSKuHly+*-<;UL$!ZCz{7rznOi$@&cr#6nTt13(=QyF zI9NNZV{+tn>V9R!FkAXPKCdo*9Wb6bKb{lYv+x)wuGrT4A0L$&UUKnl%wy-e9<=LO+undzVlQ3HPt^To zkF3}>#8A1(#(n|Hr$oQK%adofM2kE>l|fQ)ScTTJ<{HN4h=kM*lCuYQo#*x^In+_^ zZ1wqcG*-K6^_tpMD?QVYRVRUv>D8{syBoDxf9cF?*9LOxwF~zg0Vc9;|BM3Zmz2^j zbt!Yc-2Z%Ybl8^`W^iA@WkVd8ENR#EdMa+;(A7Y6aKDi%Xu6F4*D1Buj zfbD5_G*5oyC7`GBomK8vR^>(!&(C%*LZ&4yNc zA=&j57^!Xz5W~;uj}*?YTD8bLj_%UG$n-ti3?C0Jge0wjjyC_}II>9Lht(3k z#Y)C~KF1`tO~&)^m2~5OM-k_uPf>`T4e{i8P0_p?{yU1Y+5`R`g(!la-d*W}@xu*Q z^8B<)QB{9Q8Bd;%rB}M3WW-!EB9iB4RRcBe(>jvp;~NC3ZscmGYNP55uJ)-;sva`c zFGN&d8W&fy8n~W{jBMOA^Tv%=-Zb-?tF#C-#GRR4++K~Jo2g1u1xMVO-Kxvv7w}MP zUDYWX)wuC&5^ojCuk*ZhZ1yOo$Lr7P5_ud7L0K^0lXy9sv{R8%nD z2fRK_6&!Kr%=dMf`~n{Lud~0b34D*i=Q|Mx9o%rkHP?Rm$_+EWa@ALEXo^JCCkqNj zRGpb-n)1jn(0uvIn{?foHNbdnWEAkPHLbsL<5e@)vv=aotQ5C5s_LqO$s=a%b>^?CRD-%c$?#V-sML~z$;A@~xxOt@ymocf%zE|N;)3xbCLUrKeOiK{ zH?fuL=#;Ks%Jo6juInjNUs$Sos9tuI>y>Ii*Y|L}UO5+H_?2zoI{mCG)K;&pnz?kP zd&OQ>!R>9PeZ}g9L)s_2&+VOVyZ4t$C$L)<_L*+2!H+ku#=>{z!Zmg9xccse1;a;7 zSZ{>kT52Ev4A(nUv#y)`NiOPBZB#E|-!G1-Zr#qYSzMt8NL~p$eKDN26izFdVdO1t zj>N9tbmNs@nfc{3A?AoX;|AzcJh`~dw#)oMxHCoCJEi^RG#dB-Kj-!0KHKi)&p4-U zAli5m_X@B98`8{8xHGPqYG_Z{cCP^Elq|QWrM)>#h&kfUsq^R)_#14yhkq1$AOu-e zxeOjmtziZX`epD~Y82PIRaVz4xZbbYKtJk~E>piS7MY+HTw63jwJa|vC?Syi!{%RD z5lLQu)y*oqykP7Y-I8L@U5HV$ykOdhlu+Wq-{r95b8R4l;TIy(x?ah3M4IX+H<@}h zB2D$leOyPRb-jV>^{TW6?I-ncJ*(2FXQoOWKU9vh)JzlobywbWm8Ns1wlaN>xBaGT zH%ogxw-1>1t2bPEQ{zkzf6BBkb-eACACc$Tbt#^tAp^d$uGzAa>rQQF0XSpSEUmg| z@ftjqRx5Yy#GTVPbCxzmMoas`npO7R{nIL#zs2Rp9?Bv@X)DkGpXl*y$%k=Wwd%RS1uy+xPFr2~=S)b1+hcFv?_*kGe}S2@~gxj&6Pu&lxeaFrVY zvKG@`i$@bREB?`P z-$}l!36sm(Bg1KS!m0fFuL%XUcXNABq_BGFq6#x|fNx|R+aZLfH4pIf4Zb|4@!3M3 z_=IsRu0cN=^m@7PBzW*F$NPcMFwZjF$qcmy2Lq0{lc>>Ua(Sc1&$9Gm8P6I#O;ykr zzoEn=3Gj63lI%+SNQW`N=X#_2&4 z&>I(l{!)Xlh%nCd@tus98hlP#*E7!Oce$a08-!shSKz$>rkxmd{Fz`86SOk{N1ad-FzP{FCRg-GyVk5*b^9T1AHdJC zEMAy44RJ@m6%aYL5;*{znSfV1uN2HkGc+y`doSldNhYe1)0!5}QhyzE`yYx0j|X zxm~`&l}p@JF?vrTy+2U%Ie1(cM?ATzIx+$`Bh;;#S+|C_=LmO3vR_vI)vf3Cty+9srv-b=SXfjw@o5HW&+c!hF7t^&Bn&0js?C&#mvvY>eQC&}#3E>|b z41u_&Hmxew6im)r+WYm|H3j%9#NV(V)UGKyd|s>~rMHYzs-d-L{14XLS5%kxgDZ9x z)mHxvOWECMr0q5iN$k#Y-E=FlyN&A|T$*V)vAdV+CJ>3;gR1w9qSN?lA+ftwRlHer zMYL75yjgU4-eWy#;LV~%F`fZs0y-u_@OCw5Y?@>*td?u2!gw=UbP%4DjmDxy!)2yE1&()_^s<^tI@ZtIc4XRpQ&e#6#Zg? z*P2m~oKMo@&et8)_Pe4bd2en|{l6=^Ci7h6OA2V)4E8?RM>e)A3d|LzKWa$5K@o%w$=se($x(40T!t^Mj-*xG?lrla8_)i$8 zZ^P^5-0$L>*&tFAJ?7%sEFn1hfPduT-)QGkC?#s% zFt=gL08!)E0(_#2-z>4;0Q@w^#{TaiNRGS9Jk7_9+)9YQ&h>hba5)JK-|=UwJ9 z+}Y192tnQrF5cY4I5_hD&c$zqXY@e^?Q-#Z8yJVn^ZwDrZ|O96v>f<8!p#ygaeD_d zY(&FPT}xXS&Z5ja=nC4}!wqi$KjPxMq-*B`|AUL)Djh&F=6&em+cPO6XxJn)deUtxr7tb~tJVQy5?}=Ha(=8+`?-9Hd_%$vrk)h!?3@d1vCz=o{Ir5tm@IOyDs@lN$`#|d%mUb&3 z3)~aqt*jy12mDc2vFbH)iZCqm+g*HXxxu5|z-9Q+-6Z$0tF`N1av5%eLON)4CAQ!+Q_bgN>|XXegHV4 zt-#Z0<*8SnhfEXR&g;@|t~Fp3NnP+o7r#Gc@VuSSU$D+?_*Ne`5W`nod>gwo(gu91 zostue!*G3E1-!+jzju#;3y>2954!j!#z}F(Kj;oq|KlBd`waul^#%XzGTfRrcytl) zpSt+gCWGgX1^#On-#*CrQQ&`YJ#zW>-GXb>dE|V%o{3QwmAUfouk_%jcuooTiJ)>Y%yt>J3BDV6 zm5XogGlD2rit1hb8{Mn`HWsbd^AP|{N8+Iv@N1c#R%&;5uplH$(I!upHnSj1ghh9{ z3ckq(6_B8NT>SPPrr!ws0T<7AU_xB(p)xy8j*DdY3NqC-Y!3WVThRvgKq!L#1@cDZ55TZ7~(a0P7| zFnHtu=x=fjI)z~eW$b^s^xLGzkQ3YK;`f_(^nx1674w|bwx(H9J#f!ddRw=_qwT<- zbp`z$lSeiJ_nbTKXZpxa;GW^PrPnZIqNQl?tSNUvp+5S6zwave`ZmV5;~|qmx5u*? zPN5uL;?if>LwPaaDHq?ehZ*{S&-1L*zTU+u@l!l zj|&5SedCX=;`*?LW%~8NcewQTwXlLt z;GU)9ea(!6Z}?L#eYO&~&c8u4cw%{X+Az?t9DcyDJ==)79K&CA1?@^Rir5c7?9$6< zqSoP_E4Mp^9tKPs?pe6pTF-*U!gX<1(AOd={Xx;GnNwVyH>a5NQjpGc@trM*>^oA7zYBboOTPvDbVPfBHy9kgiYHpyG>!``G6J{`aqvYc%rzu)xc3Q$P>lQ=5b_LL=8{73YvRZP!_mngx$u1^2&j~;9 z1`TTie%!@(46>Xxz&+Q~cXk*&`U(0!a-=&j8koKS<;as=yvg8MDn^!D{JBNFrhx|1 z$O>2S{i3)MxaVSS2kQFB0;iB=3aJ`Td_x)zq2Xdz!R7s$T>qlm$n~y*4EH!v1NvKC zTnSzZoY$iy|2C1o4fwZR`pn%ute_1I4_n2p++$2wzW+r^-6;2o}@zpFNK^5MFX zF97E?PeCusM={cKU4EazGm(M@G`!(xMX)qk3&C>4|J7B{+Q%sM>_1%mTTEYwQ83ao z@OEUGem(92AL-KHmSPkAKT~5r!Zp|- z*WT@b;PgL!u1mi?YjAqs zblh_xk@=Rmhy;0-vA67Dh5_JLxPtC#HF!P@j(^3)cfde>pyzSgQQ>XBedUa!J^l@s zKGUml{7%JAH0*R6Zf|0SNx&b4AT2mv@}?+A0pIJ=-!^FI^HIiWLS+x_+QxE-{+HIE z=dLJc97!5~)pHG&X)q0WW6|JQyxm*P4AiqvT?OChbMY~FldTOw7vm_#crGxS`x$Qs zUe0o8Ufa=a8ln|wnCB|En>~?_WEta$+3nJUJAtpVJ!}0c%ZDkEF&E=M=fu~has%OZ z^%+lmyMxz&5%g?~XWfE9p%3!Jn6JAAnb(fv+KdGKy^HUJ;ri$V{!dnM;%f&OM=_?u zHS~6YV;KKqo_7U(9Tw>W<9iIPXSfFiUYGW}^xvpu`WDcC1_d#y#}kjYGkz8J9LKoy z+Xf6CZ2~^gfqdQ7xO0zZ*f=v>hAkB=2!=UdaPix;BDAdm?pZqC)yMRez&%?g_x3X0 z5BzUkIp50EasyoLcrF0$ZDIU;;GR>?{jH3X;%y#5?TlXv{5}`o)x$V)!13(8WK#yu z8Radal7X zOG7CbJX7i2ob9xU<9Mdhn+I7?7JE3J7~fyZcr|d(Md7WmK_BaZPZvXR4YqR+H_SuB zTxp0W?rmng5qOP@XGL)f@XOqu-BZByD2l)8(%;G*DChv5b@3g2Af)`ut3ZP%W}8sg z2V!6B*-N>niE)(0p38%5ALFgS_qhsg7969=`6n0O1kdPW5%d>7=h)bM^-gX;QTz*+ z;g(Xy2Y|or(r-sD$Wi>ROMg$=pn2dc_FPWk9g2 zi)o-0PGYi)-&V^Ey;xFuT&)@yp9=a)m;UA$<4wSqxcHU^5bEO@GSQa~P!h!&{&A=9@XUbw1E)A0U zC~K<#nLS{|b0Jpj*H+X_jGc;izcfvZjYqL#lATkSr_ED;qY;g5yLN4>9b-bbB13Z!gpf` z--D|2H?eUUXE=Hhs1UsfRQN7z{SN-j-E{as2W}q2cnp#=Vpy=85jqhl{e8|DQ5C`< zJ@M0T3ZXw1V$gdY`qA2Y(}R%}%9#OIj$9JVI1=M8$Ri`~WWGm3_#O-4>rw;zCEs>`@PeFgy~X;PnuC>6lOc=(vZT^qT{>h9-g) zj274XVn2Fi2>n)%0uhfS9eqbGJ@ljD=@5oza~U+fB$3~sA~{jv#<^dN~-wf zAq)~rpG)HpgwQ_}V$iRI-t|8mh1-S?1~ZHqAq>`^ntqJL(r3_^`62XGKKVvJ?ql8@ z!m!oHp!I|Pi4gj|A@s+B=`&*_mcAZ1lY<$YDZvVyi$drx38BANApfxddh7!@#S%-ug2Mp}M1Le$ zL82^}J|Us>$xp1rbwJQmny3p=aCe9T6U&^LG!YWAgc~yJe?6R%5*uGmB!>kXl$6l; z>8nEMb4Hogk4HtehA_MVyO6>D^L_HYU{55E2g@0Y>xoD@SI*ekX9o)!E6M1K*;w41 z{2)%#V;>6PdnCkwcXyo@8$TO<3JUl*vBIZqT!R|89ooi;dwhN#cSo?caadp77%Rz) zdpbnlvmt!Au8TaG>!xuhLgaiDET?2FWPG14vPa;9J>pKutYASU;uxO;N)U#~1^DxI zyktJ(e)X^@Y0hk`OtUhsb#lGA2jV;^=T^u2cF%2>0F)?l;sxA$7YnWM(Km9?UqQ zX4hQwdIFLrXk<>fE`+TO_{7{^PYCh)gb=S!pb757fRQrcqY#5W4K}C@dp?mPxdxTV z)Z$BnvU9z1MuAZuai?sJs`v(Zvh2oS3(6!TeM6wEMRneaR4)q&U0F!z$_}UoOsSc& zV7Yqs(vn~ela_fkxLuyKUbVz2 z#*^*{VZ1AZv29nG=6gDXPtxD#nn~}ghHnw$NeEWZI6EmGtnj1?)p8G#>ZFh!o)pr< zlh&*3=ZSA?h(77K&(M=P)WF$D#*+?)@Vydj=VXK_IxRO;lS6W7^3@@7+9Bgl5%sx8 zW5t=tM}m!*{7x|Q$(V{Gh=6}YoGc^OHwT=&IYdqu@FfxTo7-Z=%T7Lu%K5oMQz>Bg z1>hJ?(S`uLQT6PAXH%loXG}^W<%>w_8OSONkawJo_scoKxKGY0WY?U?!W{3MBB|gL zbjn>Jg7AjsDx}sa`-2TQ<;4&_JYh#WJX6jN=9_YEFyE9*Rp)KPu~Rc8#B){W{ol2*c@6lokgV#OqOuks`^W3TPgL`snJ-EMxKfj#ogFSNUjUG96 zF^4Jp)SYOc`1%Ds6(ZT9sNOo#`mQH;nMDf88#jga@f36%j#)jXcpR*x${ST_R^SO{1f36A5*#JRe zsILQ`do;wLUdXuBBS)QiMyx0^EibrV(}o3$nMN~LpGOQnlKImv36UcK^95#F7HoeT zFndhf5h7?;h(XV&R5@mWX~#nNBqeRI0 z{BVf6Bf)(7m#p4LRDE;E>ChXrLOEUh?(^^It&p)UqOSUOta#4pPlYf)9b&{As^T2@ z>h$9wd?$kWraP+XV_Nx5mx;&ct?9Eu7}u-LbKvBy!TP4(5yG}xHJt}Lr-$@!dPx7K zf1(=3QxcsqC0OAZGNJmsdd3FjJgOP*3SqoE*wQn4G-Jj&Lk5!1GiQjaeHv%bp2fV} ze3%j9;Ta(wow=A+adoiqGxn&8t;ppW;!dCKGoB6MqdY#CYx_*( zc2F+Qj0ek^Sqc2?i2BzIa(U)OA!dqenkgz(|1_D+yigF3kmH6ZlyXRd_y9=gh}Kn4bt?KC0U0V^%`Ig3|TOPlMSiCgD|!$hZmw zK8Ua4><~V@PVEAyyDNn4?hv*;tWLt<%eRW>Lij#W&U~0TI}xmJc1bYb?0KYb{On~R zY%4?9a30m_9tz=mB!sWisCy-Z?e$=`Ib(J9&voX^3TB)m(eY)>oJ&>9X>iM&%^`eS zLlo{7g-?Yr%JA_ke4iQT#)BE@CN!N#KE}B-RC_+1jOK=fVs1z%<~FJZ+D({yM~Fhn zK)=Ec49Jgj2jyIefiLss9u78q9u4jbBkKO~!<~#X4?{O{7XEzP^Uy1e`>dF^DcI_H z5->kK0v0GAy^owl*AIS%y&((;Y@k6sz+c1P2>jV2?#w$9V(2>_x473Yap$Z8Gz9Ev zoHZ?2&{@+xf;@`PlKA;Nde+^!^!oboEV0PXa4eUBE>q6FG1#E9B{V*dem*al{`14+ z`q9rotCbV@^SSi%2SWtC5^QK?NQPI6hs+Pgi|^u2C0rDA|5D|>jQb2dClO44PDu#; zb-oUm_{W`dt`F|PIgf-Wcr-)-JQ37^b1+6V?(0D2oRBO%M{>f)aPHZ@9zZVT#JT4N zci>!qkA>cJ82$GvcsfMEvmpxJ3!y(AOn)8>bv6YI5AEw8h3uc8d+-(^^CkN>74WU0ALVv_hul2{Bv}Erb5l$s= zah=aY>CM3k(p&usSkC?s`V3+pZSK94SVX9&H-KkihO1S_a28^XZx0exKv{Y4@4cLmYo6{}T}Ts{|7Jr~3P z`u!maj)%~n2&P|nHt7JjkG@828g78NKuze<=Pa zgyGZR9xRbu@hMn>TnXyHk`as#rJw68k!11pc*)A(5G<)vwX1M*`b8=`0oQ3uBz64k zJ3`oZ8TJP>duB;UhAlZ5!v6YD|DlE>?kqWsg5of=dk#IA9F$-env8_|{S1>?kgq=% zP6<(Pc?i8^s$c$fUV}LN)PoDJ5AN}W$jHDRJP|^FEQJ2O0D4;fRLkJ>^|-n$fPv^Q z3RX}ZGG?pq4WZu=vizyuAHwirh(RGkWNF9{SxOx>W7hf~2!4(3?BEzLMJ$6tuoSb7 z#(gnfiV%1QIchi{A0Zf;q*^~3PJ}4Hq!6TF*|{vp7qVsZ{R&Wr;$=4m%U_n+6rx}= z_}cL2SFn|FUyqmV4N>q^i2SD^XCIyZ{0g2m4gO)d?0AR*@tofv@*F){<(E&nLb#!q z_{W{)APkD}^0OKDDOgS+pl7{&3YJp{2=~+97$hIdpXDJTSWY3J$23{NG<>93E~gL> zp2i;zi_3iAH)wB22N0UbWgZ2e8zga1K(X;Cuz1MCvOH*FAvwoY+eO&sT8x*$m2EBgAJ~k1sRXx&)2~ksuS*)Z$>Rb>}R+-M8S0sLi;~VpT$RVNX_*q2xkRZ zeAM_uAsu+cE1$kf&<6y;%IGDi_zilDaeoh94^eQ~tANFmp+{8TIm5^0J2mg9+UfM& z!-|q%2`kEiC9IeXX&2>MxMB+9J_}dWg~*4Dz{hx2p!-qWRp58Qipv@ID?s7|CCQ3= z8TZpa=b@L;O~G2RKZM~U4+HEn2k1Wyre9eVOuuqTE<#(sJ?o9Z&ionirk4mpGWGR0QMCAd`VZgmvJBc>b)xcMXc|hQVu-; zxhA68sG2gx3|&mP5xkzMgMYo{P4R?EeF?JKLx`VMwP=oZ z8)AGtNs9YIh~HOzL|kBsT2oxFI!oc&i#93eQt%={yz^}|jXDB;(N>kF<~vZM$7R#_ zqa#ND(0rF_qGk*P-7MjCxOsq6mhnfe1?Y_7`bzTO$$C_e_s<;ey zo?bkQg=x3qbCVHvafNCC^#lw7uP(iSfTb6&R4pW|R#Qcrw9KW_Yq7hBWo-$u2or%8 zF1m$&r!jH2F2b_y;!Z==V~T!Le1a4#DXSj~$pHhdzE1UBjugGbr??Mw^s4?+6qpSB zsayX5FptM0&8QRoLn?g*oYaO|5Zkk=3C&CQqnWs+n>09xyBkFi+hO2dZF`vhi0Zil zIrha8)!6{wm+hkei_`!W7pV#=>P>B(YM|N%U7N5m*!^F`>)ab+6V>w#v9ZyQR14+r zB~w-EN^qV{;!wqJo>H}nYKv!m?nFFmB3b!ZNme7=M)HObUNss~iFkpR)lq1QJFU5Xe4;@7D*5-yVO(&g)n>{#d&c1UXqPGxNJH#mn^%ChGI~AWw6-G z{EmWkTHYh76Y8S-^ia60GuYIo5Y)TkO%ZCAmtbA7TpjjSuGR1=z`HJS>K z)obDn!6L878ma@kZbV%0NIohw<8sUO6wuBAMBT;a{x+yB%2+ysXXUNjQ!q%;^vOct$@}XMD(7z@nhB1M77ZnZ!^V% zh6m@FK*`S-s!vtL229^q)0FB-*F5x!%)GipHRyIpBJEbZe23@ItEZ~Y4X_Mwkd~_# z>1Or$uf$5}*AxS3nvIA%Lz-K4bM&yP{R$MF@Y#tWOLkrpQO@;nfiXAlno?bzEg9ys z`kL}!UDuqi+0+f!!`zVR@R}w~Ghs`J2>gZ&44L2$JHnvt{FQ1WJ9|_X_ps$%gVh~T z%gI&j>|p8vL)JJ?wcG%%Dpi4E!lGc+jdiMlsBmKr6-~Mbv$L_qG(Q+3tKA6cGDV*$ z2KCwH+D)pq31)1Dk=~T)Ge%##U1ia%{;MfAW(2*gkNSP>1F9Wh^g-PgJ*avq`qu|Itu-k$+tZcv5ZrYAlIS)AUtXwoA34 zuH74HeFEO^DmyuE9xW`~;+I&@zmM(a5^~eJ!NyhAF5Q z;Ll9Vx9^Ra_8X?D7O+Qms&oOJ(VFJ*hpʍOo|C=QqcXZxE_D=6_6! zRyE-P+4>aA(!lV3WAZb()^L?Y{nN$x0AI|{PFrCGlQt&&g~_P zGoRphEHc*LY09#@C{CU^pdgDn`0q-n+FQ`uyC$jjTM(EET}(JXc*431zx)L%^%=G` z^1fcJ??ujcwx#6*9>vGq$r(q#>Oa6$+hIMuy<1i7DRO;lfR*Ax5P>&JbY;|`NQgape}oO6Pi8qe*w(_@Z7`AW=j1B(ne9?&KJ^L zfcAgbqI$|{RR6RQfi|mV0E7@@S&hB9dWy-cX&8gCFpt z%b&TL)vkzael01 zUArvqSWjWf=xINW(lhTBYWw0&`w7O`UQ7Rx4;T7ROz!_nX|Nstf)kjI?7v*9+L0p@ zoqyRALb*?ee(Ap)f~JG`^W}pWl!#c0!qs?{vwfw53P2>eEr`?{S3k{4Z(XLV{d?*UeI42fWNQtg*l49FV``W zLTzA1s(zm~mps#9VH@g%SLl>j_x&BH1`LVslVb?y6vHPR;CldtHzk`He}r+SFBBa2 z^3%}!{t+Kvn)!Sy;6lM^TCT#M&%sYkF@bn$76pQ?cPNf|Pc2ckR9$Jp_7v`Dp=y_z zYM<)WbNfW+DGFOap8O!9^JKa61DG8YzaP-Z4v1@q0}}({*MU9TyI@zx@m*g>@xx)J zm}=&UAI^icfC=)4wITQh9-lwV>hU?(`Qd>O%2!}d9{xBDVq_n}_QQ8nr#1xpDreCg z{`3qz^<Z=MOgOre?%>lvYM0(~-~{;mm6 z6FuD$+?%JnL-0e|k9kkOW4!#d_HyD!lYO@JtA=f{@xv*VVET{ds6JGqXHzUPKZ4Gn z8SF-j4=%VSSwUOr`2 zbBwHKE@Hfb>iE$j!Exz^Yt6D}w!^jy(BK;^&pf7_Z&3RaX!8VTSUE|FJI}Oh{=8@K zf|l=)eqUdPrJ2sx7mMSvlCE{1G2QrajCxb{<7#mI7=J!%e%z|E--MPQKZQ1r$A&c- zEkAymap|St&!~pGv9<4;L59^c+c6)T;O`pap2aWv((>h5?B(l|#j~yOR=_0i?BjY8 z$T&Zl3W9*a{*yH!I8q~M68Om>&<9N7KQWVdj)OYMumu?i^LehbBUo|g8zJ~7!T3+9 z0|E2SPvL2ck0!V3BkueZTR>Q#l>KxMfVc4HGwi3`JTd+B4LvdCJ3k%d56|JLF)SrA z&U0Cha4nbq#hvG9+VrNuHpYGFAv4Bv{`3&~XIT!Xjiv7do>X@>;W6Fk`hsnEzB~k< zXC|2Ex6qYL+4JoXH6MSz?mzzwll5??pMO_>nCo=Kf(3UWIjyH5&>V56>qgb{EhK5z z9jfVDn4_@t*9)?)dl}zha9mQ|i{_^peMMEYU}U5qG$3DJs13p2+4XJcdf`3Q0`8@h z?Ey)#e;$krIJNC>0DcgEK4Y=M_TOv zh;a_*uujwo=QZrlCIy@OvkLxp=VzBww@S)>wlRe84%LTgsO)EVL9TaF#ONbMKig*J zjh`LR0w+4%fP);=J<3GCyUawRd$MZVf#8TC-8HJ|$r#SH-3{^qm**7a?k98ry7y{J z^SYm+;Fb*2zb-#ty}KiJM)Yda^z%)+T=sKJ89~8#(LadD+vvoLGKj>Bf_Lc7mHpxo zkQLx>4$))XTSZ0O`Ng9uyAu}v;xRSwZS>^{ZCTkbFaZT!GXCO(A^S+R@5H{s3^*zv z4-bUo;ekVt8jxYXOaS*9SA#l?`(=r0yC3O31vO9R6qR!GG{(8l7B4pe{Uu+e{qn)! zc>WTd42ttFd(BnaFOT{3R;198X8dZ&uK$h5 z{A#7DRaDmVobxL^N9FzME|q!!XV+itfL3x|8h;eoMk?aYuW*tI3eHOX`*O-t?$72K3BfoZVg|_&ng|JW@VA>nN_%7%JmJA2s(LkJ{;O%S{bwuId)r2FH z3CI@#l&5!S^UB=Nvo^(96cbJxHle zxbe9S`oWKM63=;=%m_HKzI-HD-pj{Ka=!eYPR=8r*RKo-$0o^j{n zP5@Bw8=BLIA&oy0)JX;K=_m*n1>KBO@_Xq8Cps^E57VFRrJn}{(r~Vifg(kUDOz3y zxM}Wz*!YaFQQmo*1#bc#kZ-@)%=FR^QM1)2M{sgvfSk;4cK8@X@h%LUVQ4c7@PQ8W z;{nDi3}XHRe-WR&j_RZq;J*sN4{98dOXGt#LP(iF#jl4bJ`8TJV(EYkg*1ux1V~1z z?!Z(xHC~+xvH%yoTBADYMT@Uqgm&+g(S|yD`0C}1vqy>qZ_uaD%&U)aJA1OI9d+V+ zf^p#!yaV{B_@l9C570jw?3h=d3wBIzIq>r%U&;~GTdf;%@k^m?KK^`)dmBUOvnsU^ zj_JJ@Jl+U!&h`3JOYo;uTPt=FdY=X#IaD0biO+CMFO_@n=d*#$gsm%ihx@5aO~7mSoh%vKx%nBEPIR-4?o52W`211APE{;Wg{pnz1XAWRqOXeaG)i(D8`0N+T7VIK z2ZN31lUbdV+9U3~U5|gli#Or2%_b4;_g#PZaV4+8E1nwD}Mct^wh@-eP{=c}6Kf0OQ*%;ftRdu30?`T$~ zcVo?t9r@j;{_8uc303-80I$?oxsm$LxkIH{JZ&x_-?@&&jE`PVQcC9h9xfjuMjH`# zeovt!quHpK;EonE=l8op_-K#?@wKUe|BGuwN@K4tIF0+4kT1qhST>ZqNSarYE9kC$ z5;D6FRG;C`mu`QU5sV+pQ)!33GdMQPc>I{Jb4C4NL`06ojmM9fPUanJRqc;LZKo-4 z?S$HdM$rBSe?IO1)~}p@#2!Kqnil0Y|B+H?bpTGZLHGgS0iArWRJB13Jp)5UxoX)= zU3(9=LZUvKaw~xA-zSCOY0W>^`FA=C1~G;S98^t3^kw`&h|>oef&~t2(HbW@1JuEQ zN#j3oTh{5w^Z&pj4}VYPMQUIV+&maCXW;p)y-C&Ln3Uo*Foe$=z+V4=0KOmz$IUH+69hQ7>5#uss1aC1T z?*#65fXnio6VI@u6NkVNVC4zQ#~>W{?!tt8XE0CIK8kJ*`bRG%A50k>p|ZL?j;hyb z(#{D!*v{!Qh@Y6#ei_6qV&we~$1?EYR0ihh-NY|DA3g<{-Z^;C==@MllcxI*A7uQa zDZ%s~O=sLk|MBI!{uvX~$3th$g87;(?tDzA0FU>FmmBpTKc_0dSN1VY`EHk8zJn_L zU6R|2a}4E@Z}@(K@fn2w2|MZE#lTuORBenx1W*6zI>t>eA{NIjv|z)Xcugpl?gUkC zK#S=|Vgr;G)3bAd_~WXFjHzR#dD99S+wn8wpV;?g7<1R^%>4D6N{tAeB2$({hn(0zp-&3_{b-Q3Gy7({ymKQG@5^j zzoGFe&a2y{+4E%7iFGZYg)j0hVflH!iDS4BG?1AkdHIuQSfVuJyR10B1_Ag9qN3*QxSr#MW8&D_lOlB@#j&GcBq_cG)IV0~?Le#15c7vXaNLPX`8Irp>Uk2r#?TMy!0^Ukd_d2j;#p6tBnzt@=RE=K~FSui%Wcib##o_V2%t{ z7G&|P5wueT?bd=a#U(Tdyz4N!b|pcF88?C+J}CIH5d1iB&+IYEL7n8tJSLHBWc(wd zr;KDvEyJhO;Nqj1VSL2Q8spoz3*+%RZ9VCZKOo2(f($ZJs+Z*ma_Lk-@Q8@!DqWSd*vn1dEcrSAvh`f=jRVV`fZDl0X)T~^J5psWEz0n$JjkCEk=V)Qw8()seCRz5Unhs`aXv=?li z2#@9wFzIQ=MUCLkn1D?>q6VJE5SVmKrG7*u9w&JgD$gg)C1v!(MqaU_QmDiFlUAw} z#^Ick>bRZ7+xClw;-mYS56>Ku_^kHw^5V%Izyrc?GVq|dpWGLWrz(xTDH*El?NQpU zcyVf(u{X7Hs9m<**AKBbwMO;)1S=8W+#dgbbe#=+l+~60Cj&wz#c^hYBm{&J5h5TC z0U^8ykDw5OYiC(kQfe_GD=AWpRv{uasihE+x~baS)LI>pN(vUI6d`3@94UpUR0iZF zBDJ#?A+^+Isej3;)&K82_uOah^Kd7h&*bKQ&$;KEd+y8gGBZ!8H%LSDBN0QI{L!7GAgw>hKMy>H7I3MzAk3x2O(%#W7%cTIXyj z>F<%eUTyu3;4uEu9oPai@EoJwpfp@0D!9 z!z_@796oFa^v604NEtuD@UUUbrM|?(N8nFG2ZoIX{}x`-G3(c(0Ra+t4UGpg48gET z%%veG)x)NG^mzz|ZIh{XJBHsK;Pu*sL38{B!y}iO8;rb8W{xIR`)ufrs zJ!zhlg6<7?(fW6Og5gOgQ89FHQm5^wa?-gRerOoTzsJwyUSQgA+LtDn7LyA^2zzYV zWbZyhnJ0OK+p)b%nwa;s&jBhY*P{M!czNQV{D?We$uxaT@ip<;+vFo6-HzMjId+E0 z@52|Z9~qCcGfY-HgUtK$@6ha__)mNEnNPWa+!WSNsbslo7n1F!-0b11-P|1ZZuRJs z8Tg+vpSg-x@r5?8zn~*iXjvFKI0cu|rg?mwm4he14HM|Pw5~q|75gU`z78|THAC7- z0FL$RIs!4Dicg2Wg^9mPB;Q1_+P*v+8=krz1H1rDJQHGSA_vDujA2I9kEFYS)6md# zO*gGro^npZ*L}%ptw>J9-I!_5hy+zP+RoAZC9{)h2kd73GiI^XlW#{@YPQSS;Jc&^ z@gN6QAqs6%bvVL00ROkx;Z#~sH}&1Z*qJyza9dA#h&T7^@e##0v4>qR?`f6Hph;;M z%NgpNe#T9_dTz+KPmX(pZ#XNu4#UKa0QUL+jZyW-Dpr{pwYQRznKzlO&#YF8?c8)` z2VXJFM2AcP&03m+cgahrijZhJh^Q(M482hit~g?cSu*=JbHhr%h#kO5U!`aJ3dNz1 zfvNOvTXa+)t_D&rJD;O3w=I7qzMxJwbt`Y-Kq|W_vLZY$ruGN|ys22EsLJ<0Zn9YI zU$D(XE*?(jU)7(t$eX9ar8YT2bt09{ALPFo50y&e#GZBlZRZUY%Mfp-MWQ!TyxN}X zC0}0+In6`QLWqO`fLd4St4&h-}GY;kV#j^)2LanlB<6(=p^X!P9ROBp^ zf4zyxzuu+@zKV6&wqX|?O5UmDpYVN{x%ean?ubU_Zbpo>VaYY~{E?VQW9AJxVy8YB zo_m7jaws529Yb`>C>r{r`t_($20h)pB>`rb^S4^&wRCGG^j%?~4mY>XW$tl*YmKxM z@jAY>!Jd+3^Qb@ixV1`y^Tsom27MvL@szK3khoXn463?GgpQzEN|ON3Hp6GLsd`dM z=i^Qr&9nJ^_-598EJD-9hewae^*g_g2Vnkc8eKG1cYNl{J3eE>-}HMTPRoeD=~*Np z#c_*(?l^xFmk;(0vv0l1WBV;URfBeq1%2#|t?c&cZp&dZjO5-vlR4+Y;dr0~S-!nS zM33QIjmFq8menmH4)K^p5F2Lt9b4JDoLRoGg*v?6u}yRxh4nkOizGGQ?NO^`wLQ#L zaEkAh&CYq6@%p<%9S2o2#qk!!ag5*%a@Sl)K^ywCP;IXZ@t`Nt$0NF^XcuWJx_LMk z$@^FS@FH( zeftqll*-;3Pdmj`mb`wNJ^IQ|N~BMqS7$}+eT?mran0|cc7w>A#3|^KCp^x%(UKg- zmOSmzw@}B>EqRu?8Un>PFjv8HCziZub8+#>{J;{G*(IAj$`z=SaaxO%K?^V33OJ%T zEi!$4mGOPdRWOQYsOxu}%h8I~o<2_8>h401zJ)rXy1RtA@}fAtJA&C-c6W|(y*tOa z-kqQ!DY|1DoAqSu?j0U?D!gMJeHDiH(8qjfu^pa&=_*nCN37u-Q7+99<)J#!hGDW0eMm+a^ ze*PGmE!r{l(k|37j^Cl#lHIL*4(|}rPF%zWI=$illud zb1!b=k3#0|8}Bi|k>5ATV?c3l<~Z{EHhc6HKOm1G-^~{dAK)Oe(LRWjeb+m4tI!-B z{q8=G8Rqv76&W<|Pun=1z*3%^pJ4cYJb>WO5Z?wi6)%tYfmOnS_^NFX8J6V(7tBVH z{4SW@9W86+9ll%6-X^%Zl@&g}v^qDUo1#Z~UmTv^V@Z79Nc=;(g?N$u&IO4%r zF@m{;l8$nU!%^Ni5KkUfEXu)G=iptiQS1{p{y9HfQrFk4REJ9jYE|9v> z=DiDjKS)c)ko*VL1XRi8K0J7zN1v1a;7aC7Uvcz-l6%1g(t~YuZdO?K;9jZVP0E9x znESP|r^tMWITg(z#SV^WSvg)=RJjWqmRV|HrVg0ISav~>syLC**U>nb}q{^;C{S2Hmnoxj-8SjeRv3< zVZl5+jJe7Xclcq9kna_|Ji$EtjG5P0vK=)7HK-%V`uR4`-s(M~1ouO5;WibnPl6j9 z+uuQKh0GIB!%#32S99DBs2x`K1@cz4j*RchPL}W3acD{Iufb>24$SW4D37)ciMW;fEp7*5R=_ z)G>ICM^G3}HX2WR^l90U{-?}&79Uew?RdNnkJU>3M|(;A`RY#Pu?7}U_$tU6R{>0IA+h6)(+3y_<@6+TC=XGfQKQpT05r z9SpC-lVa)C&$=(((_o__E*2Y5L9o+i*9`hbGyHYQ}JQodKz0% zM?Ti8H6ru$yjolItXWrjl|Id`p4qSdWg9#r6S^KZgXzlkN3@sGLh|fMKT2S0{ucv( zA50Ih19b%WBQ^fAL%zO>eq*x7NTy5xaltD7E1DzpduLl zu^)x5&yoGO7jp}x7TJ$0QPVQn&lbZD^;~~cha-rKhEH%jc-qyj=k<06&~5{B*`X}| z7+jAlfjY(e8FP#3T0g!-P1omsJi+~|_gSQ$P5l!zeM}9eGq+Ic`fB4;BcdEEgBIDb z@Y3~@sF8CyMa6%AmLFL71kFQ}(+@m6fjWBo#A)Uh)wSSNc0AMIiEjI|;w4WOL)&oD z`6Qn8jT;$r!cR_uf+3J6X?P92dD1(5xc5)WH|2YTpZr9GKF7(?Q*>fv@cfh8%)FU* zsu(b6pAUlV#G{fLzl&Z z9DI2W{&)`lVh(9(LJnH%h)G3;`nR}xD zsTw!6-dO*qBW(Tbg_hdMe)AB!~K%D-kZ)I+w)F#Z+ zs$+IQxX@CY_|wlq&CuhgRnI&25GX2Yyz__LUt9^fL79XC*AKP->Ar zGf*Ty!wJ32)CKeFnMqJK#QRK+rTffnw6u$6??N+e=Px3kh~k+&%w>0c4(|g03@^`k z{Jf8dPs;BnUimz~q(9o2E~S2cgQ#wxkB!?yOk>WT`o z3wj9h`DPUQtWun|&FOe~;(b2Hw)y-4=-y7}=-vi61;z9m5Z(X<-{lut+>kHQ6R<2c zghU1>@g*CmXSW;lZWf_SNluy3A}-EH9X;7_8y0U-9-dy`m$X*8wMsf!tHIV;8Qv=G-5%$0k^$@O%+yzV!EncTm~ z+(N0lZ$;+u?FRAUuku4Bzt{^|7hYbg8If2?U&MT|r|81^zcc)zCy)KpWHuOnaS#e^ z4LCdsZix3qtg*aXAoF;95&xl2dTg}+m=k_62`!p$Ud=sVdXL*tr%2vpZc#mZBz>`y zEpN(Ke+(40*U;CRHql@kOl=y$+(N0D+EgKu8v^~rA9@GE{^D+t!3R+bin~cC7~XW7 zeM~IdL~~vn+5S9%HhK0mhc`9n2a4?f-e}0nroDF11Hzl=P-_^f)_i()9(L%~QBW}K zF0JJvh9g;Jt9PPu-dbsQqa;{(X`OAQ8Km{2n8pMBY~3olaGvFF-A<=lWv#E82ekDQ zGyf$%KpY4ZU33$~eZ}@b;EKy>YQyj^z1ykc)gt{zoVfjRIn?xk65Q@#<}s?{UD^cw zhCO`07VZ4M#M4>I@^O9q%gx}1;r`_g<`zmV1HVMd^ZJ5#X5i+KZE!$%Gdvm%$hB6^2!`1^GAfMLgfOG~`gg2lug1$A-7GEH{qgJ1Pw2fv~%$S|zGy2)<;tNU}be@a*v<7^>io0${- z)!WcBjKr^wF_&ZOoa1c;Ho4sz5>_ppVr{jcVaUwZxb5-I@YdBi6rRb!X})W-&;G~= zX5ZFr%z5@XyiHUGu@$8d=q*t3O#7{PwD4#w{FkFVCttSIAJz6BbHXpLLNmi`d%2lC zmZ8Lt{frMp^76B&XzRe?Nx2SQPRUvSGWIId`S;5w(ca`wtp@4O8H1NUfQ=_FZ8D4yh7ukn^PROy6_>Y`d3Ok?dnj6yH|#I z+9^)?HKgN}T5!X7z48pWVcxv59ekHhT>Aw+iS|mTd1bsJ54Jms&Eg%Ubg1+1uy}dw zxGjes#YTIyXHM>DW2J9P913e^X$8Ho_QXS531ni(B8*U%$^bFDf z^qcJMjCkxRUM%8x%bPFl2ZVQ4K(7lgPe*oE^QFMfWo(E89vDNN9Nfp;uKRorUu`=W zL;K1^yu5Z>!3=}9bBBnPAoDwSiBu8dJ0Pu`MEXruPQi-drb}C2dDEpWD!QJhQ-`)v zC{m=JFxv3VCZu7E=ddKTg5fsLVaefD^6=Y+lR>({(pGDiC2d&Irmdr`&7Ka3rr$0>Lv69D;rOi@KF=`Wzmip#1d6V2L^DHz zfBUq@TpV?b`fq8@YtwXKym>%i@R-dW?P}CX+cT*LDvn7F=VJ~-OOKg?p=KwTtC$r( zX=lHLmXPVVxhq7;EZa4VoAZnv5JDYhca3JwW*r`5vpLrKuBG-E?OM%axhuzEdsiEs ztkCy-LU;(1e;2+WN~cc$<#&fOFkgoAUo@%oR4U%5`7-3D#NBE@8@KXoq7ENww;Jzh z)x@o6N@>0ZC~nF5{NIiCQGHH$_aL_cetLFzwdP$IZcmA*js}XtGzeN$ zm*J`rcnqZu!R=Awr&@=YS9+SoMC|fF(dBj@(5%@b#wgk5@UJ!p>)hyDZt)*F5$1O%VyG*U#kM@t_RK zM;(K;PYnuZ&*3*gY&cQchcj){+Szx14&DSi7t^iIA%QS`$ayG+a^D_6+FUpo{DmI` zvkwJv4u+`B-$bEJxPi!=&EIzOL5d$^&UPGqx!H?a^x-5Js7N?Vszm>F`^?Kf}v2y8D;f=EkhyW@<6mA;H|^ZgZC@jw=>B8kwq+_JPPN zy_?`M-yRd8E3xKORLXoeR1s~v+Bi4^mnnXmZN8+v#yni@czR3}$!N#J(NW&q-T-ry z5wCks<}XV?hx{H!q3t*hKLS2o+%zn3MSUr&e&kjir1)7<#mnRJjb5zJT^-bbI$XXH zWX@f6IModUL(%|O84*X39w=$Oovpfkt6)$gK)Mt~O6FKah1b_F! z|LPEa({DEPCiR>gcmjHJbPjzwGMn^isyf#ReNeG~g5fupirN`CeR%V60DbOvkpkpu zYnB1{1}QFYL*5yFQ>9F$lE#o4ZbP9*!u&1jY1UEC8I4l^ElO>6`eb>?zK-{Y-xANQ zq+|PAaR*#dfbW05l@hgi*jWycoj36EjM0HO*b)Ozf*Hp2z+N-={Oh^R1Jlq$NB>ZQ zqNnc)XEHegI#y~K7?^Gzf!$a&8^Kb}+dx_-WX>~!4xi-F=PCP#napF<-nV(6;)_so zM%eGxN?$LkSGnK1o&cpHBaw^xW2Adth zO2{csDifTcw<%DabI;zUK=r&TPJ!xN*`YukJN3TJRi^+bq9@!96hBC_B0EKWgSw^u z!AjOwfpX6d-t4wBQ1Q8Jhcjf`q0bl{ydMI?*c@CX(jx;!cdT>!QHeUJIwI{k2|SpD zKE+&sm-7QR?WmYI9ux&P_)dKj9v5a$$h=FS>S>;ifH`@~&aAYY@Y(U=nVTNO`W&8` zx#?jZ&f}GyZgZSnsRl~08UjOl()irL)rcD(k3`%H)2~9!(7p6N_Q%7tAcH!xo_>=# zyK^}09EOYDG}1&Ltw?9=k5>58pV(LX_2EPF*$_KW<8x?%+kwLudh|1>BcMZfG3S7) z6n_!iF#is1Cf*mnWCLen9!k=H7WxkzkRy7C3>h+W2ou>f(uZe4UmNMFPSg?L;Y#Kz zK*jfh8wThdTA4lQ|8dF8^qkQI07LJru>~sdELTStsqb{?oo8M8S)R1_{`&AcC!nB3 ztaiP3-e=AcJN!#F=y7x;;<3X^_ei0~j^Z@;d)$Iwo*_6ggamkb9ZX{G)t?Klb)f2` zNW}t00p+Jk#K+>GcH};<8tO>sk>$*}pK7Wd+3L~HpicVRP-Me%2H?mpa0)}&$>49& z-;JV&?{3wfo-=;Jf_=6?HOLyG#icuVg7x3_=qo!kfTS-S_nh&B2$iA3GoIvjA9&=7 zpJrZ0dcK}Bo}vN)e}qD}r}$^2g_qRdtk&2O_k>XWm=Qi&;4##MIvgAgqA+CYD6L1= zS`djcoSkQYshL_@o&+ED?g^dEV=?@^z>ebCMW}{pJ?X)BiWo2+wN;Jc@>A^MMb=U- z6mPYS*xw}8jVLjVBymr(V~Tq+c8o??*UzAi9v=Icxzgt;eC(X$>XD|-;fns7pWZ8V zzI5EV~tzi z;dCG&A2fxWpPs?+yM0C6qEA4)I}BJ4naBIx(agDv3lyjN1r}lOev$q<-FSZYh*{wT z{;@HA9Pq><$p0NLS4hF|iS;6V89f%`1g%3YB9)U9@4LC$U`~9%T+JFD?Grf$>Ai9h z9gitnVQ<`H!zX*8eRiMl4Mvr6dNRUX+RbwOQzm@eVQ~0lITQ@3I7u0JSDYFj7~wyO zC#>Pjz<(0&l;e0<|Ho10Hh;V!2fxjHeEefFhyGr({`+#6XE?i#%If=`advnUbpkKX zFui}u9>%giQFaWY^e69ODh)kk^G~Zq!)W^a*q_=(tQ;RH_yYJHygc?Z<3u&YchF|} z_=V#CA#TX|2ee?cK~x{%{-BaM52C~I;Pi=bgC3Y}ApP0Bkhd(#zzllvXZJ$R@|z$w zWb4ljwi|k8n$gW((SRuG=`7RGsXu4XtQay+j{Z!!qgCSJr>IW0D0=577(Nw5g*Ycc ziolcj>wer0!~d=ckJ*Jvc0ji*;ek7~o4IV9D!`tmU|79Q22x(JtaERN{ennihQ~Z>C=itM0qH8i1$Y*Xf zf3a+S8g~fk4TjU$hESHBrj@O^DN%Z~ur)UhA7{7AJ1w4@jc)*-Uf^y%ST(=P-Q3|z z+5KuR_ww5gr!(?q-s!XExqe1|JmSvqnfqYbFwxE|XD;*NOf>ty4{G{LY4#)kXI^yc zI~@Nv>pJAGEk_(jnx{hAfyRa_tTP#Th1DrPyzcMBC&BT4>ez569eK4h500XaC^~8O zXlZu%di!0CvQ8WfOiRD>6EpuyvFJj4dBa5YH5lc;j1~#Hj`~YXWTpYvi8vLHh~yL; zOaJ0^UL}M2%X(XT%=;Xhnz;!UpJuLRpyK>>*pFyNPQ|MLFXty1{)qHVJjd?$kvcN- zN?c~!f*ta&Z4HY5l~$JDCmyf@5$B8W+*Xb5Ul+RDI-JHwnz|T@V}I4mn$qgX6Q>*JH<4R#kM}P=~j(8&GIHTdMf0;D*foEeNj7s%R8-*!f$D zn-8WiiI0$czO#8K0U6f}4Q}TKmCR-LeGb3b%^k;eB03#u@nrKJvPS+@zbzYVad?y6 ztUqZ-yfvYzv-7k?ly&87<6d zr_QD~%Ue04pVmRa5ZU?09DEnJJ^~!sdHnM-d{;zVH!~2Pdyj%S(sBM%He#Wq;bQ%6 zT4TELd=dx4-R1m6l{?tLV{OEz%w+nok81oT;r`PlPWV-EeKrceImPcZyh4hNsp_GL)n=fjxG zK%LBeZh;&2jn6ARcE;IXN(zQQpX(Mpz(er)t<2eh!xy;uJupOL`uRfUY6!+Nzl*sF zRPiOgYur66=LWR1=wqgMtw>g23tJ7bVI)4M5j1ri?;zo7x<~kPe5MAcY4(v^OXvfA z*zE^yw+`=?8}1i)BsDfa{}>~UVd*bSat+0ME1 z7jH9{dCKw=Zu@F#e{tI8m#V4i%z%IP5!IF0V+Yzry_zQ+-ii>KVYvQD!$4`U@WRS) z_$1V{^r)r$PfEF_@9^m!eeUKzXG*S~B9RTR0s=o?1$g17q?UdoAkREpQOw*k4;@|w zx#6_)pVi=W<3ZXNf1D5q`2V@oKKGmv{wFqQ(>dfnzeEeI+bag5j;Ow*NQv|8U4eg} za#Nsih?*T=7P{pQFBPGiaB@Rg*UYNH`%-0}M@41xOO;Iv?X>;sOU|ZGaUR7l)v8vU zv;XDIXbr#9FKF_@& zeb!g@XxJ!#({4NWDE^U0zueXz8UE^HPXj3ke|65&AR)RCaKSwZ zyJ7gNZV_7Uur zeE2HN*D;EVMC=>58ul&Ap?05}^JqnUc*4}bVuSQOC6W&z>3K944es-XaC=TF4?-kw zn8&W1%aObhZhf9Lk-X7veTPp6@8QEckJ5oUhDY+|+5)wfv-}qO+^I(d|Ewhy$DORr zZil?%MDn(}9V+gR8uyfl|E3(g#=g$KGvZ(FcJx3K>b_vazmhpmM~6S+)^`GU!mY1( zk3P1e`bdu{P@oOG059h!80oPN6>WP`L)k+alo?dJM5Kpj0XzE7vK{yC5$Tbj4A5zg z*YUO-4fdK-)hb)x!NEU%up z@Vf=8v@gw7{PXB3_81R{TvTN?e90|np(VD?jvH>NAH*%ZFk%kxM(uulzvvr*$e0k8MltH1kPB!O zX~XmKI8C{tJC;DyffuI&f8i$>DOiSrxJ(^E{D9Ng=pmAM;`^9eR7Z%4pAwn*xK1ho z)S9VGd~F1C>BgD6Uz;ns5M4d(554eGQIH9E`x@;J*%{)C#+ff*&iW3o0XHQ4YxjX` zVX4G^ZMo#m^@bx@<7vR%{MtI^7D}!AUwg{DVSR054o)*B+p&N1MJvc2dc1=Ls%MJ7 zn#0h692`6EZAfg$EbcSN<==7NXNcK7{d-=+6;Pzl4LSHNlGl5uW1ngWis8gFP5U%~ z8K!Tar@{4+<@@Ev3ZvX>$p(ygdg$Y33LE>@B?h;vh^I0=qcE z+_GIb3*_Qx4tsPb#Bk)fn3&1_berS!$ig35&o9PIF%8khx8>lqXl-)5Du+HsC~M!j z3l)r9yfKHNq~3sHr61_;&A~e$HU)GVoMigeRZoUKVnGb0^An5&=b~arUC_Im@Y)J4 zWPQsv;tW~vF4Sp}vVFBigSEH|mQ97-2*2RC!Q8W8Qx2ZU!8gMkb-=<)8{%LZ`jbHl zeB#{&fnfbP{GHuJdd|S)x8wMfxkYt+B8vGXwCME2Z~`tF#@s?l{uHN-Yx-(8zhu1R z>iPZ7c7Dke(RDlCPp}|2oQ+;mL2vH$tB+hlBcU0ty9sq9@Dj>6ahdTg4&MW2=;$T; zm|G~((&=c9sdUK)q$Nh(5hxhq*gj1RFR#xok*UT9t|*s!s5guF9XJ=LyBQoIhx{Hn z=PuNXxiYJGNe;deJljQQM-DyAT-s55P9)TV$v{SFP@NwHl+3}?=E)Yq+unFvr9Kks zHYEe8w!2I;>>q3S8fzP=Fwlu`X?k;pH|yarv&F9$iqtp zbknu*I8Bdm?wa3_0hM zktNJ6l$1H!UN92D|5aRstCS?o{K80NAB1|`c*O7`yz5=ZiHn@RK%Ug)m-f0qo^i>C zT_6wr2Q4kOf9XuG9CZxvrPOVTOQk{SKf+v&i!&iEUBlc$sZEqiA4g5^pIoB;$fe?* z2Qlw1ZDzUhQ$x++|7qqH)wA2>rD}pH|0=FM&@#oF#&ju$%(JlU|L}0)!bkr_`i4aG zE}Y9#-e`xDe((qV1S5TE;Srbd62uR<>c1zhzN-JKe;jY$jrRE0_uY)5wQeVUf!U*$#lQT$ET_warZn>+X7oC9*dLT+H8B**1c1S9>%*_YFie#=qS z1Gq^f7vnMJYNzSx=^m~!H(qAg9ngIUo@`HiiW&KWg8dalC zL4LqoHR9RS?{qV6*4Fp?n8g-KEvfy^p{Dmq^_eysjjLmGzt5N}H?^q4ePM~4EB(Sj zHphvwg+H{U77js8J0K0U#V|y(jJR~*bNF~LEugvz(e-WGE##_-6i)ZZ@s-FWByh&;D!dh3i!-V^JfAto8O1w+wm;Qwq1)byQjsCKlb9uLd0kwD z?$&m{!uve(TZ9F9eH|`+?1ZoM$a&Wu`h}0U_0{c~LbZBX-{I@r`gK*P z`-1h6LhrJcf=Hov_TOwbh!i%nAr+9~E#Nep3P?}=U;=Ew-+IE8eOeXzcTu8B&}!d4 z@fWs<)ZO?_?QU0l=cKK04|5A8Qlw7i3iqOBIGZdyV4qD6h!h?pb-XOR^cjr*(7Y7O z^6$^%JAp-`L<1`QYoTEk%nxq&NKv%ZheEG22Tgnj#gw1-TYwanI&u_6=6J zEc6#o5!QF$Ee;ifx8f?>+t^4kO%j8bVwxnxExdFuO>}}?SXNA9mTl+j8zr@1r1)v( zaxAm_8H%oc8>Fr!%B^-Vx2T>ypcQ|LTGoq`gJPN$hUoeaaq0V_G=mUT|6!7g=DPzS ze}BBoiMwh3{tfo$IeJ9;%SY?gNBVE@w9lYU?Kd;$UPTp8g16%3nW6pLabTrw$IH)} zc?oioS260s1|-x`%%yX zJY&F*f{YCCjDf>nvYYo;%c6|D;ai|IG!*nck-<^GKLDQ$f|oJ0RJGtPZ(z0enXA4j zeo6+{#ld~aYV76mYSiInU@zvXx#E4~R2x_<+YjW4sLq@&FXr~6J?$08!{lhH4z%p{ z3kTBHsE4ogZq3ntfkz)zJKnpPt9TV(%Kq^0=rI_Tm(f(9D+<|P{{TL=TsD=tY@g*z z!1ee#P)B|)TP9-n;@EWAa#ZyVppNAW6tqAd_DMQczG7y zWm|21eC$LGTo(WZwoPQ}sH3}V1xG#vOT?D%X3mZrzR#_Hc?xy1_ohgpqmj!FyX8Zy z<_Gw`1Zkb~NE0FkaeV?9;z1FQxQ%%Ua}|u@YW8sFhNM}4yhmU0O6E$xOX^n+n(Jx6 zf$6 zH$>?lfIe25`1I=hOL{~GeI{xj#263y((HDy-)w$xFK})04dKZ*xIlzpuViq9<;uO1 z<0Io&(+!QmlukoG2dmYp(wTrB#(nU7*7x*t@B(lOgdJUxz~7`_i{dl9JhOf9vtZhP z9B~ph*t54@Q3FLX^ddFD%j=j1N_VXEUj;Wg{)p{R$8d)>>-b|fq#H8KezXs`!Ew~P0!roQ1S3&$sP$k71mrk6i8%*!d6M~5=Iq$vcY*6e+0Ob)m|Ijw zhZXPeiRV}5_q{W6c_TPk^$e0dSxtN!bPb+{>|!n>b36?>$+yq02$~yS5n*nj)Iz)> zj@r|Bc>=p)A($RO8g-=X3Y7vCfa0|fFB9Wd1}??h%lNVzKE!jyMleI?uE4}GeA_#6 z#TO#lhu-=fI*>orGIWal$DGJeZ#bPYoS`Zli|WX{;uMa-^-z35{UMxYys8}FU%ZW_ zlc%Bh7#J>q{a5zk;IE9DEnG<_Xoi#NEAi|j+*R%oxzZ9Da&e1&248YzOAb3{DUw3} zu%Y((=h(=wDNr=LYd9=!HZW|FXxL9_9<~e$hM^jEAM+SW%1xSzU}PA+gt!Vj*KpkI zG@YLgmtWE85gERSo=t`>l@8<&Jd~pIrnekQ=fbic0uMte?Qz5{ytLsd#Xmp)9&+@B zh*J)(8fAYCwLWrH0$PS)yK1|ckI2u#amH-2Gom~PZvr1BHvTveDI2i|f9ri|M;&P! zv5&b$_3R=ai4$LZ+I&D{ya4|sz;VOMdHU8FPeBJ zwNY_OW?}s(wF{MzVm820YJONAz7ln>gx5jqu!CLTdAQq*$}uQ zue164IQi%VK%cH|M`1|u)rZ0L$dvvu<`zndO!1RBBKQD&Ff?WE?MCFc{_4{#kc-d} zT>TOLgfVY}t3PJ$)&C5f=84C_)n79A=#QopeMpC2PlM4Vwm==_QK6q;Wb_aedM3yj z@e#}|sv{GMlU-duLt^MpVs25r9t|?|2Lw~hsT*y9S3-p%c7C9L6DmK$%gb@~kw-y! z`64jy#(WVuUdlW3=mxs^Qs^K3l)W`qj(#SGB@CvkYczSt5XREx7S*#0?3%c!{sHdr zy!L}Y2#Yn1zxjCyk!$chNvz$nYdmXB&8KTTYt7+pd_0d0geSvNh+#J{ZQik(9Q+*Y zXs5A5^QjBLNQ~x{c53ACFTkG{PdyrlRF0u@3cYOzb+jE*$eiciP{oVE|ACihgvO`? z%NSf>{tz2mqh0hr3su9~9PV;0X^`4xV;%$3ZJN<=>O1vb|tGQd}%u6Zl%5PgJkL zP0OL?7Gr5KYF!vwjyk$Fb`oC}U81W7 z>t^h3Vckndy0M*TM!|amALkQRBlHVId^PmPMMMVHX5&1=G#$nb^EyWzL5~~FTm{Y1 zjEmVHODr3ApSzt(=eU*bb`D=9quMRvPvUKuaeJUf8<#Y{rQR;#_6V3^rHwm@6-6WI z?QA#Li3|C)A(2KB`eT8bX6?1{=0_o=&B`#RuWc0#|D^NLYtM@6Ryt|8Rvja0h_UI^ z*HRITTuT#2?}p;|TA|t$#}Dx|RD7mK zzmD~3U6CV;>WEzNCH6r0$KNL!Fd+W%%SHOBKw}|avN3)IK-opiX!}rGR^Z4;?_EEw=!6#}T!=zqdM_n>O z^-6}}OrHt(COkgC&?7Pd4@|;;2pAhFr@p_6muKRX-v(wF`||tkPf3@R(*(^fN~fdc z`c!mCZW1LZ+hO0(IO?!BDJYV(k4y@Qh9BXs?Q~GesWiK#z5#!e z+DsJ0Exc%+HBbS*nomC`B~Ul4>`57Oz9!MJ&ycUl#o&g4n_Mca$1ww^4WD`Cv@rhYH ztrXlaIj5m>Cil~FjMB85z9n3qg_2r$E9xQcQ$)1NQ9ul!9aOpP$ICOj zto2}jF>rGCZ3AxygWnMs7&-#ShO1BO3y~Q^cY3d<6P1-0TD*P)m_CmiQAdierxP9G z7GAV*DLx4`UB8LM(D!b1idT|8)|F#O2^Nw7FSTPT2Q(K|1I?iZm@<07S%Pr4mE0E;idBps3}9lm4mI! zEtERnhMKOQ@c9PWk?vrDg;IBL);=KCM{b~2hB3NfAh=cyjTEHbb)JwnPG@eRB*%)Yl|zBrW5ki(SP4LeEWETxZ@d{b z-9duH!N`qsnOjuPj_HlmV||aykQn+8GmlZ-=Np>gF}e}c)pRHIMm(-W;B0fdUCjOn zZFIA=h{){6%#~Tiv6xI&XX2WKtPZt{G4s({?_8_2I&)zTzO4BPoHxw8kHymImU`8U zW`Q1LH=BFJ&9BU7z5%74b7f~U>#I(6u|Caz`%AG(pd9RWH*g#rvFCY@$jmMg|7oD; zGIC~^*0busKNCxT8n`BJig@Oyfsyp&8dLserENobr)X3PODYzj;dHzT@N#~Fk%~I| z3bmvn0W%9A@XC{-;TdXAZcOqnk%YXg0_O@Q`Ro$d)G~c#DLD^DW)Bhx#8ozX2&#sG zojr`XXXIw%iuz}m7UM;%1!2vm)kfwy&sW+d%ukVO(?vDZ#Ic_R!s1{{ptpZ^g)OM} zE*2ip*=n(P-BQ=}Zd9XA-MEXn@~?OexFOxMc|y*2j&I7b+LyeJX-C!_H=$0Bo0%)e zinq%TLd-sEkDI^J$7LTHry_CwnLu%WOd`{isa$W*mC8!8Z5Wfvr>D`^#w zz9;s|1NK#ce-8df?ay(sLAlktVxf+%%(<1h>Wbo3;D#K|SufHs*T3D|i#aEopT((I z)GYlvoS6Flby`@|AJ6>%*AD1UHSkU|pSw!hzu@~@^Jt=Hd*5?L8|vu&ywS`ps^cDk z;?#4}xA4;WLexxl)J(KU-8VUFNR3*VE!gt?E-K-e_9$)C6#vF*ky%b>&)?W<|1mZ) zKggOM3-f7hlLZSe%m-!Ro2?@G9EKoiPSLj-pltYB!~z^@O+$0L%8+#LyAr9V4&3ft z`-;zm7#R}#eijH#zg^`;&8~!OeMcqAJiMe;|Lu#I-^^UI2cS6n7u|=ai=2Ft!B0LfTpSKcVXt_eFJSgQ~0h=!3TnK{_q!mf|0vEW6qgTd~vba&SI=nlbyx$iBn&^ zhH4;~0`3WD@hTDDfSV)Ut*wh92u2n^j)G=5o4Zo+7HU?wu%;2RU*P32TXV|HzkLo| z8|j)psKd{=mIGkYBtl@&b+>x4wX5$Jbv7KNVolcJi$dr+g>#h%H3|31+KF-+TG zJbrk%0F6mc9BA$N!nYE=dHA29~k~iykpiN%6}QSCQ!{HJd}V$YkwKI zq<}Uy^1r-Y!ky3$WSC_nJ3}nRtXouXM&qK*VC-u}NU~X*1DE*c`$W~|tg{tZ{iMH% z^wZMD3jB{lV#lFh@XaX0S_yk^fnqJQM#&}+Q_k>?2{m541Le@r6%5~@6q_WR^(!bQSP_rpqX<@z;=&lil!Tk0n3oc5ze3k67U5fpTcO{3 zYc{wC^Cg==EG_jOj7qkcSc+M>WP(_RSzNOHTam`Qe4=A3e8pMTAZ5c}*7RE>oA)x} zT|#=8G!J4aQBZ41v5Q%|WIIXmJ5h!i8(svRyfNbJ%eWjkB?cw~cPp1Gt>z>QZA!wB zCEKj5ve9uME53KI}{OihcuE z2~qkR%%vZOSie=uRzRla(nBf9HW5p)UWa7Ii6xog8f-i4_TG+e{k&GfRrwN50Q5iC zBr3L}V{Bwqxs(ZNkZ9lraS8Vmd_K+)|BQf4pC`D1V_k(khv4v62&P#RM>~S^0R1mS zMa?Vd-A0lj$E(_Lc`CL~-;@K-5r-X@^{^lz;dtvlf` z8D(Lo6rQIRNp|?KPo&!@Pi=tP6)cu;9>E$jL1O0iY46{PrjH7lkh+yvVTFY%~NHlVUY9Y&66Ku_QBWG{p9U;R~l7yU>j^i?Gj-X!w6Y zJ<1IG46%8{lz(h9#MTl^v0l4mJBc+h!!AR5XTWfp(fwa=Wl2#(sQFb$X1xmSE=Hv` zT0y9Rk!7PzI;yhKaY7l^s8DE@DFNw6egOBVk(^7H{A%;<(Tn+a&Elr*Gm zw4YFnwK{Edo={q%@8hlh-H3VkZuqGd<-4=J`F>1_)36`$!3A&S)%GSxKipVDcVHp30B9c6PY+pOzGjlQz@|CDKO6PBl(g| zAjTm*5|wOm3X|`wPt>L0D=zImg6|!Zjs2vbVpb#Bd17g1_>>Xp4SyZ1fmw@W^N7_l z!_6SlTML#~D_UOHTxF!_45>$19ed9ns2A-4OG@?wY(2zg5o5g{VCNyWVh_5|2V2h` zte-w1Zh)53vcvqRg=G5L-+v%?#TPF#(3z*7`g2p@~J< zbVzhwQ(uieXD`_By_kXnNe@$SHTE2W^Y+4SEi-I6#MTmPV1^xs*iJC`YTpZA7K^as zkf`YQQ0H!~#)d;|7BLQYH8vb#D|9{VH^esStV6QnV03i z;AW**CE;;hu~xF)Z=i9E4K_+P0SxE(6>p$poQE}SQY3Wsv}F5yYd?u>>=0JqKW-_W{JaG$dgo_8x*04rKi|V(%fg z7%VR?>JDUmHDc=_(SA~|W)s+Yh@B_K;WlFHAvXLEU~$&N)dWfwB%ZrJY zKVTkwSA~YXhh%3+Kgs&tBK0;{(c55A$sP?!Hj9|WtW>fU#JKIFmSmg2aE;RTHoB!u z)JjqBgHY$t9>ss+CRY=PrPypjvc(6H!iPA{NAWdYQWOMNDVUaUKU(KSMaMxnv!s!A zzUD(vAD)KY7^7kv%_9_N6tmGK0C9@7eIm)Qj zMk@$)F-qBJ6QOEG9X2|C2)$WP2(x-!mxvxl%)JlWsVhDVKOFjFQ7Kvsk(z0b;XfLY zx*(R8CLW7Rwx3vrS&d}pi8V081v#}H{*K+H@^|2hgMADad*2t#BF0@LvEL9oPb?wzeuVwz7})S* zU`@=h-4L614BcwSc5@8AqAbI9L$aNuZ!yDmL+lK(24>i9h!q{jh`&V)BmN`oHw0%L zhhmCZt7I#{urD+ohp$=|VZVWT|4vltp4>3PzP!UKOuU`c0c*WGvY|YlFWCfQ)ubMb zJRX&7F|h__<&p_79F|%;;5Egf8YwzY>KSGYk_~?sEY7S&vU$Wfq{owzttFOZy>`iV zf??6Nzl+`Ik0F+Ii>?!tr4!JPN%o&1$z~C&WmYQL3Suc{mSmfVbuq(@J+gQF1V-*p zA<=mvJ97WoC}k7g(`?|O#-zWPn6l9(nIINtyJ^Yx6H_sDN_HL$6EgoKTvbc;CS1Iq zgxPr~p{^J%-ifW%87|(5?If1qwzzmFcIG6y@P9thO?EkqrY0$y^+)I@Ssxegq`!g~ zht`CPcVe4}rCARb@5GK1vzTEAdLOL!`{+W0D1IM96Ce?0&5yAKk!&$!Dm6dG7DP-C zYhpcYLB#eGOEJS1MC?2YTkl1-*O_Du{+kqc|4gUbF ziy7_)5}QZNVurhc#MXjg$+mm|R~Z)JW*~{q=<2u`NUZ43FcD`x+zTW&>(AJfCJ@6w zKZ%=x1Xqxv#SHfXiERSInPl6a;Y)>vYxGkP^*#mls8oL{U$P0rxLZ%*5}ouG6N|AP zF42hzVr=gzT%r@(4+d8qr{F5h>bOKF(eMwUUds%Z=)~p`Q)Y3APHe5N*Dl#ku)K_D z{}5*5Yyz9kX{Z;ShKVN0eu7Ph*sRmY%&ZVY>^cNjkYbV5WV%s5j9E#{e z=jrUw`~^vClI-PJ8lcHwq zI-L;B>x6nOGweFV)^;M?uM@+FH)Go&xRVqcm|@!?c7|9rvpUI&{$l$o{R_5-e+{t= z+YafkfXvaywnJ2b|pHCMP-NTQv8MY_Jl zT@|=jNbn5Vh_ek`uAc=fIt$h$Sqm=LiOnL$zFKg(PHY7j&Ltbq!dIHraj{OK<7eSZ zUFo#oYMo&3zrlvZinv-QHi1|zGhD3`TTCp*3|H&K1Q>31wf+shQY^yNI*HDcdPcIJ z`sfXoLNV;)Kv;F_r^Pm_e=Q1~<9Nwa4r+j(VC1z@6j|Ot)aDcdy$#9wW1{$*^eq(G zQy1Ty6zaq)Q2Z4yul+cf{aGLuyh4i9pcaL0sGE6R^WX9Ac>`*i`&Xz=tr93qty;k! z#>?wI38vZENnXiLI||KCMLF{{O6b=sLnAE~bVz~26U;MiK7sVeL8qI4OLe=;%^myH z{cNCfd=EqcU?@dJR^U?(Qu%IvKN%qXkeiRRMB?xGtk6UbEERRjC*alzOA87|q{yRYV(LUaYx?emSY%0=OF)P4LI7r zPK9O{)4(G6lhlsnA-DV+ouZcHKVtu{N8R%I4I)8umAThrZuyv6k%qirR0BBK$5FK# zo$d7xY+WP8HU9_{{p99?{1W?J11+u*DxO-A{6FY7L%(EXf{iqw)Rc$ezQR8Og@F-i zmW#i4V-NiFAK33o86|&W6<`be1W$|_fuqtV_>|o%36@ba&0JH4xn~TTyF~-q)!$3A ziTcuwLYobiV@d|7K)Q3V-Mg z$S@gdN1-=RS;&Cv`nRD@`kg3reVmAYiWyfKmGa-^d*mt61i63qDbf0AV6=aBtLU)H zr6T`4)klePDl5*48oPW+wAkfR(SANKsN{Fuu&2c_i#mun_WGJJsje#aNUK>IMX5(w zEG(#hJH}$mEgnHm$Y>me=4__oRc`%}#1M0dxPVQbRweUt( zpicH$Jo*$5@dOH8zZ!MolnmW|U*>Hnd(bDc`7kiDjs@-R1~;B!p0*og^_!SyP-+ft zY-QewQV&S+Ze1V#Z{%t7dupdQND&A|ejh@iJD@u8VidZ52lG;tn!f$fchZk}^t(`} z$B6&layOW93+luxP-qTD zQb0{8bp1HS*Oc2p+|D05oC*T2f#La8~p znlKrPqtNy1m{+0H^^2L;==zwn*N_w#fz`#l5vA^+f_aNaUv(hi(XU3G zChfi?{?HvXpiaCEh3=q^c{@s7pN}^C(jNUL*3WqKL(Drplh%Il2RZI`H<)%(HrP*v z9#D!o8Po!rmSA3tQrGWbUW!ucBmelBwv>JcBl}}0^afqbEtI+g(j$FJxu!olpLrEZ zO@Hba%&SrA`cVR8s1}9ZAjP~6rQV>Nc@s)qpY+I13kqF7-uxAw1i&+Ff18Le#EH=O zuW%xC-APgLRbX`eb*s5)x2I`R@^ zJM~F#u$>!ND76OH5GKcQ6uN#5^D30Oelc^B>-sU~wWLoIfDc>OC_w|5)?mUB)X8xp z3f(~k^A?o4z6vPe(XU3G>?Bbr{eQvV6GAL#L#aEcW1dE-8sN|I4a_@G>iYPMMP5N+ z!6XusBfR6c0OP$puOQ@~*diM93I>0p6e7*mL=N^1>b!2NOWJsYI;rcIGmpFVWBJYg zf+BTW`3;=;|4#uPGVw-(yZNLk+`Li5q2Is7Ego0PV%+$k6WKSCZuwX~gLtD2T#GhV z$L-qP`qvUhCf-P+(Dj>`XHaUrE2BE;ccSRwo9xVuSgRDgNrl#6PB-%qO5H(9#CsGJ z`p2}3njQtC3(8(%y$X@&Q828mtd{FF?smiSnNx>cenfYVg27j{crmL}c$)h$_*70$ zxS!K4s(KcTrm~UCHZD84EWSv}E4ZxVvX#q@iwXw!&zRl5)g?l`aKU)Gdw5<@Q;f= z$H(IjP+fDQu2=s6tn;yyMTGqa3R~-rx+eQWu}7ckq>q2G20xKMl)B}yXmfr+;gGQ% ztY)D!nXM3Ay$g!)wjfy%cjXs^COIKiqm35&xO~*fCCwj`tvV6E9U1&X1BcY;ZXb(^ zE{bVfIonC(u+u6s`G_egW4bk<$CN@FJ*FDeDW)_EQ%ty<6euXVDg&|BY*Y*C)U4CZ z5n?7#P*^#R&DE9r(Sm|-<+yHcT#eG?tj67V92ukFXuP!`(5cwh^iDOn<=2*? zPVJgdnEX(3HGAXgSU=(BPN!PkTy^UAUqh#^t>VThlqP5G?#5**328S+r=orIPG#Kk zYa3CgPIaL$`60Vnr^Xgb{ex6!Ty^STzMHE~z0#*3JmlIoZX88vaCWd%B>EH-g=20T z=tJn@fumi?BL_S1hs%LT z1q+I1SK0E&LCTuu$FbMt=HnAmKTU<(T=bHH!ZJ1U(jmw-d+Hu@y4cN;-S{O1MdF^H z7xWqsNyofaQAc*tc*7H$Y9wu;>ar@5@aoKkblfc;-;Fx8uSVgDmU#_roQ2cVwWw=$ zRqxYvZa$%u+clze*%P%P+EGcL{I#Gk*-Nr_m(Fo3HCbYA$YLxEC8c6O$R_ks*9{2wt zm-qheP;M;toG?DdzuI-GSbbLm3D)qqvoxhEY5A$f0hx5a&L9`TQPs4~H(W8-rN9 z_J4uiBMwL1O-I(EPK~HDnm^>a8uvLX%V{=|+(O|BmU#tAt({{p?&Tr{d(QGaT<3c})c^vr)4AKQe6Skn&!y5Ro;`O^=# zx_zhtIh=I!i8TMncM65ex5)HE;+`8)0P|_vu_!ErLrL%^Hoapq6Qq9>P02(T3N0NI z8%1p)=88J2eTTZK$wwwcq7Xxu07mn7irr$2LK@90C$_UZhSC)wbLxT1EOX1tMXX43 z7k7(k(2KCNCw6o58k8n?^1Y(SJ9X~%=uHakowL7p8r||q6h3vc1%=6O0$l6Hm|E0H zztzo0RWMJwIS;V-_u_)^q)FAR)Q-~REbVTrwy1YH|YR8pHMi04-V3tSq^4@2ob$ILRr!5U=$Mlap6@_F4FyR znNM+&T9pV5!Vb`@1m-xbBQ=tZ2cwU8loX71rrMDvw^?jUO(nEDDtigHd@?SqY`L z?6J6;PpM-4YLte|9;>nS#btvF0@?6tDRpAz;OtU9h7a&!DMyYq+WOAjE2OJ-F!pSf z^Umps%VeL-IlIvXAjjVwZx4bDw6OpWGZ>4-cYYJx!R|XH`vRya7aOD?x+mw zHlfsd==k;w=2VOITTz;9C&~7R<85wpqq@0S%FSu(A3`Ckq;)`UGMgc@k>j22=2wTB zuh0&^$H|MV@h13THmcT3%Bqcbdzxw%U3yVPFqmeQwmXkn{` z_HNwvGveJUce~LPHpNlx=152NFsueE#PT|nCc6#IPZi+d8Sgg!q!v5MzG2$^(|23k zHZ6;7wdSy8e|*XRZX213yqkiS)F=9XVyjXL>hM`7|qdDQJiQ78Qldmf$0pr(ltesl!p(e+KN z){W9&_B|47?bJ$nFW;U=Yer}@{k>wh?)52Z9E`kIio#?&MkfmX_sZ@2ApZ9(`@ErW zWI?FXN^;XUO3nR9!dG+cDl&Fj>1Z$Jo+aIUQ8NRtg)e(HG(!h{!rV7bl z38GzaY8&&n5myUqFa^v(^6`q~mp4@gyxWPv$7_-_Zz?}tm$*L+4T*2gV4IR_L9|Kk z38F=E1ax&j5pwZP|1xh?YpCD5j*UTj$vr`pGh>t76ETUKy@aI3~c(N#Y#A~|o z62Qrx`qVC71vram4u?;UN*w)4t~U$blQl`wR06qZYYsRCYeKXO)^ZoN?mDTlpg7jn zVZX=Boq9y_TPbRHOkq9onu=`^XUMO)1FOZkK~@pNE%^_WS*cBC~O`=gjH47J<-Gm1~6d{ zokr)?wx&xec^XboY5as2O;;dA@){rYc9y5AlE?HYz`Z{@Pt_%Vc1=}W-gLStc{=zY z9rvWH`{|G*x8Vlx>Ev7+KiwmFv?d9DQz8c(r9T~mXj9bFap0^dbH(_y<2@32`1CM+ z_w?lHnBYE_mNu(X*rpf*5>FH~o{{+KymCH;CDt53pUz9(jK|Yt&vHw&w7(*xs6`dw zuiqTUpDs%~bKmLd5s71!seTHxs|uLXAC>gx_|O^f>UX#nq_tUH;^&4`40dB9)08}| z8sO>NqCk3P*?1-*^)P}JihnM373n<_g%DM1JO;_SgsSW__4DuL&p47aC#laQBo3qG znV2qTQ;`%b72q2hPY3Xf#s}PsobG36nagL-@nl# zjP7TOl3a;z073ds6`m=3S6H_=I1M*T)H4-nWQOsXQHj$U0%zOLZ33st>k#eQOdVjA znX95_S`xEY)q17&v-U2@$DsS zld}YbNM1D&tlyk0JR2O=s%xL=vwh5=o z7>;Y#9Gv+VNY4&S-pqk#sR(9A7f7)4ccf>@KjX0@Mb7bdBnQ$zS$Nia^4$GwUFySM z272D5;IlN`%o$AskiF)!!lNPZvXfOZc25M3_DJKt>d>SHA;!e8%J-K^*A0N+qm;?JuC zNAb_aB#)Phwv8QQo=bogQB`aktasFblXVJ$RkO)aY4H9j%5(S$B)Cgup(fmD^PDvI z-R323M&!AI#AE7Jc;9}$1DLWYL9`1~2F|iH6Zp9iiJzNQ$pqbXY5*sHqmn;Q4JN`p z^K8x5Bzt~Fm0|6_iSb-Bz~@w*_)U&y|2zqn6{c6@TwLs&PuU{+^EO1AYMzgJr_#5a zi!o2G@Nb{li^Z2nVdKG49dpL4ke@r{1fn(YGiBT&U?k6@P@e8PWN~{VY z64Q81Uwxd16@zR^mj;>nM#qxp>5dIP-;!iMbq+>k!;MU$jgZ7mqK$~eFDQ@$_=!Ta zNwg7j_0`Mgg{SsjV1iP0EK@q!*nx?3J|#)c5&^!U9PrzHJ|%fSxwOPDaI1sAEO3#W zD(=9VPy$Th^3n|HREaj(4hQJQ(D_KlFNVCZV*F&v65koeHbonSkjbRaXUWv08Ima= zT<=b@Ci6ys$2$u!cXK7WC25n*3uMi*+(|V<|Ah#I$VTJpAMie(T6zIpbk;Q%g=9W( z8koF*t@JNYg^b@xrBI9nM7tQ2G}G^osWSYH#Y;;b@#-R8M)FCjh2rHP+Qp-qS-hQ? zRyz^Tte!6ne~iz#d;>W7ElEC!Qx@?4k?w_&08e$3-6%x6e5z9a{MJy?993VaOAfil zK#s*~N<>7bI1|5B6e@BvDv}2YWFZ;He-A7KdmT%mL1V^(U2m zAsg5ilai;21l}+1#kAxv#HJfB1JN#C7C4J{K}nV2&pXk4F)zsraSKfZ8xHVP6cty3 zXcw$3^>=nC=ORB?MUr?KF*8P1C7DdABFM3_>yp2a%B4)25bZK)N&TcfbTOOGFNK1% zin)9PINZL}BY89?4c<@ZrD%X3(RS3JHtD?NNd29-@d|(5D7=)EBpTBkBh!++5Wnzu z3D1NY!N&I@Y`PWXAlhY;2hQ}-=p6j{JNiq*ALGj|Z#q+wJWUyq4|Rh1zbJui>gXs$ zyL_rrAM?|>6epDz=75u3-8+T2OR&3A#xb{ zGzQ_7P&m|mEGlibjN-4{AP@6|;+XeMirW9_aAc3U^?QtpV}VwZ6AF}+xH-}sOG*5q zn${nH6p5({1vlrW$FllmI|TRU%(1-mghQeI85}8X?QmGq7spicGZjo@k2M08IDbi*nSQMGG139)58TTk$zPno zHv0K;4}|PbF@sL&#*( z@TdN50p1IK8JBq9-2y3JD&(tnrYG ztB2mjU%r~N3nx-0@+&>k0vAfoF5LXPq@pcjknJMHrQOP^)_1(Cf$#0Y3n@`mg|B|c zWRaFO%bVIJBXPVK5xX334y`bDR5h#0bmx_V#4n+)pgXS=A=>3!@^Txx9FxU-DfP;T zJA=l*Qt|e(M?tC+@$u5xuT68Hu*$vyBk$fOdWCXh&ai+aLHgtH zsy9OZvv67=!0$0>zS<-0&G@})OWgG4)u_ZT)xCVx0WOn_T#2P`EA zrm@A+z1UG1sBJgH{Axz>$s)GNJS*{w9gXKCzOtc;@YlPR$|5@o&*H5vsVc?u%PC17 zf4C0+gIxtel%w%cNak-VE|jkd&pq;FcuM!Hb;+T&!c~~^tH_jmHYJ~|X}l$IQ(F^v zagSpSdh{yHoa0k)aBD`SCaP&7f?rKDFgTyic@dfpWSeT53E;AtTv}JtOiK>cl+&!5 zW?-bufxh_(Bh}1#)jXH>tNHlYM0WFPN-~4bV3YdTtU$D@W)!%rrnuWwQifv3adSRcLG`??E+JUWKuFEh0T&Y+`%ZYl^Q0#^y6QFT!gMWSeSU z``FlMeQ!s4Esaf9EDCBOoL|su8OdKn>7mfqK4ExX%XtMYz1lCRAU&X<wOCbE}T)0F&$)EtWS3B&Wc9-ggxO*OAm{VW2i$socS zvk<%{aCiO0(1PE_J zutbdh8$`2$FDnz!)%`{Ug6ZQ+x!it??24G?ZAfNk&gR|-jK^g~tsip_tKDzJgLbM6 zzx^xHS}!4a-##hvm3dW%om#a5`|ulN%#&%T$Tc`WEdr)mGLnX^gWqcNZ#}<}lYE~# z0PEg0WJcx%Nu%{enD<{sttOs^Mzl)fWk{A)yfif6JzR=Wlr1H zrLDOzc%vcl%kV@H&K8-&{~ImI8@o3<^w|u8_}7|mMx^qJglfW>|I?&z+LFgPhgFER&(w?`yz&cWZV&^dVT z+f_+l>|mRs;#YEMZoOT{CXb%bJT-*jtMeKUG=vT*NJm|HBbL;6B2Z#o$INO{Emx2& zg1%!zFsD}}lzjke!xd4@$AY}Z;}S>E$`-1c5x)aGeO8MX}mBC{X8 zlac(DJ=!h@Dg0`jdcpjeHUFIgwOnn@;KA9IrlgY8HGO<%MB;uf6^UP&z&5q63eheX z{ow4k2pV2biIKARRs8sO@P;-WB_`j5`*60$wMek!uN+pfn{Z??^QqP2UEl7%i7omq zs)iYD!Iv2@a_>isZ()?_&A~@up)Pn2zv11&54<66cZ&vwnZ;77c@xI1K{<4Fx6%O` zU*8;LQIn zt*;)w*?YZr`FnAxVeT5emyq}_oLAj~7f&jHDPW+_W>0@F4VneKJfxgk&^N!ZjO5QO zs|@)57+}|L4uaX6gx||c9PfG;VMjj@zx=&n$@wLeBz|Uf=vE$TMAGJ>;k{9b<9sUZ z+S$OV^qS<;4ULmzV}Pkpf!*M4-ShV&k~d@YevkCmPyP|-eOuzYE7&GHDsj`=_o;`h zb$ZV1>V7{iiQQFflcNL#OW02+DfPX%Q=mv%5ctO4iKY58@Ix8Gb+& zGjA)@KYRgi_K+7O_(3|r4yz_&`4<@0D7-EWw97IF zoMnmEH!HAn-$o>f325Jro#*N%^vF+H>YJm@hcq}qvj8U1;~|OfEs$bY_wgQxHi;g$fipjQ zi`d3rl-V*Ep6S0^dORkT@a{rp(CcCmvUfREOF^g*<_x1$9mIui25`IBS*gCUhHY|_ zllY#3iskeYGX8kMdyH~?SXCCFqx*As_GTX79H&Vu62LZjEK7V}T;ml;k(sLGu*Y0I zqWP*fncqeb|L(@|I!G2|GyV+VA7c)g1OM@+H(J!rksK=M8>TkQ(L)@KG^5{DiSZxdULajKJ$eTg zI$F#IKWa$}Ju5Bp$FtE{S{)&Y@2BeV8!R0?5FgLd>ac;cs`Mq^8TXA-8pu*-s*4yd>z|lNA~T4r+~BI`-W8={?v&F!c#1(BQO=N#P2NL#iM1V z^)*x?Max69i$<+r(XNTA4E&ixpw&?f@TTf=(4VTpF1)`9oZ{hR>HvO}!s-~64z7$2 z-92_`XLZyheGTPL_6>-3`8Me|He2nxJ3KSIZ`e~F*MaqXwmJgLETz`C2sl>Qs=BHm zaIc=}*0`wT`!cFYyqQbm;*!5IrR+bUr5KNSA;Wz|@JMtVesRt%bX*$SEFjk8926H_ zL!BZ;s;o^#_yed^k!6jeAz}{pH&q=D=y%;P@Z+df#^QtUNFD>fst%momn84kIU@1C zjMlG69M{|#`0KwirTMDl^`XZaSC=@xXsN=^ou21dB+d*Ha1#0MN~BkS=Y2+)U^#qf*0PB9eB3t7f$?KCHYkWfD7^(`{ z4N%RLRT@HMrSSns77r&I_McMiA5NWu6tiB6m;NbI++%B#yfi_IIhc&47#LPR#iF!B zie<99Hmd#7u(nIFBJEbhROHJ@5hvA{MB@X4inBBaES;rgAp6av9v>V=3QCO$3?uFk z7h!kgiSQKln=glF_OGB3f#QT72-c~K9gW)(Ur`?V3Wi&Mt71*STUIp6>%M{(UZYE$ zK(@>mJ}^wf$X}u+q$GcB4%?Iijh1MUs=&@2Ez6pa1i~f0oj}Iy%g4*Gt(%M|wHC zLlxo0UwkK~B##eas^I(2ECWX~Ck{y7EIt#n635~b`zmf8pIOy*dC8mQXJSF(*QK?7 z2~tcEjh9W8Blr!W+3J^H)jt=3U<+fULrDh4!i@MtbpWR;mNl^fHP%X6Eeif>F|nnJ zG!H&qz}cc1u1OJZ3Aw8f?w+b^nxt30hYHvy`V2@(FyDCjs1D!eT-2I`4}7t1TGph5 zRNRtLkw3>NK7QwTGT6X4AVufT{as|zfV9Q8uNh*!1Jb0xSm3rr5v+Lw(wdZ))>td5 z#3yXvXy2q^$>S#){{pnWZEj5}1!)xn-*1+RNh6XsQ)JSp#OaGm*qM9D)})%`KSxDU zI!%Z+Q(=;OFBubla)&z=mVC{d3dyhG;A_^)$u^Ana1^l(r<0=+H}iXPVEE`0yRYGq zqaNMKc%=k8nR@7JW7A-Ak{%z-?zJYTq))R;Pd;)c#%A_?_~m6G-Mzl30Cwbp#aKMTxqHu$- z2z7EB7%$VlDa5mIIE8Q&!d+k1b|a8&X8e?jv|HMvim>a|FLGN`XqGa+_@k~>;+OUS zr+n%VjK?>U!=P`>0VcWyA;PNIFuJd;Lm|-28n1e!VNUOu;{+x|T8zE1pb9X?&pMZe z#~y)LAxEmAgeKI~k3XbUFO-yQe@oe4M+ODJNHCO^H2RkOy7yDlIZ`u;21aEiZXR-a zSb9OGbu3Q*ivb`TlUXpI%*BAid)K`j@a_ zIaQ}OHAJtK%~q4XfouM&t_q`Wmy*qkeZx&D@eP*JR7VCtN`-IuBQQ14Jgfp0u$xv! zVTJBZO-pOD>P*c@-0X}~an}3~@V@k$cz#G1SKnk;vr_|2Bp+^&5`>sT8ZSe#3UQHC zhClTqoS@IQrdA|t7QCsW-cEb;oA@g$8{*nkO)76KXuOW+$~YWMZF+0;mIu(^L3dt- zNrOed7T9RpxRv6^<^4DNBa;6^H(koxFw< zlFqn|gIOAQo4$nyq`uje!(_+9U?oMI-YqmPltxbS8}RlD<#D5KR+uES&yYUZkv+rB zd0MzA@tbUHlYSXOPTAEX3HzaGE~8gD@|Ke~Er8qxgk6`G2t1v+6Wo<@OK1qUf{1fFI? zvnm2@49A!H63p&;jpuPdQvJLDr?1*#Laz`>1m0Z z!_f2r?=Up^JK@N@n3K;XqArrzFobA=DtregiGFS+_u@?b z@;jKSX6j5I2{^-9CyW*ys%fXA0p1jfmn3jq&}U62#da;LOB^Ru$?vkcGQBDJ!)a`z zimng@t72_V;}J*}=P)Hk`Zfg9H*=*c2Au1AT~b@VhdT#mesm?>qv?58S4wJ|(}%7B ziT72pO;Ixv-`JyZ_k+LL=U81isbKoum6!M-(j$iji65@3>i4jV`-zk!k8k1r8nk}K zWOa>58rLi_@aFln)ivsk{l34Z>m*Y|T^el)sRB7Qw>7$&lE*1u1$_U_A>hb)Mg)Sj z-gI>aHG{SOU`g2}oN{RqWr+)P};kmsVOkb!Ej9y+H`p?{ZL(&+`81ZJMnbDFw1~U!5 z|7LQF=#d_XHiH?lfwQnTP+{Q`N!a#}{Y( z0I#l@E8)n9RNLfWo06?Su@DF5xteVhXiJZ zAXt6+6=!Q^k92q|B}Do$sc-h!nel*r9owYuK(K^YMqT_IYi2?cXGL7Xnn{T<12aG~ zQxdDK==t{C4UqCuFVf|J$jORg)=iRS?sq>SnFFrGl$)oveueelxnxuu}xK! zB)-zocv;W2nIrTT%4~J%kHRzkJ9aZirB#-CN8aiXtml3SxDcm@2uI<>zcoFxMVD>o zS=}KRvA&p_w%yb>hF|Pp8$r4Q188o7blYyNmen1VhIo#c`LS-ve5*S!p873ltJ^u^ z;JW_1Klbh+RbjEnp&_G?Y3b2S&hCtBv##vfq{~<|{4@*F=He!{$=9&Nu@n}_Zj+<= zz=)U~q`NHba2Tt=u6K1_+l@*dOK6jLv!iy`B#&EN_D|S_eRo6h*&?Eu7eGyi@*`p!b39mZn+hgif|M8f5zM- zBulR;gY_3NDnabhYF`?2?y<-~u6Lp}FY#1Z!3Vf4^c*_pBc28i)1VgEXfyT0bUv8e{N! zjAuELr7?aG3zv6mW>!+Nm*W=dL-1|(xmjt+(f^H$`w{GG%LX(bSCI-HInOpv zsAeZXur%?eU=jxE-`=NtcC*uxH9NrU0oRSX`w{Q$N9-uGv)+#KFd*~G5!URyKF^t5 zkdFE&Ps+FGuBx*~yj9g1p&3`yTm_P)h6f25@an`0UICvSXuG+>oE>O8ohp#i+nU-b zN!Cy_s7m}7iAF+mNU)&z`N{u^{+aQb6LAYt>;5awrtyIX3ZH`r*pb#+bEqa}YVKLi ziAmg?2+xUozK+0G_%s_z6hA>nO3Rv)l18{+*`!3wA!p8jcV4*Ur!Y4A=$x!RfCKao z7IO;H6ZV7LPqF`)2|uSO`7e%On=&aw$WGN^x9GN_<|~k_Tr+HQM!n2t|801t|2%(A zU|9YrtDQ6;MG%eCFmdO4zRV?>;h)DZNd7H`Prp-X&5cMN!(aVdJT;(NP}5v;Bf<^+ z9hz#^#JSiz+#}Ik2YM_F{hAIGdws>EPXCdEn@Y6<~+tP@-rMqp8R|K&_oZhBARl3 zhT$_+^+es_>$7@d(u+CN_c#*Ac~ub(dQEygDaqqQkSch8SLq21-|cniqYXVd2$@)n zo~o?+240u!DS%`po1XRzOMKA5HaYv)*lD~B$^4l8uxCW#hgw>{;^HU!FPZc?nxMgy z*;bJ4;2>2`3Dh81pxY@h;dP1og)}5Sn87ym=aCR`G#-Lv{>|M;YhFYWc=VOS!K&9J zKFLGNe(fIks2uPHUnp>Cdgoo89S zfg!%wQB6dmKVps}W-p!#x(^-y8y-61eX`_#!x@j61-+jzTD^`8nH#`1lI~4Hh)$?7 z{P~MQZ(1)3y=1_uH;Y1VR^qv=iu?jQy_t2rdC6Z{!ZrmC3=M|bf!(GU(Zm-aSUj`H z^p+)VMyGeg>+*Mhfv3$?=#Y<5sr$taRYeSa3$ZsaUN~3zCB~j!F6y&-8`3nE(k`14 z$7NCsR`W<55$BU&Sz`fC{}SE!;~veE6z$fy4aw~OII1eJ^RLe4Q(G913xp=? z$GdH?;!9pw>PS{M)By@tS<{P(xi`CLZJgAX1cH-C-v_jbZmvxi z)Fp0a)qnXi3~WkUN2Be7JG`KjG7dI|gX0%Q_+Cg8uOxC!v{t!Y;Rrk|DlF z@_19I2)^HUO4EZCa|h{@9c3fCQYAan{u3PV+%Ai4vP(ipyBKbrn4c}NPDq1icGv;a z;OCiUosbFe>Z|{ZSxWooIo1g|Nt#ZcP>?v~?j|!V@jH4{lalfIQh*;&_P^-Wz_Lyl zkt|x51iQ#@-KgaKmg9cyKOyHo`Iqnv^Xp{R33aJ_r|EMGxab$Q(Z>@>us-25DDtmJ z-CX6J7?C{oFbBNORDyDI{m?1~WW zQZE5#c6a1eh4L}W`iWFJ<8eo-`EOWJsWNgqDrux^|B9zulf0j9UE*};g59FK27r^_ z7DStLPwJr4x;g6MU*X=-omEfyB&w0+cxP1A;mp5tf08ZvyDHd5kdtB%?SjO;AX}^S z6`-S)6Ob$j-Vw`G*}$Dd9br5=Q3Sup4BSan8RJbSPRe-4``=V?tHQ4+CzbK;;=j{i zQdcPPVTg8#7lE@F7|b;6{AYeAl_ig^7r-yNI}M!tQbXJMt$7W3``>v(8c=4za685R zA9!x-7e>i4K3>8$g4iS&ZWb^*FpB04Ya1uY^c>}`|AFKGU6dg?i3Xe)JT7sX3P{SI z3U)&BcNeft{!$QaDz~vT(|p_dKk*&+7HT^wXCPPw<}ht%12`V|{!auq>y@3Cyy=up zNpOD-wkggq-4nDdyNFH3n(pE@oK3?TNO$ZrwH9PJhc1`z2x z;1}g7Kgz!d(Jp`YVsuXTLduu52iKiN*v~U}>K9fdKd657+wk1$@*%+FzAEWEqZ+SC z+%K;#@%(_+Z$h?9v*nHG{@=0Pd=Uj_IpY9O_#Jv;db_Ac^7)XefZuMCTSQ4Rdz0Lv zn8foV*hZ0y90-w|vTN7_anm8xy(kHiIlBvg`-MpS6+^tvu_!HB3{MX1qI;+Wa-D?` zt~H)>>+W8Z$2Rkx&#HP2I}){>%!efn_mTg=Esc8|&6gpWdvn&kr~;h1y@%2ue>DiE zZ|)f`ssrcxloshX+>`LN)}p3VFe~e#mc-4Zx+|2KjQxZqC3Pm$tb)7sQc`Q{;;_uNN zIGH-fI)f8^`wy6FW=@?K%cv8s|c`^m{QiQ^$omc#A_2qBd0| zzvditaSwP_<2`v*1+O1hE{;kThmOa+4=Hz9i{p|rl`M87ZaT9#@daM4ApWiH z#c9dYcQVBL@n|lx3b5Z*z%Tk!>NIsA4GPCdGHcPRdHKUO|GM> zW{8$hxvZ-g;#gfzvOa4`TC!%sEE$kEO$=E16JtqM@~FR1_kWSdT9TLamz&t8a)u#9 zIjTv?xJQsBC2547+fPx?8`^k8@`#xPA2v(El2LaFJ;z#7m5P2*HHrI%b%|sDE>mE? zg_J#OA!d1<_^+gaqpGD52w9c$GeK2Ph{AJ4It zI?}{fO-OuK8QYXXQsRC18&VV^UDUk3r#0yrte3vCj5NYq3$bVDo}2q7*V3G1;WGUU zRaMn43zA1y3dDcK@MZ9_D^1s459iW~w8u?e`&rmu9s*7!kssDIj7k#xcE782$@`^} ze_@Ah^4F9&;^ipb2AUP%Pa(nV@Y|(j@cw(br$oF_I{GYHXbz{R*wP42BS*Q@nB+0^ z4)Lamr#O;F6Eolk|11NXl1fYdUK`tl=O9?J_r^6|3g9V?2by_rPUF-RHb~pNW(-SYr*Y_M*QAg^VGpT4o>aR&+oBWfUa6108lmL8?VH~Bf!2?j{ zWRR9PI@o*;M-5_$&Oxwz>1C7WL1#2wfMj0jCff5DpL>n>qU7N{_q_KhT^V})zFt-8 zEjRXciDM^Hr7t@4g8S=*xR<#s&~8)EvH=+K1RU)sBk_BORSeF;=1J7DocpL?g0&16 zZhwy@fBy@3SO61Qqk%4S<5QmSsH$NRf*G`j~B;g z!?L=h?;Tai7ui|rvZmy}+Q2s2w>$*VrhUsJQXjvyQ-(kNUfy!s{S5f%i{Y8qnFN=| zrNvjNa*E(c+#J)FCnSEa+ZyO6C2r2+m#4js-TV^0+Db~~+9K+G$qZWNZySx%`8CB_H-sDvS++s9FBhY zr6V=zRd+Q}u~#t+pUpuT!B&K%5hht0e1Bh5^F5L`XJ0GqAg&6q+hdAYL0Pk8%qjJX zxWxY=f^Etp3DIUmSEQsqing0Lr8gtGVnFhy=oMLsn>B4kPU4#!Y*YOFC*TFu`~_Ze zb>Cm)^>nB*^4PSoN86XAy&04hWr_RwRlGr&{hBu@&TD*7>e2|urwn+1hOB4?_y)GA zh?c~$+Z4&}Yr4rRDcLqnUTI6aHJPE;k&Zd%TN#ry&iP{C!?zWIBP@RHkd6myt(6I> zXo_8#lDK*JxiamoAV*%Om8z*K@H+SxQSCJ+jm%oQvLNxV8U102`}!q`n;E*YEO9+U z)unIXOwv8WqtZs9Bs!*YZ{VK&DOupe*V;OcW;I!rmoz4B4E*>b_+hZOaP)fht#IhF8gxWx z?Yb^)&HK2k8WQiTYW-#a$LvLnsX32c-QiB=3D)Y6`!?!)Yjs2#Y#G*?J>K_mOWvlJ zo7@|!s{^Be-)c|3jpKp$zVB*%T6Y&2&yoTG1hzW|Bf zmROC875Xf1_B+~3x3xOZ-4*K0chEH*6~9-2S5wu^(C;4>Vi1N}7)P@btR9tSx29DL{E^$kQ?^^HYmzimdv!zNN6Og7+*}XF|#%j0^kI)g!zquKUNPZ|s23?k0qo_gSQAp+wx7F--QQV50=HrsTJ%=AX zqh-=f1b!2eUlCI|;;$jU6gMS#yku7<{tB`qJ|lUYw${P-r(2rON#67?R**RCocD0o z#{o=kix8}=uQfGZlK5o}m3dE}C8N0`k}cF#5p2I7v?_VC+Q#Y<$Aj4SQR7epFp^nA zg7tnI9+ZL~R23q?Q?CTC@j&mD@t6Dr{WNe^^l(J`$x3~F;k(OPlamIjrVa8EH^=)m z1&N#0WzBF9SM~?kp|_Gg6i1I{ea%luWHkp{vMY=_q>Aq z;ZhT;!31kfQ?C?Y{ded3$&$6q_5l@|Ulg>&W2a7cL{^7XhNs-MV zJ;qjlQQF;B#4qiTUrL9XQIABqB zl=}MMsP6g*AMhIEwb0=sb`#A{B)>K!@%2;;;Sq`BVx#;K-h9qz+Lp9g|JOz({`G>^ zryjH1O>fsaQvWu5ozpp|_v z50!_;b$SnK2CcQj0WyJYidB@j?~GDq&diC`+Oov`4vk3s{us8&|0u+`Y50%6Rfc<8 z1*GM_7qhkojs?0up(@0ibD^~j$DZ}BiQiA1LdQ-`L$HMW0tbMzgv?3C zsTqm;1!oCYJ0^6Fy*zem4jA)Ie~4^C=bSx$aRuqi$A=|u-oih%C~?2GlEl9e9h%rV z*ZqEgDx^w9B`P+N4^?1F_(N5P9m{?PRY?9C5X_&SbyMQzRjN~464&~D);i$aktuUs zNaC1-6(rpIjT{+tS?i(@EHS!&I|;lQqIGfbEWtx9l_cI2wk{#Suq(o@*RQWCdDK@Wzu!y%Cwr=sG zZ*ZjD15_{Nk%AC;s0zh16LACO%lsi;lj8Y)vy%Ty%AfoeAcS9y4?{A4bg=D2Jaaj) zp(OcR@C`h8y6`>E+AtzXbC$hfRN_a<*rp_?NEXao_~J2`_X8Q7oioGtnNHw=DQ;b> zInz349vP(1GB&iNIc}^u(`YOl;BX(0NFHOAA>J&$aa;1V7zz8>$M`Dve&61ayt&~P zPe>e>hSOp8mr1~sRvMyB>*Il;{3E>d0K47?8rm)k$-0F#pa6dRx1yRae1hM=keaCz zFG_!CPm|*L?JG+j?XkPqRE}39Z>C&)RN~)CVVml%L5R9luB+2Lv58ZatUCI|I7IWG zXvABRH*;%ah<@gKt+g>Cd2=7!ow&@enPVHhPXN@G8J#oLy+6cHTyBg>4}Jtk;+wHa z^=wQ?oIaJEf&QIY)jZYBB7?7j_jk>W1Csw%QQKu9MV~aDgJk}O3Mv-q9Q%xKW5K)0 zyf4z}-efL-^bg1z1B1DN27`(ikxntl71;Uv$i~26qKGE>HCGevoM%aytBH+u=@*mL zo(aE22RPzxA|Z-YIq+fQcT>bG=AoILV?VUB$%YXNR;*x~oYBY$XBx-H>UhU{<|YT* z%x;64(cL-M|GnT%Nl7DDryEnR*wSujpxU|5xbC|*Wu^Uwv?{{he|d3JUh?o?1wa1V zu^|g;=FqY!Fhn?1#lT-=_Nz@5>E_#%7FAz^XqR3cIIH>)`6qomCUZaG-_#5!-~tT+ z{q^lM(q|4#BBzBU{_SDal=P?Z$Es zqkeO*<+Q*cnVTr5r2=*pRfe7aip*)$CFU2+uanArExWg(#VudOay873u z+S7T`pd*b|q_GWWpQ6sPf&5P`ji(`5l6}9>_y8o+|BkKkK+^8x2=brv^ast&lkYg% zpa97NxX(?x>X2Gg$d15x^r5+@Pv)8LB?B-bx`xD$co`nJYyeF_NuvqKO}zn20M9)V!` zgQbclVvyWGS8#S*8k8s?IZ6fe9gU|US%ANxfTW*;;Qkl5_@H%m9{=D56p#!`5X@j+ zOXFoouAkO;6_V@!TH`fHu21pEe-mOHjlUj(dBd8ZK-_==!r+_;1P^ez#(N;SJ|#l> zF$k`2Ydj8V^eO(|G&PZgWClIYYCHvL4DiqY9MO0NlIv5)C~y{n>&G-c49WGcr}du< ziU9*kgzymvZeSc$fb#$pko0R1Ontnm;e*Qa>UAKXHfFoRhw zkJu7}5o7#eXFVQ3MAL3fTUl8@bwYjHU@PN+<+1xgBFBu(9vP(qu*Adx&83~Zh0wzM?(5e1|GIS8hIqMk$B^1xYu zAH}gv`sIMW@jo~cFi2yY3~CT8z{y38*CBa;f`=zaaD5#(K?!qxiU z>5oD%{Y6HfB-hVjoAetHTz{Bwoc|}9klcU*!r#~``? zhQ=&~Ipc_xzu= z)crOVW4S#k4Sqt25Iz9G^eu8scm{%X=qHp2;duzA@BSh=;RUU4&i{Xs&<3S|fnIvI zm$iXDTK;4}>yJwPna4C<4d~}J-jMqJ?(fS}M$Ldh$ul^Q1gl`?VO8ntoI91`!t6Y} zzPkd?S>EaEJY{_317)x1T%~@rqI0VH%nCy8RJj$nF}6dMNz77p@Z)DZrXnjzUay>$ zfWM5PQ;`_h&ST1nVRNy{xSL;8McRB&Rb!ne?WVd}y`B2dbbep} z9vtu*a6UDH>u=V0U;rM>YaFi{_IJ+t?D>IyKS*)W&C4C!$ z>4)%J^=t6bOheQ00FAe&*PsXC%az@aqVcG|ADdHaDu=8tS{l`6MQJvbwkcW(f@Seg zTH}-r%fdZ;k$z3Z?#J7I7tqSUc=Ni{PBI^l|LbYp(L+F&wKD|4<52err~H^7^LS%t zETCW2`cyuCxNY`_QzPeCI~}QIo;mDHNc^EXwkcW)f<+7A70k7GG2&rc^I6GH)nmUi z2b^X9Fl9mhh9S7WjK+(QT%Y2Seg%T*Pw~1iXziqSa|23*4C)ZvK(F{a8^F1K5!=vD zlHmG18V^Bo{ffqk=da~W#nYKnJLjHT*L;k4{9g~JdDSZE0OS5z*rxcD0Mo}CP|0;z zTqr!z-j^*CtmJ_A_WfP!@br=1_+E!+29Fr6Jd~O9OXAwPAaQy)1LuRL#u3mgww|(c zewUJF?jN4(=$iApbO3j-P53|nPiQ<7z{xN4dw-V=5TrjsHcmT62O}pACHtGk0s>eHICz? zpfjo+)gjsHFx}QT9x}%9^yYUIknz*fnr|tGc=F5n=^>A=;iD9nk4S!+E}({Q0>N*u z*#W+SZ4^?AL$E@+G8%UvSw7Rt8cz&uq;!%2dO*|oX)Kpd2l$re2UObSDGYPp714ZF z6{@p1sqYJ4<+lRf#VyEq=J z>n6+|(L~E7#_*bl{~;2j~f`jmH8wMMd<-C_C<_ zqVaS9r))?+>*5!WWmVTi!6nA)eELj1zcS)J=TCm$d6fbOg+p4GWwT=|jOS)D_- z{>jgN+WE-Oembr4?eM~!Hc8-z)H`RXZ(ctAB>Yy&^m&ggzGC|AQ>O3Vzu)e&>AyD~ zIIMnBoHnQba{H|7uf66*`_Q#t*k>O;VBfeed)PkpbM~GCH{ZB-_rcGHcVB<~fvZ>E zu>)wFeJ}**4|iZ|~iA z%gWt*_a5|t!#8AB8t{<|_fOwCZsM9)ET$f~X1e43>zQk&-?f>X_CwFMqc;89Ub)i7 zCb_bgh4Z%fe_7 z@^D)^hiv-}d1c!dZSwxHEPUwJ-R{VZjlGR@ zZT>$qcKd)M=*MP(??O+Ux#zi|PH{t=VzXdpZr;heeEqct_T0!L(Z4UZT{x_3Q$OE0 zZI&ut)ENpN*t0u)t-aRXd6D|}sZ0rLERsDwP3)PL+ zPrq?L9I@dxI(inkLvJv%Q@PGyX7K+nL#b|hd(vE-?M|9F)t#_3z0^PbbmG#>*>L{f z8O5{3C@u^C9}V6lckt9tW=>nUXvcwD_Z>QH@45EyAzEwfL;DWfpE|?7_QqRwUw`dh sfAo_7|3+_YM>G93<3oGg{)7AWJ%YiTIOCDV7pEV4Wa7V`w)g4(1z3qvLI3~& diff --git a/roms/SLOF b/roms/SLOF index 8ebf2f55e1..9546892a80 160000 --- a/roms/SLOF +++ b/roms/SLOF @@ -1 +1 @@ -Subproject commit 8ebf2f55e1ba1492b942ba4b682160e644fc0f98 +Subproject commit 9546892a80d5a4c73deea6719de46372f007f4a6