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[216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:27 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 1/7] thermal: sun8i: add thermal driver for H6/H5/H3/A64/A83T/R40 Date: Tue, 17 Dec 2019 20:21:15 -0800 Message-Id: <20191218042121.1471954-2-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Yangtao Li This patch adds the support for allwinner thermal sensor, within allwinner SoC. It will register sensors for thermal framework and use device tree to bind cooling device. Signed-off-by: Yangtao Li Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick Acked-by: Maxime Ripard --- MAINTAINERS | 7 + drivers/thermal/Kconfig | 14 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_thermal.c | 639 ++++++++++++++++++++++++++++++++ 4 files changed, 661 insertions(+) create mode 100644 drivers/thermal/sun8i_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index a049abccaa26..ed023d3e8e4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -694,6 +694,13 @@ L: linux-crypto@vger.kernel.org S: Maintained F: drivers/crypto/allwinner/ +ALLWINNER THERMAL DRIVER +M: Yangtao Li +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +F: drivers/thermal/sun8i_thermal.c + ALLWINNER VPU DRIVER M: Maxime Ripard M: Paul Kocialkowski diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 79b27865c6f4..8cef77fdef5a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -263,6 +263,20 @@ config SPEAR_THERMAL Enable this to plug the SPEAr thermal sensor driver into the Linux thermal framework. +config SUN8I_THERMAL + tristate "Allwinner sun8i thermal driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on HAS_IOMEM + depends on NVMEM + depends on OF + depends on RESET_CONTROLLER + help + Support for the sun8i thermal sensor driver into the Linux thermal + framework. + + To compile this driver as a module, choose M here: the + module will be called sun8i-thermal. + config ROCKCHIP_THERMAL tristate "Rockchip thermal driver" depends on ARCH_ROCKCHIP || COMPILE_TEST diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index baeb70bf0568..939301195b9e 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -31,6 +31,7 @@ thermal_sys-$(CONFIG_DEVFREQ_THERMAL) += devfreq_cooling.o obj-y += broadcom/ obj-$(CONFIG_THERMAL_MMIO) += thermal_mmio.o obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o +obj-$(CONFIG_SUN8I_THERMAL) += sun8i_thermal.o obj-$(CONFIG_ROCKCHIP_THERMAL) += rockchip_thermal.o obj-$(CONFIG_RCAR_THERMAL) += rcar_thermal.o obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c new file mode 100644 index 000000000000..639a06061305 --- /dev/null +++ b/drivers/thermal/sun8i_thermal.c @@ -0,0 +1,639 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Thermal sensor driver for Allwinner SOC + * Copyright (C) 2019 Yangtao Li + * + * Based on the work of Icenowy Zheng + * Based on the work of Ondrej Jirman + * Based on the work of Josef Gajdusek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_SENSOR_NUM 4 + +#define FT_TEMP_MASK GENMASK(11, 0) +#define TEMP_CALIB_MASK GENMASK(11, 0) +#define CALIBRATE_DEFAULT 0x800 + +#define SUN8I_THS_CTRL0 0x00 +#define SUN8I_THS_CTRL2 0x40 +#define SUN8I_THS_IC 0x44 +#define SUN8I_THS_IS 0x48 +#define SUN8I_THS_MFC 0x70 +#define SUN8I_THS_TEMP_CALIB 0x74 +#define SUN8I_THS_TEMP_DATA 0x80 + +#define SUN50I_THS_CTRL0 0x00 +#define SUN50I_H6_THS_ENABLE 0x04 +#define SUN50I_H6_THS_PC 0x08 +#define SUN50I_H6_THS_DIC 0x10 +#define SUN50I_H6_THS_DIS 0x20 +#define SUN50I_H6_THS_MFC 0x30 +#define SUN50I_H6_THS_TEMP_CALIB 0xa0 +#define SUN50I_H6_THS_TEMP_DATA 0xc0 + +#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x)) +#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) +#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) + +#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) +#define SUN50I_THS_FILTER_EN BIT(2) +#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) +#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) +#define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x) + +/* millidegree celsius */ +#define THS_EFUSE_CP_FT_MASK 0x3000 +#define THS_EFUSE_CP_FT_BIT 12 +#define THS_CALIBRATION_IN_FT 1 + +struct tsensor { + struct ths_device *tmdev; + struct thermal_zone_device *tzd; + int id; +}; + +struct ths_thermal_chip { + bool has_mod_clk; + bool has_bus_clk_reset; + int sensor_num; + int offset; + int scale; + int ft_deviation; + int temp_data_base; + int (*calibrate)(struct ths_device *tmdev, + u16 *caldata, int callen); + int (*init)(struct ths_device *tmdev); + int (*irq_ack)(struct ths_device *tmdev); + int (*calc_temp)(struct ths_device *tmdev, + int id, int reg); +}; + +struct ths_device { + const struct ths_thermal_chip *chip; + struct device *dev; + struct regmap *regmap; + struct reset_control *reset; + struct clk *bus_clk; + struct clk *mod_clk; + struct tsensor sensor[MAX_SENSOR_NUM]; + u32 cp_ft_flag; +}; + +/* Temp Unit: millidegree Celsius */ +static int sun8i_ths_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + return tmdev->chip->offset - (reg * tmdev->chip->scale / 10); +} + +static int sun50i_h5_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + if (reg >= 0x500) + return -1191 * reg / 10 + 223000; + else if (!id) + return -1452 * reg / 10 + 259000; + else + return -1590 * reg / 10 + 276000; +} + +static int sun8i_ths_get_temp(void *data, int *temp) +{ + struct tsensor *s = data; + struct ths_device *tmdev = s->tmdev; + int val = 0; + + regmap_read(tmdev->regmap, tmdev->chip->temp_data_base + + 0x4 * s->id, &val); + + /* ths have no data yet */ + if (!val) + return -EAGAIN; + + *temp = tmdev->chip->calc_temp(tmdev, s->id, val); + /* + * According to the original sdk, there are some platforms(rarely) + * that add a fixed offset value after calculating the temperature + * value. We can't simply put it on the formula for calculating the + * temperature above, because the formula for calculating the + * temperature above is also used when the sensor is calibrated. If + * do this, the correct calibration formula is hard to know. + */ + *temp += tmdev->chip->ft_deviation; + + return 0; +} + +static const struct thermal_zone_of_device_ops ths_ops = { + .get_temp = sun8i_ths_get_temp, +}; + +static const struct regmap_config config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, + .max_register = 0xfc, +}; + +static int sun8i_h3_irq_ack(struct ths_device *tmdev) +{ + int i, state, ret = 0; + + regmap_read(tmdev->regmap, SUN8I_THS_IS, &state); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & SUN8I_THS_DATA_IRQ_STS(i)) { + regmap_write(tmdev->regmap, SUN8I_THS_IS, + SUN8I_THS_DATA_IRQ_STS(i)); + ret |= BIT(i); + } + } + + return ret; +} + +static int sun50i_h6_irq_ack(struct ths_device *tmdev) +{ + int i, state, ret = 0; + + regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) { + regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS, + SUN50I_H6_THS_DATA_IRQ_STS(i)); + ret |= BIT(i); + } + } + + return ret; +} + +static irqreturn_t sun8i_irq_thread(int irq, void *data) +{ + struct ths_device *tmdev = data; + int i, state; + + state = tmdev->chip->irq_ack(tmdev); + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + if (state & BIT(i)) + thermal_zone_device_update(tmdev->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + return IRQ_HANDLED; +} + +static int sun8i_h3_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + int i; + + if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num) + return -EINVAL; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int offset = (i % 2) << 4; + + regmap_update_bits(tmdev->regmap, + SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)), + 0xfff << offset, + caldata[i] << offset); + } + + return 0; +} + +static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + struct device *dev = tmdev->dev; + int i, ft_temp; + + if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) + return -EINVAL; + + /* + * efuse layout: + * + * 0 11 16 32 + * +-------+-------+-------+ + * |temp| |sensor0|sensor1| + * +-------+-------+-------+ + * + * The calibration data on the H6 is the ambient temperature and + * sensor values that are filled during the factory test stage. + * + * The unit of stored FT temperature is 0.1 degreee celusis. + * + * We need to calculate a delta between measured and caluclated + * register values and this will become a calibration offset. + */ + ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; + tmdev->cp_ft_flag = (caldata[0] & THS_EFUSE_CP_FT_MASK) + >> THS_EFUSE_CP_FT_BIT; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int sensor_reg = caldata[i + 1]; + int cdata, offset; + int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated + * temperature from sensor reading at factory temperature + * minus actual factory temperature) * 14.88 (scale from + * temperature to register values) + */ + cdata = CALIBRATE_DEFAULT - + ((sensor_temp - ft_temp) * 10 / tmdev->chip->scale); + if (cdata & ~TEMP_CALIB_MASK) { + /* + * Calibration value more than 12-bit, but calibration + * register is 12-bit. In this case, ths hardware can + * still work without calibration, although the data + * won't be so accurate. + */ + dev_warn(dev, "sensor%d is not calibrated.\n", i); + continue; + } + + offset = (i % 2) * 16; + regmap_update_bits(tmdev->regmap, + SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), + 0xfff << offset, + cdata << offset); + } + + return 0; +} + +static int sun8i_ths_calibrate(struct ths_device *tmdev) +{ + struct nvmem_cell *calcell; + struct device *dev = tmdev->dev; + u16 *caldata; + size_t callen; + int ret = 0; + + calcell = devm_nvmem_cell_get(dev, "calibration"); + if (IS_ERR(calcell)) { + if (PTR_ERR(calcell) == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* + * Even if the external calibration data stored in sid is + * not accessible, the THS hardware can still work, although + * the data won't be so accurate. + * + * The default value of calibration register is 0x800 for + * every sensor, and the calibration value is usually 0x7xx + * or 0x8xx, so they won't be away from the default value + * for a lot. + * + * So here we do not return error if the calibartion data is + * not available, except the probe needs deferring. + */ + goto out; + } + + caldata = nvmem_cell_read(calcell, &callen); + if (IS_ERR(caldata)) { + ret = PTR_ERR(caldata); + goto out; + } + + tmdev->chip->calibrate(tmdev, caldata, callen); + + kfree(caldata); +out: + return ret; +} + +static int sun8i_ths_resource_init(struct ths_device *tmdev) +{ + struct device *dev = tmdev->dev; + struct platform_device *pdev = to_platform_device(dev); + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + tmdev->regmap = devm_regmap_init_mmio(dev, base, &config); + if (IS_ERR(tmdev->regmap)) + return PTR_ERR(tmdev->regmap); + + if (tmdev->chip->has_bus_clk_reset) { + tmdev->reset = devm_reset_control_get(dev, 0); + if (IS_ERR(tmdev->reset)) + return PTR_ERR(tmdev->reset); + + tmdev->bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(tmdev->bus_clk)) + return PTR_ERR(tmdev->bus_clk); + } + + if (tmdev->chip->has_mod_clk) { + tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod"); + if (IS_ERR(tmdev->mod_clk)) + return PTR_ERR(tmdev->mod_clk); + } + + ret = reset_control_deassert(tmdev->reset); + if (ret) + return ret; + + ret = clk_prepare_enable(tmdev->bus_clk); + if (ret) + goto assert_reset; + + ret = clk_set_rate(tmdev->mod_clk, 24000000); + if (ret) + goto bus_disable; + + ret = clk_prepare_enable(tmdev->mod_clk); + if (ret) + goto bus_disable; + + ret = sun8i_ths_calibrate(tmdev); + if (ret) + goto mod_disable; + + return 0; + +mod_disable: + clk_disable_unprepare(tmdev->mod_clk); +bus_disable: + clk_disable_unprepare(tmdev->bus_clk); +assert_reset: + reset_control_assert(tmdev->reset); + + return ret; +} + +static int sun8i_h3_thermal_init(struct ths_device *tmdev) +{ + int val; + + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN8I_THS_MFC, + SUN50I_THS_FILTER_EN | + SUN50I_THS_FILTER_TYPE(1)); + /* + * clkin = 24MHz + * filter_samples = 4 + * period = 0.25s + * + * x = period * clkin / 4096 / filter_samples - 1 + * = 365 + */ + val = GENMASK(7 + tmdev->chip->sensor_num, 8); + regmap_write(tmdev->regmap, SUN8I_THS_IC, + SUN50I_H6_THS_PC_TEMP_PERIOD(365) | val); + /* + * T_acq = 20us + * clkin = 24MHz + * + * x = T_acq * clkin - 1 + * = 479 + */ + regmap_write(tmdev->regmap, SUN8I_THS_CTRL0, + SUN8I_THS_CTRL0_T_ACQ0(479)); + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN8I_THS_CTRL2, + SUN8I_THS_CTRL2_T_ACQ1(479) | val); + + return 0; +} + +/* + * Without this undocummented value, the returned temperatures would + * be higher than real ones by about 20C. + */ +#define SUN50I_H6_CTRL0_UNK 0x0000002f + +static int sun50i_h6_thermal_init(struct ths_device *tmdev) +{ + int val; + + /* + * T_acq = 20us + * clkin = 24MHz + * + * x = T_acq * clkin - 1 + * = 479 + */ + regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, + SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); + /* average over 4 samples */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, + SUN50I_THS_FILTER_EN | + SUN50I_THS_FILTER_TYPE(1)); + /* + * clkin = 24MHz + * filter_samples = 4 + * period = 0.25s + * + * x = period * clkin / 4096 / filter_samples - 1 + * = 365 + */ + regmap_write(tmdev->regmap, SUN50I_H6_THS_PC, + SUN50I_H6_THS_PC_TEMP_PERIOD(365)); + /* enable sensor */ + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN50I_H6_THS_ENABLE, val); + /* thermal data interrupt enable */ + val = GENMASK(tmdev->chip->sensor_num - 1, 0); + regmap_write(tmdev->regmap, SUN50I_H6_THS_DIC, val); + + return 0; +} + +static int sun8i_ths_register(struct ths_device *tmdev) +{ + int i; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + tmdev->sensor[i].tmdev = tmdev; + tmdev->sensor[i].id = i; + tmdev->sensor[i].tzd = + devm_thermal_zone_of_sensor_register(tmdev->dev, + i, + &tmdev->sensor[i], + &ths_ops); + if (IS_ERR(tmdev->sensor[i].tzd)) + return PTR_ERR(tmdev->sensor[i].tzd); + } + + return 0; +} + +static int sun8i_ths_probe(struct platform_device *pdev) +{ + struct ths_device *tmdev; + struct device *dev = &pdev->dev; + int ret, irq; + + tmdev = devm_kzalloc(dev, sizeof(*tmdev), GFP_KERNEL); + if (!tmdev) + return -ENOMEM; + + tmdev->dev = dev; + tmdev->chip = of_device_get_match_data(&pdev->dev); + if (!tmdev->chip) + return -EINVAL; + + platform_set_drvdata(pdev, tmdev); + + ret = sun8i_ths_resource_init(tmdev); + if (ret) + return ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = tmdev->chip->init(tmdev); + if (ret) + return ret; + + ret = sun8i_ths_register(tmdev); + if (ret) + return ret; + + /* + * Avoid entering the interrupt handler, the thermal device is not + * registered yet, we deffer the registration of the interrupt to + * the end. + */ + ret = devm_request_threaded_irq(dev, irq, NULL, + sun8i_irq_thread, + IRQF_ONESHOT, "ths", tmdev); + if (ret) + return ret; + + return 0; +} + +static int sun8i_ths_remove(struct platform_device *pdev) +{ + struct ths_device *tmdev = platform_get_drvdata(pdev); + + clk_disable_unprepare(tmdev->mod_clk); + clk_disable_unprepare(tmdev->bus_clk); + reset_control_assert(tmdev->reset); + + return 0; +} + +static const struct ths_thermal_chip sun8i_a83t_ths = { + .sensor_num = 3, + .scale = 705, + .offset = 191668, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun8i_h3_ths = { + .sensor_num = 1, + .scale = 1211, + .offset = 217000, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun8i_r40_ths = { + .sensor_num = 3, + .offset = 251086, + .scale = 1130, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_a64_ths = { + .sensor_num = 3, + .offset = 253890, + .scale = 1170, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_h5_ths = { + .sensor_num = 2, + .has_mod_clk = true, + .has_bus_clk_reset = true, + .temp_data_base = SUN8I_THS_TEMP_DATA, + .calibrate = sun8i_h3_ths_calibrate, + .init = sun8i_h3_thermal_init, + .irq_ack = sun8i_h3_irq_ack, + .calc_temp = sun50i_h5_calc_temp, +}; + +static const struct ths_thermal_chip sun50i_h6_ths = { + .sensor_num = 2, + .has_bus_clk_reset = true, + .ft_deviation = 7000, + .offset = 187744, + .scale = 672, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun50i_h6_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + +static const struct of_device_id of_ths_match[] = { + { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, + { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths }, + { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths }, + { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, + { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, of_ths_match); + +static struct platform_driver ths_driver = { + .probe = sun8i_ths_probe, + .remove = sun8i_ths_remove, + .driver = { + .name = "sun8i-thermal", + .of_match_table = of_ths_match, + }, +}; +module_platform_driver(ths_driver); + +MODULE_DESCRIPTION("Thermal sensor driver for Allwinner SOC"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Dec 18 04:21:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11299487 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 740571580 for ; Wed, 18 Dec 2019 04:21:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 52D1124672 for ; Wed, 18 Dec 2019 04:21:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="skg64jTG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726613AbfLREVb (ORCPT ); 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[216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:29 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 2/7] dt-bindings: thermal: add YAML schema for sun8i-thermal driver bindings Date: Tue, 17 Dec 2019 20:21:16 -0800 Message-Id: <20191218042121.1471954-3-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Yangtao Li sun8i-thermal driver supports thermal sensor in wide range of Allwinner SoCs. Add YAML schema for its bindings. Signed-off-by: Yangtao Li Signed-off-by: Vasily Khoruzhick --- .../thermal/allwinner,sun8i-a83t-ths.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml new file mode 100644 index 000000000000..8768c2450633 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/allwinner,sun8i-a83t-ths.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner SUN8I Thermal Controller Device Tree Bindings + +maintainers: + - Yangtao Li + +properties: + compatible: + enum: + - allwinner,sun8i-a83t-ths + - allwinner,sun8i-h3-ths + - allwinner,sun8i-r40-ths + - allwinner,sun50i-a64-ths + - allwinner,sun50i-h5-ths + - allwinner,sun50i-h6-ths + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: Calibration data for thermal sensors + + nvmem-cell-names: + const: calibration + +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-ths + + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + + clock-names: + minItems: 1 + maxItems: 1 + items: + - const: bus + + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: bus + - const: mod + + - if: + properties: + compatible: + contains: + const: allwinner,sun8i-h3-ths + + then: + properties: + "#thermal-sensor-cells": + const: 0 + + else: + properties: + "#thermal-sensor-cells": + const: 1 + + - if: + properties: + compatible: + contains: + enum: + - const: allwinner,sun8i-h3-ths + - const: allwinner,sun8i-r40-ths + - const: allwinner,sun50i-a64-ths + - const: allwinner,sun50i-h5-ths + - const: allwinner,sun50i-h6-ths + + then: + required: + - clocks + - clock-names + - resets + +required: + - compatible + - reg + - interrupts + - '#thermal-sensor-cells' + +examples: + - | + thermal-sensor@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + + - | + thermal-sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + clocks = <&ccu 0>, <&ccu 1>; + clock-names = "bus", "mod"; + resets = <&ccu 2>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + + - | + thermal-sensor@5070400 { + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + clocks = <&ccu 0>; + clock-names = "bus"; + resets = <&ccu 2>; + interrupts = <0 15 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + +... From patchwork Wed Dec 18 04:21:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11299489 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 71CAA1580 for ; Wed, 18 Dec 2019 04:22:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5014E24676 for ; Wed, 18 Dec 2019 04:22:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D1O/XNqo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726769AbfLREV4 (ORCPT ); Tue, 17 Dec 2019 23:21:56 -0500 Received: from mail-pj1-f67.google.com ([209.85.216.67]:51761 "EHLO mail-pj1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726609AbfLREVb (ORCPT ); Tue, 17 Dec 2019 23:21:31 -0500 Received: by mail-pj1-f67.google.com with SMTP id j11so261157pjs.1; Tue, 17 Dec 2019 20:21:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KISpMLvHz5xVmytt7DhjjbLP2haRM0PkAgFQCpHv2Bk=; b=D1O/XNqoZhFSe6At2GFzjWOZQKji8mS7q/uJADGXW995QW5W2bfDqAXNwrYFLBhuRt 343GJ/jorl3lNoubrrzmfImFh5JpQmV3N+71pM3lYojO0m8xk/UfFLgyWPz9sSYm+fJB SZOpEeepYh3xl+sdOjJMSEiYg3auyD0gk9gqauTTSCMMR3lj303Ir7MNV3AUSf3Uh5Y+ nrW9WLfMc1ebVi/3CZ7mMeb/0LISiLaiwgnh/4pBlWOPEDktcpeBJAfRN1sn/v0uc3Lo 1UGEM7heCM+nIaFDJoI0HjvV3zjnvx+UFtZ1kryhe3eQdSdZ9fftYDk1uTYDHKJiK+E8 Otdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KISpMLvHz5xVmytt7DhjjbLP2haRM0PkAgFQCpHv2Bk=; b=U0dgJGdFlwhES3gZgTFiaYlll7PPtUqELlapLUKzFmbEJannYFQAmDEe+T/E0MAzMN LPpHBLnAGQLFmgbJ0M9GXSIka9Tk5cmOwlr8KNc2hh7RTmhMteIKG/ZpPLxzxUz45s+C eQzN1jb5WpW6Ugq9Bf3vtwAy3er8mAPCPPsQvbz+SHmrdPN8d6slYqxX0pWCVU2sm4M+ J5CvL3N9BO6YmhWTaM2OUbgUP2sl7xVndnQ39PEVaWVaPmX/ptI503EP3fCSf8zizTqv WdjgZNY9etFt6YzukMLPHDs6J3i7lhoIWFuWJwoloT8sagrW6bE+xFAjzIj/6Y5IpRtM dq9w== X-Gm-Message-State: APjAAAWT15C/42IaP140JpON88QgFe7cygFCU4pptvFiqA+zQsJkaAqe Uxg+oYYIAYfU6ok1DVpSgjY= X-Google-Smtp-Source: APXvYqxpQXSaBHFKvE0AQvKbWCbghFwFtWjDzqLzbpP3qGi8vq787Tb9uoBWWTtqPEr3U1c4cXYsjQ== X-Received: by 2002:a17:90a:ec0f:: with SMTP id l15mr276822pjy.39.1576642890876; Tue, 17 Dec 2019 20:21:30 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:30 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 3/7] ARM: dts: sun8i-a83t: Add thermal sensor and thermal zones Date: Tue, 17 Dec 2019 20:21:17 -0800 Message-Id: <20191218042121.1471954-4-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There are three sensors, two for each CPU cluster, one for GPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm/boot/dts/sun8i-a83t.dtsi | 36 +++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 53c38deb8a08..93a6df11cb18 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -50,6 +50,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -581,6 +582,12 @@ mmc2: mmc@1c11000 { sid: eeprom@1c14000 { compatible = "allwinner,sun8i-a83t-sid"; reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 8>; + }; }; crypto: crypto@1c15000 { @@ -1165,5 +1172,34 @@ r_rsb: rsb@1f03400 { #address-cells = <1>; #size-cells = <0>; }; + + ths: thermal-sensor@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = ; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; }; }; From patchwork Wed Dec 18 04:21:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11299483 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D08B36C1 for ; Wed, 18 Dec 2019 04:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD8062146E for ; Wed, 18 Dec 2019 04:21:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="oDxvUotx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726594AbfLREVd (ORCPT ); Tue, 17 Dec 2019 23:21:33 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35586 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726648AbfLREVc (ORCPT ); Tue, 17 Dec 2019 23:21:32 -0500 Received: by mail-pg1-f196.google.com with SMTP id l24so537940pgk.2; Tue, 17 Dec 2019 20:21:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PkNqtr4xDaqPvN6Vsjd/SlEQaI+42QLqvwGVf2EVSjU=; b=oDxvUotxmEnupXyRIMaKZb9E3c2EvhpTe0MkxDhUYMbTrig9phgJLAXLjKVoPr57GD QOVpKPOFlxOBxc1+Nzn5n7tQtmzSiQwpBNxCbmNOC8GVdrp5McZBQbtJoOpQ0/7NPROz Fv1POekWpX8Np2TcRBtsDRA3ohyQA6lPJemVWtsnSqk5ilvOrME0rniXZPXoYMoZeBO6 C9epm3/dwt7YlCEl5KxY2zxnrD5NkW0YuEsHwJ6WCIm0LKg26l6cIIj3QqFTisDNrWvu 2O3OcLCKd+LPlNPaKdjznGI+Q5sD31Sz1itjaOvnwHerMHQXGjP/8YmLDQYUxzaiDbvi ouMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PkNqtr4xDaqPvN6Vsjd/SlEQaI+42QLqvwGVf2EVSjU=; b=eIkSBGnMNmous5i2hEVzMm0yLc+5jFXh8vDB9GgXxtLLlZNsEeLGxKBzQfQ1bgTjtN 4BCad/gI9qjeXnymnUVE+zOGzczcNZXgH40wX0McR9tbBUgmdPTdyYz4b4LixGnsiHAI peBIjrjrmcqYWhIOIggJ3Y2pCNR4svQc/AgOBkkmRqreKNlXj8zG56hPC4771v8iIdsX 5o2mkjl+729++teaY6Oe8FQKdu8pAsnZQvYNEhx0+urxew/mOnrpHQGs31eNlc5OBtN4 A2DFQrGhxmzyxw/uQfudZPIlWyeAI9Hjev/priVMevkUKDXJhromH3zhVoy3kZxLVf8n fAPQ== X-Gm-Message-State: APjAAAXwqQ6YfFJ0VbFfgNdN+6jM7mHwNcSWtGbcnaVw8BlDagwCo4Dn CnLbdAnDabTQ/lL9RGbICZzJiCo6ihw= X-Google-Smtp-Source: APXvYqyaLIhC1zlYgDPB3PJwRcp6N6iXGD7adEnC/8FzIjMzlcznWf5ZIojHmwGv0rifSIQZS00k9w== X-Received: by 2002:a63:504f:: with SMTP id q15mr636016pgl.8.1576642891885; Tue, 17 Dec 2019 20:21:31 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:31 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 4/7] ARM: dts: sun8i-h3: Add thermal sensor and thermal zones Date: Tue, 17 Dec 2019 20:21:18 -0800 Message-Id: <20191218042121.1471954-5-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There is just one sensor for the CPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm/boot/dts/sun8i-h3.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index fe773c72a69b..be8f601ab8cf 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -199,6 +199,26 @@ mali: gpu@1c40000 { assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; + + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; }; }; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 0afea59486c2..6e68ed831015 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -231,6 +231,12 @@ mmc2: mmc@1c11000 { sid: eeprom@1c14000 { /* compatible is in per SoC .dtsi file */ reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 4>; + }; }; usb_otg: usb@1c19000 { From patchwork Wed Dec 18 04:21:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11299481 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8997B6C1 for ; Wed, 18 Dec 2019 04:21:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6574A24689 for ; Wed, 18 Dec 2019 04:21:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mrg17tqF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726750AbfLREVr (ORCPT ); Tue, 17 Dec 2019 23:21:47 -0500 Received: from mail-pj1-f65.google.com ([209.85.216.65]:51762 "EHLO mail-pj1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726676AbfLREVd (ORCPT ); Tue, 17 Dec 2019 23:21:33 -0500 Received: by mail-pj1-f65.google.com with SMTP id j11so261196pjs.1; Tue, 17 Dec 2019 20:21:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5JoZyySS78BiNU1aODtc8vpSYvJMQn2ITDVR9fgmYmY=; b=mrg17tqFWEI9echCXToFXJOHp77UK2JA5GbsZqzLwqAR9vCr05p/FJRVWY9OwE6y3N HWGuB1pME0LUdbMAydBMZM/sHwBJCuL3Avx6yPr3LDqgDVD6PPg16aH5QPVJbGZ4NGVv G/AXM21EGT1glWaaUNt00qP8k2WjbPjiSLJqsrkOXEK9NdMU6iR7EeNDjXoEbNeEsEu3 f8CNijAHCI+itYbDnIcycmbkBIG4AHbyc4YHGOqmjCpYt1ZNm5v4Yi5rmHY7m5hAyLh/ yVpIyHyiRlAn8ABaEv0kZoKmCGTul/w4bXFjV7KWrlL1JsGRBVHMoTq9rhqCkDyd0SRa mDCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5JoZyySS78BiNU1aODtc8vpSYvJMQn2ITDVR9fgmYmY=; b=J2Z63azT42Pph0801ZDmm0FO8MtSqi/4MZwxgUU/7KaFBj8+LMKoWFB+6equuuyfpg fh+pWRaxTbGIp6aF7cbRH2VPEz+cMJ4DYHvYGr34uF75MBQysmKGwMbhdzHB92GRk6z3 gruiLRkcj3kLg/q/hpoCyWiQaB9WRLFG8I0lSjiEZCEhUDc1BjLRZoIQd17tjk57siep UvKHftK9XEMb0ciOPc9rN85d2xT0/lsNePF1gGHJCwCI+wWCkPmm0wqSU0E/Es2Ll9tO Z2ufsSfxyylYDQ4um8EY5wgCl8EG9Q7S+8dC7ijbib0RXnoO8W9LVXSMjBkixg3UId+d 4Ncw== X-Gm-Message-State: APjAAAXcvcAc5Io+E5Fn+6SPC1RhOVTqiRUsSGEFY7BuMA/zseYFzGWg RLXD+Zn1mT4vhQCtN0ZhZQw= X-Google-Smtp-Source: APXvYqwkHZDDMPW+eIbPKCNS8iHXIe0g9IqSkmFDGFTAYkookNiFDEI9gFJvmiTBJUJtxJ4Fzg2tjA== X-Received: by 2002:a17:902:9a49:: with SMTP id x9mr261739plv.331.1576642892784; Tue, 17 Dec 2019 20:21:32 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:32 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 5/7] arm64: dts: allwinner: h5: Add thermal sensor and thermal zones Date: Tue, 17 Dec 2019 20:21:19 -0800 Message-Id: <20191218042121.1471954-6-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There are two sensors, one for CPU, one for GPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index e92c4de5bf3b..f9df95b2d542 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -176,6 +176,32 @@ mali: gpu@1e80000 { assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; + + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun50i-h5-ths"; + reg = <0x01c25000 0x400>; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; }; }; From patchwork Wed Dec 18 04:21:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11299479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B4DEF1593 for ; Wed, 18 Dec 2019 04:21:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 92F5824672 for ; Wed, 18 Dec 2019 04:21:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jVqoF0hH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726730AbfLREVm (ORCPT ); Tue, 17 Dec 2019 23:21:42 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:43533 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726695AbfLREVe (ORCPT ); Tue, 17 Dec 2019 23:21:34 -0500 Received: by mail-pg1-f193.google.com with SMTP id k197so514742pga.10; Tue, 17 Dec 2019 20:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iNX03JAOppaU3e3PkzJ7AHYN2jOBOqdXzk0VsYgjatg=; b=jVqoF0hHjloQCi5UH4qQ9ART3reXrk4ao/eieXiXlKTbZbR0O3D1JQTW42ym6leW3N lO+0DHoBNw1ZxOBfWD1jEYDPL9jIbBChkvneuNd04gDEwLdCEI76a5znDNA7ApKlaKgp 6xMo1RTDCkTfz3qB7OiNs+0JLT1Q6Uuw3CWJX3e6xvG8JUdq9Ls0X+5hZG9wmPMrbp6i KIn+wP3aC5+GmWBl1wNb4cbIgfNKHUYRz3q15ypI0HnzGS0EwYHSJB2tZZc7caAHPdm6 0pO6/LeQ4NYXLJimevLa3OGR8RuignIHeJNAEzeIBbP3/ZDnlNIbS3YpxaoJFtMzFHMY f+/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iNX03JAOppaU3e3PkzJ7AHYN2jOBOqdXzk0VsYgjatg=; b=aSHyWEI/TbWlulgKF0VbQlX6GhMbmEbeYmpUK67Tx6vjPLO6To/0Tdt/pWKuyuFfn7 dQSpxcV1YOUTubQM1/nQnLDbUJNen/PfJ7TCqWqDaVAnzdW3jrwZ7ysPZiMr5/iqZ+b0 jCDrdK6O+dY2SI/+d+rhsydQFuhGcfNQyJc0cFPmeMhrJXDSGrTlk1c246wqu5rFD+Lc um4WRMtamwkcid9E1n4lgMCdP7Ms0ctiYULOD2o1ocrlQW8T4dC/U8IOUK2GzfiXDsCd Tz2xm+iUSv2UGTfacOG2iDDmwwkiGVihDBQFdpsK/i/3P7VLUo13454Gfn/iVxGuZEBc 4fWQ== X-Gm-Message-State: APjAAAUWoUeMP8VskMbkeaA8JZDypfiUAB4l3gld40UCRFlWBssnr+nd uGYXAxgxMtUrNg7kXKWhG2I= X-Google-Smtp-Source: APXvYqy4TSEggqwbg/BFa9ETiaGNQrz9Vejq1CKVDpkMenvRmSXBpmZp8SS0b5R+mUmZ/0fqmxVYqg== X-Received: by 2002:a62:b519:: with SMTP id y25mr760491pfe.194.1576642893785; Tue, 17 Dec 2019 20:21:33 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:33 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 6/7] arm64: dts: allwinner: h6: Add thermal sensor and thermal zones Date: Tue, 17 Dec 2019 20:21:20 -0800 Message-Id: <20191218042121.1471954-7-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ondrej Jirman There are two sensors, one for CPU, one for GPU. Signed-off-by: Ondrej Jirman Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 29824081b43b..cdcb1a36301a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -233,6 +234,12 @@ dma: dma-controller@3002000 { sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x6>; + }; }; watchdog: watchdog@30090a0 { @@ -856,5 +863,31 @@ r_i2c: i2c@7081400 { #address-cells = <1>; #size-cells = <0>; }; + + ths: thermal-sensor@5070400 { + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; }; }; From patchwork Wed Dec 18 04:21:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasily Khoruzhick X-Patchwork-Id: 11299475 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF2356C1 for ; Wed, 18 Dec 2019 04:21:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ACBD2218AC for ; Wed, 18 Dec 2019 04:21:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D0pEVsIi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726648AbfLREVg (ORCPT ); Tue, 17 Dec 2019 23:21:36 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:39310 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726707AbfLREVf (ORCPT ); Tue, 17 Dec 2019 23:21:35 -0500 Received: by mail-pj1-f66.google.com with SMTP id t101so254130pjb.4; Tue, 17 Dec 2019 20:21:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z2d+ahFeOkEATCdRxK9eTJRkU69hz2zRKJpFAKDhJEA=; b=D0pEVsIipKoUZRq4dcGZk3Ly+nbar7xAXTcPpuLieCLHUVMgyiUhlKh0E6P1ZHTrQR /NQXEVt0TVbHrfMVuqUI9miC+4UOUgnt7voHAwdg1AaO1YigjcFMrVgDrnvSt5xynUFB W8ssEW1T+skz8LNQay5lDS8ubvEy7mH+eS5kkL0Yzb98UGOubqvHlaamSZlbtOy94m7I QpvhPbwE+wHox1xSY7pxvf1Me9XnewU1PEo5Ei2KNhHr/iBSSHI2MrKUlbnnbYO40kjr osSjJjP5G0MZWaGwYExQtKpw090si9mTSRRZPLhxKb2J/R2CCq+E0YjnQBeyHf0oJ7+A qWYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z2d+ahFeOkEATCdRxK9eTJRkU69hz2zRKJpFAKDhJEA=; b=Td0y3AKgNs3oZbqS0r94Tw98SrP+7dm/nL2yQ42mpPgN8MFtgT8EKhC3J0sz1XHRWD 4RF3HrsMjLgWo5O5veKt1wY5SQ6bi2Glh4uOvA66uZ3kSz4Sv6ourlqwEwuyo4GQ/s2V mQTr8Sxy3PDegGgJKoD7zys68sgopMeyfDL7h7OzFwrL889mFJ+HMyx6ogPtKYFrvLTQ wb5otR48uIeFx+yV9iDVbTUVgM/BnDPsk5+dyTjUH7Ju8rCejHbh4Cji0Tf6rHVYfrPp qQbPv/l1NUvhC1B06+otljGjZ/9WBJh1JOAecXg2hjnVPLE51WKi3fpVal8MUnYNPFuX NfSQ== X-Gm-Message-State: APjAAAXXh8ObkNkeOzrcfhEHHyUGrvacHiqMTFxVP4d86uOKhhMJML/Q jHaF1m9xFYHecAZCaxlwP98= X-Google-Smtp-Source: APXvYqxgn2rYYrjJ3k3VjIa+89rQz1elMpM1AwMjdLVAf5B6YfYs2+o275CoGDgufuj15z4XTuSpEg== X-Received: by 2002:a17:902:54f:: with SMTP id 73mr287449plf.213.1576642894642; Tue, 17 Dec 2019 20:21:34 -0800 (PST) Received: from anarsoul-thinkpad.lan (216-71-213-236.dyn.novuscom.net. [216.71.213.236]) by smtp.gmail.com with ESMTPSA id g17sm775380pfb.180.2019.12.17.20.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2019 20:21:34 -0800 (PST) From: Vasily Khoruzhick To: Yangtao Li , Zhang Rui , Daniel Lezcano , Amit Kucheria , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , linux-kernel@vger.kernel.org Cc: Vasily Khoruzhick Subject: [PATCH v7 7/7] arm64: dts: allwinner: a64: Add thermal sensors and thermal zones Date: Tue, 17 Dec 2019 20:21:21 -0800 Message-Id: <20191218042121.1471954-8-anarsoul@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191218042121.1471954-1-anarsoul@gmail.com> References: <20191218042121.1471954-1-anarsoul@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org A64 has 3 thermal sensors: 1 for CPU, 2 for GPU. Signed-off-by: Vasily Khoruzhick --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 27e48234f1c2..e6556c6d7777 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -49,6 +49,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -211,6 +212,29 @@ timer { (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu0_thermal: gpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + + gpu1_thermal: gpu1-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -485,6 +509,12 @@ mmc2: mmc@1c11000 { sid: eeprom@1c14000 { compatible = "allwinner,sun50i-a64-sid"; reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 0x6>; + }; }; crypto: crypto@1c15000 { @@ -810,6 +840,18 @@ codec: codec@1c22e00 { status = "disabled"; }; + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun50i-a64-ths"; + reg = <0x01c25000 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>;