From patchwork Wed Dec 18 20:21:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1758614B7 for ; Wed, 18 Dec 2019 20:22:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5FB024683 for ; Wed, 18 Dec 2019 20:22:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N398kDrO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727497AbfLRUWD (ORCPT ); Wed, 18 Dec 2019 15:22:03 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:39915 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbfLRUWD (ORCPT ); Wed, 18 Dec 2019 15:22:03 -0500 Received: by mail-lj1-f195.google.com with SMTP id l2so3593014lja.6; Wed, 18 Dec 2019 12:21:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zzCIXdQwIcQAOJLFhPbW0DH5W+5ZJ4BqJ3rHUds+O38=; b=N398kDrO2SqvRlUQShTiyJcFLpfcV18F4uaMLlhUc1WKa5cLelEkvdbTkR+eDQnVKr bBTK7htR1rqgzrFJJKy1AB+XlWMFqWqlK1HmYz/UvAwbTsbIVnEF6xV3P8HqMah5g0ZA zI8eB38r0MVNgzp9YoyCAFAlV6ekOX5xIQYwCSLyrOrM8X247NJsqXU/KH/kcPw4J6M5 7esGPJrLb4RZYs5eGIVrt9Omx4dmk5j86Qki/bjHwFBqgV9kaKyWEUwKe7M7gBaEY6P4 PADSPZwqExY7F40ZUFbTOMptnR1DH3N2yiGvy51GAS5lICxODZ/qFzsOVsucnGEG7nRJ 7rDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zzCIXdQwIcQAOJLFhPbW0DH5W+5ZJ4BqJ3rHUds+O38=; b=NgZfT1X0OIK2fNZmiJ1W/f0ZpyGwM8OIY9hI+kjE4mtGBl1hi4CNiFPJ1FqnEuglje F5gB8B8cAfsRjUumiNvqvzAGiqZZycmu6VpPKmv9N6pEhaQW8UkLSG36FxOjKbDkNIV5 nygADgw4n1Pq09goWyXz5KGjIOU2C2eNblKplZZVSW9kK2MmyXVIXAKeJBxXv6zrVRqD BJKnn6IyO9IDiIvnhQijD0SWp9d5m2XN8cO+H9bRkZiICWrCTkxjvNsMERsTMTHu69YB WWhEA1uMsHvUdgkmdNZT9zX/dykj71vl1OQxV9KPeLzunT6PYGskBU0Wrgm/FzEdEd1G HLDw== X-Gm-Message-State: APjAAAWKOG2tNhgF7/T9pXjuKl5320d5qPcCG4fTN/kRLV26xrfaCRpr NNE42ZraUCDWvt8QD93IS1E= X-Google-Smtp-Source: APXvYqy/1Je+6GY5LE5LTAW1Geb1np+H95GVhkeau65LsPmdk9w835BEzet7NP7005vFq9qka6qGHg== X-Received: by 2002:a2e:93c9:: with SMTP id p9mr3229011ljh.136.1576700518466; Wed, 18 Dec 2019 12:21:58 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:21:57 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 01/12] clk: tegra: Add custom CCLK implementation Date: Wed, 18 Dec 2019 23:21:31 +0300 Message-Id: <20191218202142.11717-2-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-super-cclk.c | 178 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 11 +- 3 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index df966ca06788..f04b490f5416 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -14,6 +14,7 @@ obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-super-cclk.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c new file mode 100644 index 000000000000..7bcb9e8d0860 --- /dev/null +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on clk-super.c + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Based on older tegra20-cpufreq driver by Colin Cross + * Copyright (C) 2010 Google, Inc. + * + * Author: Dmitry Osipenko + * Copyright (C) 2019 GRATE-DRIVER project + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLLP_INDEX 4 +#define PLLX_INDEX 8 + +#define SUPER_CDIV_ENB BIT(31) + +static u8 cclk_super_get_parent(struct clk_hw *hw) +{ + return tegra_clk_super_ops.get_parent(hw); +} + +static int cclk_super_set_parent(struct clk_hw *hw, u8 index) +{ + return tegra_clk_super_ops.set_parent(hw, index); +} + +static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); +} + +static unsigned long cclk_super_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + if (cclk_super_get_parent(hw) == PLLX_INDEX) + return parent_rate; + + return tegra_clk_super_ops.recalc_rate(hw, parent_rate); +} + +static int cclk_super_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *pllp_hw = clk_hw_get_parent_by_index(hw, PLLP_INDEX); + struct clk_hw *pllx_hw = clk_hw_get_parent_by_index(hw, PLLX_INDEX); + struct tegra_clk_super_mux *super = to_clk_super_mux(hw); + unsigned long pllp_rate; + long rate = req->rate; + + if (WARN_ON_ONCE(!pllp_hw || !pllx_hw)) + return -EINVAL; + + /* + * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. + * PLLX will be disabled in this case, saving some power. + */ + pllp_rate = clk_hw_get_rate(pllp_hw); + + if (rate <= pllp_rate) { + if (super->flags & TEGRA20_SUPER_CLK) + rate = pllp_rate; + else + rate = tegra_clk_super_ops.round_rate(hw, rate, + &pllp_rate); + + req->best_parent_rate = pllp_rate; + req->best_parent_hw = pllp_hw; + req->rate = rate; + } else { + rate = clk_hw_round_rate(pllx_hw, rate); + req->best_parent_rate = rate; + req->best_parent_hw = pllx_hw; + req->rate = rate; + } + + if (WARN_ON_ONCE(rate <= 0)) + return -EINVAL; + + return 0; +} + +static const struct clk_ops tegra_cclk_super_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .set_rate = cclk_super_set_rate, + .recalc_rate = cclk_super_recalc_rate, + .determine_rate = cclk_super_determine_rate, +}; + +static const struct clk_ops tegra_cclk_super_mux_ops = { + .get_parent = cclk_super_get_parent, + .set_parent = cclk_super_set_parent, + .determine_rate = cclk_super_determine_rate, +}; + +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock) +{ + struct tegra_clk_super_mux *super; + struct clk *clk; + struct clk_init_data init; + u32 val; + + super = kzalloc(sizeof(*super), GFP_KERNEL); + if (!super) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + super->reg = reg; + super->lock = lock; + super->width = 4; + super->flags = clk_super_flags; + super->hw.init = &init; + + if (super->flags & TEGRA20_SUPER_CLK) { + init.ops = &tegra_cclk_super_mux_ops; + } else { + init.ops = &tegra_cclk_super_ops; + + super->frac_div.reg = reg + 4; + super->frac_div.shift = 16; + super->frac_div.width = 8; + super->frac_div.frac_width = 1; + super->frac_div.lock = lock; + super->div_ops = &tegra_clk_frac_div_ops; + } + + /* + * Tegra30+ has the following CPUG clock topology: + * + * +---+ +-------+ +-+ +-+ +-+ + * PLLP+->+ +->+DIVIDER+->+0| +-------->+0| ------------->+0| + * | | +-------+ | | | +---+ | | | | | + * PLLC+->+MUX| | +->+ | S | | +->+ | +->+CPU + * ... | | | | | | K | | | | +-------+ | | + * PLLX+->+-->+------------>+1| +->+ I +->+1| +->+ DIV2 +->+1| + * +---+ +++ | P | +++ |SKIPPER| +++ + * ^ | P | ^ +-------+ ^ + * | | E | | | + * PLLX_SEL+--+ | R | | OVERHEAT+--+ + * +---+ | + * | + * SUPER_CDIV_ENB+--+ + * + * Tegra20 is similar, but simpler. It doesn't have the divider and + * thermal DIV2 skipper. + * + * At least for now we're not going to use clock-skipper, hence let's + * ensure that it is disabled. + */ + val = readl_relaxed(reg + 4); + val &= ~SUPER_CDIV_ENB; + writel_relaxed(val, reg + 4); + + clk = clk_register(NULL, &super->hw); + if (IS_ERR(clk)) + kfree(super); + + return clk; +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 416a6b09f6a3..ee35a847df08 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -729,8 +729,10 @@ struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates * that this is LP cluster clock. * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5 - * super mux parent using PLLP branches. To use PLLP branches to CPU, need - * to configure additional bit PLLP_OUT_CPU in the clock registers. + * super mux parent using PLLP branches. To use PLLP branches to CPU, need + * to configure additional bit PLLP_OUT_CPU in the clock registers. + * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super + * clocks, it only has a clock-skipper. */ struct tegra_clk_super_mux { struct clk_hw hw; @@ -748,6 +750,7 @@ struct tegra_clk_super_mux { #define TEGRA_DIVIDER_2 BIT(0) #define TEGRA210_CPU_CLK BIT(1) +#define TEGRA20_SUPER_CLK BIT(2) extern const struct clk_ops tegra_clk_super_ops; struct clk *tegra_clk_register_super_mux(const char *name, @@ -758,6 +761,10 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +struct clk *tegra_clk_register_super_cclk(const char *name, + const char * const *parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, u8 clk_super_flags, + spinlock_t *lock); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Wed Dec 18 20:21:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81D741580 for ; Wed, 18 Dec 2019 20:22:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 566372468C for ; Wed, 18 Dec 2019 20:22:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GfrU/U9d" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725818AbfLRUWD (ORCPT ); Wed, 18 Dec 2019 15:22:03 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:35714 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726591AbfLRUWC (ORCPT ); Wed, 18 Dec 2019 15:22:02 -0500 Received: by mail-lf1-f66.google.com with SMTP id 15so2659358lfr.2; Wed, 18 Dec 2019 12:22:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iX2kRwtJGZa5DimaLjPu5czm6QHLMvmyQt7c8wHvrWE=; b=GfrU/U9dPVZzvNwO2xBD+gfegB//ASxzS91iPz5GgqDLhCPhBCmyCzIcnCjW8B67PQ RkoeozJYPE+zZhD++4eWi4T53MLLzjkZ+ZUVWsdbygoeD1hrk2udzIW+l7RFQKFnsQIn 5uzqrD+vunswAkVkuAmf1oa9o/k1/O2LQIngoRITw4o2STizloawhh2aB5MoHVZhGu5i 8xg60tdhBN2e2cHIZ6fcQTNiyDyYKW1B/DTwhOiVpLPyAQlUOmsBpBDLBKAymrRyGuZ5 O4Y2ArPplqyhGqpd1zIQbyOokU1wooG2u9ihnn05khMT1hkSdyYwTOZjH/5ln6fACUzx v7Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iX2kRwtJGZa5DimaLjPu5czm6QHLMvmyQt7c8wHvrWE=; b=X/X5IGr/13f63S4I8QVa5nab9Ald4BIjOgp7GWuKlJcVFbxqTUfKQ6t2aMPb76515+ 5D3s4ODMtVBIYkFwf9l5OrDqlHICtrqN8xMj1rAfP0jrU7EfeLQ2+7WN61aBU7/8Shb1 m6NEjzPovX99wewTsclS7qoPC/1rsH91jSsPVVpISlUVsUOpxJGKbGg9eaUb1qnu5tpy sqQba0hBkR+Dl4tZPVAJLfkL/SiDD4YiT5vSr1PZppafdkg35FmUH6rBUojxrqRLYCnD Wm/ChNAxUR9dwi7gyCyba9KFQ/Z6LZ+AQNJ7v5PUDX7qn1MrpGCrPONaxkZAj4+vSbjB lrSw== X-Gm-Message-State: APjAAAUGAScaILghMuKvwdkmpjAuGcdm54QC+cIROkMLoMEUUhfzN7PL 9pqPmwDpqD5XwORwfox9kZ0= X-Google-Smtp-Source: APXvYqz05YVya38CeJOEAWsYmfAyaPnBWbuOwbOAWLyvHuIWZYjLrkprTsJcPZ5sSuDfSVremoFfPQ== X-Received: by 2002:a19:784:: with SMTP id 126mr2905428lfh.191.1576700519561; Wed, 18 Dec 2019 12:21:59 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:21:59 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 02/12] clk: tegra: pll: Add pre/post rate-change hooks Date: Wed, 18 Dec 2019 23:21:32 +0300 Message-Id: <20191218202142.11717-3-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 12 +++++++++++- drivers/clk/tegra/clk.h | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 531c2b3d814e..0b212cf2e794 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, state = clk_pll_is_enabled(hw); + if (state && pll->params->pre_rate_change) { + ret = pll->params->pre_rate_change(); + if (WARN_ON(ret)) + return ret; + } + _get_pll_mnp(pll, &old_cfg); if (state && pll->params->defaults_set && pll->params->dyn_ramp && (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { ret = pll->params->dyn_ramp(pll, cfg); if (!ret) - return 0; + goto done; } if (state) { @@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, pll_clk_start_ss(pll); } +done: + if (state && pll->params->post_rate_change) + pll->params->post_rate_change(); + return ret; } diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index ee35a847df08..fa18bef914af 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -266,6 +266,10 @@ struct tegra_clk_pll; * disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. + * @pre_rate_change: Callback which is invoked just before changing + * PLL's rate. + * @post_rate_change: Callback which is invoked right after changing + * PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -342,6 +346,8 @@ struct tegra_clk_pll_params { void (*set_defaults)(struct tegra_clk_pll *pll); int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg); + int (*pre_rate_change)(void); + void (*post_rate_change)(void); }; #define TEGRA_PLL_USE_LOCK BIT(0) From patchwork Wed Dec 18 20:21:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 72BA214B7 for ; Wed, 18 Dec 2019 20:22:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 517872467B for ; Wed, 18 Dec 2019 20:22:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TIMpJQye" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726594AbfLRUWs (ORCPT ); Wed, 18 Dec 2019 15:22:48 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:40097 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726454AbfLRUWD (ORCPT ); Wed, 18 Dec 2019 15:22:03 -0500 Received: by mail-lj1-f196.google.com with SMTP id u1so3589240ljk.7; Wed, 18 Dec 2019 12:22:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imexZFgDzWkCRbfUn+5A59UpWIAqIcg+AW4OI+O1fRc=; b=TIMpJQye0ghIU07cqIGBCHU9joO+b4fNoaBaOScbkcPvKoP2nynCfJeM14cZr5usf7 FtgnfOziX8i8ndnKhQC2s18IGAKHF1OhywYSh/+DAgXDBoeFTPGDpMR6HqWLrETaWLmR Xvd9Am1YDafhT49OqEz6XrLf5y1XsMM+VlGDmSaZeQHI65r//55i4qk+EkODQ/2yzSYk 1nhn9sAozV/twreFEdzjbFAyt0iKOMs4R7+DzhCFci5DRXiUfqPKNmxHNVniS0VMkR3w v14SDEH0HBLk+QmdyjiYKHEBvrNkFHw2hIMpGYy7P7mGv07RzVBaFNOx+BRuQn5FGphH SERQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=imexZFgDzWkCRbfUn+5A59UpWIAqIcg+AW4OI+O1fRc=; b=Gn9jTVgjiq6kZF1oQ8TZIJFqLcY0fn1+xI/qnKQeTn1AwuwkSqqQ4F6IArWg750tzR v7FvgXN4yNYnpeCnB4Z/3fyXM5cnGAnkpipF+j3quy+JWgpWeGsupwAmymcY53iXUP5v AW9dPl1yY6qMyUVTWr8zerdZ7Yb9TArRbd+VmnkDHz3xAj24NHY7JTtbfS8mv2MkcoEN gENSVEbFm70lerTnBgLv7w8CuZeuVB2McDC/J5B+f6W1Bg+hA44wJHN2Isbr7ZIRxs2O 0JKNrFNVHsw93aZ/0F5AHI5FPUCSfgMYrel/wSqyTT1hhrvTJPxSdTU03wOj4jTcaadO ZE6w== X-Gm-Message-State: APjAAAVfztfEejpSbgNW8MURTaDU9+1fxhbrbAcXgRvlK03+SUKx/mXw LOwnRnhw6rs92r3AhQMUk7E= X-Google-Smtp-Source: APXvYqwSKSW1uHgvLkGSyLaIihjHFbQY/XiYwGvAbXPZ9q8lzZffRW7lrZtSTiaIpKHK9WTyyk1tBg== X-Received: by 2002:a05:651c:118b:: with SMTP id w11mr3286732ljo.54.1576700520622; Wed, 18 Dec 2019 12:22:00 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:00 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 03/12] clk: tegra: cclk: Add helpers for handling PLLX rate changes Date: Wed, 18 Dec 2019 23:21:33 +0300 Message-Id: <20191218202142.11717-4-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 7bcb9e8d0860..a03119c30456 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,9 @@ #define SUPER_CDIV_ENB BIT(31) +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; + static u8 cclk_super_get_parent(struct clk_hw *hw) { return tegra_clk_super_ops.get_parent(hw); @@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, struct clk_init_data init; u32 val; + if (WARN_ON(cclk_super)) + return ERR_PTR(-EBUSY); + super = kzalloc(sizeof(*super), GFP_KERNEL); if (!super) return ERR_PTR(-ENOMEM); @@ -173,6 +179,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk = clk_register(NULL, &super->hw); if (IS_ERR(clk)) kfree(super); + else + cclk_super = super; return clk; } + +int tegra_cclk_pre_pllx_rate_change(void) +{ + if (IS_ERR_OR_NULL(cclk_super)) + return -EINVAL; + + if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX) + cclk_on_pllx = true; + else + cclk_on_pllx = false; + + /* + * CPU needs to be temporarily re-parented away from PLLX if PLLX + * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. + */ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX); + + return 0; +} + +void tegra_cclk_post_pllx_rate_change(void) +{ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fa18bef914af..0afe28f4372b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change(void); +void tegra_cclk_post_pllx_rate_change(void); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC From patchwork Wed Dec 18 20:21:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6AC451580 for ; Wed, 18 Dec 2019 20:22:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46F992465E for ; Wed, 18 Dec 2019 20:22:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CwgrWCCr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727576AbfLRUWj (ORCPT ); Wed, 18 Dec 2019 15:22:39 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:42430 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727403AbfLRUWE (ORCPT ); Wed, 18 Dec 2019 15:22:04 -0500 Received: by mail-lf1-f65.google.com with SMTP id y19so2622253lfl.9; Wed, 18 Dec 2019 12:22:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7KjPx1Wv5d8ZDM6UbOjJE0HvBiQeI+lxOPx3jO6nNXM=; b=CwgrWCCrkPxE4vnzsp5eWX0DlCVDkLzDuqtnbH2asE+7qHf4W8TzdZsfKohMWs89ec wPbK4Vd6qU9O0Szlvwe+v6452qD092tx6g8wI5EfmtRG1iDYebX7pbwb0RKXu2jWExmH sco++uaWLi3rSth627xF0mjNXsjjtnqEfVF4mc1IRpoKZB2nRtf1qLmp1XBF792rjnxA Y4u2D5AJZRWqFKwftNMy/bClxJQIaB3IEWSV5CyfruA0UAcgbwg97Cq9m9aZuuCLWFdM R72VKMVkiwoUntiDsuKC/UoPuxCRUMfnGmHtEo25U3zsmGs9St+GW/cvMTLcwxjmJ5eB vgXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7KjPx1Wv5d8ZDM6UbOjJE0HvBiQeI+lxOPx3jO6nNXM=; b=lUJKGP99mrxCkO57cy4Nf4zTwLNuYEPXnQJyZ+LWYI4a6ywOhizeSym4gg/HLOIWHQ b7aGIhXtmo3CcYpx9uRAvng8RyHxBOUMrz/OjFSwlE82ACMmXxD0H+tIFUsYKuyoD49M n3Glv19cbNb/48qrY5lVJ34O/ZPJS2W8b+pwqRn9ty8EsSEvRBvZJ6zsX7c/k5iHknJ0 Fsxuh/liVPXbbzw0Mk05/YAy4xVRVKpkdCuSoxnklFNI23Sg2aewWpzj0/7/7/yKPjiq JL35KBA8I4S+8IXBaRstCT1PP/ZesjrAdSMPR9E0WQWSR+p2yv/SRddBcofwlk1EZZJF rCHA== X-Gm-Message-State: APjAAAU717hH8N6pgM52wbN783EfyQKvKxOqKVOjyFznsZRQwFtG1G/L o4mnlr9740xI9Muhyj2uzGE= X-Google-Smtp-Source: APXvYqx4EaLXUxYnR5mzvQOrJkLC3E8upu+/JNFLZqza1KliT7qDQlT3QRhiE73+iiCu7XfTBKyNdQ== X-Received: by 2002:ac2:4946:: with SMTP id o6mr2987807lfi.170.1576700521780; Wed, 18 Dec 2019 12:22:01 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:01 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 04/12] clk: tegra20: Use custom CCLK implementation Date: Wed, 18 Dec 2019 23:21:34 +0300 Message-Id: <20191218202142.11717-5-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 4d8222f5c638..eb821666ca61 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params = { @@ -704,9 +706,10 @@ static void tegra20_super_clk_init(void) struct clk *clk; /* CCLK */ - clk = tegra_clk_register_super_mux("cclk", cclk_parents, + clk = tegra_clk_register_super_cclk("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, - clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, + NULL); clks[TEGRA20_CLK_CCLK] = clk; /* SCLK */ From patchwork Wed Dec 18 20:21:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C07A21580 for ; Wed, 18 Dec 2019 20:22:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9E55B21582 for ; Wed, 18 Dec 2019 20:22:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mDe6ldyN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725955AbfLRUWF (ORCPT ); Wed, 18 Dec 2019 15:22:05 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:38080 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727495AbfLRUWF (ORCPT ); Wed, 18 Dec 2019 15:22:05 -0500 Received: by mail-lf1-f68.google.com with SMTP id r14so2638963lfm.5; Wed, 18 Dec 2019 12:22:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bMs+lSRV0i1HSQ3p/ltut5IB/OSBXwDLX74KO1dTGWY=; b=mDe6ldyN4hmYq3D927ONzNjoBO1W3jOj5hYLATMVKxKxJObYmc56/Qrz3++NA6YpYJ nnsECK3ppHOfNMaCGbe0Zz7WXGY23dPtq5zSSr4biEoqt217dENwOeUMQphhWlER1x+t QpdDEFPMzl0uGp1D0+w/5sSYbM0OMHESBwuz9k8BCm4zdLaBicvubV+ZDZqeXqZKZVa6 n9JzwhIGtdEzF4qeV7648Dr3juegCTdACJN/UKWV6yqM2S7H7bemiwXzGTlCAME2NWHV Xb4httOLph8A5DUmwfw38hkfeON5/82AxEP/4ofOF3WLPgYKCNnXIrHiLDFGJV187n1r VjWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bMs+lSRV0i1HSQ3p/ltut5IB/OSBXwDLX74KO1dTGWY=; b=n6IH7yn1IcdEH0xTDIStREAAVFIBY004K3+7tubSTlv+zgUjYxfX3OR+8n4kQJtWae GbFGSHDx4aDGMLALIUjmI3X9m4UsBeowNf5CvD/huwKKg25nTa/iLgcxXh1KtVxaa1nj DTI0dw7C+zQ/XpSeb6u0fuKCKdF8A8wVN4+Rll3TgVOtyaqetGoYzmWoAOlI9OZ0e9Qu fm3mSQrfW+oPb7irsg82bjHQlrt4F1Fo3cyUw/oXiEGRF8Fu2R3VUVDDfgWMDSxPz6CS DsLHoorDp7U/hQhbLYgd1+jWUmJrfNy4Ocpu3yQhVv/7Lcpnb5uF+522ctKakqHmfhH7 440w== X-Gm-Message-State: APjAAAWx4r0TxcG2QODgV1r6JWegFVGUtSbsHXq+QFwA/U7H6e+IveZs FjFSBZh4dGwGY7iqYxmop+I= X-Google-Smtp-Source: APXvYqyvx8mSEOPrPIxmtyyllhYTF8IDDPTSjcpse+kxz+ZT+ZiPI/q3j6LWY6NgIEtzPvGn69dnlg== X-Received: by 2002:a19:710a:: with SMTP id m10mr2962379lfc.58.1576700522931; Wed, 18 Dec 2019 12:22:02 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:02 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 05/12] clk: tegra30: Use custom CCLK implementation Date: Wed, 18 Dec 2019 23:21:35 +0300 Message-Id: <20191218202142.11717-6-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index c8bc18e4d7e5..0fe03d69fe1a 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params __ro_after_init = { @@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void) clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); /* CCLKG */ - clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, + clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, ARRAY_SIZE(cclk_g_parents), CLK_SET_RATE_PARENT, clk_base + CCLKG_BURST_POLICY, - 0, 4, 0, 0, NULL); + 0, NULL); clks[TEGRA30_CLK_CCLK_G] = clk; /* From patchwork Wed Dec 18 20:21:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301893 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 029621580 for ; Wed, 18 Dec 2019 20:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D4F022467E for ; Wed, 18 Dec 2019 20:22:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pRKki1GK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbfLRUWH (ORCPT ); Wed, 18 Dec 2019 15:22:07 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:40102 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727548AbfLRUWG (ORCPT ); Wed, 18 Dec 2019 15:22:06 -0500 Received: by mail-lj1-f196.google.com with SMTP id u1so3589406ljk.7; Wed, 18 Dec 2019 12:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K5HlnYJPIwYxVleWdO7CO0bzUDmsMGuP+g11IVxSh3M=; b=pRKki1GKBPSMKIMwHJNJbUOoTSffcGV4/u8nAIW+KUeM33SlEpfxBX6VajkI5oDkIR r0SFc9gntwgx7UMhHyTODk2tWI+on/Zrp2j2SNFUlmYAfeWwec2DsA4j0DzY7A0tW9+f qI27MUM5oiSHkpKHQ83cMy2xAZdgBWxKKCk7WParmOy9z/INZEUsEVcun9A/tIFEvb6k Nz5H8QSlMmzubj4RmCIJiQBvCsnkwqq65DLEdDTrLM3KrSCfU2QoxCVZu00z4c2cwK4j eXR5UOB9drDVFHkEAXCe6i0zQjbIqMLE4lT1rYMavyPLKJcCsWWZBjMrKg54ztbN6dY1 q8Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K5HlnYJPIwYxVleWdO7CO0bzUDmsMGuP+g11IVxSh3M=; b=O+xAWCwHNVThr0HtWPvaZUplT02rFYEwfvZOf3YfoVVM/sxfVCGsHvRL+fiSSCXuSr KBQllEkKsbbZli/h34LhllHBi71bb70JP878nuXdL9QjOBj62k5SZpDjFAqCRX9kTqN2 IGVp12moDB+uxW1ZWqRJEsuhzQ01nUrGdayFfnf6FTd2SqL+s9QuhmiHEzL8NV8t7rd4 t/DneaZJHwND+WWSQcNTaLsXs/JECfJkWPiIl/uUWl0Y5rmBfAFX6a+z9wMKDbfr675i 4eb+Ptir1CA8rNVVxLTdmFZ9sHIpB7yf2HJatUJ8EKph4FCV8OprSsMU2PZyTbn2txf8 N7BA== X-Gm-Message-State: APjAAAV7bAbiwZdxb6Z8STzZkm+N4e2z/0n/3eYjXZCogVw9X5BOX9kW DBASaztC1mABmUInfqKAwhY= X-Google-Smtp-Source: APXvYqwQRyeToKP+ODMia48YTGwgR/XlDVi8uJnRU1eq9o72QRChD98WM/TUp0eK6iJbQd3HU/0OZg== X-Received: by 2002:a2e:9e03:: with SMTP id e3mr3258522ljk.186.1576700524025; Wed, 18 Dec 2019 12:22:04 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:03 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 06/12] ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 Date: Wed, 18 Dec 2019 23:21:36 +0300 Message-Id: <20191218202142.11717-7-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX should be simply disabled if CPU enters into suspend running off some other PLL (the case if CPUFREQ driver is active). The actual burst policy is restored by the clock drivers. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/sleep-tegra30.S | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 3341a12bbb9c..9a20c93abe48 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -383,11 +383,8 @@ _pll_m_c_x_done: ldr r4, [r5, #0x1C] @ restore SCLK_BURST str r4, [r0, #CLK_RESET_SCLK_BURST] - cmp r10, #TEGRA30 - movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX - movteq r4, #:upper16:((1 << 28) | (0x8)) - movwne r4, #:lower16:((1 << 28) | (0xe)) - movtne r4, #:upper16:((1 << 28) | (0xe)) + movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP + movt r4, #:upper16:((1 << 28) | (0x4)) str r4, [r0, #CLK_RESET_CCLK_BURST] /* Restore pad power state to normal */ From patchwork Wed Dec 18 20:21:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301897 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B97F11580 for ; Wed, 18 Dec 2019 20:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 976FC24672 for ; Wed, 18 Dec 2019 20:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PNJZuPEz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726463AbfLRUWc (ORCPT ); Wed, 18 Dec 2019 15:22:32 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:46871 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727576AbfLRUWH (ORCPT ); Wed, 18 Dec 2019 15:22:07 -0500 Received: by mail-lf1-f66.google.com with SMTP id f15so2606052lfl.13; Wed, 18 Dec 2019 12:22:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JOvh1jiKDepC3yJC5nY3q65+eBnyGCERyjo984OFVEE=; b=PNJZuPEz2g/6rZevWNKJRoOXVwhYsAWGbX3DcjYbUt1JI3gTqN1W8HDFJMFQZFh+Xz Xvpx5N4a9p2nb0+Tf780ZuZzUeu7GU14ZzC/1vpkshZRCbGI3LmNl97NcanZlkF7fKmf DLv/q0s+enln1FsK/lxadSasOLBW/PRQfEdyqBZbRGUSFHs0Ei8GaVOZdFg7gVIPtXFe 9zFKr4V5qWC9annujvm0ZFY4InP68coqA7/dBUQJMtQmghQl7mGT+CpqZ7XQ3wRLrzfE FPHzLRKtj8LmvNNfE9NsVmiPggyrShtdaUzWCWh7XojI/s5goKLI+TlAZ6VR31R80Pet uN7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JOvh1jiKDepC3yJC5nY3q65+eBnyGCERyjo984OFVEE=; b=dToWB2PQkPPnqBJ4hLUTI9bX+newX5fnyrrkLPBEZlf3IHCa9CQLuv2f9BVJl1rnJS /nQzoyRqQ4/2e01dgQsZ+CfbXk4pwmGkrnYEtTt3I0rLdmCnJq6gilVRWMghTIJlfqtn BjbAsN9iMXNeeJVhzvEoiDDEF/0K9l/fXkwjZ1Z1BTldd3nxWEjbZJiEIy8eRvncytas zz+MCJusr087uButrhbjjvF2gRcWzVgtFh8pTNfj8G+T6Oa6Aa0PUNftWAs+NsFSEWgS 4mskanpNRPoTZJAzv/+D04u6M+sFg++RiNlsNE5fPbZUgqdghvYm03VcaJkUwJ9MgUiN cJUg== X-Gm-Message-State: APjAAAVTSZK7xlA+0Zh4ZclUx5q8uOdvVzwsBU1qIHlj7ctra5NJydeC lPhTZUW+SN/H8SgVDnoQ0xw= X-Google-Smtp-Source: APXvYqywGSO74/vMKn0pZYHkm86dgV5cIW701c5aIJUh139oXzIl20t8c1aGR9jBM4nNfXjCEVuxpg== X-Received: by 2002:ac2:5e9b:: with SMTP id b27mr2998954lfq.147.1576700525243; Wed, 18 Dec 2019 12:22:05 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:04 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 07/12] ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 Date: Wed, 18 Dec 2019 23:21:37 +0300 Message-Id: <20191218202142.11717-8-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org PLLX may be kept disabled if cpufreq driver selects some other clock for CPU. In that case PLLX will be disabled later in the resume path by the CLK driver, which also can enable PLLX if necessary by itself. Thus there is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do not manage PLLX on resume and thus they are left untouched by this patch. Signed-off-by: Dmitry Osipenko Tested-by: Marcel Ziswiler --- arch/arm/mach-tegra/sleep-tegra30.S | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 9a20c93abe48..4f073869b8ac 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -358,7 +358,6 @@ _no_pll_iddq_exit: pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC - pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC _pll_m_c_x_done: pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC @@ -368,8 +367,18 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLP_BASE pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE + + /* + * CPUFreq driver could select other PLL for CPU. PLLX will be + * enabled by the Tegra30 CLK driver on an as-needed basis, see + * tegra30_cpu_clock_resume(). + */ + cmp r10, #TEGRA30 + beq _pll_m_c_x_locked + pll_locked r1, r0, CLK_RESET_PLLX_BASE +_pll_m_c_x_locked: mov32 r7, TEGRA_TMRUS_BASE ldr r1, [r7] add r1, r1, #LOCK_DELAY From patchwork Wed Dec 18 20:21:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3C251580 for ; Wed, 18 Dec 2019 20:22:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C236A24683 for ; Wed, 18 Dec 2019 20:22:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dZCt5akt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727673AbfLRUWJ (ORCPT ); Wed, 18 Dec 2019 15:22:09 -0500 Received: from mail-lj1-f194.google.com ([209.85.208.194]:44266 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727608AbfLRUWI (ORCPT ); Wed, 18 Dec 2019 15:22:08 -0500 Received: by mail-lj1-f194.google.com with SMTP id u71so3580412lje.11; Wed, 18 Dec 2019 12:22:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+VS0hDmeQXhAmkJq5950YTYXxFjVBKr1yL5L6K4MJW0=; b=dZCt5akt7NinmUFRtXOZGeL/jOKHueYlmrvy/OFIdrr86GFypQeWBMhzZrI4jwblZN SjqSDlxAeVSt4svEQUEw2abFZNyWvvuRuM/uqsT8TmYPhk9Ja1qo082OqPzX5+7pSayh A6luVAzQHn7+YGvnhgSTpGefy5BR58c6oxnZbW+VTXLrNKXfsN+GeGiSJbTkecs9na/M QanZOpQZuxmPQSZFTtERhHU7R5a/ewS87w9WYKRgguFwg6MQj3DTkFQwKF1YRCCpQ1qZ 2P+o1XZt7XlK0xpqbLmFqNup9YUxfAgQVqa/8Vo2qyoH59L5cmNZu2ATQ1Uvwo0+R7n0 HwOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+VS0hDmeQXhAmkJq5950YTYXxFjVBKr1yL5L6K4MJW0=; b=r5pwX2A63rKY1AdEFRErOEjFy0E5O/5BhY4S3Sdd+CAGeH47D4qgbdS5c5AMTpmB5o x6gvPp0YaFjvvqC66biTJn2WEassKeWmPFMt9JQqsCpn386W/EjrbBhJpLi4NbqWVXfn Tu7zBgrxlQ7ixcssJ+OYGYdoW4f9hLbJ7yS1IdNy0TT9g7PX0mCDTvOEAD5zBq4e0LrO fbHFWpV3O3K0nSgHqah3gXj8afM8hIH7F4rFilxGNiyu7J9WnGCNi3DohVIBQ8xEErcl /blGU3yJCzNDS1VTf/+jPE0X36iZIOxbn4M6TbiGSXDqjXHUHxrqsYVN+K4muPCcqrMA 9FNg== X-Gm-Message-State: APjAAAVbPkBrHvVT8Z9ravQYF9dOJ4j5WyQuMsRfPh2p8Akm6Ymlzf1I 6RXkYmVboDj+x/Qbq6V+Q84= X-Google-Smtp-Source: APXvYqyVuPEDqaRNv4qy6csyA6tsC1q5PJjWvsjVl55QFxJFUDzWy1MB0OAvj8xoTA9d/xNjHrIvRQ== X-Received: by 2002:a2e:9ad1:: with SMTP id p17mr3297973ljj.26.1576700526408; Wed, 18 Dec 2019 12:22:06 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:05 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 08/12] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Wed, 18 Dec 2019 23:21:38 +0300 Message-Id: <20191218202142.11717-9-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs. Acked-by: Viresh Kumar Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..daeca6ae6b76 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + }; From patchwork Wed Dec 18 20:21:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DD0514B7 for ; Wed, 18 Dec 2019 20:22:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47A2B2467E for ; Wed, 18 Dec 2019 20:22:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sk0HpviX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727696AbfLRUWM (ORCPT ); Wed, 18 Dec 2019 15:22:12 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:42437 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727665AbfLRUWL (ORCPT ); Wed, 18 Dec 2019 15:22:11 -0500 Received: by mail-lf1-f66.google.com with SMTP id y19so2622458lfl.9; Wed, 18 Dec 2019 12:22:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/zogdKqCHRKbZRyU/zHsA5/9yMZ209QgvglsU6ytzYI=; b=sk0HpviXZ/bb/QXY6Cmvi2H339mGSsnRwZhZKucw8IDojSpRb1kHkz3OtjJzNqKfdN hc7sHJRuDNGDXxE8yxcnurdYMTqtt5ztp+HcvQtwvMaBrK7aEcPX9wBjeAmhPQ2hxLk/ w/BqHKFJ8+jPc4CHb3ucytdV++U+dX83srY6WHc6zbsLfthgPyX/21VIW0I2wrn4QtNv ZexAN/eEkDBQWPgAfGKjyicROTGO9lC4CkbEchSh2uUyh0MlUX9Dvc1e3Miip7vbtgIu 6snJKssXEqpQxd3h4+z4v61gIya2QOtwvBTN1RPu7vW5rASG0+nleaE7Pp47vG8GJPqZ Lo7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/zogdKqCHRKbZRyU/zHsA5/9yMZ209QgvglsU6ytzYI=; b=sx2oHIJgtKxAjc6RgnPpHyaQsKkBBfD+rGxP8TsS5V9pfn0erYSTM2AA9hVNPVsjtS y2IUuWsFyg4HMeENA+L9btgoc+EdlpCa4yVFA7g24rX2xnbcDrllYOmOAowTxZiHxlor xmcAM8tROyPy4Ld1AU5f8bpo4SSmcHxwhn5Gu7GEyfQd8jH4gJdFqIF3Tnq+thWAXZtj Ozy0SQOW3Nx9m5aEusBHls/j4IYYcPQIG2oAs5tCdaQP2r1Wfm1mJHPeSiwzqcAC500j 9kr0GCQIHrWwFSLX/+5kaQC0kOHwtE8x16Gp88Rp6ytPHYGm4R3o6OzU5/F74aT8aOwo XNdg== X-Gm-Message-State: APjAAAWnAjBNw5LxE44FGrwwZJyv3xwikDGMJGntfJhSg5kMYmxGXUMP iDI9VR+rGuuVe+5fshIw2eg= X-Google-Smtp-Source: APXvYqzEDwgoc6KoeJF8J0eJmzBTMW7964AbpE8V0zAFmykCi6R6zbAv2ROZ6Jmk2UOzpEJIzXxKgA== X-Received: by 2002:a19:2d0d:: with SMTP id k13mr2966423lfj.12.1576700527756; Wed, 18 Dec 2019 12:22:07 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:07 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 09/12] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Date: Wed, 18 Dec 2019 23:21:39 +0300 Message-Id: <20191218202142.11717-10-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Re-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees. Acked-by: Viresh Kumar Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/tegra20-cpufreq.c | 217 ++++++++---------------------- 2 files changed, 59 insertions(+), 164 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 3858d86cf409..92a6a5089979 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ default y config ARM_TEGRA20_CPUFREQ - tristate "Tegra20 CPUFreq support" - depends on ARCH_TEGRA + tristate "Tegra20/30 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help - This adds the CPUFreq driver support for Tegra20 SOCs. + This adds the CPUFreq driver support for Tegra20/30 SOCs. config ARM_TEGRA124_CPUFREQ bool "Tegra124 CPUFreq support" diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index f84ecd22f488..8c893043953e 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -7,201 +7,96 @@ * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation */ -#include -#include +#include +#include #include #include #include +#include #include +#include #include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; - -struct tegra20_cpufreq { - struct device *dev; - struct cpufreq_driver driver; - struct clk *cpu_clk; - struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; -}; +#include +#include -static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, - unsigned int index) +static bool cpu0_node_has_opp_v2_prop(void) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - - /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq - */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) - return 0; - - return ifreq; -} + struct device_node *np = of_cpu_device_node_get(0); + bool ret = false; -static int tegra_target_intermediate(struct cpufreq_policy *policy, - unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; - - /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. - */ - clk_prepare_enable(cpufreq->pll_x_clk); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) - clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + if (of_get_property(np, "operating-points-v2", NULL)) + ret = true; + of_node_put(np); return ret; } -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; - int ret; - - /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. - */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ - if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); - - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); - - /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. - */ - if (cpufreq->pll_x_prepared) { - clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; - } - - return ret; -} - -static int tegra_cpu_init(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_prepare_enable(cpufreq->cpu_clk); - - /* FIXME: what's the actual transition time? */ - cpufreq_generic_init(policy, freq_table, 300 * 1000); - policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; - return 0; -} - -static int tegra_cpu_exit(struct cpufreq_policy *policy) -{ - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - - clk_disable_unprepare(cpufreq->cpu_clk); - return 0; -} - static int tegra20_cpufreq_probe(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq; + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; + struct device *cpu_dev; + u32 versions[2]; int err; - cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); - if (!cpufreq) - return -ENOMEM; + if (!cpu0_node_has_opp_v2_prop()) { + dev_err(&pdev->dev, "operating points not found\n"); + dev_err(&pdev->dev, "please update your device tree\n"); + return -ENODEV; + } + + if (of_machine_is_compatible("nvidia,tegra20")) { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.soc_speedo_id); + } else { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.cpu_speedo_id); + } + + dev_info(&pdev->dev, "hardware version 0x%x 0x%x\n", + versions[0], versions[1]); - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + cpu_dev = get_cpu_device(0); + if (WARN_ON(!cpu_dev)) + return -ENODEV; - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); - if (IS_ERR(cpufreq->pll_x_clk)) { - err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + opp_table = dev_pm_opp_set_supported_hw(cpu_dev, versions, 2); + err = PTR_ERR_OR_ZERO(opp_table); + if (err) { + dev_err(&pdev->dev, "failed to set supported hw: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + cpufreq_dt = platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + err = PTR_ERR_OR_ZERO(cpufreq_dt); + if (err) { + dev_err(&pdev->dev, + "failed to create cpufreq-dt device: %d\n", err); + goto err_put_supported_hw; } - cpufreq->dev = &pdev->dev; - cpufreq->driver.get = cpufreq_generic_get; - cpufreq->driver.attr = cpufreq_generic_attr; - cpufreq->driver.init = tegra_cpu_init; - cpufreq->driver.exit = tegra_cpu_exit; - cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; - cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; - cpufreq->driver.suspend = cpufreq_generic_suspend; - cpufreq->driver.driver_data = cpufreq; - cpufreq->driver.target_index = tegra_target; - cpufreq->driver.get_intermediate = tegra_get_intermediate; - cpufreq->driver.target_intermediate = tegra_target_intermediate; - snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra"); - - err = cpufreq_register_driver(&cpufreq->driver); - if (err) - goto put_pll_p; - - platform_set_drvdata(pdev, cpufreq); + platform_set_drvdata(pdev, cpufreq_dt); return 0; -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); +err_put_supported_hw: + dev_pm_opp_put_supported_hw(opp_table); return err; } static int tegra20_cpufreq_remove(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev); + struct platform_device *cpufreq_dt; + struct opp_table *opp_table; - cpufreq_unregister_driver(&cpufreq->driver); + cpufreq_dt = platform_get_drvdata(pdev); + platform_device_unregister(cpufreq_dt); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); + opp_table = dev_pm_opp_get_opp_table(get_cpu_device(0)); + dev_pm_opp_put_supported_hw(opp_table); + dev_pm_opp_put_opp_table(opp_table); return 0; } From patchwork Wed Dec 18 20:21:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB72B14B7 for ; Wed, 18 Dec 2019 20:22:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A986324682 for ; Wed, 18 Dec 2019 20:22:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NKW5BRmT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727688AbfLRUWM (ORCPT ); Wed, 18 Dec 2019 15:22:12 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:42269 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727548AbfLRUWL (ORCPT ); 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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:08 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 10/12] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Date: Wed, 18 Dec 2019 23:21:40 +0300 Message-Id: <20191218202142.11717-11-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index e512e606eabd..1e3b85923ca3 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -95,6 +95,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Wed Dec 18 20:21:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301879 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD7FF17EF for ; Wed, 18 Dec 2019 20:22:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B260A24682 for ; Wed, 18 Dec 2019 20:22:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jB3OuaCF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727730AbfLRUWV (ORCPT ); Wed, 18 Dec 2019 15:22:21 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:43276 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727682AbfLRUWM (ORCPT ); Wed, 18 Dec 2019 15:22:12 -0500 Received: by mail-lj1-f195.google.com with SMTP id a13so3583619ljm.10; Wed, 18 Dec 2019 12:22:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xq9tBk/6KoDVPMtQ/rhYvGgBAgv98Cu3SgI5vW4OCek=; b=jB3OuaCFCK5Ifk236GYC+fbvPOyNs8iGFfyx3NlzXicqkbNjIsW/RMg/V4BhoBRdeg wQMERb+UWWUuHf3ZAwW3svLD6dz3MV9Aoq3uQlRiUV02R26ionnNDFvIAuUkjKrDXLJM Xcx8bCfYuvIccOMQmYc3imSHZAkryPeAWAJcmmiKed3frWXcDCb0ZuWStA7yyAIR1cAD Hbe8MQiWTmB9eQfMp6jpyskMnl7Vn06hbsHifxzvbIwgQBu/t3cuT2skcZMVsEyx6jLc KRyeRBRDlj58q6Twodi8IQbVo9HDKFKeoB4O9Tp9DNQrRXbpb/VMqnjYvLgmS85Pj6Pd yuVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xq9tBk/6KoDVPMtQ/rhYvGgBAgv98Cu3SgI5vW4OCek=; b=AslLAIg7VatqJ1Xq+6gOT25xUK6vrW55QsfAjwYNyH6boioOF9Ucu0dHOYmUDy1Gff UhKI+SkZ4iDrx23Wr+AdhDZyMVExcMP7EdyE3WlgzHQ1ewdCRlRzQjyyj83TNKFDrlrw 4Kxl6Yt/6VqoOL3rE3VmA2kOUxOOSP9M8UV8adXYO+nQlMHylQpZQoYXtgOWIWpfCC9P BgREoTAXVlc7/o15nUDpcQSmGHSb0a3/55v/5wee0RM52gVqKo0jc+XHgi4k+kZYyi/o kpFwoSPRepY5eZ2ae0CThIJxBYSeQ0j30g5ToSbj5DzdMXsVk2w2Xwfvj+tmC75ZOgsK zqPA== X-Gm-Message-State: APjAAAXADa+R7D+IJ6PKgy2UpHbXv9Sn9A74jbYM4S6ghr0cBE55uG9U Xdi3jOF40DYcsXSncVnC2M8= X-Google-Smtp-Source: APXvYqzOJNV0yRI5YX/93LUSa2Vp+PjxX/hUPns3o/zSB+Md7fjo0zKesJXLYhC0ISfd5UHRllhb6g== X-Received: by 2002:a2e:9d85:: with SMTP id c5mr3290070ljj.51.1576700529912; Wed, 18 Dec 2019 12:22:09 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:09 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 11/12] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Date: Wed, 18 Dec 2019 23:21:41 +0300 Message-Id: <20191218202142.11717-12-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Set min/max voltage and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a3b0f3555cd2..6ebb3105af9e 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,9 +1806,14 @@ vdd2_reg: vdd2 { vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1873,22 @@ ldo8_reg: ldo8 { }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; From patchwork Wed Dec 18 20:21:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11301877 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A8BF81892 for ; Wed, 18 Dec 2019 20:22:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 86BE324682 for ; Wed, 18 Dec 2019 20:22:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kHuQP2LH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727727AbfLRUWU (ORCPT ); Wed, 18 Dec 2019 15:22:20 -0500 Received: from mail-lf1-f65.google.com ([209.85.167.65]:45524 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727685AbfLRUWN (ORCPT ); Wed, 18 Dec 2019 15:22:13 -0500 Received: by mail-lf1-f65.google.com with SMTP id 203so2609903lfa.12; Wed, 18 Dec 2019 12:22:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tdwll2I+0UIi7XhGuE9ZdnnXdDMdxuduY/8e8BdrqG0=; b=kHuQP2LHWukkPzJ/45IDQvB3gd/sszhYVcerwVPf3XxtIBkBOqYZmnnwdCHiWHbDpO vTfO3xLur/SZGCXjpWNpMdfPEkSNCrIL9/U7aE3EDL0QBie+ykrheURkxRb7p0h8tqJf oRpIYnOz5mavbBiEMlJdl5LFJcZT0XtbNqVU9JTXXSeJvGfF/jpVZOnwKhLW1xY1QUl2 OPz7n0y8p7q7qRr9QI/JVZC8wI/Ijdw9NCJwEWVs+u2N96FQB9AeC5SMeJ27YXO56NY3 /7oK0BaoQ/+XNIgCtKrskoXztqhPi5ah7014bySKHm2jJSJ988zwLgwL/ATpFpYjIed1 sSoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tdwll2I+0UIi7XhGuE9ZdnnXdDMdxuduY/8e8BdrqG0=; b=T8sj8C2DgV7PHx9z1xknKh2mPvansmTwVkGI7mXWZRQe2KJua1xiC+BUB83BUwQhEe rRlh61OYahnpju6xhEP83oA5klhAoi/f8THVFGLf8mfGHX5f6GFfh2e86Q9kBjO1qXAI Yo/i+H2Fg20OT+tN8/+n4MVxRHY+94syJzcf05z1WF7Fh0LxZFFzq/uj0GJWu3aLgG98 W5IVzK3AUXwKWeLEs/vtHHlex4gzcBlJopc2OITnHwDSfg9vFsNggkYolSpgwggKyijh AjZKod2UOPHfgo0YNuM7B+tUSHOqxZP+ZiZL4eyPdm/0eqJdDbAJg2JksdqA2p+918E4 zKSw== X-Gm-Message-State: APjAAAVd5p8irrQeIZK/O7NkYOjkoV0Lx6FSFV+uqGs4ITo+GE98H3Sw L0PgWZZApqzme7vIKcfu3eOvZTFj X-Google-Smtp-Source: APXvYqwcL1Z0PzCBN6ROSM2Su43KblPjIZ8Qw8lJApa5QoC8wUXlEQTcoTTHRxEvfMz6QUIrVJIZzg== X-Received: by 2002:ac2:599c:: with SMTP id w28mr3138290lfn.78.1576700530955; Wed, 18 Dec 2019 12:22:10 -0800 (PST) Received: from localhost.localdomain (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.gmail.com with ESMTPSA id m15sm1766993ljg.4.2019.12.18.12.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2019 12:22:10 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 12/12] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Date: Wed, 18 Dec 2019 23:21:42 +0300 Message-Id: <20191218202142.11717-13-digetx@gmail.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191218202142.11717-1-digetx@gmail.com> References: <20191218202142.11717-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 6ebb3105af9e..86556622be25 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -2124,4 +2126,26 @@ sound { <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };