From patchwork Thu Jul 26 23:44:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 10546527 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C84A14E2 for ; Thu, 26 Jul 2018 23:44:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 933B42B4BB for ; Thu, 26 Jul 2018 23:44:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86C482B537; Thu, 26 Jul 2018 23:44:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 311172B4BB for ; Thu, 26 Jul 2018 23:44:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 11E476E1ED; Thu, 26 Jul 2018 23:44:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 794A56E1ED for ; Thu, 26 Jul 2018 23:44:53 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2018 16:44:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,407,1526367600"; d="scan'208";a="59827967" Received: from rdvivi-vienna.jf.intel.com ([10.7.196.88]) by orsmga007.jf.intel.com with ESMTP; 26 Jul 2018 16:44:52 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Thu, 26 Jul 2018 16:44:48 -0700 Message-Id: <20180726234448.14595-1-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH] drm/i915: WaPsrDisableDpfcClkGating for glk and cnl X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arthur J Runyan , Dhinakaran Pandiyan , Rodrigo Vivi MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP "Host modification in FBC does not trigger PSR to exit sleep state" Since we are relying more on HW tracking lately it is better to protect this gen10 displays. Cc: Arthur J Runyan Cc: Dhinakaran Pandiyan Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5530c470f30d..3ba720f133f0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4027,6 +4027,7 @@ enum { #define PWM1_GATING_DIS (1 << 13) #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) +#define DPFC_GATING_DIS (1 << 31) #define BXT_GMBUS_GATING_DIS (1 << 14) #define _CLKGATE_DIS_PSL_A 0x46520 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7312ecb73415..56a46bc714c5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -137,6 +137,9 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_MISC_2, val); } + /* WaPsrDisableDpfcClkGating:glk */ + I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) | + DPFC_GATING_DIS); } static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) @@ -8715,6 +8718,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE); val |= VFUNIT_CLKGATE_DIS; I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val); + + /* WaPsrDisableDpfcClkGating:cnl (pre-prod) */ + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) + I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) | + DPFC_GATING_DIS); } static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)